Electronic paper TFT GOA drive design scheme

Abstract

The invention provides an electronic paper TFT GOA drive design scheme, and relates to the technical field of electronic information, the electronic paper TFT GOA drive design scheme comprises a gate shift register integrated on a TFT, the gate shift register is composed of ten transistors and two capacitors, and each transistor and each capacitor form a logic circuit through a specific line connection mode. A gate shift register formed by ten transistors and two capacitors forms a GOA structure, the distribution and connection relation of the transistors and the capacitors in the GOA structure follow a specific design rule, and in a traditional electronic paper TFT non-GOA design scheme, the gate shift register is integrated on a DDIC, so that the DDIC is large in size and small in output quantity, and the production cost is indirectly increased. According to the invention, the grid shift register is integrated on the TFT, so that the DDIC size is greatly reduced. By taking 960S * 680G resolution as an example, the size of the GOAIC can be reduced by 38.5% compared with that of a non-GOAIC, and the output quantity of DDICs can be increased under the condition that the size of a wafer is fixed, so that the purchase cost of the DDICs is remarkably reduced.

Description

Technical Field

[0001] The present invention belongs to the field of electronic information technology, and more specifically, relates to an electronic paper TFT GOA driving design scheme. Background Art

[0002] In the field of electronic paper display, continuously improving product performance, reducing costs and optimizing user experience are the keys to market competition. Traditional electronic paper TFT (non-GOA) gate drive solutions have many obvious defects.

[0003] First, the gate shift register is integrated on the DDIC, which results in a larger DDIC size. When the wafer size is fixed, the DDIC output quantity is small, which not only increases the production cost of DDIC, but also makes its procurement cost high.

[0004] Secondly, in the traditional solution, the left and right borders of TFT have a large space reserved due to the need for gate routing in the Fanout area, resulting in wider borders on the left and right sides of the TFT, reducing the screen-to-body ratio of the display, limiting the development of products in pursuit of narrow borders and high screen-to-body ratio, and making it difficult to meet consumers' higher requirements for aesthetics and visual effects.

[0005] Third, the circuit structure of the traditional design is relatively simple, and it is insufficient in realizing complex gate signal control and ensuring signal stability, which affects the display quality and performance of the electronic paper display.

[0006] With the continuous expansion of the electronic paper display market and the intensification of competition, an innovative driving design scheme is urgently needed to overcome the drawbacks of the above-mentioned traditional schemes. In this context, an electronic paper TFTGOA driving design scheme of the present invention comes into being, which aims to achieve the goals of reducing costs, increasing screen-to-body ratio, optimizing circuit performance, etc. by integrating the gate shift register on the TFT and adopting a unique "10T2C circuit design" to enhance the market competitiveness and user experience of electronic paper display devices. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides an electronic paper TFT GOA driving design solution to solve the above problems.

[0008] An electronic paper TFT GOA driving design scheme includes a gate shift register integrated on a TFT, wherein the gate shift register is composed of 10 transistors and 2 capacitors, and each transistor and capacitor is connected by a specific line to form a logic circuit.

[0009] Preferably, the gate shift register composed of the 10 transistors and the 2 capacitors forms a GOA structure, and the distribution and connection relationship of the transistors and capacitors in the GOA structure follow specific design rules.

[0010] Preferably, the GOA structure is produced by a TFT Array process, and the production process undergoes multiple "film formation → exposure → etching → photoresist stripping" processes.

[0011] Preferably, the driving circuit of the gate shift register composed of 10 transistors and 2 capacitors comprises an input unit, an output unit and a reset unit, and the specific structure and connection relationship of the transistors and capacitors in each unit are clear.

[0012] Preferably, the input unit is connected to the output unit and the reset unit, and the direction of the connection lines and the positions of the connection points are specific.

[0013] Preferably, the gate shift register abandons the gate wiring of the Fanout region on the left and right sides of the TFT, thereby saving the wiring space on the left and right sides of the TFT.

[0014] Preferably, each level of GOA unit provides a reset signal for the Gn-1 row and an input signal for Gn+1 while outputting a high potential at the Gn-out of the row, and the transmission path and control method of each signal are clear.

[0015] Preferably, the input unit pre-charges the gate of the transistor that controls Gn-out to output a high potential, in preparation for Gn-out outputting a high potential, and parameters such as charging voltage, current and time have specific settings.

[0016] Preferably, the output unit controls the Gn-out signal of this row to output a high potential, and when the Gate of this row refreshes the screen, the reset unit remains silent and does not interfere with the CLK unit outputting a high potential. At other times, the Gn-out signal is maintained at a low potential through the CLK and CLKB logic timing control, and the timing and logical relationship of each control signal are specific and clear.

[0017] Preferably, in the TFT Array process, no additional photomask is required and the process is compatible with the conventional non-GOA TFT production process, and the specific compatible process steps and parameters are clear.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] 1. Significantly reduce DDIC cost: In the traditional non-GOA design of electronic paper TFT, the gate shift register is integrated on the DDIC, resulting in a larger DDIC size and a smaller output quantity, which indirectly increases the production cost. However, the present invention integrates the gate shift register on the TFT, which greatly reduces the DDIC size. Taking the 960S×680G resolution as an example, the GOA IC size can be reduced by 38.5% compared with the non-GOA IC. When the wafer size is fixed, the output quantity of the DDIC can be increased, thereby significantly reducing the procurement cost of the DDIC.

[0020] 2. Improve the screen-to-body ratio: In the traditional solution, the left and right sides of the TFT frame need to reserve a large space for the Fanout area gate wiring, resulting in a larger frame and reducing the display screen-to-body ratio. The present invention abandons the Fanout area gate wiring on the left and right sides of the TFT and reduces the left and right sides of the TFT frame. For example, at the same resolution, the width of the left and right single-sided frame of GOA TFT is reduced from 4.2mm to 2.5mm, which significantly improves the screen-to-body ratio and brings a wider visual experience to users. It is particularly suitable for electronic devices with high requirements for appearance and display effects.

[0021] 3. Optimized circuit design: The "10T2C circuit design" is adopted, which consists of 10 transistors and 2 capacitors to form a logic circuit. Compared with the traditional design, it realizes more complex function control while ensuring the stable operation of the gate signal. This optimized circuit design improves the stability and reliability of the system, reduces the possibility of signal interference and distortion, and ensures the high-quality display effect of the electronic paper display.

[0022] 4. Improve the compatibility of production processes: The GOA TFT production process (Array process) is compatible with the traditional non-GOA TFT production process, and no additional mask (PHT process) is required. This means that it is relatively easy to transform and upgrade the existing production line, reducing production costs and technical difficulties, improving production efficiency, and facilitating large-scale production and promotion and application.

[0023] 5. Enhance product market competitiveness: The present invention reduces costs, increases screen-to-body ratio, and optimizes display effects, making electronic paper display devices have greater advantages in performance and price. In the fiercely competitive electronic paper display market, it can attract more customers, increase product market share, and bring greater economic benefits to enterprises.

[0024] 6. Promote the development of industry technology: This invention provides an innovative solution for the field of electronic paper display technology, breaking through the limitations of traditional design. Its technological innovation and application are expected to stimulate more research and development in the industry, promote technological progress in the entire electronic paper display industry, and promote the development and upgrading of related industries.

[0025] 7. Higher screen-to-body ratio and more optimized performance enable e-paper displays to better meet the needs of different application scenarios such as electronic price tags and readers. For example, in electronic price tags, narrower borders can make the displayed content more prominent; in readers, a higher screen-to-body ratio can provide a more immersive reading experience.

[0026] 8. The carefully designed GOA driving circuit structure and working mechanism, as well as the strict production process and quality control, effectively improve the reliability and stability of the product. It reduces display problems caused by circuit failure or unstable signal, extends the service life of the product, and reduces after-sales maintenance costs.

[0027] 9. As the requirements for electronic devices to be thin, beautiful and high-performance continue to increase, the design concept and technical solution of the present invention are in line with the development trend of future display technology. It lays the foundation for the continuous upgrading and improvement of products, enabling enterprises to better cope with the challenges of market changes and technological updates. The successful implementation of the present invention will stimulate the innovative vitality of related industries and drive the development of upstream and downstream industrial chains. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of the traditional non-GOA TFT gate drive circuit structure;

[0029] Figure 2 It is a schematic diagram of the structure of the TFT gate drive circuit of the present invention;

[0030] Figure 3 Schematic diagram of the GOA circuit architecture of the present invention;

[0031] Figure 4 It is the GOA 10T2C equivalent circuit diagram of the present invention;

[0032] Figure 5 It is a timing diagram of the GOA circuit driving of the present invention. DETAILED DESCRIPTION

[0033] Electronic paper display technology has been widely used in the fields of electronic price tags, readers, etc. due to its low power consumption and eye protection. However, the traditional electronic paper TFT driving scheme has many shortcomings, which limits the performance and market competitiveness of the product. The electronic paper TFT GOA driving design scheme of the present invention aims to solve these problems and bring new breakthroughs to the electronic paper display technology.

[0034] The core of this solution is to integrate the gate shift register on the TFT to form a GOA structure and adopt a "10T2C circuit design". This design reduces the size of the DDIC while ensuring the stable operation of the gate signal, abandons the gate routing in the Fanout area on the left and right sides of the TFT, reduces the left and right sides of the TFT, and increases the screen-to-body ratio.

[0035] GOA unit "gate shift register" design: the shift register that controls the gate signal output is changed from the traditional integration on DDIC to integration on TFT. It is manufactured through the TFTArray process. During the manufacturing process, it undergoes multiple "film formation → exposure → etching → stripping of photoresist" processes to ensure the precise formation of the circuit. The GOA circuit adopts the "10T2C circuit design" and consists of 10 transistors and 2 capacitors. These transistors and capacitors are connected through a carefully designed logic circuit to form an input unit, an output unit, and a reset unit, where:

[0036] 1. Input unit: The input unit is responsible for pre-charging the gate of the transistor that controls the high potential of the Gn-out output. At a specific timing, the input signal is written into a high potential, turning on the corresponding transistor, so that the Q point is pre-charged to a high potential through the VDD signal, preparing for the subsequent output unit operation;

[0037] 2. Output unit: The output unit controls the Gn-out signal of this row to output high potential. When the Gate of this row refreshes the screen, according to the pre-charge state of the input unit and the change of the clock signal, the transistors and capacitors in the output unit work together to pull the Vo point potential to a high potential, so that Gn-out outputs a high potential;

[0038] 3. Reset unit: The reset unit is used to change the Gn-out signal from high potential to low potential at an appropriate time. Through a specific reset signal, the corresponding transistor is turned on, the potential of the Q point and the Vo point are pulled down, and the Gn-out signal is reset.

[0039] Taking the resolution of 960S×680G as an example, the size of the traditional non-GOAI C DDIC is 30.29mm 2 , while the size of GOAIC using this solution is only 18.63mm 2 , the size is reduced by 38.5%. At the same time, the width of the left and right single-side borders of traditional non-GOATFT is 4.2mm, while the width of the left and right single-side borders of GOATFT is only 2.5mm, which significantly reduces the border size and increases the screen-to-body ratio.

[0040] Working mechanism of GOA unit "10T2C drive circuit":

[0041] 1. Pre-charging stage: In this stage, the input signal is written to a high potential, turning on the T1 tube, so that the Q point is pre-charged to a high potential through the VDD signal. At this time, the T2 tube is turned on, and the CLK signal is written to a low potential, pulling down the Vo point potential through the T2 tube, preparing for the subsequent bootstrap charging of the C1 capacitor;

[0042] 2. VGH output stage: the input signal is written to a low potential, and the T1 tube is turned off. However, since the Q point has been pre-charged to a high potential in the pre-charging stage and maintained by the C1 capacitor, the T2 tube is in the on state at this time. At the same time, the CLK signal is changed from a low potential to a high potential, and the Vo point potential is pulled up from a low potential to a high potential. Through the bootstrap effect of the C1 capacitor, the Q point is coupled to a higher potential, the Vgs of the T2 tube is further increased, and the Ion on-state current of the T2 tube increases, ensuring that the CLK high potential signal is fully written to the Vo point. At this time, the gate of the T6 tube is controlled to open by the Vo point, and the D point is written to a low potential through the VSS signal, turning off the T8 and T9 tubes to avoid the VSS signal from interfering with the Gn-out signal output, ensuring that the Gn-out signal stably outputs a high potential;

[0043] 3. VGL pull-down stage: When the reset signal is written to a high potential, T4 and T5 are turned on, Q and Vo points are written to a low potential through the VSS signal, T2 and T6 are turned off, and the Gn-out signal outputs a low potential;

[0044] 4. VGL maintenance stage: When the CLKB signal is written to a high potential, the CLK signal is written to a low potential, the T7 tube is turned on, the D point is written to a high potential, the T8 and T9 tubes are turned on, the Q point and the Vo point are written to a low potential through the VSS signal, and the Gn-Out outputs a low potential. When the CLKB outputs a low potential, the CLK outputs a high potential. When the CLK rises from a low potential to a high potential, the T10 tube is turned on, and at the same time, through the bootstrap effect of the C2 capacitor, the D point is coupled to a high potential, the T8 and T9 tubes are turned on, and the Q point and the Vo point are written to a low potential. Through the timing control of the CLK signal and the CLKB signal, the Gn-Out signal continues to output a low potential in this stage and maintains it for 1 frame time.

[0045] This solution is designed with full consideration of compatibility with existing TFT production processes. TFTArray process is a mature manufacturing technology that is widely used in the field of electronic displays. By optimizing and adjusting the process flow, the production of GOA structure can be achieved without the need for additional photomasks (PHT process).

[0046] During the production process, we strictly follow mature and stable process parameters and use the most stringent industry standards for reliability testing. From the selection of raw materials to the testing of finished products, every link is strictly controlled to ensure product performance and reliability.

[0047] The shift register that controls the gate signal output is integrated on the TFT to form a GOA structure, which is one of the key innovations of this solution. This structural design not only reduces the size of the DDIC and reduces the cost, but also makes it possible to achieve a narrow frame design. The "10T2C circuit design" is adopted to achieve complex gate signal control logic by cleverly combining 10 transistors and 2 capacitors. This circuit design improves the integration and performance of the circuit while ensuring signal stability. Through the implementation of this solution, not only the cost of the DDIC is reduced, but also the screen-to-body ratio of the electronic paper display device is improved. Under the premise of ensuring display quality, it brings a better visual experience to users.

[0048] like Figure 1 As shown in Figure 1, the gate drive circuit of the traditional electronic paper TFT (non-GOA design) integrates the shift register on the DDIC, resulting in a large DDIC size, high procurement cost, large borders on both sides of the TFT, and a low screen-to-body ratio of the display device. Figure 2 As shown, the "TFT gate drive circuit structure" of the present invention integrates the gate shift register on the TFT, optimizes the circuit layout, GOATFT, and the GOA unit only needs to occupy a certain area, which can realize the gate signal line-by-line scanning and realize the narrow frame design of the product. Taking the resolution of 960S×680G as an example, the width of the left and right single-side frame of non-GOATFT TFT is 4.2mm, while the width of the left and right single-side frame of GOATFT is only 2.5mm; GOATFT can greatly reduce the width of the left and right side frames and improve the screen-to-body ratio. DDIC, the gate shift register does not need to be integrated here, and the size of GOAIC can be greatly reduced. Taking the resolution of 960S×680G as an example, the size of non-GOAI C is 30.29mm 2 ; GOAIC size is only 18.63mm 2 ,GOAIC size can be reduced by 38.5% compared with non-GOAIC, which can significantly reduce IC cost;

[0049] like Figure 3 As shown in the figure, the “GOA circuit architecture” shows the overall structure and connection method of the GOA unit, such as Figure 4 As shown in FIG. 1 , the “GOA10T2C equivalent circuit diagram” describes in detail the connection relationship and working principle of 10 transistors and 2 capacitors. Point Q is the gate potential of T2 and T3, which is high in the Gn output stage. Turning on T2 outputs a high potential for the current Gn, and turning on T3 to provide a reset signal to Gn-1 and an input (start) signal to Gn+1. Point D is the gate potential of T8 and T9, which is low in the Gn output stage. Turning off T8 and T9 is high in the Gn reset stage. Turning on T8 and T9 inputs a low potential to the gate and drain of T2, and Gn outputs a low potential for one frame time. Figure 5As shown in the figure, the "GOA circuit driving timing diagram" intuitively shows the timing relationship of each signal at different stages, providing a clear guide for understanding the working process of the circuit.

[0050] In the traditional non-GOA design of electronic paper TFT, the gate shift register is integrated on the DDIC, which leads to a larger DDIC size and a smaller output quantity, which indirectly increases the production cost. However, the present invention integrates the gate shift register on the TFT, which greatly reduces the DDIC size. Taking the resolution of 960S×680G as an example, the GOAIC size can be reduced by 38.5% compared with the non-GOAIC. When the wafer size is fixed, the output quantity of the DDIC can be increased, thereby significantly reducing the procurement cost of the DDIC;

[0051] In the traditional solution, the left and right sides of the TFT frame need to reserve a large space for the Fanout area gate wiring, resulting in a larger frame and reducing the display screen ratio. The present invention abandons the Fanout area gate wiring on the left and right sides of the TFT and reduces the left and right sides of the TFT frame. For example, at the same resolution, the width of the left and right single-sided frame of GOATFT is reduced from 4.2mm to 2.5mm, which significantly improves the screen ratio and brings a wider visual experience to users. It is particularly suitable for electronic devices with high requirements for appearance and display effects;

[0052] The "10T2C circuit design" is adopted, and the logic circuit is composed of 10 transistors and 2 capacitors. Compared with the traditional design, more complex function control is achieved under the premise of ensuring the stable operation of the gate signal. This optimized circuit design improves the stability and reliability of the system, reduces the possibility of signal interference and distortion, and ensures the high-quality display effect of the electronic paper display. The GOATFT production process (Array process) is compatible with the traditional non-GOATFT production process, and no additional mask (PHT process) is required. This means that it is relatively easy to transform and upgrade the existing production line, reducing production costs and technical difficulties, improving production efficiency, and facilitating large-scale production and promotion and application;

[0053] The present invention enables electronic paper display devices to have greater advantages in performance and price by reducing costs, increasing screen-to-body ratio and optimizing display effects. In the fiercely competitive electronic paper display market, it can attract more customers, increase product market share, and bring greater economic benefits to enterprises. The present invention provides an innovative solution to the field of electronic paper display technology, breaking through the limitations of traditional designs. Its technological innovation and application are expected to inspire more research and development in the industry, promote technological progress in the entire electronic paper display industry, and promote the development and upgrading of related industries. Higher screen-to-body ratio and more optimized performance enable electronic paper displays to better meet the needs of different application scenarios such as electronic price tags and readers. For example, in electronic price tags, narrower borders can make the displayed content more prominent; in readers, a higher screen-to-body ratio can provide a more immersive reading experience;

[0054] The carefully designed GOA driving circuit structure and working mechanism, as well as the strict production process and quality control, effectively improve the reliability and stability of the product. It reduces display problems caused by circuit failure or unstable signal, prolongs the service life of the product, and reduces after-sales maintenance costs. As the requirements of electronic equipment for thinness, beauty and high performance continue to increase, the design concept and technical solution of the present invention are in line with the development trend of future display technology. It lays the foundation for the continuous upgrading and improvement of products, enabling enterprises to better cope with the challenges of market changes and technological updates. The successful implementation of the present invention will stimulate the innovative vitality of related industries and drive the development of upstream and downstream industrial chains.

[0055] The embodiments of the present invention are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

Claims

1. An electronic paper TFT GOA driving design scheme, characterized by: The invention comprises a gate shift register integrated on a TFT, wherein the gate shift register is composed of 10 transistors and 2 capacitors.

2. The electronic paper TFT GOA driving design scheme as claimed in claim 1, characterized in that: The gate shift register composed of the 10 transistors and the 2 capacitors forms a GOA structure.

3. The electronic paper TFT GOA driving design scheme as claimed in claim 2, characterized in that: The GOA structure is produced by a TFT Array process.

4. The electronic paper TFT GOA driving design scheme as claimed in claim 3, characterized in that: The driving circuit of the gate shift register composed of 10 transistors and 2 capacitors comprises an input unit, an output unit and a reset unit.

5. The electronic paper TFT GOA driving design scheme as claimed in claim 4, characterized in that: The input unit is connected with the output unit and the reset unit.

6. The electronic paper TFT GOA driving design scheme as claimed in claim 5, characterized in that: The gate shift register abandons the gate wiring of the Fanout region on the left and right sides of the TFT.

7. The electronic paper TFT GOA driving design scheme as claimed in claim 6, characterized in that: Each level of GOA unit provides a reset signal for the Gn-1 row and an input signal for Gn+1 while outputting a high potential at the Gn-out of the row.

8. The electronic paper TFT GOA driving design scheme as claimed in claim 7, characterized in that: The input unit pre-charges the gate of the transistor that controls Gn-out to output a high potential, preparing for Gn-out to output a high potential.

9. The electronic paper TFT GOA driving design scheme as claimed in claim 8, characterized in that: The output unit controls the Gn-out signal of this row to output a high potential, and when the Gate of this row refreshes the screen, the reset unit remains silent and does not interfere with the CLK unit outputting a high potential. At other times, the Gn-out signal is maintained at a low potential through the CLK and CLKB logic timing control.

10. The electronic paper TFT GOA driving design scheme as claimed in claim 9, characterized in that: During the TFT Array process production and manufacturing, no additional photomask is required.

Images