Pixel structure, imaging device and electronic device
By designing the pixel structure in the image sensor and using the shared capacitance of sub-pixels to isolate and float diffusion nodes, the problem of low signal-to-noise ratio in the prior art is solved, and a high signal-to-noise ratio and powerful phase difference autofocus function is realized.
Patent Information
- Application Number
- CN202280096402.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-08
- Publication Date
- 2025-01-07
AI Technical Summary
The signal-to-noise ratio (SNR) of existing image sensors is low, which affects image quality, especially in the phase difference autofocus (PDAF) function, making it difficult to simultaneously improve PDAF performance and signal-to-noise ratio.
A pixel structure is designed in which the first pixel component is divided into a pair of sub-pixel components by sub-pixel isolation, and the floating diffusion node is set at the center of the 2*2 array, so that the active area is between 4 pixel components Shared, reduces the capacitance of the floating diffusion node, thereby increasing the conversion gain (CG), and thus improving the signal-to-noise ratio.
It realizes high signal-to-noise ratio and enhanced phase difference autofocus function, improves image quality, and improves spatial resolution and quantum efficiency while ensuring PDAF performance.
Smart Images
Figure CN119278672A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a pixel structure, an imaging device and an electronic device. Background Art
[0002] Image sensors convert optical images into electrical signals and are widely used in cameras or other optical devices.
[0003] Typically, the phase difference auto focus (PDAF) function is one of the basic characteristics of focus detection pixels in image sensors. For such pixels, it is also important to pay attention to the signal-to-noise ratio (SNR), because the SNR is used to evaluate the performance of the image sensor in terms of image quality. The higher the SNR, the better the image quality.
[0004] The purpose of the background art is to disclose information that the applicant believes may be relevant to the present application. It is not necessary to admit nor should it be construed that any of the above information constitutes prior art against the present application. Summary of the invention
[0005] Embodiments of the present application provide a pixel structure, an imaging device, and an electronic device with a high signal-to-noise ratio (SNR).
[0006] The above and other objects are achieved by the subject matter claimed in the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.
[0007] A first aspect of the present application provides a pixel structure, comprising 4 pixel components, 4 pixel parts corresponding to the 4 pixel components, and a floating diffusion node;
[0008] wherein the pixel components in the four pixel parts are arranged in a 2*2 array, and each of the pixel components is arranged in a corresponding pixel part;
[0009] The floating diffusion node is disposed at the center of the array such that an active area of the floating diffusion node is shared among the pixel components;
[0010] The pixel components include at least one first pixel component, which is divided into a pair of sub-pixel components by sub-pixel isolation, and the sub-pixel isolation extends outward from the center of the array to the periphery of the first pixel component in one direction.
[0011] In the pixel structure provided in the embodiment of the present application, since the first pixel component is divided into the pair of sub-pixel components by the sub-pixel isolation extending from the center of the array to the periphery of the first pixel component in one direction, the phase difference of the pair of sub-pixel components can be obtained, thereby realizing phase difference autofocus (PDAF) (including horizontal AF function and vertical AF function). In addition, the floating diffusion node is arranged at the center of the array, so that the active area of the floating diffusion node is shared among the four pixel components, thereby reducing the total amount of the floating diffusion node, thereby reducing the capacitance of the floating diffusion node. Since the capacitance of the floating diffusion node is inversely proportional to the conversion gain (CG), the CG is improved, and while ensuring the enhancement of the PDAF function, a higher SNR is obtained through the improved CG.
[0012] In a possible implementation, each of the four pixel portions includes a deep region and a shallow region according to depth;
[0013] A peripheral isolation is provided in the peripheral area of the pixel structure, and a cross isolation is provided in the cross area which divides the pixel structure into the four pixel parts;
[0014] The peripheral isolation and the cross isolation both extend into the shallow region, and the sub-pixel isolation does not extend into the shallow region.
[0015] By setting the deep region and the shallow region according to depth, the pixel structure can not only achieve high quantum efficiency and high full well capacity, but also effectively realize charge transfer.
[0016] In a possible implementation, the sub-pixel isolation includes a sub-pixel channel isolation or a sub-pixel p-type doping layer. Since there is no channel isolation as an additional damage source, the sub-pixel channel isolation has better dark performance, and the configuration of the sub-pixel p-type doping layer is more robust because there is no overlap error of the doping layer.
[0017] In one possible implementation, the sub-pixel isolation includes a sub-pixel channel isolation covered by a sub-pixel p-type doping layer, and such sub-pixel channel isolation can achieve a balance between dark performance and robust performance. The sub-pixel p-type doping layer is used as a protective layer for the sub-pixel channel isolation (e.g., deep trench isolation (DTI)), which is beneficial to enhancing the dark performance because electrons in the dark current can be neutralized by holes provided by the sub-pixel p-type doping layer.
[0018] In a possible implementation manner, the sub-pixel channel isolation is provided with a gap.
[0019] In a possible implementation manner, a preset distance is set between the sub-pixel channel isolation and the center of the array.
[0020] Since longer trench isolations degrade optical crosstalk performance, reducing the length of trench isolations can improve optical crosstalk performance.
[0021] In one possible implementation, the peripheral isolation includes a peripheral trench isolation covered by a peripheral p-type doped layer, which is conducive to achieving a balance between dark performance and robust performance. The peripheral p-type doped layer is used as a protective layer for the peripheral trench isolation (e.g., DTI), which is conducive to enhancing the dark performance because the electrons in the dark current can be neutralized by the holes provided by the peripheral p-type doped layer.
[0022] In a possible implementation, the depth of the sub-pixel channel isolation is less than the depth of the peripheral channel isolation, and due to less silicon damage, the shallower sub-pixel channel isolation has better dark performance.
[0023] In a possible implementation, a grid is provided on the sub-pixel isolation area, which is helpful in reducing light crosstalk.
[0024] In a possible implementation, in the shallow region of the first pixel component, an overflow path is formed between the pair of sub-pixel components of the first pixel portion to perform charge exchange.
[0025] In a possible implementation, each sub-pixel component of the pair of sub-pixel components includes a photodiode;
[0026] The overflow path is a path for transferring photoelectric charges exceeding the full well capacity of the photodiode of one of the pair of sub-pixels to the photodiode of the other of the pair of sub-pixels.
[0027] When the capacity of the photoelectric charge that can be accommodated by one photodiode is full, the capacity of another photodiode can be used to store the photoelectric charge through the overflow path, so the first pixel component can store more photoelectric charge.
[0028] In a possible implementation manner, the pixel structure is rotated by a preset angle relative to an imaging device including the pixel structure.
[0029] The rotation angle is related to the spatial resolution. By rotating at a certain angle, the spatial resolution can be improved in the horizontal and vertical directions.
[0030] In a possible implementation, the pixel structure further includes an amplifier device, a reset device, a dual conversion device and / or a row selection device;
[0031] The amplifier device, the reset device, the dual conversion device and / or the row selection device are all arranged in the cross isolation or the peripheral isolation;
[0032] or,
[0033] A portion of the amplifying device, the resetting device, the dual conversion device and / or the row selecting device is arranged in the sub-pixel isolation, and the rest of the amplifying device, the resetting device, the dual conversion device and / or the row selecting device is arranged in the cross isolation or the peripheral isolation.
[0034] The configuration of the amplifier device, the reset device, the dual conversion device and / or the row selection device makes the layout design more flexible, so more devices can be placed, thereby providing more functions.
[0035] In a possible implementation manner, the pixel structure further includes a metal shielding layer, and the metal shielding layer shields at least a portion of the pixel structure to protect it from the influence of incident light.
[0036] Shielding certain portions of the pair of sub-pixels is effective, especially in high light conditions, that is, when the incident signal is very strong, the pixel structure still maintains the PDAF function because part of the incident light is shielded.
[0037] A second aspect of the present application provides an imaging device, comprising a pixel structure according to any one of the first aspects.
[0038] A third aspect of the present application provides an electronic device, comprising the imaging device according to the second aspect.
[0039] The present application provides a pixel structure, an imaging device and an electronic device. The pixel structure includes at least one first pixel component, and the first pixel component is divided into a pair of sub-pixel components by isolating the sub-pixels extending outward from the center of the array to the periphery of the first pixel component in one direction, so that the phase difference of the pair of sub-pixel components can be obtained, thereby realizing the PDAF function. In addition, the floating diffusion node is arranged at the center of the array, so that the active area of the floating diffusion node is shared among the four pixel components, thereby reducing the total amount of the floating diffusion node, thereby reducing the capacitance of the floating diffusion node. Since the capacitance of the floating diffusion node is inversely proportional to the CG, the CG is improved, and while ensuring the enhancement of the PDAF function, a higher SNR is obtained through the improved CG. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The present application can be further understood in conjunction with the accompanying drawings, which constitute a part of the specification and are used together with the following specific embodiments to explain the present application, but should not be construed as limiting the present application.
[0041] Figure 1 A scenario to which the solid-state imaging device according to the embodiment of the present application is applied is shown.
[0042] Figure 2 A block diagram of an imaging system using a pixel structure according to an embodiment of the present application is shown.
[0043] Figure 3 Different layout configurations of components of a solid-state imaging device according to an embodiment of the present application are shown.
[0044] Figure 4 A block diagram of a solid-state imaging device according to an embodiment of the present application is shown.
[0045] Figure 5 A layout configuration diagram of a pixel structure according to an embodiment of the present application is shown.
[0046] Figure 6 The embodiment according to the present application is shown Figure 5 A cross-sectional view of a pixel portion in a pixel structure of FIG.
[0047] Figure 7 Another cross-sectional view of the solid-state imaging device according to the embodiment of the present application is shown.
[0048] Figure 8 A plan view showing a solid-state imaging device including a plurality of pixel structures according to an embodiment of the present application is shown.
[0049] Fig. 9 Different structures of pixel isolation according to embodiments of the present application are shown.
[0050] Fig.10 Different layout configurations of deep trench isolation according to embodiments of the present application are shown.
[0051] Fig.11 A schematic diagram of the rotation of a pixel array including four pixel structures according to an embodiment of the present application is shown.
[0052] Fig.12 A schematic configuration diagram of a pixel structure according to an embodiment of the present application is shown.
[0053] Fig.13 A schematic configuration diagram of a metal shielding layer of a pixel structure according to an embodiment of the present application is shown.
[0054] Fig.14 A circuit diagram for a pixel structure according to an embodiment of the present application is shown.
[0055] FIG. 15A to FIG. 15D A circuit diagram for a pixel structure according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0056] In the following description, reference is made to the accompanying drawings that form a part of the present application, which illustrate specific aspects of the embodiments of the present application or specific aspects of the embodiments of the present application that can be used by way of illustration. It should be understood that the embodiments of the present application can be used in other aspects and can include structural changes or logical changes not depicted in the accompanying drawings. Therefore, the following detailed description is not to be understood in a restrictive sense, and the scope of the present application is defined by the appended claims.
[0057] Typically, the phase difference autofocus (PDAF) function is one of the basic characteristics of focus detection pixels in image sensors. For such pixels, it is also important to pay attention to the signal-to-noise ratio (SNR), because the SNR is used to evaluate the performance of the image sensor in terms of image quality, and the higher the SNR, the better the image quality. Current image sensors have the problem of low SNR.
[0058] The present application provides a pixel structure, an imaging device including the pixel structure, and an electronic device including the imaging device. The pixel structure includes at least one first pixel component, which divides a pair of sub-pixel components, and the phase difference of the pair of sub-pixel components can be obtained, thereby realizing the phase difference autofocus (PDAF) function. In addition, the floating diffusion node of the pixel structure is arranged at the center of the 2*2 array, so that the active area of the floating diffusion node is shared among the 4 pixel components of the pixel structure, thereby reducing the total amount of floating diffusion nodes, thereby reducing the capacitance of the floating diffusion node. Since the capacitance of the floating diffusion node is inversely proportional to the conversion gain (CG), the CG is improved, and while ensuring the enhanced PDAF function, a higher SNR is obtained through the improved CG.
[0059] The PDAF function mentioned in this article includes not only the horizontal AF function, but also the vertical AF function. Generally, in order to enhance the PDAF function, in the technical solution of the present application, for a pixel component, intra-pixel isolation, such as intra-pixel vertical deep trench isolation (DTI) or doping, is used to divide or separate the pixel component into two sub-pixel components, so that since the intra-pixel isolation extends almost diagonally or in a radiation pattern, the divided sub-pixel components can support both the horizontal AF function and the vertical AF function, as described below.
[0060] The following first introduces possible application scenarios of the embodiments of the present application, and then describes the embodiments of the present application in detail with reference to the accompanying drawings.
[0061] The technical solution of the present application provides a pixel structure, which can be used in a solid-state imaging device (such as an image sensor) and can be applied to various fields that require taking pictures or filming. Figure 1 As shown, solid-state imaging devices can be applied to sports equipment (such as wearable cameras), medical equipment (such as endoscopes and beauty equipment), vehicles or transportation equipment (such as trucks), entertainment equipment (such as mobile phones, game consoles), digital cameras, camcorders, equipment in the agricultural field (such as farmland monitoring cameras), household appliances (such as televisions, refrigerators, etc.), equipment in the security field (such as surveillance cameras, webcams, machine vision cameras), etc.
[0062] Figure 2 A block diagram of an imaging system to which an embodiment of the present application can be applied is shown, and the imaging system includes a control circuit, a pixel array, a readout circuit, and a signal processing circuit. The pixel array is a two-dimensional pixel array, and the pixels are arranged in rows (R1 to Ry) and columns (C1 to Cx) to obtain image data of the subject. The control circuit controls the pixel array, for example, to generate a shutter signal. The image data is read out by the readout circuit through Vout and sent to the signal processing circuit. In one possible implementation, the number of Vout can be more than two, and at least two rows are read simultaneously.
[0063] Figure 3 Different layout configurations of components of a solid-state imaging device according to an embodiment of the present application are shown. Typically, a typical solid-state imaging device includes a pixel array, a control circuit, and a logic circuit. The pixel array includes a photoelectric conversion portion and a charge retention portion, which is used to retain the charge transferred from the photoelectric conversion portion. The pixel circuit always appears with the pixel array and may include an amplifier transistor that generates a signal of a voltage corresponding to a charge level retained in the charge retention portion (e.g., in a floating diffusion node). The control circuit is used to control the pixel array. The logic circuit is used to process output signals from the pixel array. The solid-state imaging device may also include a memory circuit that is used to store image data generated based on the result of the photoelectric conversion.
[0064] It should be noted that the pixel array is the main component of the solid-state imaging device. Each pixel structure in the pixel array may be the same or different. This article takes the structure in which each pixel structure is the same as an example. The pixel array may have a front-illuminated pixel structure or a back-illuminated pixel structure. The semiconductor substrate may be composed of a semiconductor material (e.g., silicon or gallium). In some implementations, the semiconductor substrate may be composed of one or more other materials that are sensitive to electromagnetic radiation, such as silicon germanium, silicon carbide, potassium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium, antimony, a semiconductor on an insulator, or a combination thereof.
[0065] The above circuits in the solid-state imaging device can be arranged in different ways, such as Figure 3 shown.
[0066] like Figure 3 As shown in (A), the solid-state imaging device includes a pixel array, a control circuit, and a logic circuit mounted on a single semiconductor chip.
[0067] like Figure 3 As shown in (B), the solid-state imaging device includes a pixel array and a control circuit mounted on a first semiconductor chip portion and a logic circuit mounted on a second semiconductor chip portion, the logic circuit including a signal processing circuit for signal processing. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other, and a single semiconductor chip can be formed to provide a solid-state imaging device.
[0068] like Figure 3 As shown in (C), in a solid-state imaging device, a pixel array is mounted on a first semiconductor chip portion, and a control circuit and a logic circuit including a signal processing circuit are mounted on a second semiconductor chip portion. The first semiconductor chip portion and the second semiconductor chip portion are electrically connected to each other, and a single semiconductor chip can be formed to provide a solid-state imaging device.
[0069] like Figure 3 As shown in (D), in a solid-state imaging device, a pixel array is mounted on a first semiconductor chip portion, a memory circuit is mounted on a second semiconductor chip portion, and a control circuit and a logic circuit including a signal processing circuit are mounted on a third semiconductor chip portion. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected, and a single semiconductor chip or two semiconductor chips can be formed to provide a solid-state imaging device.
[0070] like Figure 3As shown in (E), in a solid-state imaging device, a pixel array is mounted on a first semiconductor chip portion, a pixel circuit is mounted on a second semiconductor chip portion, and a control circuit and a logic circuit including a signal processing circuit are mounted on a third semiconductor chip portion. The first semiconductor chip portion, the second semiconductor chip portion, and the third semiconductor chip portion are electrically connected, and a single semiconductor chip or two semiconductor chips can be formed to provide a solid-state imaging device.
[0071] Figure 4 4 shows a block diagram of a solid-state imaging device. The solid-state imaging device may include: a lens 401; an imaging device array 402; a shutter 403 disposed between the lens 401 and the imaging device array 402; a control circuit 404 for controlling the imaging device array 402 and the shutter 403; a signal processing circuit 405 for processing output signals from the imaging device array 402; a display 406 for displaying an image output after processing by the signal processing circuit 405; and a memory 407 for storing the image output after processing by the signal processing circuit 405.
[0072] refer to Figure 5 The embodiment of the present application provides a pixel structure 100, which includes four pixel components 1101, four pixel parts 110 corresponding to the four pixel components 1101 (i.e., one pixel part corresponding to one pixel component), and a floating diffusion node 120. The pixel components 1101 in the four pixel parts 110 are arranged in a 2*2 array, and each pixel component 1101 is arranged in a corresponding pixel part 110. The 2*2 array can correspond to Figure 2 P11, P12, P21 and P22 in.
[0073] In this document, the pixel portion 110 refers to a portion including Figure 5 When the solid-state imaging device of the pixel structure shown in the figure works, it is possible to convert light into a voltage signal. For example, the pixel part 110 may include a photodiode, a transmission gate, an amplifier device, a reset device, a dual conversion device, a row selection device, etc. The functions of these devices will be described below. The pixel component 1101 in the embodiment of the present application refers to a component provided in the pixel part 110 for realizing photoelectric conversion, for example, a photodiode.
[0074] The floating diffusion node 120 is arranged at the center of the array so that the active area of the floating diffusion node 120 is shared between the pixel components 1101. The floating diffusion node 120 is used to accommodate the signal charge converted by the pixel components 1101. That is, four pixel components 1101 can be placed in a radial pattern, and one floating diffusion node 120 is placed in the center of the radial pattern, so the active area of one floating diffusion node 120 is shared between the four pixel components 1101. In addition, the active area of the floating diffusion node 120 refers to a doped region. The technology used to form the doped region is usually different from the technology used to form the DTI.
[0075] The pixel component 1101 includes at least one first pixel component, which is divided into a pair of sub-pixel components 1102 by sub-pixel isolation, and the sub-pixel isolation extends outward from the center of the array to the periphery of the first pixel component in one direction. In this document, the first pixel component refers to a pixel component divided into a pair of sub-pixel components 1102, for example, the pair of sub-pixel components 1102 can be photodiode 1 (photodiode 1, PD1) and photodiode 2 (photodiode 2, PD2). In addition, Figure 5 The extended arrangement (layout configuration) of the pixel components shown can also be referred to as a radial direction diagram, because it appears that the four sub-pixels are isolated and radiate outward from the center of the array. It should be noted that the extension is defined as the direction from the center of the array to the periphery of the first pixel component, not necessarily starting from the center of the array. For example, the following will be combined with Fig.10 (D) Describe possible implementations.
[0076] In this paper, each first pixel component is divided into Figure 5 It should be noted that only one of the first pixel components that is divided can implement the PDAF function. That is, it is not necessary for the four pixel components to adopt the same implementation method. Different implementation methods will be described below. For example, Fig.10 The number of first pixel components in the pixel structure may be selected based on actual needs.
[0077] In one implementation, the pixel component is provided with a transfer gate for transferring the signal charge to the floating diffusion node. The pixel portion corresponding to the pixel component is provided with an amplifier device and a reset device, wherein the amplifier device is used to convert the signal voltage of the floating diffusion node into an output signal, and the reset device is used to set the voltage of the floating diffusion node. In a possible implementation, the charge-to-voltage conversion is performed by the amplifier device using a source follower operation with a gain equal to 1 or less than 1. It should be noted that the charge-to-voltage conversion is performed by the amplifier device, the gain is greater than 1, and a differential amplification mode can be adopted.
[0078] In another implementation, the pixel portion corresponding to the pixel component may also include a dual conversion device and a row selection device, wherein the dual conversion device combines two gains to achieve a high dynamic range, and the row selection device is used to select pixels in the pixel array.
[0079] It should be noted that for each pixel component in each pixel portion, some devices are set, for example, a transmission gate. When the pixel component is divided into two sub-pixel components, each divided sub-pixel component is provided with its own transmission gate; and some devices are shared between pixel portions, such as an amplifier device, a reset device, etc. In this article, a black dot and a frame together represent a device in the figure. The pixel device including the reset device, the dual conversion device, the row selection device and the amplifier device can be shared by at least two photodiodes.
[0080] In one possible implementation, the pixel structure also includes an amplifier device, a reset device, a dual conversion device and / or a row selection device; the amplifier device, the reset device, the dual conversion device and / or the row selection device are all arranged in the cross isolation or the peripheral isolation; or, a part of the amplifier device, the reset device, the dual conversion device and / or the row selection device is arranged in the sub-pixel isolation, and the rest of the amplifier device, the reset device, the dual conversion device and / or the row selection device is arranged in the cross isolation or the peripheral isolation.
[0081] Herein, some of the reset devices, dual conversion gain devices, amplifier devices, or row selection devices may be fabricated from different wafers and combined with the wafer including the photodiodes, transfer gate devices, and floating diffusion nodes.
[0082] In one possible implementation, there is no row selection device. In one possible implementation, there is no dual conversion gain device. That is, in one implementation, the pixel structure includes a photodiode, a floating diffusion node, a transmission gate, an amplifier device, and a reset device. In another implementation, the pixel structure includes at least one of a photodiode, a floating diffusion node, a transmission gate, an amplifier device, a reset device, a row selection device, and a dual conversion gain device.
[0083] In one possible implementation, the PD is made of an n-type doped layer, and the pixel-to-pixel isolation (cross isolation) is made of a p-type doped layer; in some cases, the PD can be made of a p-type doped layer, and the pixel-to-pixel isolation can be made of an n-type doped layer.
[0084] In a possible implementation, the transmission gates of the first pixel component are arranged around the center of the array, so that the transmission gates are close to the floating diffusion nodes, which facilitates the transmission of signal charges. In addition, the shapes of the transmission gates can be the same or different, and the embodiments of the present application do not limit this.
[0085] In a possible implementation, the pixel structure is disposed on a substrate, and at least one of the transfer gates is embedded in the substrate, so that a higher full well capacity can be achieved.
[0086] In one possible implementation, the amplifier device and the dual conversion device are placed close to the active area of the floating diffusion node surrounded by the transmission gate in the pixel structure, and the parasitic capacitance of the wiring between the gate of the amplifier device and the floating diffusion node is small. In addition, the active area of the source of the dual conversion device is shared with the active area of the floating diffusion node. This configuration also helps to reduce the capacitance of the floating diffusion node, thereby improving the conversion gain.
[0087] In addition, if Figure 5 As shown, each of the sub-pixel components is provided with a transmission gate, and the four pixel components are four first pixel components, and the structures of the four first pixel components are the same. That is to say, all the photodiodes included in the pixel structure can be the same, which is more convenient to implement and can have a more uniform full well capacity. However, it should be understood that Figure 5 This is just an exemplary configuration of the pixel structure. The four pixel components may include only one first pixel component, that is, only one pixel component is divided into two sub-pixel components, and the other three pixel components remain undivided. The number of first pixel components should be determined according to actual needs. In addition, the photodiodes included in the pixel structure may be the same or different, and the embodiments of the present application are not limited to this.
[0088] It should be noted that the center of the array generally refers to the substantial center of the array. For example, the position of the floating diffusion node 120 may be shared among the four pixel components 1101 in the array, and may include but is not limited to the geometric center of the array.
[0089] According to the pixel structure provided by the embodiment of the present application, since the first pixel component is divided into a pair of sub-pixel components by isolating the sub-pixels extending outward from the center of the array to the periphery of the first pixel component in one direction, the phase difference of the pair of sub-pixel components can be obtained, thereby realizing the PDAF function (including the horizontal AF function and the vertical AF function). In addition, the floating diffusion node is arranged at the center of the array, so that the active area of the floating diffusion node is shared between the pixel components, thereby reducing the total amount of the floating diffusion node, thereby reducing the capacitance of the floating diffusion node. Since the capacitance of the floating diffusion node is inversely proportional to the CG, the CG is improved, and while ensuring the enhanced PDAF function, a higher SNR is obtained through the improved CG.
[0090] Figure 6 Shows Figure 5 A cross-sectional view of a pixel portion shown in the pixel structure of FIG. Figure 6Taking only one pixel as an example, Figure 5 Other pixel portions in the Figure 6 For the sake of brevity, the same structure as shown in the figure will not be described in detail in detail in other pixel parts.
[0091] Combination Figure 5 and Figure 6 , the pixel part includes deep area and shallow area according to depth. In this paper, depth refers to the Figure 5 , so in the direction perpendicular to the display Figure 5 These two regions are not seen in Figure 6 The cross-sectional view of FIG. Figure 6 , the deep region may refer to a region close to the microlens, and the shallow region may refer to a region far from the microlens. Specifically, the deep region may refer to a deep p-well, and the shallow region may refer to a shallow p-well, such as Figure 6 shown.
[0092] In addition to the deep area and the shallow area, a peripheral area 130 and a cross area 140 are also provided for the pixel structure 100. Figure 5 As shown, the peripheral area 130 refers to the area defined by the dotted line, and the intersection area 140 refers to the area between two pixel components, which is schematically shown by the cross-connected solid line. The periphery of the four pixel parts is the peripheral area 130 with the peripheral isolation, and the intersection area 140 that divides the pixel structure into four pixel parts 110 is provided with a cross isolation. Figure 6 As shown, both the peripheral isolation and the cross isolation extend into the shallow area, and the sub-pixel isolation (such as Figure 6 In this article, preventing the sub-pixel isolation from extending into the shallow area is beneficial to obtaining an overflow path, as described below.
[0093] As mentioned above, both the peripheral area and the intersection area are provided with corresponding isolation, that is, the peripheral area is provided with peripheral isolation, and the intersection area is provided with cross isolation. Figure 6 As shown, there are 5 vertical grids from left to right, the peripheral isolation may refer to the first vertical grid and the fifth vertical grid extending to the shallow area, the cross isolation may refer to the third vertical grid extending to the shallow area, and the sub-pixel isolation may refer to the second vertical grid and the fourth vertical grid not extending to the shallow area.
[0094] Specifically, the deep area may include a deep photoelectric conversion device, such as a deep photodiode (PD); the shallow area may include a shallow photoelectric conversion device, such as a shallow photodiode. On the one hand, the deep PD can play a role in higher quantum efficiency and higher full well capacity. Quantum efficiency is a key indicator for evaluating the effectiveness of converting incident photons into electrons, while full-well capacity (FWC) refers to the maximum number of electrons that a photodiode can store. On the other hand, the shallow PD can play a role in charge transfer and overflow paths, which can transfer photoelectric charges exceeding the full well capacity of one photodiode to another photodiode in the pixel. Therefore, the pixel structure can achieve better performance. It should be noted that the photodiode regions where the pair of shallow photodiodes are located may be different and designed according to actual needs.
[0095] For the above overflow path, in a possible implementation, as Figure 6 As shown, in a shallow area of a first pixel component in a pixel portion, an overflow path is formed between a pair of sub-pixel components in the first pixel portion for charge exchange. The overflow path is used to increase the full well capacity of the first pixel component so that the first pixel component can store more electrons. Specifically, the overflow path can be provided near a floating diffusion node relative to the center of a pair of sub-pixel components, which helps to reduce image delay.
[0096] In one possible implementation, each sub-pixel component in a pair of sub-pixel components includes a photodiode, and the overflow path is a path for transferring photoelectric charges exceeding the full well capacity of the photodiode of one sub-pixel component in the pair of sub-pixel components to the photodiode of the other sub-pixel component in the pair of sub-pixel components. That is, the two photodiodes included in one pixel component store electrons as a whole, and when the electron capacity that one photodiode can accommodate is full, the capacity of the other photodiode can be used to store electrons through the overflow path. For example, in imaging mode, Figure 5 The addition of both PD1 and PD2 shown is necessary. If PD1 is saturated first, since there is an overflow path between PD1 and PD2, the full well capacity of PD1+PD2 becomes the full well capacity of one pixel component. Therefore, one pixel can store more electrons and the full well capacity of one pixel is improved.
[0097] Figure 7 Shown based on Figure 6 Another cross-sectional view of the solid-state imaging device, Figure 7 Other parts of the solid-state imaging device besides the pixel array, such as a wiring layer, are also shown. Figure 7A back-illuminated solid-state imaging device is shown, and it should be noted that the solid-state imaging device may be a front-illuminated solid-state imaging device. Moreover, the depth of the deep trench isolation may be less than the radiation sensitive depth, may be equal to the radiation sensitive depth, or may be greater than the radiation sensitive depth, wherein the radiation sensitive depth refers to the depth at which electromagnetic waves can be converted into photocharges. In addition, the pixel array may be integrated in the first chip, and the control circuit and the logic circuit may be integrated in the second chip.
[0098] Figure 8 Shown include Figure 5 The plan view of a solid-state imaging device with multiple pixel structures is shown, from which a portion of a pixel array in which 4 pixels share a 2*2 architecture can be seen.
[0099] It should be noted that isolation (including sub-pixel isolation, peripheral isolation and cross isolation) can be set in different ways. The shapes and depths of these isolations shown in the figures are for illustrative purposes only and are not limited to the embodiments of the present application.
[0100] Below, these different settings will be described in detail with reference to specific drawings.
[0101] Fig. 9 Different structures of pixel isolation are shown, including peripheral isolation, cross isolation and sub-pixel isolation. Fig.10 Different layout configurations of deep trench isolation are shown. Fig. 9 and Fig.10 To describe pixel isolation. Fig. 9 In the figure, the solid dark bars represent trench isolation and the bars with slashes represent doped layers.
[0102] In one possible implementation, the sub-pixel isolation includes a sub-pixel trench isolation or a sub-pixel p-type doping layer. Trench isolation and doping isolation are different technologies for isolating devices, and have different advantages, and can be selected according to actual needs. Trench isolation can include shallow trench isolation (STI) and deep trench isolation (DTI), where the depth of STI is shallower than that of DTI, and the depth of these trench isolations can be selected according to actual needs. For example, Fig. 9 (A) shows a possible layout configuration of sub-pixels according to an embodiment of the present application. Fig. 9 In (A), the sub-pixel isolation is a sub-pixel p-type doped layer. In this way, better dark performance can be achieved because there is no channel isolation as an additional damage source. Fig. 9 (B) shows another possible layout configuration of sub-pixels according to an embodiment of the present application, in Fig. 9In (B), the sub-pixel isolation is a sub-pixel trench isolation, which is more robust because there is no coverage error of the sub-pixel doping layer.
[0103] In one possible implementation, the sub-pixel isolation includes a sub-pixel channel isolation covered by a sub-pixel p-type doped layer, and this sub-pixel channel isolation is conducive to achieving a balance between dark performance and robust performance. The sub-pixel p-type doped layer is used as a protective layer for sub-pixel channel isolation (e.g., deep trench isolation (DTI)), which is conducive to enhancing dark performance because electrons in the dark current can be neutralized by holes provided by the sub-pixel p-type doped layer. There may be a variety of possible layout configurations. It should be noted that the coverage in this article refers to the sub-pixel channel isolation being completely covered by the sub-pixel p-type doped layer, or the sub-pixel channel isolation being partially covered by the sub-pixel p-type doped layer. Fig. 9 (C) shows another possible layout configuration of sub-pixels according to an embodiment of the present application, in Fig. 9 In (C), the depth of sub-pixel isolation (or intra-pixel trench isolation) is shallower than that of cross isolation (or intra-pixel to pixel isolation). Due to less silicon damage, the shallower sub-pixel trench isolation has better dark performance. Dark performance means that there may be a signal (i.e., dark current) even without illumination. Fig. 9 (D) shows another possible layout configuration of sub-pixels according to an embodiment of the present application. Fig. 9 In (D), there is a grid on the area of the sub-pixel isolation that is beneficial for reducing optical crosstalk. It should be noted that it is also possible to set the grid on top of one sub-pixel isolation instead of on two of the two sub-pixel isolations. In this way, when photons falling on one pixel are mistakenly perceived by other pixels around the pixel, optical crosstalk can be reduced. Fig. 9 (E) shows another possible layout configuration of sub-pixels according to an embodiment of the present application, in Fig. 9 In (E), the depth of the p-well isolation is shallower than that of the DTI (solid dark bars in the figure), i.e., only a shallowly doped layer exists. Since there is no deep pixel-to-pixel isolation, this configuration is more robust and has the advantage of low cost. Fig. 9 (F) shows another possible layout configuration of sub-pixels according to an embodiment of the present application, in Fig. 9 In (F), the peripheral isolation on the boundary of the pixel structure includes the full depth DTI. This enables the performance of the pixel structure to trade off between autofocus function and image quality (such as modulation transfer function), and the full depth DTI does not have the pixel-to-pixel highlight blooming problem.
[0104] In one possible implementation, the sub-pixel trench isolation starts from the center of the array and extends to the peripheral area of the pixel structure, for example, Fig.10 (A) and Fig.10(B) is shown. The difference between the two figures is that the number of pixel components divided into two sub-pixel components is different. In fact, the number can be determined according to actual needs, and the embodiments of the present application do not limit this.
[0105] In a possible implementation, a gap is provided in the sub-pixel channel isolation. Fig.10 (C) shows a sub-pixel isolation (eg, DTI) with a gap. A longer intra-pixel DTI will reduce the optical crosstalk performance, so reducing the length of the intra-pixel DTI can improve the optical crosstalk performance. The length of the gap can be designed according to actual needs.
[0106] In one possible implementation, the sub-pixel trench isolation is provided at a preset distance from the center of the array. On the basis of providing the sub-pixel trench isolation with a gap, the length of the sub-pixel isolation (eg, DTI) can be further reduced, for example, Fig.10 (D) shows each sub-pixel isolation (eg, DTI) having only one side. The preset distance can be designed according to actual needs.
[0107] In one possible implementation, the peripheral isolation includes a peripheral channel isolation covered by a peripheral p-type doped layer, which is conducive to achieving a balance between dark performance and robust performance. The peripheral p-type doped layer is used as a protective layer for the peripheral channel isolation (e.g., DTI), which is conducive to enhancing the dark performance because the electrons in the dark current can be neutralized by the holes provided by the peripheral p-type doped layer. In addition, the cross isolation in the deep area can include a cross channel isolation covered by a p-type doped layer. This configuration of peripheral isolation and cross isolation has been described above. Fig. 9 In this article, the coverage in the peripheral isolation refers to the peripheral channel isolation (for example, Fig. 9 (A) to Fig. 9 (D)) or partially covered by a peripheral p-type doped layer peripheral channel isolation (e.g., Fig. 9 (E) and Fig. 9 (F)), similarly, coverage in cross isolation refers to the complete coverage of the cross trench isolation by the p-type doped layer (e.g., Fig. 9 (A) to Fig. 9 (D)) or partially covered by a p-type doped layer to isolate the cross-channel (e.g., Fig. 9 (E) and Fig. 9 (F)). By isolating the channel covered by a doped layer, a balance between dark performance and robust performance can be achieved.
[0108] In a possible implementation, the depth of the sub-pixel trench isolation is less than the depth of the peripheral trench isolation (for example, Fig. 9 (C)). In another possible implementation, the depth of the sub-pixel trench isolation is equal to the depth of the peripheral trench isolation (for example, Fig. 9 (B) Fig. 9 (D) and Fig. 9 (E)). The peripheral trench isolation is used to isolate one pixel structure from another pixel structure, and the sub-pixel trench isolation is used to isolate one sub-pixel component in one pixel component of the pixel structure from another sub-pixel component, so the depth of the sub-pixel trench isolation should be less than or equal to the depth of the peripheral isolation.
[0109] In a possible implementation, a pair of sub-pixel components have the same shape, that is, two photodiodes included in one pixel component may be the same, which is easy to implement and can have a more uniform full well capacity. It should be noted that the shapes of the two photodiodes included in one pixel component may be different.
[0110] The present application provides various configurations of peripheral isolation, cross isolation and sub-pixel isolation, which can flexibly change the performance of the pixel structure, thereby making a trade-off between autofocus function and image quality.
[0111] In a possible implementation, the pixel structure is rotated by a preset angle relative to an imaging device including the pixel structure. The preset angle and the rotation direction may be predetermined according to actual needs. Fig.11 FIG. 2 shows a rotation diagram of a pixel array including four pixel structures according to an embodiment of the present application. Fig.11 In (A), the pixel array is arranged to be tilted 45 degrees relative to the horizontal direction of the imaging device; Fig.11 (B) has a more general configuration, in which the pixel array is arranged to be inclined at a predetermined angle relative to the horizontal direction of the imaging device. In this article, the horizontal direction of the imaging device may refer to the direction parallel to the horizon when the imaging device is normally placed. It should be noted that the rotated pixel array may also include other numbers of pixel structures, which is not limited to the embodiments of the present application. Rotation can modify the acquisition of omnidirectional autofocus information by the traditional dual-pixel readout method and improve the spatial resolution in the horizontal and vertical directions. The effective spatial resolution is the pixel spacing multiplied by cos(rotation angle). For example, when the rotation angle is 45 degrees, the effective spatial resolution becomes the pixel spacing multiplied by cos(45 degrees).
[0112] In addition to the three different isolation configurations mentioned above, other components in the pixel section except the transfer gate can also be arranged in different ways. This will be combined with Fig.12 Give a description.
[0113] As reference Figure 5 As described, the pixel structure may also include other pixel devices, such as an amplifier device, a reset device, a dual conversion device and / or a row selection device. Fig.12A schematic configuration diagram of a pixel structure according to an embodiment of the present application is shown. Fig.12 (A) shows a case where pixel devices of a pixel structure are placed in a row on a boundary of the pixel structure, that is, in peripheral isolation. Fig.12 (B) shows a case where pixel devices of a pixel structure are placed in rows and columns, ie, in peripheral isolation. Fig.12 (C) shows a situation where some pixel devices of a pixel structure are placed in sub-pixel isolation. Fig.12 (D) shows a case where pixel devices of a pixel structure are placed in two rows, that is, in cross isolation, and in peripheral isolation. Fig.12 (E) shows a pixel structure in which the pixel device is placed between transmissions, i.e., in sub-pixel isolation and cross isolation. These different configurations of pixel devices make the layout design more flexible, so more devices can be placed, thereby providing more functions. In addition, setting pixel devices on the peripheral area can make it easier to transmit electrons, thereby providing relatively small power fluctuations and better stability.
[0114] In one possible implementation, the pixel structure also includes a metal shielding layer that shields at least a portion of the pixel structure from incident light. As described above, since there is an overflow path between a pair of sub-pixel components in a pixel component to ensure a high full well capacity in the imaging mode, the pixel structure may lose the autofocus function when the incident signal is very strong (for example, under high light conditions). That is, since there is an overflow path between PD1 and PD2, when the input signal is strong, PD1 and PD2 can be connected together, and the pixel structure will lose the PDAF function. Therefore, for such a high signal situation, it is effective to shield a portion of a pair of sub-pixels, and even if the incident light is strong, the signal of PD1 or PD2 is not saturated, and the pixel structure still maintains the PDAF function. Fig.13 A schematic configuration diagram of a metal shielding layer of a pixel structure is shown, and a specific shielding area can be designed according to actual needs.
[0115] Fig.14A circuit diagram for a pixel structure according to an embodiment of the present application is shown. A photodiode (PD) converts electromagnetic waves into charges. The charges are selectively transmitted to a floating diffusion node (FD) through a transmission gate (TX). FD is connected to the gate of an amplifying device (AMP), and an output signal (Vout) is transmitted to a signal line through a row-selecting device (SEL). A current source (Icolumn) is connected between SEL and ground. Therefore, if the gates of TX and SEL are turned on, an output signal corresponding to an electrical signal from PD is obtained on the signal line. A reset device (RST) selectively resets the accumulated charge in FD. A dual conversion gain device (DCG) can be connected between RST and FD to achieve a high dynamic range by combining two types of gains. AVSS1 can be grounded or a negative voltage in the range of -5.0V to 0V. In one possible implementation, AVSS1 and AVSS2 are the same, so it is easy to reduce the size of the pixel structure. It should be noted that AVSS2 is in the logic chip, so AVSS2 does not have to be the same as AVSS1. In one possible implementation, AVDD1 and AVDD2 are power supply voltages and can be the same. Similarly, it is easy to reduce the layout size of the pixel structure. It should be noted that AVDD1 and AVDD2 can also be different and can be designed according to different requirements, so that since AVDD2 consumes a lot of current, the pixel circuit is more stable.
[0116] PDAF information can be obtained from calculations of a first signal from one subpixel (PD1) and a second signal from another subpixel (PD2), respectively. In one possible implementation, the signal is obtained by performing correlated double sampling (CDS), which uses the difference between the reset level and the signal level to reduce fixed pattern noise and reset noise.
[0117] The transistor in the embodiment of the present application may be an NMOS device, which has a relatively small resistance when turned on. In a possible implementation, some of RST, DCG, AMP, SEL and TX may be PMOS devices, which is not limited in the present application, and the noise of PMOS devices is lower than that of NMOS devices.
[0118] An example of reading out data frame by frame can be to sequentially read out the pixel charges stored in all pixels in the array through a row selection transistor. However, alternatively, a solid-state imaging device that works in a manner known as event-driven can be implemented by using the pixel structure of the present application, rather than reading out data frame by frame. In an event-driven solid-state imaging device, data can be output asynchronously at any time in response to changes in the intensity of electromagnetic waves incident on the pixel. Specifically, for example, when the pixel charge generated by the electromagnetic wave incident on the pixel and stored in the pixel exceeds a predetermined threshold, data can be output to indicate that the intensity of the electromagnetic wave (or the intensity of the electromagnetic wave combined with the coordinates and time information of the pixel) exceeds the threshold. In one possible implementation, the pixel has a global shutter scheme, and the solid-state imaging device has a full-pixel synchronized electronic shutter function through a voltage domain or a charge domain.
[0119] In one possible implementation, a large capacitor, such as a PN junction capacitor, a MOS capacitor, a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, a polysilicon-insulator-polysilicon (PIP) capacitor, or a dynamic random access memory (DRAM), a magnetoresistive random access memory (MRAM), other types of on-chip memory, or a combination thereof, is electrically connected to a node between the drain of DCG and the source of RST. In high illumination mode, the floating diffusion node is electrically connected to the above capacitor. For example, in high illumination mode, the overflow charge from the photodiode is not discharged, but maintained by using an expanded full well capacity. Compared with the amount of overflow charge, the expanded full well capacity can make the potential change of the floating diffusion node area relatively small. For example, in high illumination mode, the conversion gain becomes smaller. This is achieved by activating a dual conversion gain control signal to be provided to the solid-state imaging device so that the dual conversion gain transistor is turned on. In this case, the dual conversion gain transistor can always be kept in the on state when operating in the high illumination mode.
[0120] like FIG. 15A to FIG. 15D Specifically, one end of the additional capacitor is connected to the node between the drain of DCG and the source of RST, and the other end of the additional capacitor can be grounded, such as Fig.15A The other end of the additional capacitor can be connected to AVDD2, as shown Fig. 15B As shown; the other end of the additional capacitor can be connected to a voltage constant, such as Fig. 15C As shown; the other end of the additional capacitor can be connected to the pulse wave, such as Fig.15D shown.
[0121] An embodiment of the present application further provides an imaging device, comprising a pixel structure according to any of the above embodiments.
[0122] An embodiment of the present application further provides an electronic device, comprising the above-mentioned imaging device.
[0123] The technical effects of the imaging device and the electronic device are similar to the technical effects of the above-mentioned pixel structure and will not be repeated here.
[0124] The terms "a" or "an" are not limited to specifying one or a single element, but rather, the term can be used to refer to multiple elements where appropriate.
[0125] In the embodiments of the present application, expressions such as "exemplary" or "for example" are used to indicate an illustration of an example or instance. In the embodiments of the present application, any embodiment or design described as "exemplary" or "for example" should not be interpreted as being superior to or advantageous over other embodiments or designs. Specifically, the use of "exemplary" or "for example" is intended to present related concepts in a specific way.
[0126] In one or more examples, the functions described may be implemented by hardware, software, firmware, or any combination thereof. If implemented by software, the functions may be stored in or transmitted by a computer-readable medium as one or more instructions or codes and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media corresponding to tangible media (e.g., data storage media), or any communication media that facilitates sending a computer program from one place to another according to a communication protocol, etc. In this way, computer-readable media may generally correspond to (1) non-transient tangible computer-readable storage media, or (2) communication media such as signals or carrier waves. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this application. A computer program product may include a computer-readable medium.
[0127] Finally, it should be noted that the above embodiments are only used to describe the technical solutions of the present invention, but not to limit the present invention. Although the present invention is described in detail in conjunction with the above embodiments, it should be understood by those skilled in the art that the technical solutions described in the above embodiments can still be modified, or certain technical features can be replaced by equivalents, without departing from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A pixel structure comprising 4 pixel components, 4 pixel parts corresponding to the 4 pixel components, and a floating diffusion node; in, The pixel components in the four pixel parts are arranged in a 2*2 array, and each of the pixel components is arranged in a corresponding pixel part; The floating diffusion node is disposed at the center of the array such that an active area of the floating diffusion node is shared among the pixel components; The pixel components include at least one first pixel component, which is divided into a pair of sub-pixel components by sub-pixel isolation, and the sub-pixel isolation extends outward from the center of the array to the periphery of the first pixel component in one direction.
2. The pixel structure according to claim 1, characterized in that: Each of the four pixel portions includes a deep region and a shallow region according to depth; A peripheral isolation is provided in the peripheral area of the pixel structure, and a cross isolation is provided in the cross area which divides the pixel structure into the four pixel parts; The peripheral isolation and the cross isolation both extend into the shallow region, and the sub-pixel isolation does not extend into the shallow region.
3. The pixel structure according to claim 2, characterized in that: The sub-pixel isolation includes a sub-pixel channel isolation or a sub-pixel p-type doping layer.
4. The pixel structure according to claim 2, characterized in that: The sub-pixel isolation includes a sub-pixel channel isolation covered by a sub-pixel p-type doping layer.
5. The pixel structure according to claim 3 or 4, characterized in that: The sub-pixel channel isolation is provided with a gap.
6. The pixel structure according to claim 3 or 4, characterized in that: The sub-pixel trench isolation is disposed at a preset distance from the center of the array.
7. The pixel structure according to any one of claims 2 to 6, characterized in that: The peripheral isolation includes a peripheral trench isolation covered by a peripheral p-type doping layer.
8. The pixel structure according to claim 7, characterized in that: The depth of the sub-pixel trench isolation is less than the depth of the peripheral trench isolation.
9. The pixel structure according to claim 7, characterized in that: The depth of the sub-pixel trench isolation is equal to the depth of the peripheral trench isolation.
10. The pixel structure according to any one of claims 2 to 9, characterized in that: The cross isolation in the deep region includes a cross trench isolation covered by a p-type doped layer.
11. The pixel structure according to any one of claims 2 to 10, characterized in that: In the shallow area of the first pixel component, an overflow path is formed between the pair of sub-pixel components of the first pixel portion to perform charge exchange.
12. The pixel structure according to claim 11, characterized in that: Each sub-pixel component of the pair of sub-pixel components comprises a photodiode; The overflow path is a path for transferring photoelectric charges exceeding the full well capacity of the photodiode of one of the pair of sub-pixel components to the photodiode of the other of the pair of sub-pixel components.
13. The pixel structure according to any one of claims 1 to 12, characterized in that: The pair of sub-pixel components have the same shape.
14. The pixel structure according to any one of claims 1 to 13, characterized in that: The pixel structure is rotated by a preset angle relative to an imaging device including the pixel structure.
15. The pixel structure according to any one of claims 1 to 14, characterized in that: Each of the sub-pixel components is provided with a transmission gate, the four pixel components are four first pixel components, and the four first pixel components have the same structure.
16. The pixel structure according to claim 15, characterized in that: The transfer gates of the first pixel components are arranged around the center of the array.
17. The pixel structure according to claim 15 or 16, characterized in that: The pixel structure is disposed on a substrate, and at least one of the transmission gates is embedded in the substrate.
18. The pixel structure according to claim 15 or 16, further comprising an amplifier device, a reset device, a dual conversion device and / or a row selection device; The amplifier device, the reset device, the dual conversion device and / or the row selection device are all arranged in the cross isolation or the peripheral isolation; or, A portion of the amplifying device, the resetting device, the dual conversion device and / or the row selecting device is arranged in the sub-pixel isolation, and the rest of the amplifying device, the resetting device, the dual conversion device and / or the row selecting device is arranged in the cross isolation or the peripheral isolation.
19. The pixel structure according to any one of claims 1 to 18, further comprising a metal shielding layer, The metal shielding layer shields at least a portion of the pixel structure to protect it from the impact of incident light.
20. An imaging device comprising the pixel structure according to any one of claims 1 to 19.
21. An electronic device comprising the imaging device according to claim 20.