Side wall etching method, field effect transistor and semiconductor process equipment

Abstract

The invention discloses a side wall etching method, a field effect transistor and semiconductor process equipment, and the method comprises the steps: providing a to-be-etched device which comprises a substrate, a grid electrode disposed on the substrate, and a to-be-etched film layer covering the grid electrode and the substrate, the to-be-etched film layer comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer which are sequentially arranged in a stacked mode in the direction away from the substrate, the third semiconductor layer is etched through first etching gas so that etching can be stopped on the surface of the second semiconductor layer, and the second semiconductor layer is etched through second etching gas so that etching can be stopped on the surface of the second semiconductor layer; according to the side wall etching method and the side wall etching device, the etching is stopped on the surface of the first semiconductor layer, so that the third semiconductor layer or the second semiconductor layer can be etched only through one etching step, the third semiconductor layer or the second semiconductor layer does not need to be etched through two etching steps any more, the side wall etching process can be simplified, and the side wall etching efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a sidewall etching method, a field effect transistor and semiconductor process equipment. Background Art

[0002] With the development of semiconductor technology, the length of the gate of field effect transistors is getting smaller and smaller, and the influence of hot carrier effect on the gate is getting greater and greater. In order to reduce the influence of hot carrier effect on the gate, a sidewall is usually formed around the gate. At present, the sidewall is formed by etching the thin film deposited on the gate, and the two etching steps of main etching and over etching are performed on each layer of the thin film. However, when there are many layers of thin films, the etching process of the sidewall will be more complicated, which is not conducive to improving the efficiency of sidewall etching. Summary of the invention

[0003] The invention discloses a sidewall etching method, a field effect transistor and a semiconductor process equipment, so as to simplify the sidewall etching process and improve the sidewall etching efficiency.

[0004] In a first aspect, the present invention discloses a sidewall etching method, comprising: providing a device to be etched, the device to be etched comprising a substrate, a gate arranged on the substrate, and a film layer to be etched covering the gate and the substrate, the film layer to be etched comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked in sequence in a direction away from the substrate; etching the third semiconductor layer using a first etching gas, the first etching gas being used to make an etching selectivity ratio of the third semiconductor layer to the second semiconductor layer greater than or equal to a first preset value, so that the etching stops on the surface of the second semiconductor layer; etching the second semiconductor layer using a second etching gas, the second etching gas being used to make an etching selectivity ratio of the second semiconductor layer to the first semiconductor layer greater than or equal to a second preset value, so that the etching stops on the surface of the first semiconductor layer, so that the first semiconductor layer, the second semiconductor layer and the third semiconductor layer on the side wall of the gate form the sidewall of the gate.

[0005] In some embodiments of the present invention, the first etching gas is used to make the etching selectivity ratio of the third semiconductor layer to the second semiconductor layer greater than or equal to a first preset value and less than or equal to a third preset value.

[0006] In some embodiments of the present invention, the first preset value is 3; the second preset value is 10; and the third preset value is 6.

[0007] In some embodiments of the present invention, the third semiconductor layer includes a silicon oxide layer, the second semiconductor layer includes a silicon nitride layer, and the first etching gas includes a carbon-fluorine gas and an oxygen-containing gas.

[0008] In some embodiments of the present invention, the fluorocarbon gas includes at least hexafluorobutadiene, and the oxygen-containing gas includes at least oxygen; the gas ratio of the hexafluorobutadiene to the oxygen is in the range of 1.5-3.

[0009] In some embodiments of the present invention, the gas flow rate of hexafluorobutadiene is in the range of 20 sccm-80 sccm; and the gas flow rate of oxygen is in the range of 5 sccm-50 sccm.

[0010] In some embodiments of the present invention, the first semiconductor layer includes a silicon oxide layer, the second semiconductor layer includes a silicon nitride layer, and the second etching gas includes a carbon, hydrogen, fluorine gas and an oxygen-containing gas.

[0011] In some embodiments of the present invention, the hydrocarbon-fluorine gas includes at least fluoromethane, and the oxygen-containing gas includes at least oxygen; the gas ratio of the fluoromethane to the oxygen is in the range of 1-3.

[0012] In some embodiments of the present invention, the gas flow rate of fluoromethane is in the range of 50 sccm-200 sccm; the gas flow rate of oxygen is in the range of 40 sccm-80 sccm.

[0013] In some embodiments of the present invention, after the third semiconductor layer is etched using the first etching gas, at least a portion of the second semiconductor layer remains on the top of the gate.

[0014] In some embodiments of the present invention, after the third semiconductor layer is etched using the first etching gas, the thickness of the second semiconductor layer retained on the top of the gate is greater than or equal to 10 nm.

[0015] In a second aspect, the present invention discloses a field effect transistor, which is formed by etching using the sidewall etching method as described in any one of the above items.

[0016] In a third aspect, the present invention discloses a semiconductor process equipment, including a process chamber, an air intake component and a controller, wherein the controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the sidewall etching method as described in any one of the above items is implemented.

[0017] The sidewall etching method, field effect transistor and semiconductor process equipment disclosed in the present invention can stop etching the third semiconductor layer on the surface of the second semiconductor layer because the first etching gas can make the etching selectivity ratio of the third semiconductor layer to the second semiconductor layer greater than or equal to the first preset value; and can stop etching the second semiconductor layer on the surface of the first semiconductor layer because the second etching gas can make the etching selectivity ratio of the second semiconductor layer to the first semiconductor layer greater than or equal to the second preset value. Thus, only one etching step is required to etch the third semiconductor layer or the second semiconductor layer, and two etching steps are no longer required to etch the third semiconductor layer or the second semiconductor layer, thereby simplifying the sidewall etching process and improving the sidewall etching efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0019] Figure 1 The present invention discloses a flow chart of a sidewall etching method.

[0020] Figure 2 The present invention is a schematic diagram of a cross-sectional structure of a device to be etched according to an embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the cross-sectional structure of a device to be etched after etching the third semiconductor layer according to an embodiment of the present invention.

[0022] Figure 4 It is a schematic diagram of the cross-sectional structure of a device to be etched after etching the second semiconductor layer according to an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram of the cross-sectional structure of another device to be etched after etching the third semiconductor layer according to an embodiment of the present invention.

[0024] Figure 6 for Figure 5 The SEM image of the cross-sectional structure of the device to be etched is shown.

[0025] Figure 7 for Figure 5 The SEM image of the partial top-down structure of the device to be etched is shown.

[0026] Figure 8 It is a schematic diagram of the cross-sectional structure of another device to be etched after etching the second semiconductor layer according to an embodiment of the present invention.

[0027] Fig. 9 for Figure 3 The SEM image of the cross-sectional structure of the device to be etched is shown.

[0028] Fig.10 for Figure 4 The SEM image of the cross-sectional structure of the device to be etched is shown.

[0029] Fig.11 A schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] As mentioned in the background art, in order to reduce the influence of hot carrier effect on the gate, a thin film is usually deposited on the gate, and the thin film is etched to form a side wall. At present, the thin films commonly used to form the side wall include a silicon oxide layer, a silicon nitride layer and a silicon oxide layer stacked in sequence in the direction away from the gate. The commonly used side wall etching method is: using carbon tetrafluoride CF4 to perform the main etching on the silicon oxide layer, and using a carbon hydrogen fluorine gas to perform an over-etching on the silicon oxide layer; using carbon tetrafluoride CF4 to perform the main etching on the silicon nitride layer, and using a carbon hydrogen fluorine gas to perform an over-etching on the silicon nitride layer, so as to ensure that the silicon oxide layer and the silicon nitride layer on the top of the gate are etched cleanly, and the silicon oxide layer and the silicon nitride layer on the side wall of the gate form a side wall. However, because the process of etching the silicon oxide layer and the silicon nitride layer includes two etching steps, the overall etching process of the side wall is relatively cumbersome, which is not conducive to improving the side wall etching efficiency.

[0032] Based on this, the present invention discloses a side wall etching scheme, which utilizes a first etching gas to etch a silicon oxide layer and stops the etching on the surface of a silicon nitride layer, and utilizes a second etching gas to etch a silicon nitride layer and stops the etching on the surface of the silicon oxide layer, thereby simplifying the two etching steps of each film layer into one etching step, thereby simplifying the side wall etching process and improving the side wall etching efficiency.

[0033] As an optional implementation of the content disclosed in the present invention, an embodiment of the present invention discloses a sidewall etching method, such as Figure 1 As shown, the method includes:

[0034] S101: providing a device to be etched, the device to be etched comprising a substrate, a gate arranged on the substrate, and a film layer to be etched covering the gate and the substrate, the film layer to be etched comprising a first semiconductor layer, a second semiconductor layer and a third semiconductor layer stacked in sequence in a direction away from the gate.

[0035] In the embodiment of the present invention, Figure 2 As shown, the device to be etched includes a substrate 10, a gate 11 located on the substrate 10, and a film layer 12 to be etched covering the gate 11 and the substrate 10. The film layer 12 to be etched covers the top and sidewalls of the gate 11 and the substrate 10 around the gate 11. In addition, the film layer 12 to be etched includes a first semiconductor layer 121, a second semiconductor layer 122, and a third semiconductor layer 123 which are sequentially stacked in a direction away from the substrate 10.

[0036] S102: Etching the third semiconductor layer using a first etching gas, where the first etching gas is used to make an etching selectivity ratio between the third semiconductor layer and the second semiconductor layer greater than or equal to a first preset value, so that the etching stops at the surface of the second semiconductor layer.

[0037] In the embodiment of the present invention, the third semiconductor layer 123 can be etched by using the first etching gas. Figure 3 As shown, the second semiconductor layer 122 on the top of the gate 11 may be exposed, and a portion of the third semiconductor layer 123 on the sidewall of the gate 11 may be retained.

[0038] Because the first etching gas can make the etching selectivity ratio of the third semiconductor layer 123 to the second semiconductor layer 122 greater than or equal to the first preset value, the etching can be stopped on the surface of the second semiconductor layer 122. Because the first etching gas can stop the etching on the surface of the second semiconductor layer 122, it is not necessary to use two etching steps of main etching and over etching to etch the third semiconductor layer 123, but one etching step to etch the third semiconductor layer 123, thereby simplifying the sidewall etching process and improving the sidewall etching efficiency.

[0039] It should be noted that in this etching step, it is necessary to remove all the third semiconductor layer 123 on the top of the gate 11, and it is also possible to remove a small portion of the second semiconductor layer 122 on the top of the gate 11, but it is necessary to retain most of the second semiconductor layer 122 on the top of the gate 11, or retain all of the second semiconductor layer 122 on the top of the gate 11. If too little of the second semiconductor layer 122 is retained on the top of the gate 11, in the subsequent process of etching the second semiconductor layer 122 on the top of the gate 11, the first semiconductor layer 121 on the top of the gate 11 and even the top of the gate 11, such as the top corner, will be etched away, resulting in damage to the structure of the gate 11, resulting in poor performance stability of the gate 11. In some embodiments, the thickness of the second semiconductor layer 122 retained on the top of the gate 11 is greater than or equal to 10nm.

[0040] S103: Etch the second semiconductor layer using a second etching gas, where the second etching gas is used to make the etching selectivity ratio of the second semiconductor layer to the first semiconductor layer greater than or equal to a second preset value, so that the etching stops on the surface of the first semiconductor layer, so that the first semiconductor layer, the second semiconductor layer and the third semiconductor layer on the side wall of the gate form the side wall of the gate.

[0041] In the embodiment of the present invention, the second semiconductor layer 122 can be etched by using the second etching gas. Figure 4 As shown, the first semiconductor layer 121 on the top of the gate 11 can be exposed, and part of the third semiconductor layer 123 and part of the second semiconductor layer 122 at the sidewall of the gate 11 are retained. The first semiconductor layer 121, the second semiconductor layer 122 and the third semiconductor layer 123 at the sidewall of the gate 11 can form a sidewall of the gate 11, which is used to protect the gate 11 from being affected by the hot carrier effect in the subsequent ion implantation process of the source region and the drain region.

[0042] Because the second etching gas can make the etching selectivity ratio of the second semiconductor layer 122 to the first semiconductor layer 121 greater than or equal to the second preset value, the etching can be stopped on the surface of the first semiconductor layer 121. Because the second etching gas can stop the etching on the surface of the first semiconductor layer 121, it is not necessary to use two etching steps of main etching and over etching to etch the second semiconductor layer 122, but one etching step to etch the second semiconductor layer 122, thereby simplifying the sidewall etching process and improving the sidewall etching efficiency.

[0043] In some embodiments of the present invention, the substrate 10 is a silicon substrate, the gate 11 is a polysilicon gate, the first semiconductor layer 121 is a silicon oxide layer, the second semiconductor layer 122 is a silicon nitride layer, and the third semiconductor layer 123 is a silicon oxide layer. Of course, the present invention is not limited to this. In other embodiments, the first semiconductor layer 121, the second semiconductor layer 122 and the third semiconductor layer 123 can also be other film layers.

[0044] In some embodiments of the present invention, the first etching gas is used to make the etching selectivity ratio of the third semiconductor layer 123 to the second semiconductor layer 122 greater than or equal to the first preset value and less than or equal to the third preset value, so that the etching stops on the surface of the second semiconductor layer 122 while the sidewalls of the retained portion of the third semiconductor layer 123 are smooth sidewalls.

[0045] In some embodiments of the present invention, the first preset value is 3 and the third preset value is 6, that is, the first etching gas can make the etching selectivity ratio of the silicon oxide layer, i.e., the third semiconductor layer 123, and the silicon nitride layer, i.e., the second semiconductor layer 122 greater than or equal to 3 and less than or equal to 6.

[0046] It should be noted that if the etching selectivity of the third semiconductor layer 123 to the second semiconductor layer 122 is less than 3, it cannot be guaranteed that the etching stops on the surface of the second semiconductor layer 122, and the structure of the first semiconductor layer 121 and the gate 11 at the bottom thereof will be damaged. If the etching selectivity of the third semiconductor layer 123 to the second semiconductor layer 122 is greater than 6, the etching rate of the third semiconductor layer 123 close to the second semiconductor layer 122 will be lower than the etching rate of the third semiconductor layer 123 far from the second semiconductor layer 122, resulting in a portion of the third semiconductor layer 123 close to the second semiconductor layer 122 being retained to form Figure 5 and Figure 6 The protrusions shown, when viewed from the top of the gate 11 downward, will form Figure 7 The wall surrounding the gate 11 is shown, and after etching the second semiconductor layer 122, as shown in Figure 8 As shown, the wall will not be eliminated, which greatly affects the smoothness of the side wall of the gate 11, and further affects the performance of the manufactured semiconductor devices such as transistors.

[0047] It should also be noted that, although when difficult-to-eliminate substances appear at the interface during the etching of two different substances, the difficult-to-etch walls standing at the interface can be knocked down by adding a large amount of inert gas with strong physical bombardment ability, this will damage the morphology of other locations of the device, causing the morphology of the side walls to be uneven and discontinuous, affecting the performance of the device.

[0048] In some embodiments of the present invention, by making the etching selectivity ratio of the third semiconductor layer 123 to the second semiconductor layer 122 greater than or equal to 3 and less than or equal to 6, it is possible to ensure that the etching stops on the surface of the second semiconductor layer 122 to avoid damaging the first semiconductor layer 121 and the gate 11 at the bottom of the second semiconductor layer 122, and the third semiconductor layer 123 at the side wall of the gate 11 is Figure 3 or Fig. 9 Continuous smooth sidewalls shown.

[0049] In some embodiments of the present invention, the first etching gas includes a carbon fluorine gas and an oxygen-containing gas, wherein the etching selectivity of the third semiconductor layer 123 to the second semiconductor layer 122 can be controlled by controlling the gas ratio of the carbon fluorine gas to the oxygen-containing gas in the first etching gas.

[0050] In some embodiments of the present invention, the fluorocarbon gas includes at least hexafluorobutadiene C4F6, and the oxygen-containing gas includes at least oxygen O2. In addition, the gas ratio of hexafluorobutadiene to oxygen is in the range of 1.5-3, so that the etching selectivity ratio of the third semiconductor layer 123 to the second semiconductor layer 122 is greater than or equal to 3 and less than or equal to 6. Of course, the present invention is not limited to this, and in other embodiments, the fluorocarbon gas may also include carbon tetrafluoride CF4 and the like.

[0051] In some embodiments of the present invention, the gas flow rate of hexafluorobutadiene is in the range of 20 sccm-80 sccm; the gas flow rate of oxygen is in the range of 5 sccm-50 sccm. Of course, the present invention is not limited thereto. In practical applications, the gas flow rates of hexafluorobutadiene and oxygen can be adjusted according to demand, as long as the ratio thereof is kept in the range of 1.5-3.

[0052] It should be noted that, because CF4 has almost no selectivity for the silicon oxide layer and the silicon nitride layer, it cannot be guaranteed that the etching stops on the surface of the silicon nitride layer, i.e., the second semiconductor layer 122, which can easily cause damage to the gate 11. C4F6 not only has a high etching rate for silicon oxide, but also can adjust the etching selectivity ratio of silicon oxide, i.e., the third semiconductor layer 123, and silicon nitride layer, i.e., the second semiconductor layer 122 by adjusting the gas ratio of C4F6 and O2. In addition, the O ions dissociated from O2 can react with the C ions in C4F6 to generate gases such as CO and CO2, so that C4F6 releases more F ions to etch silicon oxide, which can better remove the walls at the interface. In addition, the introduction of an appropriate amount of O2 can also remove polymers adsorbed on the surface of the material that have almost no help for etching, can reduce the shielding of the polymer on the silicon oxide at the interface, and can better remove the walls at the interface.

[0053] Of course, the present invention is not limited to this. In other embodiments, the first etching gas may also include an inert gas, which includes helium or argon, so as to control the etching rate through the inert gas and optimize the etching uniformity. In some embodiments, the gas flow rate of the inert gas ranges from 100 sccm to 400 sccm.

[0054] In some embodiments of the present invention, when the third semiconductor layer 123 is etched using the first etching gas, the etching chamber pressure may be 5mTorr-50mTorr, the upper RF power may be 500W-2000W, and the lower RF power may be 200W-800W.

[0055] Among them, using a lower etching chamber pressure helps to improve the lateral etching ability of the first etching gas; using a higher upper RF power helps to increase the etching rate of the third semiconductor layer 123; using a lower lower electrode power can allow sufficient third semiconductor layer 123 to be retained on the side wall of the gate 11 to prevent the side wall formed subsequently from being too short and unable to protect the gate 11.

[0056] In some embodiments of the present invention, the second preset value is greater than or equal to 10, that is, the second etching gas can make the etching selectivity ratio of the silicon nitride layer, i.e., the second semiconductor layer 122, to the silicon oxide layer, i.e., the first semiconductor layer 121, greater than or equal to 10. Based on this, it can not only ensure that the etching stops on the surface of the first semiconductor layer 121 to avoid damaging the gate 11 at the bottom of the first semiconductor layer 121, but also make the third semiconductor layer 123 and the second semiconductor layer 122 at the side wall of the gate 11 be Figure 4 or Fig.10 Continuous smooth sidewalls shown.

[0057] In some embodiments of the present invention, the second etching gas includes a carbon, hydrogen, fluorine gas and an oxygen-containing gas. The etching selectivity ratio of the silicon nitride layer, i.e., the second semiconductor layer 122, and the silicon oxide layer, i.e., the first semiconductor layer 121, can be controlled by controlling the gas ratio of the carbon, hydrogen, fluorine gas to the oxygen-containing gas in the second etching gas.

[0058] In some embodiments of the present invention, the hydrocarbon-fluorine gas includes at least fluoromethane CH3F, and the oxygen-containing gas includes at least oxygen O2. Moreover, the gas ratio of fluoromethane to oxygen is in the range of 1-3, so that the etching selectivity of the silicon nitride layer, i.e., the second semiconductor layer 122, and the silicon oxide layer, i.e., the first semiconductor layer 121, is greater than or equal to 10.

[0059] Of course, the present invention is not limited thereto, and in other embodiments, the carbon-hydrogen-fluorine gas may also include CH2F2 or CHF3, etc. In other embodiments, the second etching gas may also include a carbon-fluorine gas such as CF4 and an oxygen-containing gas.

[0060] It should be noted that after CH3F is ionized, a large amount of CHx will be decomposed. Although CHx can easily react with -O-Si- to form a high molecular polymer -Si-O-CHx, because the bond energy of the Si-N bond is much lower than the bond energy of the Si-O bond, the Si-N bond in the silicon nitride layer is more easily interrupted by the high molecular polymer -Si-O-CHx, so that the silicon nitride layer, i.e., the second semiconductor layer 122, can be etched away. On the contrary, the high molecular polymer -Si-O-CHx will adhere to the surface of the silicon oxide layer, but will not react with the silicon oxide layer, thereby preventing the first semiconductor layer 121 at the bottom of the second semiconductor layer 122 from being etched away. In addition, because the H ions decomposed by CH3F after ionization promote the etching of the silicon nitride layer, i.e., the second semiconductor layer 122, and do not generate by-products, the silicon nitride layer, i.e., the second semiconductor layer 122, can be etched away faster.

[0061] In some embodiments of the present invention, the gas flow rate of fluoromethane is in the range of 50sccm-200sccm; the gas flow rate of oxygen is in the range of 40sccm-80sccm. Of course, the present invention is not limited thereto. In practical applications, the gas flow rates of fluoromethane and oxygen can be adjusted according to demand, as long as the ratio thereof is kept in the range of 1-3.

[0062] In some embodiments of the present invention, when etching the second semiconductor layer 122 with the second etching gas, the etching chamber pressure may be 50mTorr-100mTorr, the upper RF power may be 800W-1500W, and the lower RF power may be 50W-200W.

[0063] Among them, using a lower etching chamber pressure is helpful to improve the etching selectivity ratio of the second semiconductor layer 122 to the first semiconductor layer 121; using a higher upper RF power is helpful to improve the etching rate of the second semiconductor layer 122; using a lower lower electrode power can make the second semiconductor layer 122 at the side wall of the gate 11 form a full sidewall morphology to avoid the side wall being too short and unable to protect the gate 11.

[0064] As another optional implementation of the content disclosed in the present invention, an embodiment of the present invention further discloses a field effect transistor, which is formed by etching using the sidewall etching method disclosed in any of the above embodiments.

[0065] like Figure 2 As shown, the field effect transistor before etching includes a substrate 10, a gate 11 located on the substrate 10, and a film layer 12 to be etched covering the gate 11 and the substrate 10. Figure 4 As shown, the field effect transistor after etching exposes the first semiconductor layer 121 on the top of the gate 11, and retains part of the third semiconductor layer 123 and part of the second semiconductor layer 122 at the sidewall of the gate 11. The first semiconductor layer 121, the second semiconductor layer 122 and the third semiconductor layer 123 at the sidewall of the gate 11 constitute the sidewall of the gate 11.

[0066] As another optional implementation of the content disclosed in the present invention, an embodiment of the present invention further discloses a semiconductor process equipment, which includes but is not limited to an inductively coupled plasma etching equipment.

[0067] like Fig.11As shown, the semiconductor process equipment includes a process chamber 6, an air inlet assembly 7, an upper RF power supply SRF, a lower RF power supply BRF and a controller (not shown in the figure), wherein the controller is used to control the gas flow rate and chamber pressure of the process chamber 6, as well as the upper RF power output by the upper RF power supply SRF and the lower RF power output by the lower RF power supply BRF, etc., and the controller includes a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the sidewall etching method disclosed in any of the above embodiments is implemented.

[0068] Among them, the gas inlet assembly 7 is used to introduce etching gas, etc. into the process chamber 6. The upper RF power source SRF is electrically connected to the upper electrode 1 in the process chamber 6 through an adapter. The upper electrode 1 includes an outer coil and an inner coil of an inductive coupling coil, which are used to load the upper RF power to the outer coil and the inner coil. The outer coil and the inner coil are coupled to the process chamber 6 through a dielectric window 2 to ionize the gas in the process chamber 6 into a plasma 3. The lower RF power source BRF is electrically connected to the base 4 through an adapter to apply the lower RF power to the base 4. The base 4 is used to carry the device 5 to be etched. The structure of the device 5 to be etched can be as follows Figure 2 shown.

[0069] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. A sidewall etching method, characterized in that: include: A device to be etched is provided, the device to be etched comprising a substrate, a gate disposed on the substrate, and a film layer to be etched covering the gate and the substrate, the film layer to be etched comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence in a direction away from the substrate; Etching the third semiconductor layer using a first etching gas, wherein the first etching gas is used to make an etching selectivity ratio between the third semiconductor layer and the second semiconductor layer greater than or equal to a first preset value, so that the etching stops at a surface of the second semiconductor layer; The second semiconductor layer is etched using a second etching gas, and the second etching gas is used to make the etching selectivity ratio of the second semiconductor layer to the first semiconductor layer greater than or equal to a second preset value, so that the etching stops on the surface of the first semiconductor layer, so that the first semiconductor layer, the second semiconductor layer and the third semiconductor layer on the side wall of the gate form the side wall of the gate.

2. The method according to claim 1, characterized in that The first etching gas is used to make the etching selection ratio of the third semiconductor layer to the second semiconductor layer greater than or equal to a first preset value and less than or equal to a third preset value.

3. The method according to claim 2, characterized in that The first preset value is 3; the second preset value is 10; and the third preset value is 6.

4. The method according to any one of claims 1 to 3, characterized in that: The third semiconductor layer includes a silicon oxide layer, and the second semiconductor layer includes a silicon nitride layer; The first etching gas includes a carbon-fluorine gas and an oxygen-containing gas.

5. The method according to claim 4, characterized in that The fluorocarbon gas at least includes hexafluorobutadiene, and the oxygen-containing gas at least includes oxygen; The gas ratio of the hexafluorobutadiene to the oxygen is in the range of 1.5-3.

6. The method according to claim 5, characterized in that The gas flow rate of hexafluorobutadiene is in the range of 20 sccm-80 sccm; the gas flow rate of oxygen is in the range of 5 sccm-50 sccm.

7. The method according to any one of claims 1 to 3, characterized in that: The first semiconductor layer includes a silicon oxide layer, and the second semiconductor layer includes a silicon nitride layer; The second etching gas includes a carbon, hydrogen, fluorine gas and an oxygen-containing gas.

8. The method according to claim 7, characterized in that The hydrocarbon-fluorine gas at least includes fluoromethane, and the oxygen-containing gas at least includes oxygen; The gas ratio of the fluoromethane to the oxygen is in the range of 1-3.

9. The method according to claim 8, characterized in that The gas flow rate of the fluoromethane is in the range of 50 sccm-200 sccm; the gas flow rate of the oxygen is in the range of 40 sccm-80 sccm.

10. The method according to claim 1, characterized in that After the third semiconductor layer is etched by using the first etching gas, at least a portion of the second semiconductor layer remains on the top of the gate.

11. The method according to claim 10, characterized in that After the third semiconductor layer is etched by using the first etching gas, the thickness of the second semiconductor layer retained on the top of the gate is greater than or equal to 10 nm.

12. A field effect transistor, characterized in that: The field effect transistor is formed by etching using the sidewall etching method according to any one of claims 1 to 11.

13. A semiconductor process equipment, comprising a process chamber, an air intake assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the sidewall etching method according to any one of claims 1 to 11 is implemented.

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