FPGA test case logic resource expansion method and device, equipment, medium and product

Abstract

The invention relates to the technical field of FPGAs, and discloses an FPGA test case logic resource expansion method and device, equipment, a medium and a product, and the method comprises the steps: obtaining a native test case corresponding to a to-be-tested FPGA chip; copying the native test case to obtain a plurality of copied test cases, and taking the native test case and the plurality of copied test cases as initial test cases; and based on the initial test case, generating an expanded target test case. According to the method and the device, the test case can be expanded only on the basis of the original native test case without adopting a transplantation mode, so that the formed test case resource is several times, even dozens and hundreds of times of that of the native test case, and the pin is almost as much as that of the native test case; in this way, the problem that resources are insufficient due to the fact that the use number of the pins is increased synchronously is solved, and therefore the logic resource capacity of the test case is remarkably increased.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a method, device, equipment, medium and product for expanding logic resources of FPGA test cases. Background Art

[0002] FPGA (Field Programmable Gate Array, FPGA for short) is an integrated circuit that can be programmed at any time, and the effective use of FPGA chips is based on the maturity, ease of use and stability of its development tools. At present, the commonly used development tools for FPGA chips are EDA (Electronic design automation, EDA for short) software, which can convert the user's design ideas into the actual functions of the chip, and can assist in the design, simulation and optimization of digital logic circuits in FPGA.

[0003] However, due to the increasing demand for testing FPGA chips, the testing process of EDA software is no longer limited to unit testing. Test engineers generally accumulate a large number of different types of test cases, hoping that these test cases can be applied to the testing process of FPGA chips under development to more comprehensively verify the functions of FPGA chips.

[0004] However, the migration process of this test case is usually limited by many resources such as FPGA capacity, memory blocks, DSP (Digital Signal Processor, which is the computing unit inside the FPGA) blocks, package pins, etc. As long as one item exceeds the limitation of the target device, it means the failure of the migration process. Among these resource limitations, the most easily encountered is the limitation of pin resources, which will directly lead to the inability to fully utilize the logic resources in the test case, resulting in the inability to fully test the FPGA chip function. Summary of the invention

[0005] In view of this, the present invention provides a method, device, equipment, medium and product for expanding logic resources of FPGA test cases to solve the problem in the prior art that the expansion of test cases is limited by pin resources.

[0006] In a first aspect, the present invention provides a method for expanding logic resources of an FPGA test case, the method comprising:

[0007] Get the native test case corresponding to the FPGA chip to be tested;

[0008] Copy the original test case to obtain multiple copied test cases, and use the original test case and the multiple copied test cases as initial test cases;

[0009] Generate expanded target test cases based on the initial test cases.

[0010] In this embodiment, there is no need to adopt the transplantation method, that is, there is no need to transplant test cases of other different types and devices to the FPGA chip to be tested for testing the FPGA chip to be tested. The test case expansion can be achieved only on the basis of the original native test case. The test case resources formed in this way are several times, even dozens or hundreds of times that of the native test case, while the pins are almost the same as the native test case. In this way, the problem of insufficient resources while the number of pins used increases synchronously is solved, thereby achieving a significant increase in the logical resource capacity of the test case.

[0011] In an optional implementation, generating an expanded target test case based on the initial test case includes:

[0012] All initial test cases are cascaded in sequence to obtain the target test cases.

[0013] In this embodiment, multiple copies of the native test case are instantiated, and input and output signal cascading is implemented to increase the logic resources of the test case without increasing or increasing the device pins as little as possible, thereby forming a test case with higher complexity that can activate more FPGA logic and resources, thereby effectively improving the testing efficiency of FPGA logic resources and EDA tools.

[0014] In an optional implementation, generating an expanded target test case based on the initial test case includes:

[0015] Add a linear feedback shift register and a wrapper to each initial test case to generate an intermediate test case that corresponds one-to-one with the initial test case;

[0016] All intermediate test cases are connected in parallel to obtain the target test case.

[0017] In this embodiment, the wiring delay between the source register and the destination register is effectively shortened, and the timing is greatly optimized.

[0018] In an optional implementation, the input data is copied using a linear feedback shift register and passed to the input of each initial test case in turn through a shift operation; the output of each initial test case is passed to a wrapper in turn, and finally the highest bit in the wrapper is used as the output of the target test case.

[0019] This embodiment not only realizes the expansion of use case resources, but also satisfies the condition that IO resources remain basically unchanged, and also optimizes the timing.

[0020] In an optional implementation, all initial test cases are sequentially cascaded to obtain target test cases, including:

[0021] A constraint mark is added between the initial test case and the initial test case connection, and the constraint mark is used to prevent the signal node from being optimized.

[0022] The constraint marking in this embodiment ensures that these signal nodes will be retained and not optimized during the synthesis phase, thereby facilitating comprehensive testing of the FPGA.

[0023] In an optional implementation, when the native test case is one-dimensional data, the native test case is expanded into two-dimensional data.

[0024] This extension can make data management clearer, thus ensuring the correct execution of multi-level cascades.

[0025] In a second aspect, the present invention provides an FPGA test case logic resource expansion device, the device comprising:

[0026] The acquisition module is used to obtain the native test cases corresponding to the FPGA chip to be tested;

[0027] A copy module is used to copy the original test case, obtain multiple copy test cases, and use the original test case and the multiple copy test cases as the initial test case;

[0028] The expansion module is used to generate expanded target test cases based on the initial test cases.

[0029] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the FPGA test case logic resource expansion method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0030] In a fourth aspect, the present invention provides a computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the FPGA test case logic resource expansion method of the first aspect or any corresponding embodiment thereof.

[0031] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the FPGA test case logic resource expansion method of the above-mentioned first aspect or any corresponding embodiment thereof.

[0032] It should be noted that the FPGA test case logic resource expansion device, computer device and computer-readable storage medium provided by the present invention correspond to the above-mentioned FPGA test case logic resource expansion method. Therefore, for the beneficial effects of the FPGA test case logic resource expansion device, computer device and computer-readable storage medium, please refer to the description of the corresponding beneficial effects of the FPGA test case logic resource expansion method above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 It is a flow chart of a method for expanding logic resources of FPGA test cases according to an embodiment of the present invention;

[0035] Figure 2 is a code schematic diagram of a certain use case implementation fragment according to an embodiment of the present invention;

[0036] Figure 3 is a schematic diagram of one of the expansion methods according to an embodiment of the present invention;

[0037] Figure 4 is a schematic diagram of another expansion method according to an embodiment of the present invention;

[0038] Figure 5 is a schematic diagram of a code implemented by a shift operation according to an embodiment of the present invention;

[0039] Figure 6 is another schematic diagram of a code implemented by a shift operation according to an embodiment of the present invention;

[0040] Figure 7 is a schematic diagram of code for the overall framework connection according to an embodiment of the present invention;

[0041] Figure 8 is a structural block diagram of an FPGA test case logic resource expansion device according to an embodiment of the present invention;

[0042] Fig. 9 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0044] A product provider of FPGA chips generally has a rich set of test cases. Currently, many websites also provide some test benchmarks for everyone to use, but the common feature of these test cases is that they occupy fewer logical resources. If the resource usage of the expansion case is to be expanded, the conventional method is to copy the case multiple times and then expand it in parallel to obtain a test case with several times the original design resources. Obviously, the method of parallel expansion of resources will be limited by the number of device pins, so that after the pins are used up, the logic resources are only used by a fraction or even a few tens of percent. Therefore, in the expansion of FPGA test cases, the limitation of the number of pins is obvious and prominent. For example, if a certain FPGA chip has 100 available pins, and a test case requires more than 100 pins, the test case will fail during the wiring process. Simply removing a few pins will affect the function of the test case and the demand for other resources, thereby reducing the quality of the test case.

[0045] Therefore, in the current related technologies, it is difficult to ensure that the resources can be expanded based on the original test cases and that they can be successfully laid out and routed. This is a major problem that EDA software testing work must face.

[0046] In view of this, according to an embodiment of the present invention, an embodiment of an FPGA test case logic resource expansion method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0047] In this embodiment, a method for expanding logic resources of FPGA test cases is provided, which can be executed by devices such as servers, terminals, and mobile terminals. Figure 1 is a flow chart of a method for expanding logic resources of an FPGA test case according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0048] Step S101, obtaining a native test case corresponding to the FPGA chip to be tested. The native test case may be a test case provided when the FPGA chip to be tested leaves the factory.

[0049] Step S102, copy the native test case to obtain multiple copied test cases, and use the native test case and the multiple copied test cases together as initial test cases.

[0050] Step S103, based on the initial test case, an expanded target test case is generated. Specifically, the expansion method can be to cascade all the initial test cases in sequence, so as to obtain the cascaded target test case, thereby expanding the test case; or to add a shift register before and after each initial test case, use a linear feedback shift register to "copy" the data input, and pass it to the input end of each initial test case in sequence through a shift operation, thereby expanding the test case.

[0051] In this embodiment, there is no need to adopt the transplantation method, that is, there is no need to transplant test cases of other different types and devices to the FPGA chip to be tested for testing the FPGA chip to be tested. The test case expansion can be achieved only on the basis of the original native test case. The test case resources formed in this way are several times, even dozens or hundreds of times that of the native test case, while the pins are almost the same as the native test case. In this way, the problem of insufficient resources while the number of pins used increases synchronously is solved, thereby achieving a significant increase in the logical resource capacity of the test case.

[0052] The approach of the present invention fully complies with the basic functions and logic requirements of the original design, and the logic resource capacity of the use case generated later is approximately the amount of native resources multiplied by the number of connections. Therefore, under normal circumstances, use cases with hundreds of KB or even several MB of logic resources can be obtained, and the logic resources are very rich.

[0053] In addition, in FPGA chip design, it is necessary to identify the cascaded signals and cascade the resources with obvious diffusion of logic and data. Randomly cascading a group of signals may not necessarily increase the logic resources.

[0054] For the output signals of the initial test cases, they are either cascaded or output to independent signals (not participating in cascading). In other words, the functional coverage and logic resource multiplication of the original design can be achieved without cascading all the output signals.

[0055] The use of the present invention to obtain large-capacity test cases is not effective for all native use cases. It is mainly effective for use cases used for data transformation in OpenCores, such as encryption and decryption of data. For example, some industrial control use cases cannot achieve the doubling of logic resources because they do not have significant logical diffusion. In the past, there was almost no particularly effective way to implement use cases with more than 50K logic resources. Although the present invention has clear ideas, simple and convenient implementation, it is extremely practical.

[0056] The idea of ​​input and output cascade is reflected in Figure 2 In the box shown, Figure 2 Shows a snippet of the implementation of a use case.

[0057] In some optional implementations, generating an expanded target test case based on the initial test case includes:

[0058] All initial test cases are cascaded in sequence to obtain the target test cases.

[0059] That is, copy the original test case multiple times and arrange them in sequence, that is, serial expansion, refer to Figure 3 As shown, the output of the previous initialization test case is connected to the input of the next initialization test case to form a connection between multiple test cases.

[0060] For multiple instantiations of native test cases, input and output signal cascades are implemented to increase the logic resources of the test cases without increasing or minimizing the number of device pins, forming test cases with higher complexity that can activate more FPGA logic and resources, thereby effectively improving the test efficiency of FPGA logic resources and EDA tools. It is also possible to effectively generate large-capacity or even extra-large-capacity test cases without being limited by FPGA chip pins, making it possible to generate test cases with specific (generally hundreds of K LUTs) logic resource capacity when testing and verifying EDA software.

[0061] In some optional implementations, generating an expanded target test case based on the initial test case includes:

[0062] A linear feedback shift register and a wrapper are added to each initial test case to generate an intermediate test case that corresponds one-to-one to the initial test case.

[0063] All intermediate test cases are connected in parallel to obtain the target test case.

[0064] For the previous implementation, the expansion of the use case resources is completed under the premise of solving the problem of insufficient pin resources. However, when the number of cascades continues to increase, the routing delay may also increase synchronously, which is not conducive to timing analysis. In order to optimize the timing, in this embodiment, refer to Figure 4 As shown, a linear feedback shift register is added to the front end of each initial test case, and a wrapper (the wrapper contains a shift register) is added to the back end of each initial test case, which effectively shortens the routing delay between the source register and the destination register and greatly optimizes the timing.

[0065] In some optional implementations, the input data is copied using a linear feedback shift register and sequentially transferred to the input end of each initial test case through a shift operation; the output of each initial test case is sequentially transferred to a wrapper, and finally the highest bit in the wrapper is used as the output of the target test case. The input data is the test data for inputting the FPGA chip to be tested.

[0066] The specific implementation method is as follows: use the linear feedback shift register to "copy" the data input and pass it to the input end of each initial test case in turn through the shift operation. The specific implementation process refers to Figure 5 shown.

[0067] At the same time, the output of each initial test case is passed to the shift register in the wrapper in turn, and finally the highest bit is sent out. For the specific implementation process, refer to Figure 6 As shown. The implementation method of the overall framework connection refers to Figure 7 shown.

[0068] Compared with the cascade implementation method, this embodiment not only realizes the expansion of use case resources, but also satisfies the condition that IO resources remain basically unchanged, and also optimizes the timing.

[0069] In some optional implementations, all initial test cases are sequentially cascaded to obtain target test cases, including:

[0070] A constraint mark is added between the initial test case and the initial test case connection, and the constraint mark is used to prevent the signal node from being optimized.

[0071] For expanding test cases in a cascaded manner, the key operation is to "connect the output of the previous test case to the input of the next test case". For EDA tools, based on the basic concept of saving chip logic resources, completely identical repeated modules are highly likely to be optimized in the comprehensive link of FPGA design, and thus fail to meet the demand for expanding resources. This is also the reason why parallel expansion is often used in this field; therefore, it is necessary to establish an unoptimizable node group to make it a "link" between a previous test case and a subsequent test case. In this regard, for general EDA tools, a constraint instruction of a "keep" node is provided for each initial test case, which is also the constraint mark in this embodiment, to ensure that these signal nodes will be retained and not optimized during the comprehensive link, which is conducive to the comprehensive test of FPGA. Based on this method, a single test case with only simple complexity can be transformed into a complex test case with extremely high complexity that can activate a large amount of FPGA logic and various resources, thereby improving the test efficiency of FPGA logic resources and EDA tools.

[0072] In some optional implementations, when the native test case is one-dimensional data, the native test case is expanded into two-dimensional data.

[0073] The generated target test case is actually a multi-level cascade of native test cases, so it is necessary to add one dimension to some arrays in the native test case. The original one-dimensional array needs to be expanded to a two-dimensional array, and the added one dimension is used to store data between native test cases. This expansion can make data management clearer, thereby ensuring the correct execution of multi-level cascades.

[0074] In the present embodiment, a FPGA test case logic resource expansion device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0075] This embodiment provides a FPGA test case logic resource expansion device, such as Figure 8 As shown, the device comprises:

[0076] An acquisition module 201 is used to acquire a native test case corresponding to the FPGA chip to be tested;

[0077] A copy module 202 is used to copy the original test case, obtain multiple copied test cases, and use the original test case and the multiple copied test cases as initial test cases;

[0078] The expansion module 203 is used to generate an expanded target test case based on the initial test case.

[0079] In some optional implementations, the expansion module 203 includes:

[0080] The first expansion unit is used to cascade all initial test cases in sequence to obtain target test cases.

[0081] The second expansion unit is used to add a linear feedback shift register and a wrapper to each initial test case, generate an intermediate test case corresponding to the initial test case one by one, connect all the intermediate test cases in parallel, and obtain the target test case. It is also used to copy the input data using the linear feedback shift register, and pass it to the input end of each initial test case in turn through the shift operation; the output of each initial test case is passed to the wrapper in turn, and finally the highest bit in the wrapper is used as the output of the target test case.

[0082] The marking unit is used to add a constraint mark between the initial test case and the initial test case connection, and the constraint mark is used to prevent the signal node from being optimized.

[0083] The third expansion unit is used to expand the native test case into two-dimensional data when the native test case is one-dimensional data.

[0084] The FPGA test case logic resource expansion device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0085] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0086] The embodiment of the present invention also provides a computer device having the above Figure 8 The FPGA test case logic resource expansion device is shown.

[0087] See also Fig. 9 , Fig. 9 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig. 9 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig. 9 A processor 10 is taken as an example.

[0088] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0089] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0090] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0091] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0092] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0093] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0094] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0095] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for expanding logic resources of FPGA test cases, characterized in that: The method comprises: Get the native test case corresponding to the FPGA chip to be tested; Copying the original test case to obtain multiple copied test cases, and using the original test case and the multiple copied test cases together as initial test cases; Based on the initial test case, an expanded target test case is generated.

2. The method according to claim 1, characterized in that The step of generating an expanded target test case based on the initial test case includes: All the initial test cases are cascaded in sequence to obtain the target test case.

3. The method according to claim 1, characterized in that The step of generating an expanded target test case based on the initial test case includes: Adding a linear feedback shift register and a wrapper to each of the initial test cases to generate intermediate test cases corresponding one to one to the initial test cases; All the intermediate test cases are connected in parallel to obtain the target test case.

4. The method according to claim 3, characterized in that The input data is copied by using the linear feedback shift register and is passed to the input end of each of the initial test cases in turn through a shift operation; the output of each of the initial test cases is passed to the wrapper in turn, and finally the highest bit in the wrapper is used as the output of the target test case.

5. The method according to claim 2, characterized in that: The step of sequentially cascading all the initial test cases to obtain the target test case includes: A constraint mark is added between the initial test case and the initial test case connection, wherein the constraint mark is used to prevent a signal node from being optimized.

6. The method according to claim 2, characterized in that When the native test case is one-dimensional data, the native test case is expanded into two-dimensional data.

7. An FPGA test case logic resource expansion device, characterized in that: The device comprises: The acquisition module is used to obtain the native test cases corresponding to the FPGA chip to be tested; A copy module, used to copy the native test case to obtain multiple copied test cases, and use the native test case and the multiple copied test cases together as initial test cases; The expansion module is used to generate an expanded target test case based on the initial test case.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the FPGA test case logic resource expansion method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the FPGA test case logic resource expansion method according to any one of claims 1-6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to enable a computer to execute the FPGA test case logic resource expansion method according to any one of claims 1 to 6.

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