An address calculation array management method, device, equipment and storage medium

Abstract

Embodiments of the present application disclose an address calculation array management method, device and equipment and a storage medium. With the development and application of DMA technology, high-performance DMA has supported linear addressing, constant addressing (FIFO form), and forward cross-continuous address jump mode addressing to meet flexible mapping of data space. Embodiments of the present application are based on the background of DMA address mapping requirements, and adopt an address array mode. By comparing elements of the address array, division and remainder operations used when calculating addresses are avoided, multiplication is avoided, circuit structure is optimized, and the array is compared column by column in a pipeline mode, so that the logic area is reduced and the timing is greatly improved.

Description

Technical Field

[0001] This application relates to the field of address access technology, and in particular to an address calculation array management method, apparatus, device and storage medium. Background Technology

[0002] With the development and application of DMA technology, high-performance DMA can support current addressing, constant addressing (FIFO form), and forward cross-link address hopping to meet the flexible mapping of data space.

[0003] In constant addressing and forward cross-region hop addressing, due to the discontinuous nature of the access space (e.g., during negative or positive hops), after accessing each address block (i.e., the boundary of a contiguous address access space), it is necessary to skip to the next address block. To efficiently perform DMA address block access, the address of the next data access needs to be calculated. However, current systems lack sophisticated address calculation capabilities and cannot calculate forward or negative hop addresses. Therefore, how to calculate the address of the next data access when addresses are discontinuous has become a pressing technical problem to be solved in this field. Summary of the Invention

[0004] To address the aforementioned issues, this application provides an address calculation array management method, apparatus, device, and storage medium that can calculate the address for the next data access when addresses are not contiguous.

[0005] The embodiments of this application disclose the following technical solutions: In a first aspect, this application provides an address calculation array management method, the method comprising: Obtain the start computation enable high pulse signal, which is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block; At time T0, it is determined whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, the internal startup pipeline array valid flag is set to valid at time T1. When the internal startup pipeline array valid flag is valid, it is a high pulse signal. At time T1, it is determined whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal. At time T1 and thereafter, each address pipeline accumulation array is started to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows in each clock cycle, for a total of 16 clock cycles, which is equivalent to M A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2.

[0006] Optionally, when the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a high pulse signal, the accumulated value s_dssize_Nx of the block address boundary includes: s_dssize_1x = block address boundary; s_dssize_2x = block address boundary + block address boundary; s_dssize_3x = block address boundary + block address boundary + block address boundary; ... s_dssize_Mx = the sum of the address boundaries of M blocks; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x = block address boundary + jump step; s_addr_inc_2x = block address boundary + jump step + block address boundary + jump step; s_addr_inc_3x = block address boundary + jump step + block address boundary + jump step + block address boundary + jump step; ... s_addr_inc_Mx = the sum of M block address boundaries plus jump steps; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

[0007] Optionally, when the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a low pulse signal, the accumulated value s_dssize_Nx of the block address boundary includes: s_dssize_1x= s_dssize_1x+ s_dssize_Mx; s_dssize_2x= s_dssize_2x+ s_dssize_Mx; s_dssize_3x= s_dssize_3x+ s_dssize_Mx; ... s_dssize_Mx= s_dssize_Mx+ s_dssize_Mx; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x= s_addr_inc_1x+ s_addr_inc_Mx; s_addr_inc_2x=s_addr_inc_2x+s_addr_inc_Mx; s_addr_inc_3x= s_addr_inc_3x+ s_addr_inc_Mx; ... s_addr_inc_Mx= s_addr_inc_Mx+ s_addr_inc_Mx; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

[0008] Optionally, the step of initiating the calculation of the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result for each address pipeline accumulation array includes: Compare each of the 16 elements in the matrix to determine whether the sum of the remaining space of the first address block and the block address boundary is greater than the access address length and whether the internal pipeline array start effective flag latch signal is a high pulse signal; If both are true, set the valid level signal of the matched element to 1, latch the accumulated value of the block address boundary into the content of the element and assign it to s_dssize_inc_lck, and latch the accumulated value of the sum of the block address boundary and the jump step size into the content of the element and assign it to s_addr_inc_lck. If the matched element does not exist, the valid level signal of the matched element will be set to 0. Based on the comparison of each element in the same matrix, the calculation results are output, including the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result.

[0009] Optionally, when the calculation enable is a high pulse signal at time T0 and the access address length is less than the remaining space of the first address block, the calculation result, based on the comparison of elements in the same matrix, outputs the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result, including: Next address to be written = starting address + access address length; Remaining length in the last address block = Remaining space in the first address block - Length of the accessed address; The length occupied by the last address block = block address boundary - remaining space of the first address block + access address length; The calculation result is valid = 2'b11.

[0010] Optionally, at a time other than T0, when the rising edge of the valid level signal for a matched element is detected, the calculation result of outputting the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result based on the comparison of each element in the same matrix includes: Next address to be written = starting address + s_addr_inc_lck - s_dssize_inc_lck + block address boundary; The remaining length in the last address block = s_dssize_inc_lck + the remaining space in the first address block - the length of the accessed address; The length occupied by the last address block = block address boundary - s_dssize_inc_lck - remaining space of the first address block + access address length; The calculation result is valid = 2'b01.

[0011] Secondly, embodiments of this application provide an address calculation array management device, the device comprising: The startup computing enable acquisition module is used to acquire the startup computing enable high pulse signal, which is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block; The internal startup pipeline array valid flag setting module is used to determine at time T0 whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, the internal startup pipeline array valid flag is set to valid at time T1. When the internal startup pipeline array valid flag is valid, it is a high pulse signal. The internal startup pipeline array valid flag latch signal setting module is used to determine at time T1 whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal. Each address pipeline accumulation array calculation module is used to start calculating the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result at time T1 and thereafter. The address pipeline accumulation array has M rows per clock cycle, for a total of 16 clock cycles, equivalent to M... A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2.

[0012] Optionally, the address pipeline accumulation array calculation module includes: The matrix element comparison submodule is used to compare the 16 elements in the matrix respectively, and determine whether the sum of the remaining space of the first address block and the block address boundary is greater than the access address length and whether the internal start pipeline array valid flag latch signal is a high pulse signal. The first setting submodule for the matched element valid level signal is used to set the matched element valid level signal to 1 if both are true, and to latch the accumulated value of the block address boundary into the element content and assign it to s_dssize_inc_lck, and to latch the accumulated value of the sum of the block address boundary and the jump step size into the element content and assign it to s_addr_inc_lck. The second setting submodule for matching the valid level signal of the element is used to set the valid level signal of the matched element to 0 if no element exists. The calculation result output submodule is used to output the calculation results based on the comparison of each element in the same matrix, including the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result.

[0013] Thirdly, embodiments of this application provide an electronic device, including: Memory, used to store computer programs; A processor is used to implement the steps of the address calculation array management method described above when executing the computer program.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the above-described address calculation array management method.

[0015] Compared with the prior art, this application has the following beneficial effects: This application provides an address calculation array management method, comprising: acquiring a start calculation enable high pulse signal, wherein the start calculation enable high pulse signal is accompanied by matching start address, block boundary address, jump step size, access address length, and remaining space information of the first address block; at time T0, determining whether the start calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block; if both are true, at time T1, setting the internal start pipeline array valid flag to valid; the internal start pipeline array valid flag being valid is a high pulse signal; at time T1, determining whether the internal start pipeline array valid flag is a high pulse signal; if yes, at time T2, setting the internal start pipeline array valid flag latch signal to valid; the internal start pipeline array valid flag latch signal being valid is a high pulse signal; at time T1 and thereafter, starting each address pipeline accumulation array to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows per clock cycle, for a total of 16 clock cycles, equivalent to M A matrix of 16, each element of which includes the accumulated value s_dssize_Nx of the block address boundary and the accumulated value s_addr_inc_Nx of the sum of the block address boundary and the jump step size, where N is an integer between 1 and M, inclusive; the time T0 is earlier than the time T1, which is earlier than the time T2. A high-pulse signal to enable the calculation is used as the criterion for determining whether each address pipeline accumulation array is started. The array is compared column by column in a pipelined manner, which reduces the logic area and greatly improves timing. The use of address arrays avoids the division and modulo operations used in address calculation, and can calculate the number of block address boundaries crossed, i.e., the number of elements matched indicates the number of elements crossed. This allows for the calculation of the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the validity signal of the calculation result, enabling the calculation of the next data access address even when addresses are discontinuous.

[0016] The address calculation array management device, electronic device, and computer-readable storage medium provided in this application embodiment can implement the steps of the above-described address calculation array management method, and thus also have the above-described beneficial effects. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a forward jump address mapping provided in an embodiment of this application; Figure 2 A schematic diagram of constant addressing address mapping provided in an embodiment of this application; Figure 3 This application provides a schematic flowchart of an address calculation array management method. Figure 4 This is a schematic diagram of an address pipeline accumulation array calculation method provided in an embodiment of this application; Figure 5 This is a schematic diagram of another address calculation array management method provided in an embodiment of this application; Figure 6 A schematic diagram of an address calculation array management device provided in this application embodiment; Figure 7 This is a schematic diagram of an electronic device structure provided in an embodiment of this application. Detailed Implementation

[0019] As described earlier, efficient DMA address block access currently requires calculating the address of the next data access. However, there is currently no sophisticated address calculation function, and it is not possible to calculate the positive or negative jump address.

[0020] Through research, the inventors have developed an address calculation array management method, device, equipment, and storage medium that can calculate the address of the next data access when addresses are not contiguous.

[0021] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0022] Method Implementation Examples

[0023] This application's embodiments are based on DMA address mapping requirements, taking the forward jump address mapping method as an example. See [link to relevant documentation]. Figure 1This diagram illustrates a forward jump address mapping provided in an embodiment of this application, demonstrating the address mapping between S_addr and D_addr. For example, the transmission length is the access address length (length). The forward jump mapping method involves jumping the address according to the block address boundary (size). That is, starting from the starting address, after each consecutive transmission of size, the address jumps forward by a step size (distance). For example, the starting address ini_addr is 0x0, the size occupies 0 bytes, size = 4 bytes, distance = 8 bytes, and length = 10 bytes. This indicates the source is in forward jump mode, and the destination is linear addressing. The address is divided into segments of size (length / size = 2), meaning it spans two distances. The starting address for the next data access is calculated as ini_addr + length + 2. Given distance=0x1a, the number of bytes occupied within size is length%size=2Byte, and the number of remaining bytes within size is size-length%size=2Byte. The result of this calculation can be used as input for the next calculation.

[0024] Taking constant addressing (negative address jump) as another example, see [link to relevant documentation]. Figure 2 This figure is a schematic diagram of a constant addressing address mapping provided in an embodiment of this application. Figure 2 In this context, the source S_addr represents a negative address jump, and the destination D_addr represents a linear address. Since the jump step size distance is negative, constant addressing is a type of negative addressing, where the block address boundary size = -distance. For example, if the starting address ini_addr is 0x0, size = 4 bytes, distance = -4 bytes, and length = 10 bytes, and the address is divided by size, then length / size = 2, meaning it jumps across two distances. The starting address for the next data access is calculated as ini_addr + length - 2. distance=0x2, the number of bytes occupied within size is length%size=2Byte, and the number of bytes remaining within size is size-length%size=2Byte.

[0025] It should be noted that in the hardware implementation of the chip, since the supported range of length, size, and distance is relatively large, if the calculation method of remainder and division is used in the calculation, it will generate a bottleneck with more logic resources and poor timing. In order to meet the requirements of high-performance chip hardware, this application changes the implementation algorithm of the core remainder and division, avoids the easily thought-out implementation algorithm of remainder and division, and designs an address pipeline accumulation array management method to calculate the final address under multiple addressing rules (linear addressing, constant addressing, positive jump, negative jump) in one go, so as to meet the calculation under multiple addressing rules.

[0026] See Figure 3 The figure is a schematic flowchart of an address calculation array management method provided in an embodiment of this application, including the following steps: S301, obtain the start calculation enable high pulse signal, the start calculation enable high pulse signal is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block.

[0027] It should be noted that the start-calcul enable high pulse signal can be obtained as input. There are two types of start-calcul enable signals: high pulse and low pulse. In this step, the high pulse signal is obtained. Simultaneously with obtaining the start-calcul enable high pulse signal, the starting address, block boundary address, jump step size, access address length, and remaining space information of the first address block are matched. In subsequent embodiments, the start-calcul enable signal may be represented by `i_calcul_vld`; the starting address may be represented by `input_addr`; the block address boundary may be represented by `size`; the jump step size may be represented by `distance`; the access address length may be represented by `length`; and the remaining space of the first address block may be represented by `i_dssize_left`.

[0028] S302, at time T0, determine whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, at time T1, set the internal startup pipeline array valid flag to valid. When the internal startup pipeline array valid flag is valid, it is a high pulse signal.

[0029] It should be noted that since step S301 obtains a high-pulse signal for enabling computation, the computation enable signal will generally be a high-pulse signal at this time. The key is to determine whether the access address length is greater than or equal to the remaining space of the first address block, i.e., to determine whether i_calcul_vld && (length >= i_dssize_left) is 1. If so, the internal startup pipeline array valid flag is set to valid at time T1, and a high-pulse signal indicates that the internal startup pipeline array valid flag is valid. If not, it means that the access address length does not exceed the remaining length of the current address block. It should be noted that in subsequent embodiments, the internal startup pipeline array valid flag may be represented by s_calcul_vld.

[0030] It should be noted that during the first run, it is not necessary to remove all internal pipeline calculation results and status flag signals. However, during subsequent runs, it is necessary to remove all internal pipeline calculation results and status flag signals.

[0031] S303, at time T1, determine whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, set the internal startup pipeline array valid flag latch signal to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal.

[0032] It should be noted that the internal startup pipelined array valid flag latch signal is not the same as the internal startup pipelined array valid flag. In subsequent steps, the internal startup pipelined array valid flag latch signal can be used to determine whether a valid level signal of an element has been matched, while the internal startup pipelined array valid flag is a flag signal indicating the status. In subsequent embodiments, the internal startup pipelined array valid flag latch signal may be represented by s_calcul_mux_lck.

[0033] At time S304, T1 and thereafter, each address pipeline accumulation array is started to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows in each clock cycle, for a total of 16 clock cycles, equivalent to M A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2.

[0034] Specifically, at time T1, the pipelined accumulation array calculation for each address is initiated. The array can have any number of rows per clock cycle; taking 16 rows as an example, self-accumulation is performed within these 16 rows of elements each clock cycle, for a total of 16 clock cycles. From a global perspective encompassing all time points, this is 16. A matrix of size 16. Each element of the matrix contains two items: the first item is s_dssize_Nx (N is 1~16), which represents the accumulated value of the block address boundary size; the second item is s_addr_inc_Nx (N is 1~16), which represents the accumulated value of the sum of the block address boundary size and the jump step size distance.

[0035] It should be noted that the logic of each address pipeline accumulator array is different when s_calcul_vld is a high pulse signal and a low pulse signal.

[0036] When the logic of each address pipeline accumulator array is high in s_calcul_vld (high pulse signal): s_dssize_1x(s_dssize_Nx, N=1) = size, s_dssize_2x = size + size, s_dssize_3x = s_dssize_1x + s_dssize_2x, and so on, up to s_dssize_16x = the sum of 16 sizes. Each row's elements are summed to calculate the s_dssize_Nx element values ​​for rows 1 to 16.

[0037] s_addr_inc_1x (i.e., s_addr_inc_Nx when N=1) = size + distance, s_addr_inc_2x = size + distance + size + distance; s_addr_inc_3x = s_addr_inc_1x + s_addr_inc_2x; and so on, s_addr_inc_16x = the sum of 16 s_addr_inc_1x. Each row of elements is calculated using a cumulative summation method, calculating the s_addr_inc_Nx element values ​​for rows 1 to 16.

[0038] For a more intuitive explanation of address pipelined accumulation arrays, see [link to documentation]. Figure 4 This figure is a schematic flowchart of an address calculation array management method provided in an embodiment of this application. Taking a 16-row array in each clock cycle of an address pipeline accumulation array as an example, at time T1: S_size_1x=size;S_addr_inc_1x=size+distance; S_size_2x=size 2;S_addr_inc_2x=2 (size + distance); ... S_size_16x=size 16;S_addr_inc_16x=16 (size + distance).

[0039] At time T2: S_size_17x=size+S_size_16x;S_addr_inc_17x=size+distance+ addr_inc_16x; S_size_18x=size 2 + S_size_16x; S_addr_inc_18x = 2 (size+distance)+ addr_inc_16x; ... S_size_32x=size 16+S_size_16x;S_addr_inc_32x=16 (size + distance) + addr_inc_16x; ... At time T16: S_size_251x=size+S_size_250x;S_addr_inc_251x=size+distance+ addr_inc_250x; S_size_252x=size 2+S_size_250x;S_addr_inc_252x=2 (size+distance)+addr_inc_252x; ... S_size_256x=size 16+S_size_250x;S_addr_inc_256x=16 (size+distance)+addr_inc_250x.

[0040] It should be noted that when the matched element valid level signal s_dssize_hit is high, the value of each element is maintained at each clock cycle and no longer accumulated, in order to reduce power consumption.

[0041] Specifically, at time T1 and thereafter, if ((i_dssize_left + s_dssize_Nx) > length) && s_calcul_mux_lck, where N in s_dssize_Nx is 1~16, and the 16 elements in the matrix are compared one by one, if the above logic is high, then s_dssize_hit is 1, and the content of the element in s_dssize_Nx is latched and assigned to s_dssize_inc_lck, and the content of the element in s_addr_inc_Nx is latched and assigned to s_addr_inc_lck; if it is low, then s_dssize_hit is 0, indicating that the matrix element has not been matched in the current clock cycle.

[0042] After comparing each element in the same matrix, four final calculation results are output. It should be noted that the calculation methods for the four output results differ depending on the circumstances.

[0043] Specifically, if i_calcul_vld&&(length< i_dssize_left) holds true at time T0, then: The next address to be written, o_addr, is equal to the starting address input_addr plus the length of the access address. The remaining length within the last address block, o_left_len, equals the remaining space in the first address block, i_dssize_left, minus the length of the accessed address. The length of the last address block already occupied, o_use_len, is equal to the block address boundary size minus the remaining space of the first address block, i_dssize_left, plus the length of the accessed address. The valid signal of the calculation result is o_calcul_vld, 2bit=2'b11; If the rising edge of the s_dssize_hit signal is detected at a time other than T0, then: The address to be written next, o_addr, is equal to the starting address input_addr + s_addr_inc_lck - s_dssize_inc_lck + block address boundary size; 2) The remaining length within the last address block, o_left_len, is equal to s_dssize_inc_lck plus the remaining space in the first address block, i_dssize_left, minus the length of the accessed address. 3) The length of the last address block already occupied, o_use_len = block address boundary size - s_dssize_inc_lck - remaining space of the first address block, i_dssize_left + access address length; 4) The valid signal of the calculation result is o_calcul_vld, a 2-bit signal = 2'b01.

[0044] It should be noted that the rising edge of the s_dssize_hit signal is established when the s_dssize_hit signal changes from a low level to a high level.

[0045] This application provides an address calculation array management method, comprising: acquiring a start calculation enable high pulse signal, wherein the start calculation enable high pulse signal is accompanied by matching start address, block boundary address, jump step size, access address length, and remaining space information of the first address block; at time T0, determining whether the start calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block; if both are true, at time T1, setting the internal start pipeline array valid flag to valid; the internal start pipeline array valid flag being valid is a high pulse signal; at time T1, determining whether the internal start pipeline array valid flag is a high pulse signal; if yes, at time T2, setting the internal start pipeline array valid flag latch signal to valid; the internal start pipeline array valid flag latch signal being valid is a high pulse signal; at time T1 and thereafter, starting each address pipeline accumulation array to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows per clock cycle, for a total of 16 clock cycles, equivalent to M A matrix of 16, each element of which includes the accumulated value s_dssize_Nx of the block address boundary and the accumulated value s_addr_inc_Nx of the sum of the block address boundary and the jump step size, where N is an integer between 1 and M, inclusive; the time T0 is earlier than the time T1, which is earlier than the time T2. A high-pulse signal to enable the calculation is used as the criterion for determining whether each address pipeline accumulation array is started. The array is compared column by column in a pipelined manner, which reduces the logic area and greatly improves timing. The use of address arrays avoids the division and modulo operations used in address calculation, and can calculate the number of block address boundaries crossed, i.e., the number of elements matched indicates the number of elements crossed. This allows for the calculation of the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the validity signal of the calculation result, enabling the calculation of the next data access address even when addresses are discontinuous.

[0046] As one possible implementation, this application also provides another address calculation array management method, see [link to relevant documentation]. Figure 5 This figure is a schematic diagram of another address calculation array management method provided in an embodiment of this application.

[0047] exist Figure 5 First, it determines whether the transmission length is less than the remaining address in the current first block. If so, the calculation result is output directly. If not, the address pipeline accumulation array is started, and the array information of the block address accumulation boundary of the first element in the array plus the remaining space of the first block address is greater than the access address length is matched, and then the calculation result is output.

[0048] Specifically, the input consists of six elements: the starting address input_addr, the block address boundary size, the jump step size distance, the access address length length, the remaining space of the first address block i_dssize_left, and the start calculation enable i_calcul_vld. Taking the starting address as the origin, after filling the first address block, the remaining access address length is divided according to size. Each time it is divided, the address is increased by size and distance is added until the length is mapped. The next address to be written under the addressing rule o_addr, the remaining length in the last address block o_left_len, the occupied length of the last address block o_use_len, and the valid calculation result o_calcul_vld 2-bit signal, for a total of four calculation results.

[0049] This application provides a schematic flowchart of another address calculation array management method. It employs an address array approach, avoiding division and modulo operations used in address calculation by comparing the elements of the address array. By comparing elements column by column, the number of elements spanned is calculated; that is, the matching element indicates the number of elements spanned. The elements in the array are obtained through incremental accumulation, avoiding multiplication. This optimizes the circuit structure and avoids the use of complex multiplication circuits. Furthermore, the pipelined column-by-column comparison of the array reduces the logic area and significantly improves timing. Address calculation can be performed even when the first address block is occupied. Additionally, for DMA applications, the result of the previous calculation can be used as the output of the next calculation, providing repeatability and flexibility.

[0050] Device Examples

[0051] See Figure 6 The figure is a schematic diagram of an address calculation array management device provided in an embodiment of this application, including: The startup computing enable acquisition module 601 is used to acquire the startup computing enable high pulse signal, which is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block; The internal startup pipeline array valid flag setting module 602 is used to determine at time T0 whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, the internal startup pipeline array valid flag is set to valid at time T1. When the internal startup pipeline array valid flag is valid, it is a high pulse signal. The internal startup pipeline array valid flag latch signal setting module 603 is used to determine at time T1 whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal. Each address pipeline accumulation array calculation module 604 is used to start each address pipeline accumulation array at time T1 and thereafter to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows in each clock cycle, for a total of 16 clock cycles, which is equivalent to M A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2.

[0052] Optionally, the address pipeline accumulation array calculation module 604 includes: The matrix element comparison submodule is used to compare the M elements in the matrix respectively, and determine whether the sum of the remaining space of the first address block and the block address boundary is greater than the access address length and whether the internal start pipeline array valid flag latch signal is a high pulse signal. The first setting submodule for the matched element valid level signal is used to set the matched element valid level signal to 1 if both are true, and to latch the accumulated value of the block address boundary into the element content and assign it to s_dssize_inc_lck, and to latch the accumulated value of the sum of the block address boundary and the jump step size into the element content and assign it to s_addr_inc_lck. The second setting submodule for matching the valid level signal of the element is used to set the valid level signal of the matched element to 0 if no element exists. The calculation result output submodule is used to output the calculation results based on the comparison of each element in the same matrix, including the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result.

[0053] Optionally, when the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a high pulse signal, the accumulated value s_dssize_Nx of the block address boundary includes: s_dssize_1x = block address boundary; s_dssize_2x = block address boundary + block address boundary; s_dssize_3x = block address boundary + block address boundary + block address boundary; ... s_dssize_Mx = the sum of the address boundaries of M blocks; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x = block address boundary + jump step; s_addr_inc_2x = block address boundary + jump step + block address boundary + jump step; s_addr_inc_3x = block address boundary + jump step + block address boundary + jump step + block address boundary + jump step; ... s_addr_inc_Mx = the sum of M block address boundaries plus jump steps; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

[0054] Optionally, when the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a low pulse signal, the accumulated value s_dssize_Nx of the block address boundary includes: s_dssize_1x= s_dssize_1x+ s_dssize_Mx; s_dssize_2x= s_dssize_2x+ s_dssize_Mx; s_dssize_3x= s_dssize_3x+ s_dssize_Mx; ... s_dssize_Mx= s_dssize_Mx+ s_dssize_Mx; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x= s_addr_inc_1x+ s_addr_inc_Mx; s_addr_inc_2x=s_addr_inc_2x+s_addr_inc_Mx; s_addr_inc_3x= s_addr_inc_3x+ s_addr_inc_Mx; ... s_addr_inc_Mx= s_addr_inc_Mx+ s_addr_inc_Mx; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

[0055] Optionally, when the calculation enable is a high pulse signal at time T0 and the access address length is less than the remaining space of the first address block, the calculation result output submodule is specifically used for: Calculate the next address to be written = starting address + access address length; Calculate the remaining length within the last address block = remaining space in the first address block - access address length; Calculate the occupied length of the last address block = block address boundary - remaining space of the first address block + access address length; The calculated effective signal is 2'b11.

[0056] Optionally, at a time other than T0, when the rising edge of the valid level signal of the matched element is detected, the calculation result output submodule is specifically used for: Calculate the address to be written next = starting address + s_addr_inc_lck - s_dssize_inc_lck + block address boundary; Calculate the remaining length within the last address block = s_dssize_inc_lck + remaining space in the first address block - access address length; The length occupied by the last address block is calculated as follows: Block address boundary - s_dssize_inc_lck - Remaining space in the first address block + Access address length; The calculated effective signal is 2'b01.

[0057] An address calculation array management device utilizes a startup calculation enable acquisition module, an internal startup pipeline array valid flag setting module, an internal startup pipeline array valid flag latching signal module, and address pipeline accumulation array calculation modules. It acquires a startup calculation enable high-pulse signal, which is accompanied by matching start address, block boundary address, jump step size, access address length, and remaining space information of the first address block. At time T0, it determines whether the startup calculation enable is a high-pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, at time T1, it sets the internal startup pipeline array valid flag. For validity, the internal startup pipeline array valid flag is a high pulse signal when valid; at time T1, it is determined whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid, and the internal startup pipeline array valid flag latch signal is a high pulse signal when valid; at time T1 and thereafter, each address pipeline accumulation array is started to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows per clock cycle, for a total of 16 clock cycles, equivalent to M A matrix of 16, each element of which includes the accumulated value s_dssize_Nx of the block address boundary and the accumulated value s_addr_inc_Nx of the sum of the block address boundary and the jump step size, where N is an integer between 1 and M, inclusive; the time T0 is earlier than the time T1, which is earlier than the time T2. A high-pulse signal to enable the calculation is used as the criterion for determining whether each address pipeline accumulation array is started. The array is compared column by column in a pipelined manner, which reduces the logic area and greatly improves timing. The use of address arrays avoids the division and modulo operations used in address calculation, and can calculate the number of block address boundaries crossed, i.e., the number of elements matched indicates the number of elements crossed. This allows for the calculation of the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the validity signal of the calculation result, enabling the calculation of the next data access address even when addresses are discontinuous.

[0058] Electronic device examples

[0059] See Figure 7 The figure is a schematic diagram of an electronic device structure provided in an embodiment of this application, including: Memory 11 is used to store computer programs; The processor 12 is used to implement the steps of the address calculation array management method described in any of the above method embodiments when executing the computer program.

[0060] In this embodiment, the device can be an in-vehicle computer, a PC (Personal Computer), or a terminal device such as a smartphone, tablet computer, handheld computer, or portable computer.

[0061] The device may include a memory 11, a processor 12, and a bus 13.

[0062] The memory 11 includes at least one type of readable storage medium, such as flash memory, hard disk, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the device, such as the hard disk of the device. In other embodiments, the memory 11 can also be an external storage device of the device, such as a plug-in hard disk, SmartMedia Card (SMC), Secure Digital (SD) card, Flash Card, etc. Furthermore, the memory 11 can include both internal and external storage units of the device. The memory 11 can be used not only to store application software and various types of data installed on the device, such as program code executing address calculation array management methods, but also to temporarily store data that has been output or will be output.

[0063] In some embodiments, processor 12 may be a central processing unit (CPU), controller, microcontroller, microprocessor or other data processing chip, used to run program code stored in memory 11 or process data, such as program code for executing address calculation array management method, etc.

[0064] This bus 13 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0065] Furthermore, the device may also include a network interface 14, which may optionally include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), typically used to establish communication connections between the device and other electronic devices.

[0066] Optionally, the device may further include a user interface 15, which may include a display, an input unit such as a keyboard, and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the device and to display a visual user interface.

[0067] Figure 7 Only devices with components 11-15 are shown; those skilled in the art will understand that... Figure 7 The structure shown does not constitute a limitation on the device and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0068] Readable storage medium embodiments

[0069] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the address calculation array management method described in any of the above method embodiments.

[0070] The storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the embodiments of apparatus, electronic devices, and readable storage media, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The apparatus, electronic devices, and readable storage media embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components indicated as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0072] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for managing an address calculation array, characterized in that, The method includes: Obtain the start computation enable high pulse signal, which is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block; At time T0, it is determined whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, the internal startup pipeline array valid flag is set to valid at time T1. When the internal startup pipeline array valid flag is valid, it is a high pulse signal. At time T1, it is determined whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal. At time T1 and thereafter, each address pipeline accumulation array is started to calculate the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result; the address pipeline accumulation array has M rows in each clock cycle, for a total of 16 clock cycles, which is equivalent to M A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2; The process of initiating the pipeline accumulation array for each address to calculate the next address to be written, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result includes: Compare each of the M elements in the matrix to determine whether the sum of the remaining space of the first address block and the block address boundary is greater than the access address length and whether the internal start pipeline array valid flag latch signal is a high pulse signal. If both are true, set the valid level signal of the matched element to 1, latch the accumulated value of the block address boundary into the content of the element and assign it to s_dssize_inc_lck, and latch the accumulated value of the sum of the block address boundary and the jump step size into the content of the element and assign it to s_addr_inc_lck. If the matched element does not exist, the valid level signal of the matched element will be set to 0. Based on the comparison of each element in the same matrix, the calculation results are output, including the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result.

2. The method according to claim 1, characterized in that, When the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a high pulse signal, the accumulated value s_dssize_Nx at the block address boundary includes: s_dssize_1x = block address boundary; s_dssize_2x = block address boundary + block address boundary; s_dssize_3x = block address boundary + block address boundary + block address boundary; …… s_dssize_Mx = the sum of the address boundaries of M blocks; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x = block address boundary + jump step; s_addr_inc_2x = block address boundary + jump step + block address boundary + jump step; s_addr_inc_3x = block address boundary + jump step + block address boundary + jump step + block address boundary + jump step; …… s_addr_inc_Mx = the sum of M block address boundaries plus jump steps; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

3. The method according to claim 1, characterized in that, When the logic of each address pipelined accumulator array internally activates the pipelined array valid flag as a low pulse signal, the accumulated value s_dssize_Nx at the block address boundary includes: s_dssize_1x= s_dssize_1x+ s_dssize_Mx; s_dssize_2x= s_dssize_2x+ s_dssize_Mx; s_dssize_3x= s_dssize_3x+ s_dssize_Mx; …… s_dssize_Mx= s_dssize_Mx+ s_dssize_Mx; The accumulated value s_addr_inc_Nx, which is the sum of the block address boundary and the jump step size, includes: s_addr_inc_1x= s_addr_inc_1x+ s_addr_inc_Mx; s_addr_inc_2x=s_addr_inc_2x+s_addr_inc_Mx; s_addr_inc_3x= s_addr_inc_3x+ s_addr_inc_Mx; …… s_addr_inc_Mx= s_addr_inc_Mx+ s_addr_inc_Mx; When the matched element's valid level signal is 1, the element's value is maintained at each clock cycle and no further accumulation is performed.

4. The method according to claim 1, characterized in that, When the calculation is enabled by a high pulse signal at time T0 and the access address length is less than the remaining space of the first address block, the calculation results, based on the comparison of elements in the same matrix, output the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result, including: Next address to be written = starting address + access address length; Remaining length in the last address block = Remaining space in the first address block - Length of the accessed address; The length occupied by the last address block = block address boundary - remaining space of the first address block + access address length; The calculation result is valid = 2'b11.

5. The method according to claim 1, characterized in that, At a time other than T0, when the rising edge of the valid level signal for a matched element is detected, the calculation results, based on the comparison of elements in the same matrix, output the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the calculation result valid signal, including: Next address to be written = starting address + s_addr_inc_lck - s_dssize_inc_lck + block address boundary; The remaining length in the last address block = s_dssize_inc_lck + the remaining space in the first address block - the length of the accessed address; The length occupied by the last address block = block address boundary - s_dssize_inc_lck - remaining space of the first address block + access address length; The calculation result is valid = 2'b01.

6. An address calculation array management device, characterized in that, The device includes: The startup computing enable acquisition module is used to acquire the startup computing enable high pulse signal, which is accompanied by the matching start address, block boundary address, jump step size, access address length and the remaining space information of the first address block; The internal startup pipeline array valid flag setting module is used to determine at time T0 whether the startup calculation enable is a high pulse signal and whether the access address length is greater than or equal to the remaining space of the first address block. If both are true, the internal startup pipeline array valid flag is set to valid at time T1. When the internal startup pipeline array valid flag is valid, it is a high pulse signal. The internal startup pipeline array valid flag latch signal setting module is used to determine at time T1 whether the internal startup pipeline array valid flag is a high pulse signal. If so, at time T2, the internal startup pipeline array valid flag latch signal is set to valid. When the internal startup pipeline array valid flag latch signal is valid, it is a high pulse signal. Each address pipeline accumulation array calculation module is used to start calculating the next address to be written, the remaining length in the last address block, the occupied length of the last address block, and the valid signal of the calculation result at time T1 and thereafter. The address pipeline accumulation array has M rows per clock cycle, for a total of 16 clock cycles, equivalent to M... A matrix of 16, each element of which includes the accumulated value of block address boundaries s_dssize_Nx and the accumulated value of the sum of block address boundaries and jump steps s_addr_inc_Nx, where N is an integer between 1 and M, including 1 and M; the time T0 is earlier than the time T1 is earlier than the time T2; The address-based pipeline accumulation array calculation module includes: The matrix element comparison submodule is used to compare the M elements in the matrix respectively, and determine whether the sum of the remaining space of the first address block and the block address boundary is greater than the access address length and whether the internal start pipeline array valid flag latch signal is a high pulse signal. The first setting submodule for the matched element valid level signal is used to set the matched element valid level signal to 1 if both are true, and to latch the accumulated value of the block address boundary into the element content and assign it to s_dssize_inc_lck, and to latch the accumulated value of the sum of the block address boundary and the jump step size into the element content and assign it to s_addr_inc_lck. The second setting submodule for matching the valid level signal of the element is used to set the valid level signal of the matched element to 0 if no element exists. The calculation result output submodule is used to output the calculation results based on the comparison of each element in the same matrix, including the address to be written next, the remaining length in the last address block, the length already occupied in the last address block, and the valid signal of the calculation result.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the address calculation array management method as described in any one of claims 1-5 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the address calculation array management method as described in any one of claims 1-5.

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