Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: providing a substrate, forming a shallow trench isolation structure in the substrate, forming a gate structure on the surface of the substrate, forming a source and a drain in the substrate on both sides of the gate structure, respectively, the shallow trench isolation structure is located outside the drain or the source and away from the gate structure; forming at least one groove in at least one of the source and the drain; forming a dielectric layer, covering the surface of the substrate and filling the groove. By forming at least one groove in at least one of the source or the drain and filling the groove, the stress in the vertical direction of the channel surface of the MOS device can be reduced by adding the groove, so that the stress distribution of the active area is more uniform, thereby ensuring the electrical performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the manufacturing process of integrated circuits (ICs), in order to ensure the normal operation of devices, it is usually necessary to isolate the active areas of transistors on the wafer substrate. The shallow trench isolation (STI) technology used in related technologies can effectively ensure that the N-type and P-type doped areas can be completely isolated. The shallow trench isolation technology first etches the silicon area defined by the mask in the N-type and P-type doped areas to form a shallow trench, and then fills the shallow trench with insulating materials to achieve the insulation effect. Compared with traditional intrinsic oxide isolation technology, shallow trench isolation technology can have a larger breakdown voltage than intrinsic oxide isolation technology, and can reduce leakage current between electrodes.

[0003] STI technology is widely used in the current MOS tube preparation process due to its excellent isolation performance and low leakage current. However, in the process of STI manufacturing, the isolation dielectric oxide is filled in the shallow trench. Due to the different thermal expansion coefficients of the silicon substrate and the isolation dielectric oxide, STI will produce compressive stress to squeeze the active area and channel of the adjacent MOS transistor, causing the electrical parameters of the device to change. That is, after using STI technology, a stress effect (Length of Diffusion effect, LOD) will be generated, resulting in uneven stress distribution in the active area, affecting the diffusion of ions in the active area, and further having an adverse effect on the electrical properties of the semiconductor device. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, in which a shallow trench isolation structure is formed, a gate structure is formed on the surface of the substrate, a source and a drain are respectively formed in the substrate on both sides of the gate structure, and the shallow trench isolation structure is located outside the drain or the source and away from the gate structure;

[0007] forming at least one groove in at least one of the source and the drain;

[0008] A dielectric layer is formed to cover the surface of the substrate and fill the groove.

[0009] Exemplarily, the width of the groove in the connection direction between the source and the drain is no more than 100 nm, and the depth of the groove is no more than 100 nm.

[0010] Exemplarily, the distance between the groove and the gate structure is greater than the distance between the groove and the adjacent shallow trench isolation structure.

[0011] Exemplarily, when there are multiple grooves, the multiple grooves are arranged in an array; and / or

[0012] When there are multiple grooves, at least two of the multiple grooves have different depths and / or widths; and / or

[0013] When there are multiple grooves, the distances between the multiple grooves are equal or different.

[0014] Exemplarily, forming at least one groove in at least one of the source and the drain comprises:

[0015] forming a patterned mask layer on the surface of the substrate and the top surface of the gate structure;

[0016] The substrate is etched using the patterned mask layer as a mask to form the groove.

[0017] Exemplarily, the forming of a dielectric layer to cover the surface of the substrate and fill the groove includes:

[0018] Depositing a dielectric material layer on the substrate so that the dielectric material layer covers the upper surface of the substrate and fills the groove;

[0019] The dielectric material layer is planarized to form a dielectric layer covering the surface of the substrate and filling the groove.

[0020] Exemplarily, the dielectric layer includes an oxide layer.

[0021] Exemplarily, the method for forming a shallow trench isolation structure in the substrate includes:

[0022] forming a patterned hard mask layer on the surface of the substrate;

[0023] Etching using the patterned hard mask layer as a mask to form a shallow trench;

[0024] The shallow trench is filled and the filled shallow trench is planarized to obtain a shallow trench isolation structure.

[0025] Exemplarily, the hard mask layer includes an isolation oxide layer and a silicon nitride layer formed in sequence.

[0026] One aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the manufacturing method as described above.

[0027] The semiconductor manufacturing method provided by the present invention forms at least one groove in at least one of the source or the drain and fills the groove. The added groove can reduce the stress in the vertical direction of the channel surface of the MOS device, thereby making the stress distribution in the active area more uniform, thereby ensuring the electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0029] Figure 1 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0030] FIG. 2A to FIG. 2E The cross-sectional view of a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0032] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0033] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0034] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0035] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] In the IC manufacturing process, in order to ensure the normal operation of devices, it is usually necessary to isolate the active areas of transistors on the wafer substrate. The use of STI technology in related technologies can effectively ensure that the N-type and P-type doped areas can be completely isolated.

[0037] However, during the STI manufacturing process, the shallow trench is filled with isolation dielectric oxide. Due to the different thermal expansion coefficients of the silicon substrate and the isolation dielectric oxide, STI will produce compressive stress to squeeze the active area and channel of the adjacent MOS transistor, causing the electrical parameters of the device to change. That is, after adopting the STI technology, a stress effect will be generated, resulting in uneven stress distribution in the active area, affecting the diffusion of ions in the active area, and further having an adverse effect on the various electrical properties of the device.

[0038] Therefore, in view of the existence of the above-mentioned technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 1 As shown, it mainly includes the following steps:

[0039] Step S110: providing a substrate, forming a shallow trench isolation structure in the substrate, forming a gate structure on the surface of the substrate, forming a source and a drain in the substrate on both sides of the gate structure, respectively, and the shallow trench isolation structure is located outside the drain or the source and away from the gate structure;

[0040] Step S120: forming at least one groove in at least one of the source and the drain;

[0041] Step S130: forming a dielectric layer to cover the surface of the substrate and fill the groove.

[0042] The semiconductor manufacturing method provided by the embodiment of the present invention forms at least one groove in at least one of the source or the drain and fills the groove. The added groove can reduce the stress in the vertical direction of the channel surface of the MOS device, thereby making the stress distribution in the active area more uniform, thereby ensuring the electrical performance of the device.

[0043] Below, reference FIG. 2A to FIG. 2E The method for preparing a semiconductor device according to an embodiment of the present invention is described in detail, wherein: FIG. 2A to FIG. 2E The cross-sectional view of a semiconductor device obtained by sequentially implementing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0044] First, perform step S110: provide a substrate, form a shallow trench isolation structure in the substrate, form a gate structure on the surface of the substrate, form a source and a drain in the substrate on both sides of the gate structure, respectively, and the shallow trench isolation structure is located outside the drain or the source and away from the gate structure.

[0045] like Figure 2AAs shown, a substrate 200 is provided, a shallow trench isolation structure 201 is formed in the substrate 200, a gate structure 204 is formed on the surface of the substrate 200, a source 203 and a drain 202 are formed in the substrate 200 on both sides of the gate structure 204, and the shallow trench isolation structure 201 is located outside the drain 202 or the source 203 and away from the gate structure 204.

[0046] The material of the substrate 200 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, or silicon on dielectric (SOI), stacked silicon on dielectric (SSOI), stacked silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI) and germanium on dielectric (GeOI).

[0047] Exemplarily, a method for forming a shallow trench isolation structure in a substrate includes: forming a patterned hard mask layer on the surface of the substrate; etching using the patterned hard mask layer as a mask to form a shallow trench; filling the shallow trench and planarizing the filled shallow trench to obtain a shallow trench isolation structure.

[0048] In a specific example, a method for forming a shallow trench isolation structure in a substrate includes: first forming a hard mask layer on the surface of the substrate, then forming a patterned photoresist layer on the hard mask layer, etching the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer, and then etching using the patterned hard mask layer as a mask to form a shallow trench. Exemplarily, various etching methods commonly used in the art can be used to perform etching to form the shallow trench. Exemplarily, the hard mask layer includes an isolation oxide layer and a silicon nitride layer formed in sequence, and the isolation oxide layer can be an isolation oxide commonly used in the art, such as silicon oxide.

[0049] Next, a filling layer is formed in the shallow trench, and then the shallow trench is planarized to obtain a shallow trench isolation structure, and finally the hard mask layer is removed. Exemplarily, a conventional planarization method in the art is used to achieve surface planarization. Non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method. The chemical mechanical polishing planarization method is usually selected. Optionally, the top surface of the shallow trench isolation structure is higher than or flush with the surface of the substrate.

[0050] Exemplarily, the method for forming a gate structure on the surface of the substrate includes: first forming a gate dielectric material layer on the surface of the substrate; depositing a gate electrode material layer to cover the gate dielectric material layer; and sequentially etching the gate electrode material layer and the gate dielectric material layer to form a gate electrode layer and a gate dielectric layer, respectively, and the gate electrode layer and the gate dielectric layer constitute the gate structure.

[0051] like Figure 2A As shown, sidewall spacers 208 may be formed on both sides of the gate structure 204. Specifically, the sidewall spacers 208 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The sidewall spacers 208 include but are not limited to a silicon oxide layer, a silicon nitride layer, or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer).

[0052] like Figure 2A As shown, ion implantation is performed on the substrate 200 based on the gate structure 204 and the spacer 208 to form a source 203 and a drain 202 on both sides of the gate structure 204 and the spacer 208 respectively.

[0053] Next, step S120 is performed: forming at least one groove in at least one of the source and the drain.

[0054] Exemplarily, at least one groove is formed in at least one of the source and the drain, including: forming a patterned mask layer on the surface of the substrate and the top surface of the gate structure; etching the substrate using the patterned mask layer as a mask to form the groove.

[0055] like Figure 2B , Figure 2C As shown, a patterned mask layer 206 is formed on the surface of the substrate 200 and the top surface of the gate structure 204 , that is, the patterned mask layer 206 is formed to cover the surface of the substrate 200 , the gate structure 204 and the sidewall spacer 208 , and the mask layer 206 includes a hard mask layer.

[0056] The patterned mask layer 206 defines the size and position of the predetermined groove 205, and then the substrate 200 is etched using the patterned mask layer 206 as a mask to form the groove 205. By way of example, various etching methods commonly used in the art can be used to etch the groove 205, such as reactive ion etching, and then the mask layer 206 is removed.

[0057] In another embodiment, the mask layer may include a photoresist mask material. The photoresist mask material may include a photoresist material selected from the group consisting of a positive photoresist material, a negative photoresist material, and a hybrid photoresist material. Typically, the mask layer includes a positive photoresist material or a negative photoresist material having a thickness from about 2000 angstroms to about 5000 angstroms.

[0058] Exemplarily, the width of the groove 205 in the connection direction between the source 203 and the drain 202 does not exceed 100 nm, and the depth of the groove does not exceed 100 nm. Figure 2C As shown, the width of the groove 205 is 1 nm-100 nm, and the depth of the groove 205 is 1 nm-100 nm. A groove 205 much smaller than the shallow trench isolation structure 201 is formed in at least one of the source 203 or the drain 202 .

[0059] Exemplarily, the distance between the groove and the gate structure is greater than the distance between the groove and the adjacent shallow trench isolation structure. By locating the groove before the gate structure and the shallow trench isolation structure and being closer to the STI, the groove can better play a stress sharing role, thereby reducing the stress in the vertical direction of the channel surface of the semiconductor device including the MOS device, thereby making the stress distribution in the active area more uniform, thereby ensuring the electrical performance of the device.

[0060] like Figure 2C-2E As shown, the groove 205 is located between the gate structure 204 and the shallow trench isolation structure 201, and the groove 205 is close to the adjacent shallow trench isolation structure 201. For example, the groove 205 formed in the drain 202 is close to the shallow trench isolation structure 201 adjacent to the drain 202, and the groove formed in the source 203 is close to the shallow trench isolation structure 201 adjacent to the source 203.

[0061] The number of the grooves 205 can be reasonably set according to actual needs. For example, when there are multiple grooves 205, the multiple grooves 205 are arranged in an array, or can also be arranged irregularly.

[0062] Exemplarily, when there are multiple grooves 205 , at least two grooves 205 among the multiple grooves 205 have different depths and / or widths; and / or when there are multiple grooves 205 , distances between the multiple grooves 205 are equal or different.

[0063] When there are multiple grooves 205, the grooves 205 are arranged in an array at intervals. The spacing between the grooves 205 can be equal or unequal, and the size specifications of the grooves 205 can be the same or different. It can be reasonably set according to actual needs, and the present invention does not make specific limitations.

[0064] Then, step S130 is performed: forming a dielectric layer to cover the surface of the substrate and fill the groove.

[0065] Exemplarily, the forming of a dielectric layer that covers the surface of the substrate and fills the groove includes: depositing a dielectric material layer on the substrate so that the dielectric material layer covers the upper surface of the substrate and fills the groove; and planarizing the dielectric material layer to form a dielectric layer that covers the surface of the substrate and fills the groove.

[0066] like Figure 2D As shown, a dielectric material layer 2071 covering the surface of the substrate 200 is deposited on the surface of the substrate 200, and the dielectric material layer 2071 also covers the gate structure 204. During the deposition process, the groove 205 is filled with the dielectric material layer 2071. Due to the presence of the groove 205 in the substrate 200, after the dielectric material layer 2071 is deposited, a dielectric material layer groove on a vertical line with the groove 205 also exists in the dielectric material layer 2071.

[0067] Then, the dielectric material layer 2071 is planarized, and the planarization stops at the surface of the gate structure 204, and the top surface of the dielectric layer 207 is flush with the top surface of the gate structure 204, thereby forming a dielectric layer 207 that covers the surface of the substrate 200 and fills the groove 205. Exemplarily, a conventional planarization method in the art is used to achieve surface planarization. Non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method. A chemical mechanical polishing planarization method is usually selected. Exemplarily, the dielectric layer includes an oxide layer, wherein the oxide in the oxide layer can be polyethylene oxide (PEOX) or TEOS (tetraethoxysilane), etc. Exemplarily, the deposition method in the present invention can be completed using various deposition processes commonly used in the art, such as a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, etc.

[0068] At this point, the process steps implemented in the manufacturing method of a semiconductor device according to an embodiment of the present invention have been completed. It can be understood that the semiconductor device manufacturing method of this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of this embodiment.

[0069] The semiconductor manufacturing method provided by the embodiment of the present invention forms at least one groove in at least one of the source or the drain and fills the groove. The added groove can reduce the stress in the vertical direction of the channel surface of the MOS device, thereby making the stress distribution in the active area more uniform, thereby ensuring the electrical performance of the device.

[0070] The present invention also provides a semiconductor device, which can be prepared by the method in the above embodiment.

[0071] Below, reference Figure 2E The semiconductor device of the present invention is introduced and described in detail. It is worth mentioning that in order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment. For specific explanations and descriptions, reference can be made to the description in the aforementioned embodiment.

[0072] Specifically, Figure 2E As shown, the semiconductor device of the embodiment of the present invention includes a substrate 200, a shallow trench isolation structure 201 located in the substrate 200, a gate structure located on the surface of the substrate 200, and a source 203 and a drain 202 located on both sides of the gate structure, at least one of the source 203 or the drain 202 includes at least one groove 205, and a dielectric layer 207 covering the surface of the substrate 200 and filling the groove 205. The shallow trench isolation structure 201 is located outside the drain 202 or the source 203 and away from the gate structure 204.

[0073] It is worth mentioning that the semiconductor device of the present application can be any device including a MOS transistor, and is not specifically limited here.

[0074] The stress of the semiconductor device of the embodiment of the present invention is reduced compared with the semiconductor device of the related art. At the same time, as shown in Table 1 below, the threshold voltage (Vth) and saturation current (Idsat) of the semiconductor device of the embodiment of the present invention are reduced compared with the semiconductor device of the related art, wherein the semiconductor device before improvement in the table is the semiconductor device in the related art, and the device after improvement is the semiconductor device of the present invention.

[0075] Table 1 Comparison of electrical performance of semiconductor devices before and after improvement

[0076] Semiconductor Devices Threshold voltage Saturation current Before improvement 0.509V 495µA / um After Improvement 0.497V 512µA / um

[0077] Since the semiconductor device of the embodiment of the present invention is manufactured by the aforementioned method, the stress of the device can be reduced, thereby making the stress distribution of the active area more uniform, thereby ensuring the electrical performance of the semiconductor device.

[0078] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim listing several on-board systems, several of these on-board systems may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0079] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, in which a shallow trench isolation structure is formed, a gate structure is formed on the surface of the substrate, a source and a drain are respectively formed in the substrate on both sides of the gate structure, and the shallow trench isolation structure is located outside the drain or the source and away from the gate structure; forming at least one groove in at least one of the source and the drain; A dielectric layer is deposited to cover the surface of the substrate and fill the groove.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The width of the groove in the connection direction between the source electrode and the drain electrode does not exceed 100 nm, and the depth of the groove does not exceed 100 nm.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The distance between the groove and the gate structure is greater than the distance between the groove and the adjacent shallow trench isolation structure.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: When there are multiple grooves, the multiple grooves are arranged in an array; and / or When there are multiple grooves, at least two of the multiple grooves have different depths and / or widths; and / or When there are multiple grooves, the distances between the multiple grooves are equal or different.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of at least one groove in at least one of the source and the drain comprises: forming a patterned mask layer on the surface of the substrate and the top surface of the gate structure; The substrate is etched using the patterned mask layer as a mask to form the groove.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a dielectric layer to cover the surface of the substrate and fill the groove comprises: Depositing a dielectric material layer on the substrate so that the dielectric material layer covers the upper surface of the substrate and fills the groove; The dielectric material layer is planarized to form a dielectric layer covering the surface of the substrate and filling the groove.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric layer includes an oxide layer.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for forming a shallow trench isolation structure in the substrate comprises: forming a patterned hard mask layer on the surface of the substrate; Etching using the patterned hard mask layer as a mask to form a shallow trench; The shallow trench is filled and the filled shallow trench is planarized to obtain a shallow trench isolation structure.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The hard mask layer includes an isolation oxide layer and a silicon nitride layer which are formed in sequence.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the manufacturing method according to any one of claims 1 to 9.

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