Supporting 8-bit floating point format operands in computing architecture

Abstract

An apparatus for facilitating support of 8-bit floating point format operands in a computing architecture is disclosed. In one embodiment, the apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, where the decoded instruction is a matrix instruction that operates on an 8-bit floating point operand to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for an 8-bit floating point operand according to an 8-bit floating point data format indicated by the decoded instruction; and a pulsation dot product circuit to execute the decoded instruction using pulsation layers, each pulsation layer comprising one or more sets of interconnected multipliers, shifters and adders, each set of multipliers, shifters and adders to generate a dot product of 8-bit floating point operands.

Description

This invention patent application is a divisional application of the invention patent application with application number 202210175439.2 filed on February 24, 2022 and named “Supporting 8-bit floating point format operands in computing architecture”. Technical Field

[0001] The present application relates generally to data processing, and more particularly to supporting 8-bit floating point format operands in computing architectures. Background Art

[0002] Current parallel graphics data processing includes systems and methods developed to perform specific operations on graphics data, such as, for example, linear interpolation, tessellation, rasterization, texture mapping, depth testing, etc. Traditionally, graphics processors have used fixed-function compute units to process graphics data; however, recently portions of graphics processors have been made programmable, enabling such processors to support a wider variety of operations to process vertex and fragment data.

[0003] To further improve performance, graphics processors typically implement processing techniques such as pipelining, which attempt to process as much graphics data as possible in parallel throughout different parts of the graphics pipeline. Parallel graphics processors with single instruction multiple data (SIMD) or single instruction multiple thread (SIMT) architectures are designed to maximize the amount of parallel processing in the graphics pipeline. In a SIMD architecture, a computer with multiple processing elements attempts to perform the same operation on multiple data points at the same time. In a SIMT architecture, groups of parallel threads attempt to execute program instructions together synchronously as frequently as possible to improve processing efficiency.

[0004] Graphics processors are often used for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these areas have enabled ML models to train neural networks using low-precision arithmetic. Traditional training platforms support floating point 16 (FP16) and brain floating point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. Recent progress has been made to support the use of lower precision data formats (such as 8-bit data formats) to train deep neural networks. However, traditional systems do not provide hardware support for performing operations using 8-bit floating point format operands. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Therefore, in order that the manner in which the features of the present embodiments set out above may be understood in detail, a more particular description of the embodiments briefly outlined above may be made with reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments and, therefore, should not be considered to limit the scope of the embodiments.

[0006] Figure 1 It is a block diagram of the processing system.

[0007] Figure 2A-2D Illustration of a computing system and a graphics processor.

[0008] Figure 3A-3C A block diagram illustrating an additional graphics processor and computing accelerator architecture.

[0009] Figure 4 is a block diagram of a graphics processing engine of a graphics processor.

[0010] Figure 5A-Figure 5B The diagram includes thread execution logic for an array of processing elements employed in a graphics processor core.

[0011] Figure 6 Figure 1 shows additional execution units.

[0012] Figure 7 is a block diagram illustrating a graphics processor instruction format.

[0013] Figure 8 is a block diagram of the attached graphics processor architecture.

[0014] Figure 9A-9B Diagram of the graphics processor command format and command sequence.

[0015] Fig.10 An example graphical software architecture for a data processing system is illustrated.

[0016] Fig.11A is a block diagram illustrating an IP core development system.

[0017] Fig. 11B A cross-sectional side view of an integrated circuit package assembly is shown.

[0018] Fig. 11C A package assembly is shown that includes a hardware logic chiplet (eg, base die) of multiple units connected to a substrate.

[0019] Fig.11D The illustration shows a package assembly including interchangeable chiplets.

[0020] Fig.12 is a block diagram illustrating an example system-on-a-chip integrated circuit.

[0021] Figure 13A-13B is a block diagram illustrating an example graphics processor for use within a SoC.

[0022] Fig.14 is a block diagram of a data processing system according to an embodiment.

[0023] Fig.15is a block diagram illustrating the Brain Floating Point 8 (BFLOAT8 or BF8) binary format according to an embodiment.

[0024] Fig.16 is a block diagram illustrating systolic DP 8-bit FP format operations performed by an instruction pipeline according to an embodiment.

[0025] Figure 17A-17B is a block diagram illustrating a systolic array circuit for performing systolic point accumulation additions on 8-bit floating point format input operands in accordance with an embodiment.

[0026] Fig.18A Instructions executable by a systolic array circuit according to embodiments described herein are illustrated.

[0027] Fig.18B The program code compiling process according to the embodiment is illustrated.

[0028] Fig.19 is a flow chart illustrating an embodiment of a method for executing an instruction for ripple-point accumulate-add of 8-bit floating point format input operands.

[0029] Fig. 20 is a flow chart illustrating an embodiment of a method for ripple-point accumulation of 8-bit floating point format input operands.

[0030] Fig.21 is a block diagram illustrating an 8-bit FP format conversion operation performed by an instruction pipeline according to an embodiment.

[0031] Fig.22A Instructions executable by a processing unit according to embodiments described herein are illustrated.

[0032] Fig. 22B The program code compiling process according to the embodiment is illustrated.

[0033] Fig.23 is a flow chart illustrating an embodiment of a method for executing instructions for converting floating point data to 8-bit floating point format data.

[0034] Fig.24 is a flow chart illustrating an embodiment of a method for converting floating point data to 8-bit floating point format data.

[0035] Fig.25 is a block diagram illustrating an 8-bit FP format conversion operation with random rounding performed by an instruction pipeline according to an embodiment.

[0036] Fig.26 is a block diagram illustrating fixed-point addition of sign-magnitude representations of mantissa and random numbers according to an embodiment.

[0037] Fig.27AInstructions executable by a processing unit according to embodiments described herein are illustrated.

[0038] Fig.27B The program code compiling process according to the embodiment is illustrated.

[0039] Fig.28 is a flow chart illustrating an embodiment of a method for executing instructions for performing efficient random rounding on floating point values.

[0040] Fig.29 is a flow chart illustrating an embodiment of a method for performing efficient random rounding on floating point values.

[0041] Fig.30 is a block diagram illustrating two 8-bit floating point formats using different binary encodings and exponent biases according to an embodiment.

[0042] Fig.31 is a block diagram illustrating mixed 8-bit FP format systolic operations performed by an instruction pipeline according to an embodiment.

[0043] Fig.32 is a block diagram illustrating a hybrid FMA unit of a systolic array circuit for performing hybrid floating-point systolic operations according to an embodiment.

[0044] Fig.33A Instructions executable by a systolic array circuit according to embodiments described herein are illustrated.

[0045] Fig.33B The program code compiling process according to the embodiment is illustrated.

[0046] Fig.34 is a flow chart illustrating an embodiment of a method for executing instructions for blending floating point systolic operations.

[0047] Fig.35 is a flow chart illustrating an embodiment of a method for blending floating point systolic operations.

[0048] Fig.36 is a block diagram illustrating mixed mode 8-bit FP format operations performed by an instruction pipeline according to an embodiment.

[0049] Fig.37 An example schematic representation of a hardware circuit for performing a mixed mode MAC operation using at least one 8-bit FP format operand according to an embodiment is shown.

[0050] Fig.38A A set of instructions executable by a processing unit according to embodiments described herein is illustrated.

[0051] Fig.38B The program code compiling process according to the embodiment is illustrated.

[0052] Fig.39 is a flow chart illustrating an embodiment of a method for executing instructions for performing mixed mode operations utilizing 8-bit floating point format operands.

[0053] Fig.40 is a flow chart illustrating an embodiment of a method for performing mixed mode operations utilizing 8-bit floating point format operands. DETAILED DESCRIPTION

[0054] A graphics processing unit (GPU) is communicatively coupled to a host / processor core to accelerate, for example, graphics operations, machine learning operations, pattern analysis operations, and / or various general purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to a host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). Alternatively, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0055] In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to those skilled in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the details of the current embodiments. System Overview

[0056] Figure 1 1 is a block diagram of a processing system 100 according to an embodiment. System 100 may be used in a single processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in a mobile device, handheld device, or embedded device, such as for use within an Internet of Things (IoT) device having wired or wireless connectivity to a local area network or a wide area network.

[0057] In one embodiment, the system 100 may include, be coupled with, or be integrated into a server-based gaming platform, a gaming console including a gaming and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is part of a mobile phone, a smart phone, a tablet computing device, or a mobile Internet-connected device such as a notebook with low internal storage capacity. The processing system 100 may also include, be coupled with, or be integrated into a wearable device such as a smart watch wearable device; smart glasses or clothing enhanced with augmented reality (AR) or virtual reality (VR) features to provide visual, audio, or tactile output to supplement the real-world visual, audio, or tactile experience or otherwise provide text, audio, graphics, video, holographic images or video, or tactile feedback; other augmented reality (AR) devices; or other virtual reality (VR) devices. In some embodiments, the processing system 100 includes a television or set-top box device, or is part of a television or set-top box device. In one embodiment, system 100 may include, be coupled to, or be integrated within an autonomous vehicle, such as a bus, a tractor trailer, an automobile, an electric or electrical cycle, an airplane, or a glider (or any combination thereof). The autonomous vehicle may use system 100 to process the environment sensed around the vehicle.

[0058] In some embodiments, one or more processors 102 each include one or more processor cores 107 for processing instructions, which, when executed, perform operations for system or user software. In the embodiments herein, a processor may refer to a dedicated hardware circuit for efficiently processing commands / instructions, and may be referred to as a processor circuit. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, the instruction set 109 may facilitate calculations of complex instruction sets (CISC), reduced instruction set calculations (RISC), or calculations via very long instruction words (VLIW). One or more processor cores 107 may process different instruction sets 109, and different instruction sets 109 may include instructions for facilitating the simulation of other instruction sets. The processor core 107 may also include other processing devices, such as a digital signal processor (DSP).

[0059] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared between various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a third level (L3) cache or a last level cache (LLC)) (not shown), which can be shared between the processor cores 107 using known cache coherence techniques. A register file 106 may additionally be included in the processor 102 and may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0060] In some embodiments, one or more processors 102 are coupled to one or more interface buses 110 to transmit communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 can be a processor bus, such as a version of a direct media interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI express), a memory bus, or other types of interface buses. In one embodiment, the processor(s) 102 include an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connections to I / O devices via a local I / O bus.

[0061] The memory device 120 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device with appropriate performance to act as a process memory. In one embodiment, the memory device 120 may operate as a system memory for the system 100 to store data 122 and instructions 121 for use when one or more processors 102 execute applications or processes. The memory controller 116 is also coupled to an optional external graphics processor 118, which may communicate with one or more graphics processors 108 in the processor 102 to perform graphics operations and media operations. In some embodiments, graphics operations, media operations, or computing operations may be assisted by an accelerator 112, which is a coprocessor that can be configured to perform a collection of specialized graphics operations, media operations, or computing operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator for optimizing machine learning or computing operations. In one embodiment, the accelerator 112 is a ray tracing accelerator that can be used to perform ray tracing operations in concert with the graphics processor 108. In one embodiment, external accelerator 119 may be used instead of accelerator 112 , or may be used in conjunction with accelerator 112 .

[0062] In some embodiments, display device 111 may be connected to processor(s) 102. Display device 111 may be one or more of: an internal display device, such as in a mobile electronic device or laptop device; or an external display device attached via a display interface (e.g., display port, etc.). In one embodiment, display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

[0063] In some embodiments, the platform controller hub 130 enables peripheral devices to be connected to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, a data storage device 124 (e.g., non-volatile memory, volatile memory, hard drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 may be connected via a storage interface (e.g., SATA) or via a peripheral bus (e.g., PCI, PCI express). The touch sensor 125 may include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G or long term evolution (LTE) transceiver. The firmware interface 128 enables communication with the system firmware and may be, for example, a unified extensible firmware interface (UEFI). The network controller 134 may enable a network connection to a wired network. In some embodiments, a high performance network controller (not shown) is coupled to the interface bus 110. In one embodiment, the audio controller 146 is a multi-channel high definition audio controller. In one embodiment, the system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. The platform controller hub 130 may also be connected to one or more Universal Serial Bus (USB) controllers 142 to connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

[0064] It will be appreciated that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured in different manners may also be used. For example, instances of the memory controller 116 and the platform controller hub 130 may be integrated into a discrete external graphics processor, such as the external graphics processor 118. In one embodiment, the platform controller hub 130 and / or the memory controller 116 may be external to one or more processors 102. For example, the system 100 may include the external memory controller 116 and the platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset that communicates with the processor(s) 102.

[0065] For example, a circuit board ("sled") may be used on which components (such as CPUs, memory and other components) are placed, designed to achieve improved thermal performance. In some examples, processing components such as processors are located on the top side of the sled, while nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the enhanced airflow provided by the design, the components can operate at higher frequencies and power levels than typical systems, thereby improving performance. In addition, the sled is configured to blindly mate power and data communication cables in the rack, thereby enhancing their ability to be quickly removed, upgraded, reinstalled and / or replaced. Similarly, the various components (such as processors, accelerators, memory and data storage drives) located on the sled are configured to be easily upgraded due to their increased spacing relative to each other. In an illustrative embodiment, the components additionally include hardware authentication features for proving their authenticity.

[0066] The data center may utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and omni-path. The sleds may be coupled to the switches via optical fiber, which provides higher bandwidth and lower latency than typical twisted pair cabling (e.g., Category 5, Category 5e, Category 6, etc.). Due to the high-bandwidth, low-latency interconnect and network architecture, the data center may, in use, centralize physically disaggregated resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and data storage drives, and provide them to computing resources (e.g., processors) based on requests, thereby enabling the computing resources to access these centralized resources as if the centralized resources were local.

[0067] A power supply or power source may provide voltage and / or current to the system 100 or any component or system described herein. In one example, the power supply includes an AC-DC (alternating current-direct current) adapter for plugging into a wall socket. Such AC power may be a renewable energy (e.g., solar) power source. In one example, the power source includes a DC power source, such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging by approaching a charging field. In one example, the power source may include an internal battery, an AC supply, a motion-based power supply, a solar power supply, or a fuel cell source.

[0068] Figure 2A-2D Illustrated is a computing system and graphics processor provided by embodiments described herein. Figure 2A-2D Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0069] Figure 2A 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. The processor 200 may include additional cores up to and including the additional core 202N represented by the dashed box. Each of the processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache units 206 represent a cache memory hierarchy within the processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a second level (L2), a third level (L3), a fourth level (L4), or other levels of cache, wherein the highest level of cache before the external memory is classified as LLC. In some embodiments, cache coherency logic maintains coherency between cache units 206 and 204A-204N.

[0070] In some embodiments, the processor 200 may further include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI buses or PCI express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, the system agent core 210 includes one or more integrated memory controllers 214 for managing access to various external memory devices (not shown).

[0071] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreaded processing. The system agent core 210 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 202A-202N and the graphics processor 208.

[0072] In some embodiments, the processor 200 additionally includes a graphics processor 208 for performing graphics processing operations. In some embodiments, the graphics processor 208 is coupled to a set of shared cache units 206 and a system agent core 210, which includes one or more integrated memory controllers 214. In some embodiments, the system agent core 210 also includes a display controller 211 for driving the graphics processor output to one or more coupled displays. In some embodiments, the display controller 211 can also be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 208.

[0073] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of the processor 200. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those known in the art. In some embodiments, the graphics processor 208 is coupled to the ring interconnect 212 via an I / O link 213.

[0074] The example I / O link 213 represents at least one of a plurality of various I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 may use the embedded memory module 218 as a shared last-level cache.

[0075] In some embodiments, the processor cores 202A-202N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of the processor cores 202A-202N execute a first instruction set, and at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of computing power. In addition, the processor 200 may be implemented on one or more chips, or implemented as a SoC integrated circuit having the components illustrated in addition to other components.

[0076] Figure 2B is a block diagram of the hardware logic of graphics processor core 219 according to some embodiments described herein. Figure 2BElements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. A graphics processor core 219 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. A graphics processor core 219 is an example of a graphics core slice, and based on a target power envelope and performance envelope, a graphics processor as described herein may include multiple graphics core slices. Each graphics processor core 219 may include a fixed function block 230 coupled to a plurality of sub-cores 221A-221F (also referred to as sub-slices), the plurality of sub-cores 221A-221F including blocks of modular general purpose and fixed function logic.

[0077] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231, which may be shared by all sub-cores in graphics processor core 219, for example, in a lower performance and / or lower power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., as described below). Figure 3A and Figure 4 ), a video front end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., as described below in Figure 4 The unified return buffer 418 in .

[0078] In one embodiment, fixed function block 230 also includes graphics SoC interface 232, graphics microcontroller 233, and media pipeline 234. Graphics SoC interface 232 provides an interface between graphics processor core 219 and other processor cores within the system on chip integrated circuit. Graphics microcontroller 233 is a programmable subprocessor that can be configured to manage various functions of graphics processor core 219, including thread dispatching, scheduling, and preemption. Media pipeline 234 (e.g., Figure 3A and Figure 4 The media pipeline 316 of the embodiment includes logic for facilitating decoding, encoding, pre-processing and / or post-processing of multimedia data including image data and video data. The media pipeline 234 implements media operations via requests to computational or sampling logic within the sub-cores 221A-221F.

[0079] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 232 may also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable the use and / or implementation of global memory atomicity, which may be shared between the graphics processor core 219 and the CPU within the SoC. The SoC interface 232 may also implement power management control for the graphics processor core 219 and enable an interface between the clock domain of the graphics core 219 and other clock domains within the SoC. In one embodiment, the SoC interface 232 enables receiving a command buffer from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of the one or more graphics cores within the graphics processor. These commands and instructions may be dispatched to media pipeline 234 when media operations are to be performed, or to geometry and fixed function pipelines (eg, geometry and fixed function pipeline 231, geometry and fixed function pipeline 237) when graphics processing operations are to be performed.

[0080] The graphics microcontroller 233 may be configured to perform various scheduling and management tasks for the graphics processor core 219. In one embodiment, the graphics microcontroller 233 may perform graphics and / or computational workload scheduling for each graphics parallel engine within the execution unit (EU) arrays 222A-222F, 224A-224F within the sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of a SoC including the graphics processor core 219 may submit a workload via one of a plurality of graphics processor doorbells, which invokes a scheduling operation to the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to the command stream converter, preempting an existing workload running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, graphics microcontroller 233 may also facilitate a low power or idle state for graphics processor core 219, thereby providing graphics processor core 219 with the ability to save and restore registers within graphics processor core 219 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0081] The graphics processor core 219 may have more or fewer sub-cores 221A-221F than those shown, up to N modular sub-cores. For each group of N sub-cores, the graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipelines 237, and additional fixed function logic 238 for accelerating various graphics and compute processing operations. The shared function logic 235 may include the same Figure 4 The shared function logic 420 (e.g., sampler logic, math logic, and / or inter-thread communication logic) associated with the graphics processor core 219 may be a logic unit that can be shared by each N sub-core within the graphics processor core 219. The shared and / or cache memory 236 may be a last-level cache for the set 221A-221F of N sub-cores within the graphics processor core 219, and may also serve as a shared memory accessible by multiple sub-cores. The geometry / fixed function pipeline 237 may be included in the fixed function block 230 instead of the geometry / fixed function pipeline 231, and the geometry / fixed function pipeline 237 may include the same or similar logic units.

[0082] In one embodiment, the graphics processor core 219 includes additional fixed function logic 238, which may include various fixed function acceleration logic for use by the graphics processor core 219. In one embodiment, the additional fixed function logic 238 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a full geometry pipeline within the geometry / fixed function pipelines 238, 231; and a culling pipeline, which is an additional geometry pipeline that may be included in the additional fixed function logic 238. In one embodiment, the culling pipeline is a streamlined version of the full geometry pipeline. The full pipeline and the culling pipeline can execute different instances of the same application, each with a separate context. Position-only shading can hide long culling runs for discarded triangles, thereby enabling shading to be completed earlier in some instances. For example and in one embodiment, the culling pipeline logic within the additional fixed function logic 238 can execute the position shader in parallel with the main application and generally generate results faster than the full pipeline because the culling pipeline only takes the position attributes of the vertices and shades them without performing rasterization and rendering of the pixels to the frame buffer. The culling pipeline can use the generated results to calculate visibility information for all triangles, regardless of whether those triangles are culled. The full pipeline (which can be referred to as a replay pipeline in this example) can consume this visibility information to skip culled triangles, thereby only shading visible triangles that are ultimately passed to the rasterization stage.

[0083] In one embodiment, the additional fixed function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, which is used to include an optimized implementation for machine learning training or inference.

[0084] Included within each graphics sub-core 221A-221F is a collection of execution resources that can be used to perform graphics operations, media operations, and compute operations in response to requests made by a graphics pipeline, a media pipeline, or a shader program. Graphics sub-cores 221A-221F include: multiple EU arrays 222A-222F, 224A-224F; thread dispatch and inter-thread communication (TD / IC) logic 223A-223F; 3D (e.g., texture) samplers 225A-225F; media samplers 206A-206F; shader processors 227A-227F; and shared local memory (SLM) 228A-228F. EU arrays 222A-222F, 224A-224F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics operations, media operations, or computing operations (including graphics programs, media programs, or computing shader programs). TD / IC logic 223A-223F performs local thread dispatch and thread control operations for execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. 3D samplers 225A-225F can read textures or other 3D graphics-related data into memory. 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. Media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 221A-221F can alternately include unified 3D and media samplers. Threads executing on execution units within each of the sub-cores 221A-221F may utilize shared local memory 228A-228F within each sub-core, such that threads executing within a thread group can execute using a common pool of on-chip memory.

[0085] Figure 2C A graphics processing unit (GPU) 239 is illustrated that includes a collection of dedicated graphics processing resources arranged as multi-core groups 240A-240N. While details of only a single multi-core group 240A are provided, it will be understood that other multi-core groups 240B-240N may be equipped with the same or similar collection of graphics processing resources.

[0086] As illustrated, multi-core group 240A may include a set 243 of graphics cores, a set 244 of tensor cores, and a set 245 of ray tracing cores. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set 242 of register files stores operand values ​​used by cores 243, 244, 245 when executing graphics threads. These register files may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and slice registers for storing tensor / matrix values. In one embodiment, the slice registers are implemented as a set of combined vector registers.

[0087] One or more combined first level (L1) caches and shared memory units 247 store graphics data locally within each multi-core group 240A, such as texture data, vertex data, pixel data, light data, bounding volume data, etc. One or more texture units 247 may also be used to perform texture operations, such as texture mapping and sampling. A second level (L2) cache 253 shared by all multi-core groups 240A-240N or a subset of multi-core groups 240A-240N stores graphics data and / or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 253 may be shared across multiple multi-core groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to a memory 249, which may be a system memory (e.g., DRAM) and / or a dedicated graphics memory (e.g., GDDR6 memory).

[0088] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as digital signal processors (DSPs), network controllers, or user input devices. On-chip interconnects may be used to couple I / O devices 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O devices 252 to system memory 249. In one embodiment, IOMMU 251 manages page tables for mapping virtual addresses to multiple sets of physical addresses in system memory 249. In this embodiment, I / O devices 252, CPU(s) 246, and GPU(s) 239 may share the same virtual address space.

[0089] In one implementation, the IOMMU 251 supports virtualization. In this case, the IOMMU 251 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 249). The base address of each of the first set of page tables and the second set of page tables can be stored in a control register and swapped out upon context switch (e.g., so that the new context is provided with access to the relevant set of page tables). Although not described in detail in the prior art, the IOMMU 251 can manage a first set of page tables for mapping guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables for mapping guest / graphics physical addresses to system / host physical addresses (e.g., within system memory 249). Figure 2C , but each of the cores 243, 244, 245 and / or multi-core groups 240A-240N may include a translation lookaside buffer (TLB) that is used to cache guest virtual to guest physical translations, guest physical to host physical translations, and guest virtual to host physical translations.

[0090] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated on a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated on the same chip, or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, but the underlying principles of the embodiments herein are not limited to this particular implementation.

[0091] In one embodiment, the tensor core 244 includes multiple execution units specifically designed to perform matrix operations, which are basic computational operations for performing deep learning operations. For example, synchronized matrix multiplication operations can be used for neural network training and inference. The tensor core 244 can perform matrix processing using a variety of operand precisions, including single-precision floating point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half bytes (4 bits). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0092] In a deep learning implementation, parallel matrix multiplication work can be scheduled for execution on the tensor core 244. The training of neural networks, among other things, utilizes a large number of matrix dot product operations. To handle the inner product formulation of the N x N x N matrix multiplication, the tensor core 244 may include at least N dot product processing elements. Before the matrix multiplication begins, a complete matrix is ​​loaded into the slice register, and for each of the N cycles, at least one column of the second matrix is ​​loaded. For each cycle, there are N dot products that are processed.

[0093] Depending on the specific implementation, matrix elements can be stored in different precisions, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit nibbles (e.g., INT4). Different precision modes can be specified for the tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., such as inference workloads, which can tolerate quantization to bytes and nibbles).

[0094] In one embodiment, the ray tracing core 245 accelerates ray tracing operations for both real-time ray tracing implementations and non-real-time ray tracing implementations. Specifically, the ray tracing core 245 includes a ray traversal / intersection circuit for performing ray traversals using a bounding volume hierarchy (BVH) and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 245 may also include circuits for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing core 245 performs traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be performed on the tensor core 244. For example, in one embodiment, the tensor core 244 implements a deep learning neural network to perform denoising on frames generated by the ray tracing core 245. However, the CPU(s) 246, the graphics core 243, and / or the ray tracing core 245 may also implement all or part of the denoising and / or deep learning algorithms.

[0095] In addition, as described above, a distributed approach to denoising may be employed in which the GPU 239 is in a computing device coupled to other computing devices via a network or high-speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0096] In one embodiment, the ray tracing core 245 handles all BVH traversals and ray-primitive intersections, thereby preventing the graphics core 243 from being overloaded with thousands of instructions for each ray. In one embodiment, each ray tracing core 245 includes a first set of specialized circuits for performing bounding box tests (e.g., for traversal operations) and a second set of specialized circuits for performing ray-triangle intersection tests (e.g., intersecting rays that have been traversed). Thus, in one embodiment, the multi-core group 240A can simply initiate ray detection, and the ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hits, no hits, multiple hits, etc.) to the thread context. While the ray tracing core 245 performs traversal and intersection operations, the other cores 243, 244 are freed up to perform other graphics or computational work.

[0097] In one embodiment, each ray tracing core 245 includes a traversal unit for performing BVH test operations and an intersection unit for performing ray-primitive intersection tests. The intersection unit generates a "hit", "no hit", or "multiple hits" response, which it provides to the appropriate thread. During traversal and intersection operations, execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed up to perform other forms of graphics work.

[0098] In one particular embodiment described below, a hybrid rasterization / ray tracing approach is used in which the work is distributed between graphics core 243 and ray tracing core 245.

[0099] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set, such as Microsoft's DirectX Ray Tracing (DXR), which includes the DispatchRays command; and ray generation shaders, nearest hit shaders, any hit shaders, and miss shaders, which enable the assignment of a set of shaders and textures for each object. Another ray tracing platform that can be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it is noted that the underlying principles of the embodiments herein are not limited to any particular ray tracing ISA.

[0100] In general, each core 245, 244, 243 may support a ray tracing instruction set including instructions / functions for: ray generation, nearest hit, any hit, ray-primitive intersection, per-primitive and hierarchy bounding box construction, misses, visits, and exceptions. More specifically, one embodiment includes ray tracing instructions for performing the following functions:

[0101] Light Generation - Executes ray generation instructions for each pixel, sample, or other user-defined work distribution.

[0102] Recent Hits - A nearest hit command may be executed to locate the closest intersection of a ray with a primitive within the scene.

[0103] Any hit - Any hit instruction identifies multiple intersections between rays and primitives within the scene, thereby potentially identifying new closest intersection points.

[0104] intersect ——The intersection instruction performs a ray-primitive intersection test and outputs the result.

[0105] Per-primitive bounding box construction- This instruction builds a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0106] miss - Indicates that the ray missed the scene or all geometry within a specified region of the scene.

[0107] Visits – Indicates the subvolumes that the ray will traverse.

[0108] abnormal -- Includes various types of exception handlers (e.g., called for various error conditions).

[0109] Figure 2D 2 is a block diagram of a general purpose graphics processing unit (GPGPU) 270 according to an embodiment described herein, which GPGPU 270 can be configured as a graphics processor and / or a computing accelerator. GPGPU 270 can be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that can be shared with one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 can be mapped to memory addresses accessible by one or more CPUs 246. Access to memories 271 and 272 can be facilitated via a memory controller 268. In one embodiment, memory controller 268 includes an internal direct memory access (DMA) controller 269, or can include logic for performing operations that would otherwise be performed by a DMA controller.

[0110] GPGPU 270 includes a plurality of cache memories, including an L2 cache 253, an L1 cache 254, an instruction cache 255, and a shared memory 256, at least a portion of which may also be partitioned as cache memories. GPGPU 270 also includes a plurality of compute units 260A-260N. Each compute unit 260A-260N includes a set 261 of vector registers, a set 262 of scalar registers, a set 263 of vector logic units, and a set 264 of scalar logic units. Computing units 260A-260N may also include a local shared memory 265 and a program counter 266. Computing units 260A-260N may be coupled to a constant cache 267, which may be used to store constant data, which is data that will not change during the execution of a kernel program or a shader program executed on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data may be fetched directly into scalar registers 262 .

[0111] During operation, one or more CPUs 246 may write commands to registers in GPGPU 270, or to memory in GPGPU 270 that has been mapped into an accessible address space. Command processor 257 may read commands from registers or memory and determine how to process those commands within GPGPU 270. Thread dispatcher 258 may then be used to dispatch threads to computing units 260A-260N to execute those commands. Each computing unit 260A-260N may execute threads independently of other computing units. In addition, each computing unit 260A-260N may be independently configured for conditional computation and may conditionally output the results of the computation to memory. Command processor 257 may interrupt one or more CPUs 246 when the submitted commands are completed.

[0112] Figure 3A-3C Block diagram illustrating additional graphics processor and computing accelerator architectures provided by embodiments described herein. Figure 3A-3C Those elements having the same reference numerals (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0113] Figure 3A3 is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores or other semiconductor devices, such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and using commands placed into processor memory. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0114] In some embodiments, the graphics processor 300 also includes a display controller 302 for driving display output data to a display device 318. The display controller 302 includes hardware for compositing one or more overlay planes and multiple layers of video or user interface elements for a display. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, the graphics processor 300 includes a video codec engine 306 for encoding media to one or more media coding formats, decoding media from one or more media coding formats, or transcoding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as, MPEG-2), Advanced Video Coding (AVC) formats (such as, H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as, JPEG, and Motion JPEG (MJPEG) formats).

[0115] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0116] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed-function elements that perform various tasks within the element and / or spawn execution threads to 3D / media subsystem 315. While 3D pipeline 312 may be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0117] In some embodiments, the media pipeline 316 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, instead of, or on behalf of, the video codec engine 306. In some embodiments, the media pipeline 316 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 315. The generated threads perform calculations for media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0118] In some embodiments, the 3D / media subsystem 315 includes logic for executing threads generated by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D threads and media threads. In some embodiments, the 3D / media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes a shared memory for sharing data between threads and for storing output data, which includes registers and addressable memory.

[0119] Figure 3B A graphics processor 320 having a tiled architecture is shown in accordance with an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having graphics engine slices 310A-310D. Figure 3A310D. Each graphics engine slice 310A-310D may be interconnected via a set 323A-323F of slice interconnects. Each graphics engine slice 310A-310D may also be connected to a memory module or memory device 326A-326D via a memory interconnect 325A-325D. The memory device 326A-326D may use any graphics memory technology. For example, the memory device 326A-326D may be a graphics double data rate (GDDR) memory. In one embodiment, the memory device 326A-326D is a high bandwidth memory (HBM) module that may be on a die with its corresponding graphics engine slice 310A-310D. In one embodiment, the memory device 326A-326D is a stacked memory device that may be stacked on top of their corresponding graphics engine slice 310A-310D. In one embodiment, each graphics engine slice 310A-310D and associated memory 326A-326D resides on separate chiplets that are bonded to a base die or base substrate, such as in Figure 11B-Figure 11D As described in further detail in .

[0120] Graphics processor 320 may be configured with a non-uniform memory access (NUMA) system in which memory devices 326A-326D are coupled to associated graphics engine slices 310A-310D. A given memory device may be accessed by a different slice than the graphics engine slice to which the memory device is directly connected. However, access latency to memory devices 326A-326D may be minimal when accessing the local slice. In one embodiment, a cache-consistent NUMA (ccNUMA) system is enabled that uses slice interconnects 323A-323F to enable communication between cache controllers within graphics engine slices 310A-310D to maintain consistent memory mirroring when more than one cache stores the same memory location.

[0121] The graphics processing engine cluster 322 may be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 may enable communication between the graphics engine slices 310A-310D and components such as the video codec 306 and one or more replica engines 304. The replica engines 304 may be used to move data out of the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory), move data into the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory), and move data between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 may also be used to interconnect the graphics engine slices 310A-310D. The graphics processor 320 may optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor may also be configured as a graphics accelerator or a computing accelerator. In an accelerometer configuration, display controller 302 and display device 318 may be omitted.

[0122] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCIexpress bus or another type of host system interface.

[0123] Figure 3C FIG. 3 shows a computing accelerator 330 according to an embodiment described herein. The computing accelerator 330 may include Figure 3B The computing engine cluster 332 may include a set 340A-340D of computing engine slices, which include execution logic optimized for parallel or vector-based general computing operations. In some embodiments, the computing engine slices 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computing engine slices 340A-340D may include logic for performing media acceleration. The computing engine slices 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and the memory interconnects 325A-325D may be technologies similar to those in the graphics processor 320, or may be different technologies. The graphics compute engine slices 340A-340D may also be interconnected via a set of slice interconnects 323A-323F and may be connected to and / or interconnected by a fabric interconnect 324. In one embodiment, the compute accelerator 330 includes a large L3 cache 336 that may be configured as a device-wide cache. The compute accelerator 330 may also be configured to communicate with the CPU 324. Figure 3B The graphics processor 320 in FIG. 1 is connected to a host processor and memory via a host interface 328 in a similar manner. Graphics processing engine

[0124] Figure 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is Figure 3A A version of the GPE 310 shown in FIG. Figure 3B The graphics engine slices 310A-310D in FIG. Figure 4 Elements having the same reference numeral (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Figure 3A 410. The 3D pipeline 312 and the media pipeline 316 of the GPE 410. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included in the GPE 410. For example and in at least one embodiment, separate media and / or image processors are coupled to the GPE 410.

[0125] In some embodiments, GPE 410 is coupled to or includes a command stream converter 403, which provides a command stream to 3D pipeline 312 and / or media pipeline 316. In some embodiments, command stream converter 403 is coupled to a memory, which can be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 403 receives commands from the memory and sends these commands to 3D pipeline 312 and / or media pipeline 316. These commands are instructions taken from a circular buffer that stores commands for 3D pipeline 312 and media pipeline 316. In one embodiment, the circular buffer may additionally include a batch command buffer that stores a batch of multiple commands. Commands for 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex data and geometry data for 3D pipeline 312 and / or image data and memory objects for media pipeline 316. 3D pipeline 312 and media pipeline 316 process commands and data by executing operations via logic within the respective pipelines or by dispatching one or more execution threads to graphics core array 414. In one embodiment, graphics core array 414 includes blocks of one or more graphics cores (e.g., (multiple) graphics cores 415A, (multiple) graphics cores 415B), each block including one or more graphics cores. Each graphics core includes a collection of graphics execution resources, including: general execution logic and graphics-specific execution logic for performing graphics operations and computing operations; and fixed-function texture processing logic and / or machine learning and artificial intelligence acceleration logic.

[0126] In various embodiments, the 3D pipeline 312 may include fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified execution resource block for use in processing these shader programs. The multi-function execution logic (e.g., execution unit) within the (multiple) graphics cores 415A-415B of the graphics core array 414 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0127] In some embodiments, graphics core array 414 includes execution logic for performing media functions such as video and / or image processing. In one embodiment, the execution units include general purpose logic that is programmable to perform parallel general purpose computing operations in addition to performing graphics processing operations. The general purpose logic may be combined with other general purpose computing operations in parallel. Figure 1 (multiple) processor cores 107 or Figure 2A The processing operations are performed by the general logic within the cores 202A-202N.

[0128] Output data generated by threads executing on graphics core array 414 may output data to memory in unified return buffer (URB) 418. URB 418 may store data for multiple threads. In some embodiments, URB 418 may be used to send data between different threads executing on graphics core array 414. In some embodiments, URB 418 may additionally be used for synchronization between threads on the graphics core array and fixed function logic within shared function logic 420.

[0129] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled.

[0130] The graphics core array 414 is coupled to shared function logic 420, which includes a plurality of resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logic 420 are hardware logic units that provide specialized, complementary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421 logic, math 422 logic, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 within the shared function logic 420.

[0131] Shared functionality is implemented at least in cases where demand for a given specialized functionality is insufficient to be included in the graphics core array 414. Instead, a single instantiation of that specialized functionality is implemented as an independent entity in the shared functionality logic 420 and is shared between execution resources within the graphics core array 414. The exact set of functions that are shared between the graphics core array 414 and included within the graphics core array 414 varies from embodiment to embodiment. In some embodiments, specific shared functionality within the shared functionality logic 420 that is widely used by the graphics core array 414 may be included within the shared functionality logic 416 within the graphics core array 414. In various embodiments, the shared functionality logic 416 within the graphics core array 414 may include some or all of the logic within the shared functionality logic 420. In one embodiment, all logic elements within the shared functionality logic 420 may be replicated within the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared functionality logic 420 is excluded in favor of the shared functionality logic 416 within the graphics core array 414. Execution Unit

[0132] Figure 5A-Figure 5B Thread execution logic 500 is illustrated including an array of processing elements employed in a graphics processor core, according to embodiments described herein. Figure 5A-Figure 5B Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Figure 5A-Figure 5B An overview of thread execution logic 500 is shown, which may represent a Figure 2B The hardware logic of each sub-core 221A-221F is shown in FIG. Figure 5A represents an execution unit within a general-purpose graphics processor, and Figure 5B Represents an execution unit that can be used within a computing accelerator.

[0133] As in Figure 5AAs shown in FIG. 5 , in some embodiments, thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including a plurality of execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., execution units 508A, 508B, 508C, 508D, up to any one of 508N-1 and 508N) based on the computational requirements of the workload. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, thread execution logic 500 includes one or more connections to a memory (such as a system memory or a cache memory) through the instruction cache 506, the data port 514, the sampler 510, and one or more of the execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a self-contained programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of separate execution units.

[0134] In some embodiments, execution units 508A-508N are primarily used to execute shader programs. Shader processor 502 can process various shader programs and can dispatch execution threads associated with shader programs via thread dispatcher 504. In one embodiment, thread dispatcher includes logic for arbitrating thread initiation requests from graphics pipelines and media pipelines and instantiating the requested threads on one or more execution units in execution units 508A-508N. For example, a geometry pipeline can dispatch vertex shaders, tessellation shaders, or geometry shaders to thread execution logic for processing. In some embodiments, thread dispatcher 504 can also process runtime thread generation requests from executed shader programs.

[0135] In some embodiments, execution units 508A-508N support an instruction set including native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. These execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). Each execution unit in execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operations enable efficient execution environments in the face of high latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and an associated independent thread state. For pipelines capable of integer operations, single-precision floating-point operations, and double-precision floating-point operations, capable of SIMD branching capabilities, capable of logical operations, capable of transcendental operations, and capable of other miscellaneous operations, execution is for multiple issues per clock. While waiting for data from a shared function in memory or a shared function, dependency logic within execution units 508A-508N puts the waiting thread to sleep until the requested data has returned. While the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, a fragment shader, or another type of shader program including different vertex shaders. Embodiments may be applied to use execution utilizing single instruction multiple threads (SIMT) as an alternative to the use of SIMD, or as an addition to the use of SIMD. References to SIMD cores or operations may also be applied to SIMT, or to a combination of SIMD and SIMT.

[0136] Each execution unit in execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size," or number of lanes for an instruction. An execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) used for a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0137] The execution unit instruction set includes SIMD instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process each element based on the data size of the element. For example, when a 256-bit wide vector is operated, 256 bits of the vector are stored in registers, and the execution unit operates the vector as four separate 64-bit compact data elements (quad word (QW) size data elements), eight separate 32-bit compact data elements (double word (DW) size data elements), sixteen separate 16-bit compact data elements (word (W) size data elements) or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

[0138] In one embodiment, one or more execution units may be combined into a fused execution unit 509A-509N having a thread control logic (507A-507N) common to the fused EU. Multiple EUs may be fused into a EU group. Each EU in a fused EU group may be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group may vary according to the embodiment. In addition, various SIMD widths may be executed EU by EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 509A-509N includes at least two execution units. For example, a fused execution unit 509A includes a first EU 508A, a second EU 508B, and a thread control logic 507A common to the first EU 508A and the second EU 508B. Thread control logic 507A controls threads executing on fused graphics execution unit 509A, allowing each EU within fused execution units 509A-509N to execute using a common instruction pointer register.

[0139] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 512) are included to cache thread data during thread execution. Threads executed on the execution logic 500 may also store explicitly managed data in the shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 510 includes specialized texture or media sampling functions to process texture data or media data during the sampling process before providing the sampled data to the execution unit.

[0140] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 500 via thread generation and dispatch logic. Once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 502 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader calculates the value of each vertex attribute, and the value of each vertex attribute is interpolated across the rasterized object. In some embodiments, the pixel processor logic within the shader processor 502 then executes the pixel shader program or fragment shader program supplied by the application programming interface (API). To execute the shader program, the shader processor 502 dispatches the thread to the execution unit (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses the texture sampling logic in the sampler 510 to access the texture data in the texture map stored in the memory. Arithmetic operations on texture data and input geometry data compute pixel color data for each geometry fragment, or discard one or more pixels without further processing.

[0141] In some embodiments, data port 514 provides a memory access mechanism for thread execution logic 500 to output processed data to memory for further processing in the graphics processor output pipeline. In some embodiments, data port 514 includes or is coupled to one or more cache memories (e.g., data cache 512) to cache data for memory access via the data port.

[0142] In one embodiment, the execution logic 500 may also include a ray tracer 505 that can provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be used with Figure 2C The ray tracing instruction set supported by the ray tracing core 245 in may be similar or different.

[0143] Figure 5BExample internal details of an execution unit 508 are illustrated in accordance with an embodiment. Graphics execution unit 508 may include instruction fetch unit 537, general register file array (GRF) 524, architectural register file array (ARF) 526, thread arbiter 522, issue unit 530, branch unit 532, set 534 of SIMD floating point units (FPUs), and set 535 of dedicated integer SIMD ALUs in one embodiment. GRF 524 and ARF 526 include a set of general register files and architectural register files associated with each simultaneous hardware thread that may be active in graphics execution unit 508. In one embodiment, per-thread architectural state is maintained in ARF 526, while data used during thread execution is stored in GRF 524. The execution state of each thread, including the instruction pointer for each thread, may be maintained in thread-specific registers in ARF 526.

[0144] In one embodiment, graphics execution unit 508 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are divided across logic for executing multiple simultaneous threads. The number of logical threads that can be executed by graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0145] In one embodiment, the graphics execution unit 508 may issue multiple instructions in coordination, which may each be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 may dispatch the instruction to one of the following for execution: the send unit 530, the branch unit 532, or (multiple) SIMD FPUs 534. Each execution thread may access 128 general registers within the GRF 524, wherein each register may store 32 bytes accessible as a SIMD 8 element vector with 32-bit data elements. In one embodiment, each execution unit thread has access to 4 kilobytes within the GRF 524, but the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. In one embodiment, the graphics execution unit 508 is partitioned into seven hardware threads that may independently perform computing operations, but the number of threads of each execution unit may also vary according to the embodiment. For example, in one embodiment, up to 16 hardware threads are supported. In an embodiment in which seven threads may access 4 kilobytes, the GRF 524 may store a total of 28 kilobytes. With 16 threads accessing 4 kilobytes, a total of 64 kilobytes can be stored by GRF 524. Flexible addressing modes may permit multiple registers to be addressed together, creating effectively wider registers or representing strided rectangular block data structures.

[0146] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched via "send" instructions executed through message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to facilitate SIMD divergence and eventual convergence.

[0147] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 for performing floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 534 can SIMD perform up to a number M of 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capabilities that support high throughput transcendental math functions and double precision 64-bit floating points. In some embodiments, a set 535 of 8-bit integer SIMD ALUs also exists and can be specifically optimized to perform operations associated with machine learning calculations.

[0148] In one embodiment, an array of multiple instances of graphics execution unit 508 may be instantiated in graphics sub-core groupings (e.g., sub-slices). For scalability, product architects may choose the exact number of execution units per sub-core grouping. In one embodiment, execution unit 508 may execute instructions across multiple execution lanes. In further embodiments, each thread executed on graphics execution unit 508 is executed on a different lane.

[0149] Figure 6 An additional execution unit 600 according to an embodiment is shown. The execution unit 600 may be a processor for executing, for example, Figure 3C The execution unit 600 may be a computationally optimized execution unit used in the computing engine slices 340A-340D in the embodiment of the present invention, but is not limited thereto. A variation of the execution unit 600 may also be used in the embodiment of the present invention. Figure 3B 310D in the graphics engine slices 310A-310D. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604 (also referred to herein as a decoder). The execution unit 600 additionally includes a register file 606, which stores registers that can be assigned to hardware threads within the execution unit. The execution unit 600 additionally includes a dispatch unit 607 and a branch unit 608. In one embodiment, the dispatch unit 607 and the branch unit 608 can be used in conjunction with Figure 5B The dispatch unit 530 and the branch unit 532 of the graphics execution unit 508 in FIG. 5 operate in a similar manner.

[0150] The execution unit 600 also includes a computation unit 610, which includes a plurality of functional units of different types. In one embodiment, the computation unit 610 includes an ALU unit 611, which includes an array of arithmetic logic units. The ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. Integer and floating point operations can be performed simultaneously. The computation unit 610 can also include a systolic array 612 and a math unit 613. The systolic array 612 includes a wide W and deep D network of data processing units, which can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, the systolic array 612 can be configured to perform matrix operations, such as matrix dot product operations. In one embodiment, the systolic array 612 supports 16-bit floating point operations and 8-bit and 4-bit integer operations. In one embodiment, the systolic array 612 can be configured to accelerate machine learning operations. In such embodiments, the systolic array 612 can be configured with support for the bfloat 16-bit floating point format. In one embodiment, math unit 613 may be included to perform a specific subset of math operations in an efficient and lower power manner than ALU unit 611. Math unit 613 may include math logic that may be found in shared functional logic of a graphics processing engine provided by other embodiments (e.g., Figure 4 In one embodiment, math unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0151] Thread control unit 601 includes logic for controlling the execution of threads within execution units. Thread control unit 601 may include thread arbitration logic for starting, stopping, and preempting the execution of threads within execution unit 600. Thread state unit 602 may be used to store thread states for threads assigned to execute on execution unit 600. Storing thread states within execution unit 600 enables fast preemption of threads when they become blocked or idle. Instruction fetch / prefetch unit 603 may fetch instructions from an instruction cache of higher level execution logic (e.g., Figure 5A The instruction fetch / prefetch unit 603 may also issue prefetch requests for instructions to be loaded into the instruction cache based on an analysis of the current execution thread. The instruction decode unit 604 may be used to decode instructions to be executed by the computing unit. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into constituent micro-operations.

[0152] Execution unit 600 additionally includes a register file 606 that can be used by hardware threads executing on execution unit 600. Registers in register file 606 can be divided across logic used to execute multiple simultaneous threads within compute unit 610 of execution unit 600. The number of logical threads that can be executed by graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 606 can vary from embodiment to embodiment based on the number of hardware threads supported. In one embodiment, register renaming can be used to dynamically assign registers to hardware threads.

[0153] Figure 7 700 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, the graphics processor execution unit supports an instruction set of instructions in multiple formats. Solid line boxes illustrate components that are typically included in the execution unit instructions, while dashed lines include components that are optional or included only in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations that result from instruction decoding that is performed once the instruction is processed.

[0154] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit instruction format 710. Based on the selected instructions, instruction options, and number of operands, 64-bit compact instruction format 730 can be used for some instructions. Native 128-bit instruction format 710 provides access to all instruction options, while some options and operations are limited in 64-bit format 730. The native instructions available in 64-bit format 730 vary from embodiment to embodiment. In some embodiments, the instruction is partially compressed using a set of index values ​​in index field 713. The execution unit hardware references a set of compression tables based on the index values ​​and uses the compression table output to reconstruct the native instructions of 128-bit instruction format 710. Instructions of other sizes and formats can be used.

[0155] For each format, the instruction opcode 712 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a synchronous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 714 enables control of certain execution options, such as channel selection (e.g., assertion) and data channel order (e.g., mixing). For instructions of the 128-bit instruction format 710, the execution size field 716 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 716 is not available for the 64-bit compact instruction format 730.

[0156] Some execution unit instructions have up to three operands, including two source operands src0 720, src1 722, and one destination operand 718. In some embodiments, the execution unit supports dual destination instructions, where one of the dual destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 724), where the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed with the instruction.

[0157] In some embodiments, the 128-bit instruction format 710 includes an access / addressing mode field 726 that specifies, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly by bits in the instruction.

[0158] In some embodiments, the 128-bit instruction format 710 includes an access / addressing mode field 726 that specifies the addressing mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in a first mode, the instruction may use byte-aligned addressing for source operands and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source operands and destination operands.

[0159] In one embodiment, the addressing mode portion of the access / addressing mode field 726 determines whether the instruction uses direct addressing or indirect addressing. When direct register addressing mode is used, the bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0160] In some embodiments, instructions are grouped based on the opcode 712 bit field to simplify opcode decoding 740. For 8-bit opcodes, bit 4, bit 5, and bit 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is only an example. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares five most significant bits (MSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. The flow control instruction group 744 (e.g., call (call), jump (jmp)) includes the instruction of 0010xxxxb (e.g., 0x20) form. The miscellaneous instruction group 746 includes a mixture of instructions, including the synchronization instruction (e.g., wait (wait), send (send)) of 0011xxxxb (e.g., 0x30) form. The parallel math instruction group 748 includes component-by-component arithmetic instructions (e.g., add, multiply (mul)) of the form 0100xxxxb (e.g., 0x40). The parallel math group 748 performs arithmetic operations in parallel across data channels. The vector math group 750 includes arithmetic instructions (e.g., dp4) of the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic on vector operands, such as dot product calculations. In one embodiment, the illustrated opcode decode 740 can be used to determine which portion of the execution unit will be used to execute the decoded instructions. For example, some instructions may be designated as systolic instructions to be executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), may be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution logic. Graphics Pipeline

[0161] Figure 8 is a block diagram of another embodiment of a graphics processor 800 . Figure 8 Elements having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0162] In some embodiments, the graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, a thread execution logic 850, and a rendering output pipeline 870. In some embodiments, the graphics processor 800 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 800 through the ring interconnect 802. In some embodiments, the ring interconnect 802 couples the graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 802 are interpreted by a command stream converter 803, which supplies instructions to various components of the geometry pipeline 820 or the media pipeline 830.

[0163] In some embodiments, the command stream converter 803 directs the operation of the vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 803. In some embodiments, the vertex fetcher 805 provides the vertex data to the vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 805 and the vertex shader 807 execute the vertex processing instructions by dispatching execution threads to the execution units 852A-852B via the thread dispatcher 831.

[0164] In some embodiments, execution units 852A-852B are arrays of vector processors with instruction sets for performing graphics operations and media operations. In some embodiments, execution units 852A-852B have an attached L1 cache 851 that is dedicated to each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or partitioned into a single cache containing data and instructions in different partitions.

[0165] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, the programmable shell shader 811 configures the tessellation operation. The programmable domain shader 817 provides back-end evaluation of the tessellation output. The tessellation device 813 operates under the instruction of the shell shader 811 and contains dedicated logic for generating a detailed set of geometric objects based on a rough geometric model, which is provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, the tessellation component (e.g., the shell shader 811, the tessellation device 813, and the domain shader 817) can be bypassed. The tessellation component can operate based on data received from the vertex shader 807.

[0166] In some embodiments, the complete geometric object may be processed by the geometry shader 819 via one or more threads dispatched to the execution units 852A-852B, or may proceed directly to the clipper 829. In some embodiments, the geometry shader operates on the entire geometric object rather than on vertices or vertex patches as in previous stages of the graphics pipeline. If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation when the tessellation unit is disabled.

[0167] Before rasterization, the clipper 829 processes the vertex data. The clipper 829 can be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, the rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches a pixel shader to convert the geometric object into a pixel-by-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 850. In some embodiments, the application can bypass the rasterizer and depth test component 873 and access the unrasterized vertex data via the outflow unit 823.

[0168] The graphics processor 800 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) are interconnected via data ports 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 can also be configured as a sampler cache.

[0169] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. In some embodiments, an associated rendering cache 878 and depth cache 879 are also available. The pixel operation component 877 performs pixel-based operations on data, but in some instances, pixel operations associated with 2D operations (e.g., using mixed bit block image transfer) are performed by the 2D engine 841, or replaced by the display controller 843 using an overlay display plane when displaying. In some embodiments, a shared L3 cache 875 can be used for all graphics components, allowing data to be shared without using main system memory.

[0170] In some embodiments, the graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from the command stream converter 803. In some embodiments, the media pipeline 830 includes a separate command stream converter. In some embodiments, the video front end 834 processes the media commands before sending them to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function for generating threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0171] In some embodiments, the graphics processor 800 includes a display engine 840. In some embodiments, the display engine 840 is external to the processor 800 and is coupled to the graphics processor via the ring interconnect 802, or some other interconnect bus or structure. In some embodiments, the display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, the display engine 840 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 843 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer) or an external display device attached via a display device connector.

[0172] In some embodiments, geometry pipeline 820 and media pipeline 830 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not dedicated to any application programming interface (API). In some embodiments, the driver software for the graphics processor converts the API call dedicated to a specific graphics or media library into a command that can be processed by the graphics processor. In some embodiments, all open graphics libraries (OpenGL), open computing language (OpenCL) and / or Vulkan graphics and computing APIs from Khronos Group are provided with support. In some embodiments, support can also be provided for the Direct3D library from Microsoft. In some embodiments, the combination of these libraries can be supported. Support can also be provided for the open source computer vision library (OpenCV). If the mapping from the pipeline of the future API to the pipeline of the graphics processor can be carried out, the future API with compatible 3D pipelines will also be supported. Graphics pipeline programming

[0173] Fig. 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Fig. 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. Fig. 9A The solid-line boxes in illustrate components that are generally included in the graphics commands, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig. 9A The example graphics processor command format 900 includes data fields for identifying the client 902 of the command, a command operation code (opcode) 904, and data 906. A sub-opcode 905 and a command size 908 are also included in some commands.

[0174] In some embodiments, client 902 specifies the client unit of processing command data of graphics device. In some embodiments, graphics processor command parser checks the client field of each command to adjust the further processing of command and route command data to appropriate client unit. In some embodiments, graphics processor client unit includes memory interface unit, rendering unit, 2D unit, 3D unit and media unit. Each client unit has corresponding processing pipeline for processing command. Once command is received by client unit, client unit reads opcode 904 and sub-opcode 905 (if exists) to determine the operation to be performed. Client unit uses information in data field 906 to execute command. For some commands, explicit command size 908 is expected to specify the size of command. In some embodiments, command parser automatically determines the size of at least some commands in command based on command opcode. In some embodiments, command is aligned via multiples of double word. Other command formats can be used.

[0175] Fig. 9B 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to establish, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these particular commands or command sequences. Moreover, commands may be issued as batches of commands in a command sequence so that the graphics processor will process the command sequence in an at least partially concurrent manner.

[0176] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline dump clear command 912 to cause any active graphics pipeline to complete the currently pending commands of the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate concurrently. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active painting engine completes the pending operation and the associated read cache is invalidated. Optionally, any data marked as "dirty" in the rendering cache can be dumped to memory. In some embodiments, the pipeline dump clear command 912 can be used for pipeline synchronization, or before placing the graphics processor in a low power state.

[0177] In some embodiments, when a command sequence utilizes a graphics processor to explicitly switch between pipelines, a pipeline select command 913 is used. In some embodiments, a pipeline select command 913 is utilized once in an execution context before issuing pipeline commands, unless the context will issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is utilized immediately prior to a pipeline switch via a pipeline select command 913.

[0178] In some embodiments, pipeline control commands 914 configure the graphics pipeline for operation and are used to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of the active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0179] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for a corresponding pipeline to write data. Some pipeline operations utilize the allocation, selection, or configuration of one or more return buffers to which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to be used for the set of pipeline operations.

[0180] The remaining commands in the command sequence differ based on the active pipeline for operation.Based on pipeline decision 920 , the command sequence is tailored for either 3D pipeline 922 starting at 3D pipeline state 930 , or media pipeline 924 starting at media pipeline state 940 .

[0181] The commands for configuring the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, if certain pipeline elements will not be used, the 3D pipeline state 930 commands can also selectively disable or bypass those elements.

[0182] In some embodiments, 3D primitive 932 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 932 commands are forwarded to the vertex fetching function in the graphics pipeline. The vertex fetching function uses the 3D primitive 932 command data to generate multiple vertex data structures. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitive 932 commands are used to perform vertex operations on 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 922 dispatches the shader execution thread to the graphics processor execution unit.

[0183] In some embodiments, the 3D pipeline 922 is triggered via an execution 934 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a "go" or "kick" command in the command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric objects are rasterized and the pixel engine shades the resulting pixels. For those operations, additional commands for controlling pixel shading and pixel backend operations may also be included.

[0184] In some embodiments, when performing media operations, the graphics processor command sequence 910 follows the media pipeline 924 path. Generally, the specific purpose and manner of programming for the media pipeline 924 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be transferred to the media pipeline. In some embodiments, the media pipeline can also be bypassed, and the media decoding can be performed in whole or in part using resources provided by one or more general processing cores. In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to the rendering of graphics primitives.

[0185] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands for configuring the media pipeline state 940 is dispatched or placed into a command queue, before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data for configuring the video decoding and video encoding logic within the media pipeline, such as encoding or decoding formats. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain batches of state settings.

[0186] In some embodiments, media object commands 942 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer that contains video data to be processed. In some embodiments, all media pipeline states should be valid before issuing media object commands 942. Once the pipeline state is configured and the media object commands 942 are queued, the media pipeline 924 is triggered via an execution command 944 or an equivalent execution event (e.g., a register write). The output from the media pipeline 924 can then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations. Graphics software architecture

[0187] Fig.10An example graphics software architecture of data processing system 1000 is illustrated in accordance with some embodiments. In some embodiments, the software architecture includes 3D graphics application 1010, operating system 1020, and at least one processor 1030. In some embodiments, processor 1030 includes graphics processor 1032 and one or more general purpose processor cores 1034. Graphics application 1010 and operating system 1020 are each executed in system memory 1050 of the data processing system.

[0188] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by the general purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0189] In some embodiments, operating system 1020 is from Microsoft Corporation Operating system 1020 may be a graphics API 1022, such as Direct3D API, OpenGL API or Vulkan API. When Direct3D API is in use, operating system 1020 uses front-end shader compiler 1024 to compile any shader instruction 1012 using HLSL into a lower-level shader language. Compilation may be just-in-time (JIT) compilation, or application executable shader precompilation. In some embodiments, during the compilation of 3D graphics application 1010, high-level shaders are compiled into low-level shaders. In some embodiments, shader instructions 1012 are provided in an intermediate form, such as a certain version of a standard portable intermediate representation (SPIR) used by Vulkan API.

[0190] In some embodiments, the user mode graphics driver 1026 includes a backend shader compiler 1027 for converting shader instructions 1012 into hardware-specific representations. When the OpenGL API is in use, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses the operating system kernel mode function 1028 to communicate with the kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with the graphics processor 1032 to dispatch commands and instructions. IP core implementation

[0191] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit (such as a processor). For example, a machine-readable medium may include instructions representing various logics within a processor. In some embodiments, a machine-readable medium is also referred to herein as a computer-readable medium or a non-transient computer-readable medium. When read by a machine, the instructions may enable the machine to manufacture logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of logic of an integrated circuit, which may be stored on a tangible, machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to each customer or manufacturing facility that loads the hardware model on a manufacturing machine that manufactures the integrated circuit. An integrated circuit may be manufactured so that the circuit performs the operations described in association with any of the embodiments described herein.

[0192] Fig.11A 1 is a block diagram of an IP core development system 1100 that can be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 1130 can generate a software simulation 1110 of the IP core design using a high-level programming language (e.g., C / C++). The software simulation 1110 can be used to design, test and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 can include functional simulation, behavioral simulation and / or timing simulation. A register transfer level (RTL) design 1115 can then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 1115, a lower level design at the logic level or transistor level can also be created, designed or synthesized. Thus, the specific details of the initial design and simulation can be different.

[0193] The RTL design 1115 or an equivalent solution can be further synthesized into a hardware model 1120 by the design facility, which can adopt a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. Non-volatile memory 1140 (e.g., a hard disk, flash memory, or any non-volatile storage medium) can be used to store the IP core design for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design can be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 can then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit can be configured to perform operations according to at least one embodiment described herein.

[0194] Fig. 11B A cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein is illustrated. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices as described herein. The package assembly 1170 includes a plurality of hardware logic units 1172, 1174 connected to a substrate 1180. The logic 1172, 1174 may be implemented at least in part in configurable logic or fixed-function logic hardware, and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein (multiple) processor cores, (multiple) graphics processors, or other accelerator devices. Each logic unit 1172, 1174 may be implemented within a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180, and may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the substrate 1180 may include other suitable types of substrates. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to the surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0195] In some embodiments, logic units 1172, 1174 are electrically coupled to a bridge 1182 that is configured to route electrical signals between logic 1172 and logic 1174. Bridge 1182 may be a dense interconnect structure that provides routing for electrical signals. Bridge 1182 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between logic 1172 and logic 1174.

[0196] Although two logic cells 1172, 1174 and bridge 1182 are illustrated, the embodiments described herein may include more or fewer logic cells on one or more dies. The one or more dies may be connected by zero or more bridges, as bridge 1182 may be excluded when the logic is included on a single die. Alternatively, multiple dies or logic cells may be connected by one or more bridges. Additionally, multiple logic cells, dies, and bridges may be connected together in other possible configurations, including three-dimensional configurations.

[0197] Fig. 11C The illustrated package assembly 1190 includes a hardware logic chiplet (e.g., a base die) of multiple units connected to a substrate 1180. A graphics processing unit, parallel processor, and / or computing accelerator as described herein may be composed of various silicon chiplets manufactured separately. In this context, a chiplet is an integrated circuit that is at least partially packaged, and the at least partially packaged integrated circuit includes different logic units that can be assembled into a larger package with other chiplets. Chipsets with various sets of different IP core logic can be assembled into a single device. In addition, chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable interconnection and communication between different forms of IP within a GPU. IP cores can be manufactured using different process technologies and assembled during manufacturing, which avoids the complexity of aggregating multiple IPs into the same manufacturing process, especially for large SoCs with several styles of IP. Allowing the use of multiple process technologies improves time to market and provides a cost-effective method to create multiple product SKUs. Furthermore, decomposed IP is more easily modified to be independently power gated, and components not in use for a given workload can be shut down, thereby reducing overall power consumption.

[0198] The hardware logic chiplets may include dedicated hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented at least in part in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor core(s), graphics processor(s), parallel processors, or other accelerator devices described herein. The memory chiplets 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0199] Each chiplet may be fabricated as a separate semiconductor die and coupled to substrate 1180 via interconnect structure 1173. Interconnect structure 1173 may be configured to route electrical signals between various chiplets and logic within substrate 1180. Interconnect structure 1173 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structure 1173 may be configured to route electrical signals such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of logic, I / O, and memory chiplets.

[0200] In some embodiments, substrate 1180 is an epoxy-based laminate substrate. In other embodiments, substrate 1180 may include other suitable types of substrates. Package assembly 1190 may be connected to other electrical devices via package interconnect 1183. Package interconnect 1183 may be coupled to the surface of substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, other chipsets, or multi-chip modules.

[0201] In some embodiments, the logic or I / O chiplet 1174 and the memory chiplet 1175 may be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplet 1174 and the memory chiplet 1175. The bridge 1187 may be a dense interconnect structure that provides routing for electrical signals. The bridge 1187 may include a bridge substrate composed of glass or a suitable semiconductor material. Circuit features may be formed on the bridge substrate to provide a chip-to-chip connection between the logic or I / O chiplet 1174 and the memory chiplet 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, in some embodiments, the bridge 1187 is an embedded multi-die interconnect bridge (EMIB). In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another chiplet.

[0202] The substrate 1180 may include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 may be embedded in the substrate 1180 to enable communication between the various logic chiplets within the substrate 1180 and the logic 1191, 1193. In one embodiment, the I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 may be integrated into a base die stacked on top of the substrate 1180. Fabric 1185 may be an on-chip network interconnect or another form of packet-switched fabric that exchanges data packets between components of the package assembly.

[0203] In various embodiments, the package assembly 1190 may include a fewer or greater number of components and chiplets interconnected by the structure 1185 or one or more bridges 1187. The chiplets within the package assembly 1190 can be arranged in a 3D arrangement or a 2.5D arrangement. In general, the bridge structure 1187 can be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. The structure 1185 can be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, the cache memory 1192 within the substrate can act as a global cache for the package assembly 1190, as part of a distributed global cache, or as a dedicated cache for the structure 1185.

[0204] Fig.11D A package assembly 1194 including interchangeable chiplets 1195 is illustrated according to an embodiment. Interchangeable chiplets 1195 can be assembled into standardized sockets on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be similar to other bridge interconnects described herein and can be, for example, EMIB. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. The I / O and logic chiplets can communicate via an interconnect structure. The base chiplets can each support one or more sockets in a standardized format for one of logic or I / O or memory / cache.

[0205] In one embodiment, the SRAM and power delivery circuits may be fabricated into one or more of the base chiplets 1196, 1198, which may be fabricated using a different process technology relative to the interchangeable chiplets 1195, which are stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 may be fabricated using a larger process technology while the interchangeable chiplets may be fabricated using a smaller process technology. One or more of the interchangeable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package assembly 1194 based on power and / or performance for the product using the package assembly 1194. In addition, logic chiplets with different numbers of types of functional units may be selected at assembly time based on power and / or performance for the product. In addition, chiplets containing IP logic cores of different types may be inserted into the interchangeable chiplet socket, thereby enabling hybrid processor designs that can mix and match IP blocks of different technologies. Example System-on-Chip Integrated Circuit

[0206] Figure 12-13B An example integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are illustrated. In addition to what is illustrated, other logic and circuits may also be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0207] Fig.12 1 is a block diagram illustrating an example system-on-chip integrated circuit 1200 that may be fabricated using one or more IP cores according to an embodiment. The example integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same design facility or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic, including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I 2 S / I 2 The integrated circuit may include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 1265 to obtain access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

[0208] Figure 13A-13B is a block diagram illustrating an example graphics processor for use within a SoC according to embodiments described herein. Fig.13A An example graphics processor 1310 of a system on chip integrated circuit is illustrated that may be fabricated using one or more IP cores in accordance with an embodiment. Fig. 13B An additional example graphics processor 1340 is illustrated that may be fabricated using one or more IP cores of a system on a chip integrated circuit in accordance with an embodiment. Fig.13A Graphics processor 1310 is an example of a low-power graphics processor core. Fig. 13B The graphics processor 1340 of FIG. 1 is an example of a higher performance graphics processor core. Each of the graphics processors 1310 and 1340 may be Fig.12 A variant of graphics processor 1210.

[0209] like Fig.13A As shown in , the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, all the way to 1315N-1 and 1315N). The graphics processor 1310 can execute different shader programs via separate logic, so that the vertex processor 1305 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. The vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. (Multiple) fragment processors 1315A-1315N use the primitive data and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on the display device. In one embodiment, the fragment processor(s) 1315A-1315N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0210] The graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuit interconnect(s) 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual to physical address mappings for the graphics processor 1310 (including for the vertex processor 1305 and / or fragment processor(s) 1315A-1315N), which may reference vertex data or image / texture data stored in memory in addition to vertex data or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B may be synchronized with other MMUs within the system so that each processor 1205-1220 may participate in a shared or unified virtual memory system, including with other MMUs within the system. Fig.12 One or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220. According to an embodiment, one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0211] like Fig. 13B As shown in FIG. 1 , the graphics processor 1340 includes Fig.13A One or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of a graphics processor 1310. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F, all the way to 1355N-1 and 1355N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary by embodiment and implementation. In addition, the graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 for accelerating tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial consistency within a scene or to optimize the use of internal caches.

[0212] In some embodiments, as described herein, a processing resource represents a processing element (e.g., a GPGPU core, a ray tracing core, a tensor core, an execution resource, an execution unit (EU), a stream processor, a streaming multiprocessor (SM), a graphics multiprocessor) associated with a graphics processor structure (e.g., a parallel processing unit, a graphics processing engine, a multi-core group, a computing unit, a computing unit of a next graphics core) in a graphics processor or GPU. For example, a processing resource can be one of a GPGPU core or a tensor / ray tracing core of a graphics multiprocessor; a ray tracing core, a tensor core, or a GPGPU core of a graphics multiprocessor; an execution resource of a graphics multiprocessor; one of a GFX core, a tensor core, or a ray tracing core of a multi-core group; one of a vector logic unit or a scalar logic unit of a computing unit; an execution unit with an EU array or an EU array; an execution unit of execution logic; and / or an execution unit. A processing resource can also be, for example, a graphics processing engine, a processing cluster, a GPGPU, a GPGPU, a graphics processing engine, a graphics processing engine cluster, and / or an execution resource within a graphics processing engine. A processing resource can also be a graphics processor, a graphics processor, and / or a processing resource within a graphics processor. Support for 8-bit floating point format operands in the compute architecture

[0213] Parallel computing is a type of computing in which many calculations or processes are performed simultaneously. Parallel computing can take various forms, including but not limited to SIMD or SIMT. SIMD describes a computer with multiple processing elements that perform the same operation on multiple data points at the same time. In one example, the Figure 5A-Figure 5B Refers to SIMD and its implementation in general-purpose processors in terms of EU, FPU, and ALU. In common SIMD machines, data is packed into registers, each of which contains a channel array. Instructions operate on data found in channel n of a register with data found in the same channel of another register. SIMD machines are advantageous in fields where a single instruction sequence can be applied to a large amount of data simultaneously. For example, in one embodiment, a graphics processor (e.g., GPGPU, GPU, etc.) can be used to perform SIMD vector operations using compute shader programs.

[0214] Embodiments may also be applied to use execution performed using single instruction multiple threads (SIMT) as an alternative to the use of SIMD, or as an addition to the use of SIMD. References to SIMD cores or operations may also be applied to SIMT, or to a combination of SIMD and SIMT. The following description is discussed in terms of SIMD machines. However, the embodiments herein are not limited to applications in the context of SIMD, and may also be applied to other parallel computing paradigms, such as, for example, SIMT. For ease of discussion and explanation, the following description generally focuses on SIMD implementations. However, without modifying the described techniques and methods, the embodiments may also be similarly applied to SIMT machines. With respect to SIMT machines, similar patterns discussed below may be followed to provide instructions to a systolic array and execute instructions on a SIMT machine. Other types of parallel computing machines may also utilize the embodiments herein.

[0215] Various embodiments may implement a GPGPU with a matrix acceleration circuit. Such a matrix acceleration circuit may be used for machine learning (ML) operation acceleration.

[0216] Fig.14 1400 is a block diagram of a data processing system 1400 according to an embodiment. Various embodiments discussed herein may be implemented in a system such as data processing system 1400. Data processing system 1400 is a heterogeneous processing system having a processor 1402, a unified memory 1410, and a GPGPU 1420 including machine learning acceleration logic. Processor 1402 and GPGPU 1420 may be any of a processor and a GPGPU / parallel processor as described herein. Processor 1402 may execute instructions for compiler 1415 stored in system memory 1412. Compiler 1415 is executed on processor 1402 to compile source code 1414A into compiled code 1414B. Compiled code 1414B may include instructions executable by processor 1402 and / or instructions executable by GPGPU 1420. During compilation, compiler 1415 may perform operations to insert metadata including hints about the level of data parallelism present in compiled code 1414B and / or hints about data locality associated with threads to be dispatched based on compiled code 1414B. Compiler 1415 may include information for performing such operations, or these operations may be performed with the assistance of runtime library 1416. Runtime library 1416 may also assist compiler 1415 in compiling source code 1414A, and may also include instructions that are linked with compiled code 1414B at runtime for facilitating execution of compiled instructions on GPGPU 1420.

[0217] Unified memory 1410 represents a unified address space accessible by processor 1402 and GPGPU 1420. Unified memory may include system memory 1412 and GPGPU memory 1418. GPGPU memory 1418 is memory within the address space of GPGPU 1420 and may include some or all of system memory 1412. In one embodiment, GPGPU memory 1418 may also include at least a portion of any memory dedicated for use by GPGPU 1420. In one embodiment, compiled code 1414B stored in system memory 1412 may be mapped into GPGPU memory 1418 for access by GPGPU 1420.

[0218] GPGPU 1420 includes a plurality of computing blocks 1424A-1424N, which may include one or more of the various computing units or execution elements described herein. In one embodiment, GPGPU 1420 additionally includes a matrix accelerator 1423, which may include one or more dedicated function computing units designed to accelerate a subset of matrix operations (e.g., dot products, etc.). GPGPU 1420 may also include a collection of resources that may be shared by computing blocks 1424A-1424N and matrix accelerator 1423, including but not limited to a collection of registers 1425, a power and performance module 1426, and a cache 1427. In one embodiment, registers 1425 include directly and indirectly accessible registers, wherein the indirectly accessible registers are optimized for use by matrix accelerator 1423. The power and performance module 1426 may be configured to adjust the power delivery and clock frequency for the compute blocks 1424A-1424N so as to power gate idle components within the compute blocks 1424A-1424N. In various embodiments, the cache 1427 may include an instruction cache and / or a low-level data cache. The GPGPU 1420 may additionally include an L3 data cache 1430 that may be used to cache data accessed from the unified memory 1410 by the matrix accelerator 1423 and / or the compute elements within the compute blocks 1424A-1424N. In one embodiment, the L3 data cache 1430 includes a shared local memory 1432 that may be shared by the compute elements within the compute blocks 1424A-1424N and the matrix accelerator 1423.

[0219] In one embodiment, GPGPU 1420 includes instruction handling logic, such as fetch and decode unit 1421 (also referred to herein as a decoder, such as decoder 1421) and scheduler controller 1422. Fetch and decode unit 1421 includes a fetch unit and a decode unit for fetching and decoding instructions for execution by one or more of computing blocks 1424A-1424N or matrix accelerator 1423. Instructions can be scheduled to appropriate functional units within computing blocks 1424A-1424N or matrix accelerators via scheduler controller 1422. In one embodiment, scheduler controller 1422 is an ASIC that can be configured to perform advanced scheduling operations. In one embodiment, scheduler controller 1422 is a microcontroller or a processing core with low per-instruction energy that can execute scheduler instructions loaded from a firmware module.

[0220] In one embodiment, some functions for being performed by computing blocks 1424A-1424N can be directly scheduled or transferred to matrix accelerator 1423. In various embodiments, matrix accelerator 1423 includes processing element logic configured to efficiently perform matrix calculation operations, such as multiplication and addition operations and dot product operations used by 3D graphics or computing shader programs. In one embodiment, matrix accelerator 1423 can be configured to accelerate operations used by machine learning frameworks. In one embodiment, matrix accelerator 1423 is a dedicated integrated circuit explicitly configured to perform a specific set of parallel matrix multiplication and / or addition operations. In one embodiment, matrix accelerator 1423 is a field programmable gate array (FPGA) that provides fixed-function logic that can be updated between workloads. The set of matrix operations that can be performed by matrix accelerator 1423 may be limited relative to the operations that can be performed by computing blocks 1424A-1424N. However, matrix accelerator 1423 is able to perform those operations with significantly higher throughput relative to computing blocks 1424A-1424N.

[0221] In an embodiment, Fig.14The data processing system 1400 can be used for applications in the fields of artificial intelligence (AI) and machine learning (ML). Advances in these fields have enabled ML models to train neural networks using low-precision arithmetic. Traditional training platforms support IEEE-754 floating point 16 (FP16) and brain floating point 16 (bfloat16 or BF16) data formats in high-performance systolic array implementations. However, recent progress has been made to support the use of lower-precision data formats (such as 8-bit floating point data formats) to train deep neural networks. One such 8-bit floating point data format is bfloat8 or BF8. The binary format of BF8 is 1 sign bit, 5 exponent bits, and 2 mantissa bits. In some cases, using the BF8 format can provide up to 2 times improvement in the training throughput of the neural network compared to the FP16 or BF16 implementation. However, traditional systems do not provide hardware support for performing operations using 8-bit floating point operands (such as BF8 operands).

[0222] The embodiments herein address the above shortcomings by providing support for 8-bit floating point format operands in a computing architecture. In one implementation, the 8-bit floating point format discussed herein is the BF8 format. The embodiments introduce a variety of techniques for supporting 8-bit floating point format operands in a computing architecture. One technique of the embodiments is pulsating point accumulation and addition of 8-bit floating point format input operands. Another technique of the embodiments is converting floating point data to 8-bit floating point format data or converting from 8-bit floating point format data to floating point data. Another technique of the embodiments is performing efficient random rounding of floating point format data values. Another technique of the embodiments is hybrid floating point pulsating operations. A further technique of the embodiments is performing mixed mode operations using 8-bit floating point format operands. The techniques of the embodiments herein are described in more detail below. Ripple-point accumulation of 8-bit floating-point input operands

[0223] Embodiments provide ripple-point accumulation addition on 8-bit floating point format input operands.

[0224] As previously discussed, traditional training platforms support IEEE-754FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These data formats are also supported in the systolic point accumulation and addition (DPAS) engine. As described above, deep neural networks can be trained using 8-bit floating point data formats (BFLOAT8 or BF8, binary format = 1s-5e-2m). BFLOAT8 can provide up to 2 times improvement in training throughput compared to FP16 and BFLOAT16 implementations. However, there is no known traditional solution that supports systolic dot product operations using the BFLOAT8 numerical format.

[0225] Embodiments provide an extension to the DPAS (dot accumulation systolic) engine to support the BF8 data format. The implementation provides instructions for performing a matrix dot product c+=a*b on three input operands, where the a matrix and the b matrix have a BF8 data type. In addition, the embodiment provides hardware circuits to fetch, decode, and execute the instructions. In some implementations, the accumulated result of the dot product can be returned as a 32-bit (FP32) or 16-bit (FP16, BF16) floating point. The embodiment provides the following technical advantages: improving systolic computing density and throughput, reducing data movement costs (because BF8 utilizes half the bandwidth and cache / register space compared to 16-bit data formats), and accelerating training by enabling mixed precision BFLOAT8 training.

[0226] Embodiments provide DPAS instructions for supporting dot product and accumulate operations on input variables presented in an 8-bit floating point (eg, BF8) data format. Fig.15 1 is a block diagram illustrating a BFLOAT8 (BF8) binary format 1500 according to an embodiment. The BF8 binary format 1500 is represented using a sign bit 1510, an exponent bit 1520, and a mantissa bit 1530. The sign bit 1510 is 1 bit, the exponent 1520 is 5 bits, and the mantissa 1530 is 2 bits. The 5-bit exponent 1520 uses an offset value of 15, which can represent normal floating point values ​​between 6.1e-05 and 5.7344e+04. The BF8 binary format 1500 also supports subnormal values ​​that extend the dynamic range down to the minimum representable value of 1.5e-05.

[0227] Fig.16 1 is a block diagram illustrating a systolic DP 8-bit FP format operation 1610 performed by an instruction pipeline 1600 according to an embodiment. The instruction pipeline 1600 may be configured to perform a systolic DP 8-bit format operation 1610, such as, but not limited to, a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of the corresponding components of the vectors. The dot product may be calculated as shown in equation (1) below.

[0228] The dot product may be used in a convolution operation for a neural network, such as a convolutional neural network (CNN). The instruction pipeline 1600 for accelerating hardware instructions may include an instruction fetch and decode unit 1421 that may fetch and decode hardware instructions, and a controller unit 1620, such as a scheduler controller 1422, that may schedule decoded instructions to one or more execution units within a computation block 1424A-1424N (collectively, a computation block 1424) and / or a matrix accelerator 1423. The instruction pipeline 1600 may also include a selection circuit 1630, such as a set of multiplexers (muxes), for routing input data to the computation block 1424 and / or the matrix accelerator 1423 according to an 8-bit FP format encoded in a hardware instruction of a systolic DP 8-bit format operation 1610.

[0229] In one embodiment, the hardware instructions may be dispatched to the compute block 1424 and may be transferred to the matrix accelerator 1423. One or more hardware instructions and associated data for performing the systolic DP 8-bit FP format operation 1610 may be stored in the memory 1650. The output of the hardware instructions may also be stored in the memory 1650. The memory 1650 may be any of the memories described herein, including, for example, Fig.14 In some embodiments, the memory 1650 may be one or more register files.

[0230] In one embodiment, the matrix accelerator 1423 may use a systolic array circuit 1640 to execute one or more hardware instructions to perform the systolic DP 8-bit format operation 1610. The systolic array circuit 1640 may include a combination of programmable hardware and fixed-function hardware that can be configured to perform dot product operations. Although the functional units within the computation block 1424 may also be configured to perform dot product operations, the systolic array circuit 1640 may be configured to perform a limited subset of dot product operations at a significantly higher throughput relative to the computation block 1424.

[0231] In embodiments herein, a DPAS instruction is provided to perform a systolic dot product and accumulate operation on 8-bit floating point format (such as BF8) source operands from a register file, accumulate the results at a selected precision (fp32, fp16, bf16), and write the final output back to the register file. This DPAS instruction for performing a systolic DP 8-bit format operation 1610 accepts three input operands for computing c+=a*b, where the 'a' operand and the 'b' operand have an 8-bit FP type, such as BF8. Some of the supported combinations of input operands and output operands are shown below.

[0234] DPAS is a multiply-add and accumulate operation (src1 x src2) in a systolic pipeline with BFLOAT8 inputs. Each fused multiply-accumulate (FMA) stage of the systolic pipeline represents a 32-bit SIMD lane in the systolic array circuit 1640 and performs a DPAS operation (e.g., a dp4a operation) on 4 input elements from src1 and src2, respectively. dst and src0 accept IEEE754 floating point or half floating point operands, and src0 contains the accumulated output from the previous DPAS iteration in the systolic array. Embodiments may utilize any iteration of the block normalization technique, including but not limited to dp4a, dp2a (block=2), dp8a (block=8), dp32a (block=32), and the like. Each block normalization technique is associated with its own advantages (e.g., improved area efficiency) and disadvantages (e.g., loss of accuracy). The specific block normalization technique implemented may be based on the specific application used.

[0235] The 'sdepth' parameter indicates the systolic depth of the operation, which means that a sequence of these 'sdepth' operations are performed, advancing on consecutive registers. The output of each stage is maintained in 32-bit precision, which will be the accumulation input to the next systolic stage. The dst and src0 variables can accept IEEE-754 floating point, half floating point, or bfloat16 data types, and the result of the previous accumulation is passed to the instruction via the source register (src0). The final accumulation output is converted to the destination data format and written to the destination register (dst). The 'rcount' parameter is the repeat count of the operation, which means that 'rcount' number of dpas instructions are generated as dst and src0 advance on consecutive registers, src1 remains unchanged, and src2 advances 32 elements.

[0236] In an embodiment, the accumulator operand 'c' may be FP32, FP16, or BF16. The systolic array circuit 1640 hardware should support subnormal values ​​on input (i.e., DAZ=0). In an embodiment, the input subnormal value may be up-converted and normalized on the trellis before being fed to the first stage of the systolic array circuit 1640.

[0237] In some implementations, the partial sums passed through the input variable 'c' may be accumulated at the end of the systolic chain to minimize the loss of precision due to the internal normalization and addition operations. This accumulation of the accumulator input variable ('c') at the end of the systolic chain is referred to as "late accumulation". The internal sums at each stage of the systolic array are accumulated and rounded to FP32 values ​​using round-to-nearest. In some embodiments, the accumulation of the accumulator input variable ('c') may occur at the first stage of the systolic chain, or may occur at any intermediate stage(s) of the systolic chain.

[0238] Fig.17A 1 is a block diagram illustrating a systolic array circuit 1700 for performing systolic accumulation on 8-bit floating point format input operands according to an embodiment. Fig.17A The systolic accumulation of 8-bit floating point format input operands depicted in FIG. 1 is an example dp4a operation. In one implementation, the systolic array circuit 1700 is similar to the reference Fig.16 The systolic array circuit 1700 is the same as the systolic array circuit 1640 described herein. The systolic array circuit 1700 may include a combination of programmable hardware and fixed function hardware that can be configured to perform a dot product operation. Other variations and combinations of circuits and elements of the systolic array circuit 1700 may be implemented and are not limited to those shown herein. Fig.17A One example architecture of a systolic array circuit 1700 is provided, and other architectures may be implemented to provide systolic-point accumulate-add operations on 8-bit floating-point format input operands as discussed herein.

[0239] Each FMA unit in the systolic array circuit 1700 performs a vector dot product operation (e.g., such as a 4-element vector dot product operation (dp4a)) on 4 pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of multipliers 1710a-1710d and shifters 1715b-1715e pairs, and an adder 1720. The third input register src0 contains the partial accumulated sum from the previous dot product iteration. Multiple such FMA units linked together in a systolic array can perform a DPAS operation as discussed further below. A systolic array implementation can link these individual FMA units in any possible order that produces an efficient design, and the order of accumulation is not an issue.

[0240] In embodiments herein, the systolic array circuit 1700 should support subnormal values ​​(e.g., DAZ=0) on the BF8 input. This can be achieved by expanding the input exponent on the grid and normalizing the subnormal input value. The multiplication can be performed using, for example, 4-bit multipliers 1710a-1710d and 1730a-1730d without loss of precision. A shifter can be used after each multiplier to normalize the output of the multipliers 1710a-1710d and 1730a-1730d, such as 32-bit shifters 1715a-1715e and 1735a-1735e. Although the shifters 1715a-1715e, 1735a-1735e are depicted as 32-bit shifters, in embodiments herein, the shifters 1715a-1715e, 1735a-1735e can be of any arbitrary precision. For example, the shifters 1715a-1715e, 1735a-1735e may be increased to 48 bits in the case of utilizing a block normalization operation with a large block size of 32. Thus, although 32-bit shifters 1715a-1715e, 1735a-1735e are shown for illustrative purposes, embodiments are not limited to a specific 32-bit shifter size and the shifters 1715a-1715e, 1735a-1735e may be of any arbitrary precision.

[0241] The normalized products output from the shifters 1715a-1715e, 1735a-1735e are added together in an adder (such as 5-way FP32 adders 1720, 1740) and rounded using nearest rounding to produce FP32 output. In some embodiments, the 5-way FP32 adder can be an N-way adder tree (where N is configurable) based on the block size selected for normalization. In an embodiment, any subnormal values ​​on the FP32 intermediate results thereafter (e.g., at adders 1720, 1740) are each flushed to zero.

[0242] As previously discussed, the systolic array circuit 1700 may implement late accumulation. For late accumulation, src0 is accumulated at the final adder (such as the FP32 adder 1750) at the end of the systolic chain. Thus, the 'c' value of the first stage (e.g., 'depth 0') of the systolic array circuit 1700 is zero. Late accumulation prevents loss of numerical accuracy of the accumulated output and may provide improved performance in workload level accuracy. As previously discussed, in some embodiments, accumulation of the accumulator input variable ('c') may occur at the first stage of the systolic chain, or may occur at any (multiple) intermediate stages of the systolic chain.

[0243] The final output after the late accumulation (e.g., destination (FP32) 1752) is rounded to the destination precision by the adder 1750 using round-nearest-even (RNE). Implementations of the systolic array circuit 1700 may support a variety of output formats, including FP32, FP16, and BF16, to name a few. In some embodiments, if the output is FP32 or BF16, subnormal values ​​on the final output of the adder 1750 are flushed to zero. In some embodiments, subnormal values ​​are supported on FP16 output.

[0244] Fig. 17B 1 is a block diagram illustrating a systolic array circuit 1755 for performing systolic accumulation on 8-bit floating point format input operands according to an embodiment. Fig. 17B The systolic dot-accumulate addition of 8-bit floating point format input operands depicted in FIG. 1 is an example dp2a operation, which is a 2-element vector dot product operation. In one implementation, the systolic array circuit 1755 is similar to the reference dp2a operation. Fig.16 The systolic array circuit 1755 may be the same as the systolic array circuit 1640 described herein. The systolic array circuit 1755 may include a combination of programmable hardware and fixed function hardware that can be configured to perform a dot product operation. Other variations and combinations of circuits and elements of the systolic array circuit 1755 may be implemented and are not limited to those shown herein. Fig. 17B One example architecture of a systolic array circuit 1755 is provided, and other architectures may be implemented to provide systolic point accumulate-add operations on 8-bit floating point format input operands as discussed herein.

[0245] Each FMA unit in the systolic array circuit 1755 performs a vector dot product operation (e.g., such as a 2-element vector dot product operation (dp2a)) on 4 pairs of BF8 input values ​​from the src1 and src2 registers. In one embodiment, each FMA unit includes a combination of rebiasing and normalization circuits 1760a-1760h, multipliers 1770a-1770d, and adders 1780a-b, 1785a-b. The third input register src0 contains the partial accumulated sum from the previous dot product iteration. Multiple such FMA units linked together in a systolic array can perform a DPAS operation as discussed further below. The systolic array implementation can link these individual FMA units in any possible order that produces an efficient design, and the order of accumulation is not an issue.

[0246] In embodiments herein, systolic array circuit 1755 should support subnormal values ​​(e.g., DAZ=0) on BF8 inputs. This can be accomplished by extending the input exponent on the grid and normalizing the subnormal input values. Rebiasing and normalization circuits 1760a-1760h can convert both incoming operands (src1(BF8) and src2(BF8)) to a common binary format (e.g., FP32) that can accommodate both the 8-bit FP format and its subnormal value (e.g., DAZ=0).

[0247] Multiplication can be performed using, for example, FP32 multipliers 1770a-1770d without loss of precision. The outputs of multipliers 1770a-1770d can be added together in an adder tree (e.g., an N-way adder tree based on the selected block size) and rounded using round-to-nearest (RNE) to produce FP32 outputs, such as the adder tree provided by FP32 adders 1780a, 1780b and FP32 adders 1785a, 1785b. In an embodiment, any subnormal values ​​on the FP32 intermediate results thereafter (e.g., at adders 1780a-b, 1785a-b) are each flushed to zero.

[0248] As previously discussed, the systolic array circuit 1755 may implement late accumulation. For late accumulation, src0 is accumulated at the final adder tree (such as provided by the FP32 adders 1790, 1795) at the end of the systolic chain. Thus, the 'c' value of the first stage (e.g., 'depth 0') of the systolic array circuit 1755 is zero. Late accumulation prevents loss of numerical accuracy of the accumulated output and may provide improved performance in workload level accuracy. As previously discussed, in some embodiments, accumulation of the accumulator input variable ('c') may occur at the first stage of the systolic chain, or may occur at any (multiple) intermediate stages of the systolic chain.

[0249] The final output after late accumulation (e.g., destination (FP32) 1792) is rounded to the destination precision by adder 1795 using round-nearest-even (RNE). Implementations of systolic array circuit 1755 may support a variety of output formats, including FP32, FP16, and BF16, to name a few. In an embodiment, if the output is FP32 or BF16, subnormal values ​​on the final output of adder 1795 are flushed to zero. In some embodiments, subnormal values ​​are supported on FP16 output.

[0250] The following is example pseudo-code for implementing a ripple-point accumulate-add on an 8-bit floating-point format input operand, such as a BF8 operand, according to an embodiment.

[0251] Fig.18A A dot product and accumulate instruction 1800 is illustrated that may be executed by a systolic array circuit according to embodiments described herein. Fig.18A Illustrated are fields of a dot product and accumulate instruction that operates on 8-bit floating point format input operands and that may be executed by systolic matrix logic provided by embodiments. Fig.18A 1800, which, when executed, causes the systolic matrix accelerator to perform a dot product and accumulate on 8-bit floating point format input operands (e.g., BF8 operands). In one embodiment, instruction 1800 includes an opcode field 1802, a systolic depth 1804 (sdepth), a repeat count 1806 (rcount), and operand fields for specifying a destination 1808, a zeroth source 1810 (src0), a first source 1812 (srcl), and a second source 1814 (src2).

[0252] The opcode field 1802 may specify an opcode that identifies the instruction 1800 to the execution logic. In one embodiment, the opcode field 1802 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 1802 may also include one or more bits that specify that the instruction 1800 is to be executed by dedicated dot product logic, such as dot product logic within the matrix accelerator 1423 (e.g., systolic array circuit 1640).

[0253] The systolic depth 1804 (sdepth) may be used to specify the number of systolic layers used to process the input data. In one embodiment, the systolic depth 1804 may be provided as an immediate value. The repeat count 1806 (rcount) may be used to specify the number of dpas instructions generated if dst and src0 are advanced on consecutive registers, src1 remains unchanged, and src2 is advanced N elements (where N is the destination format).

[0254] Destination 1808, zeroth source 1810 (src0), first source 1812 (src1), and second source 1814 (src2) may be used to specify a destination to which computations are written and a location from which source data may be retrieved. In one embodiment, destination 1808 may specify a register to which data is to be written. In one embodiment, destination 1808 may be a scalar register, but in some embodiments, the destination may also be a vector register storing outputs from multiple channels. Zeroth source 1810, first source 1812, and second source 1814 may be registers or immediate values ​​that include source data for one or more channels, each channel having four elements for processing by the systolic array circuit.

[0255] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0256] Fig.18B The program code compilation process 1815 according to an embodiment is illustrated. In one embodiment, the source code level description 1820 of the software program is compiled at the compiler 1830 (which may include multiple levels of compilation) to a level with an operation 1840, which includes or specifies an 8-bit dot product for execution by the processing logic. The operation 1840 may be an operation specified in an intermediate language, or may be program code that references a primitive of a computational framework, such as a primitive provided by a machine learning framework. The operation 1840 that includes or specifies an 8-bit dot product may then be further compiled by an additional compiler 1850 (which may be a shader compiler) into a machine-level target code 1860 that includes 8-bit dot product instructions for execution by an accelerator for matrix operations, as described herein.

[0257] Fig.19is a flow chart illustrating an embodiment of a method 1900 for executing an instruction for ripple-point accumulation-add of 8-bit floating-point format input operands. The method 1900 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 1900 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 1 Many of the components and processes described in 8 may not be repeated or discussed below. In one implementation, a data processing system (such as Fig.14 The data processing system 1400 can execute the method 1900.

[0258] Method 1900 begins at processing block 1910, where a single instruction may be fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction is decoded into a decoded matrix instruction that may operate on 8-bit floating point format operands to enable the GPGPU to perform parallel dot product operations. At processing block 1920, a set of pipeline commands is determined to execute the decoded matrix instruction on a matrix accelerator using one or more 8-bit floating point format operands (such as BF8 operands).

[0259] Subsequently, at processing block 1930, the set of pipeline commands is dispatched to the systolic dot product pipeline to execute the decoded matrix instruction using one or more 8-bit floating point format operands. Finally, at processing block 1940, in response to completion of the set of pipeline commands, the decoded matrix instruction is retired.

[0260] Fig. 20 is a flow chart illustrating an embodiment of a method 2000 for ripple-point accumulation of 8-bit floating-point format input operands. The method 2000 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 2000 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 19 Many of the components and processes described may not be repeated or discussed below. In one implementation, a systolic array (such as Fig.16 The method 2000 may be performed by the systolic array circuit 1640 of FIG. 17 or the systolic array circuit 1700 of FIG. 17 .

[0261] Method 2000 begins at processing block 2010, where the source value and computation depth of the instruction are fetched for execution by a matrix operation accelerator of a GPGPU. In one implementation, the source value is an 8-bit floating point format operand (such as a BF8 operand). At processing block 2020, a set of products is generated based on element-by-element multiplication of the source input elements using a 4-bit multiplier.

[0262] At processing block 2030, the multiplier outputs are normalized using a 32-bit shifter for each multiplier. Then, at processing block 2040, the sum of the set of normalized multiplier outputs is calculated and the sum is rounded to even nearest. Finally, at processing block 2050, at the last depth level of the matrix operation accelerator, the sum of the set of normalized multiplier outputs and the initial accumulator value is calculated. The sum is then rounded to the destination output precision using even nearest rounding. Converts floating-point data to or from 8-bit floating-point format

[0263] Embodiments herein provide for converting floating point data to or from 8-bit floating point format data.

[0264] As previously discussed, advances in deep learning have enabled ML models to utilize low-precision arithmetic to train neural networks. Traditional training platforms support IEEE-754FP16 and BFLOAT16 data formats in high-performance systolic array implementations. These implementations use high-precision accumulators to prevent loss of accuracy during long chains of dot product calculations. Within a neural network, these high-precision outputs should be rounded down to a low-precision format during post-processing of the layer before being sent as input to the next layer. For example, traditional hardware implementations for neural networks support rounding from FP32 to FP16 and BF16.

[0265] As mentioned above, 8-bit FP format data (such as BFLOAT8, 1s-5e-2m) can improve training and inference performance. The hardware implementation of BFLOAT8 FMA can use FP32 or FP16 accumulators to maintain numerical accuracy. However, traditional systems do not have hardware support for rounding FP32 or FP16 FMA outputs to BFLOAT8 during post-processing. Traditional systems can provide a slower software implementation that uses sequence arithmetic and bit-by-bit instructions to perform the rounding operation. For example, this function can be simulated in software using a sequence of arithmetic, bit-by-bit, and comparison instructions. This slower software implementation results in performance impairments for smaller and irregular kernels that are commonly used for deep neural network training.

[0266] The embodiment provides instructions for converting floating point data to 8-bit floating point format data. In one implementation, the conversion instruction of the embodiment performs a down conversion from IEEE-754 FP32 and FP16 to BFLOAT8 with even rounding to nearest. In one implementation, the conversion instruction of the embodiment performs an up conversion from BFLOAT8 to FP32 and FP16 to facilitate mixed precision computing operations using the BFLOAT8 memory format.

[0267] Embodiments provide instructions and hardware solutions for converting floating point data to 8-bit floating point format data. The instructions and hardware techniques of the embodiments herein replace a long string of instructions with a single instruction that can be used by a programmer. This can produce performance improvements for irregular core operations in neural networks. Embodiments also implement mixed precision 8-bit floating point format (e.g., BFLOAT8) training, which can speed up the training throughput of neural networks.

[0268] Fig.21 2 is a block diagram illustrating an 8-bit FP format conversion operation 2110 performed by an instruction pipeline 2100 according to an embodiment. The instruction pipeline 2100 may be configured to perform the 8-bit FP format conversion operation 2110. The instruction pipeline 2100 for accelerating hardware instructions may include: an instruction fetch and decode unit 1421, which may fetch and decode hardware instructions; and a controller unit 2120 (such as a scheduler controller 1422), which may schedule the decoded instructions to one or more execution units within a computation block 1424A-1424N (collectively referred to as a computation block 1424) and / or a matrix accelerator 1423. The instruction pipeline 2100 may also include a selection circuit 2130, such as a set of multiplexers (mux), for routing input data to the computation block 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instruction of the 8-bit FP format conversion operation 2110.

[0269] In one embodiment, the hardware instructions may be dispatched to the computation block 1424 and / or may be transferred to the matrix accelerator 1423 (e.g., for computation using the systolic array circuit 2140). One or more hardware instructions and associated data for performing the 8-bit FP format conversion operation 2110 may be stored in the memory 2150. The output of the hardware instructions may also be stored in the memory 2150. The memory 2150 may be any of the memories described herein, including, for example, Fig.14 The system memory 1412, GPGPU memory 1418 or one or more cache memories 1427, 1430.

[0270] In one embodiment, the computation block 1424 may use a processing unit 2160 to execute one or more hardware instructions to perform an 8-bit FP format conversion operation 2110. The processing unit 2160 may include a combination of programmable hardware and fixed-function hardware that may be configured to perform an 8-bit FP format conversion operation. In some implementations, the processing unit 2160 may be a vector processing unit (VPU). In some implementations, the processing unit 2160 may be a floating point unit (FPU). The processing unit 2160 may include a conversion circuit 2162, a round-to-nearest (RNE) rounding circuit 2164, and a dedicated processing circuit 2166.

[0271] In an embodiment, hardware instructions for performing 8-bit FP format conversion operation 2110 provide data conversion between IEEE-754 FP32 or FP16 data and BFLOAT8 format. Data conversion may include down-conversion from FP32 / FP16 to 8-bit FP format (e.g., BF8) or up-conversion from 8-bit FP format (e.g., BF8) to FP32 / FP16. Fig.15 Depicted is an example BF8 binary format, which can be used as an 8-bit FP format for an embodiment. The BFLOAT8 binary format is represented as a sign, exponent, and mantissa. The 5-bit exponent uses an offset value of 15, which can represent a normal floating point value between 6.1e-05 and 5.7344e+04. The format also supports a subnormal value that extends the dynamic range downward to the minimum representable value 1.5e-05.

[0272] When converting down from FP32 or FP16 to BF8, the value is rounded using the round-nearest-to-even (RTNE) process. Subnormal values ​​are supported in both cases when converting from FP32 or FP16. When converting up from BF8 to FP16 or FP32, the 8-bit FP format (BF8) exponent value is scaled appropriately and the mantissa is zero-extended.

[0273] In an embodiment, conversion circuitry 2162 may include programmable and fixed-function hardware for performing the conversion process described above. RNE rounding circuitry 2164 may include programmable and fixed-function hardware for performing RNE rounding of the converted data. Special processing circuitry 2166 may include programmable and fixed-function hardware for resolving boundary conditions encountered when converting and / or rounding data, such as, for example, underflow, overflow, or denormal.

[0274] In some implementations, instructions for conversion of 8-bit FP format data as described herein may take the following form:

[0275] mov dst,src0

[0276] When the conversion circuit 2162 is converting down from FP32 / FP16 to BF8, the instruction should preserve subnormal values ​​on the output. In some embodiments, the dedicated processing circuit 2166 can provide saturation behavior that causes overflow (i.e., large values ​​are not saturated to BF8_MAX). The RNE rounding circuit 2164 should round the mantissa using a round-to-even process. When performing a down conversion from FP32 or FP16 to BF8, some example implementations of instructions for conversion of 8-bit FP format data are detailed below:

[0277] mov <bf8> , <fp32>

[0278] rice <bf8> , <fp16>

[0279] When the conversion circuit 2162 is converting up from FP32 / FP16 to BF8, the exponent value is rescaled and the value is renormalized. The mantissa bits are extended with zeros on the LSB bits. When performing an up-conversion from BF8 to FP32 or FP16, some example implementations of instructions for conversion of 8-bit FP format data are detailed below:

[0280] mov <fp32> , <bf8>

[0281] rice <fp16> , <bf8>

[0282] Fig.22A Instructions 2200 are illustrated that may be executed by a processing unit according to embodiments described herein. Fig.22A Illustrated are fields of a mov instruction provided by an embodiment for converting an 8-bit floating point format input operand and executable by a processing unit such as a VPU or FPU. Fig.22A Illustrated are fields of a mov instruction 2200, which, when executed, causes a processing unit to execute a mov instruction to convert to or from an 8-bit floating point format input operand (e.g., a BF8 operand). The mov instruction copies the data item (i.e., register contents, memory contents, or constant value) referenced by its second operand to the location (i.e., register or memory) referenced by its first operand.

[0283] In one embodiment, instruction 2200 includes an opcode field 2202 and an operand field for specifying a destination 2204 and a source 2206 (src).

[0284] Opcode field 2202 may specify an opcode that identifies instruction 2200 to execution logic. In one embodiment, opcode field 2202 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a computation block (eg, computation block 1424).

[0285] Destination 2204 and source 2206 (src) may be used to specify a destination to which computations are written and a location from which source data may be retrieved. In one embodiment, destination 2204 may specify a register to which data is to be written. In one embodiment, destination 2204 may be a scalar register, but in some embodiments, the destination may also be a vector register storing outputs from multiple channels. Source (src) 2206 may be a register or immediate value comprising source data for one or more channels.

[0286] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0287] Fig. 22B The program code compilation process 2215 according to an embodiment is illustrated. In one embodiment, the source code level description 2220 of the software program is compiled at the compiler 2230 (the compiler 2230 may include multiple levels of compilation) to a level with an operation 2240, which includes or specifies an 8-bit FP format conversion instruction for execution by the processing logic. The operation 2240 may be an operation specified in an intermediate language, or may be a program code that references a primitive of a computational framework, such as a primitive provided by a machine learning framework. The operation 2240 that includes or specifies the 8-bit FP format conversion instruction may then be further compiled by an additional compiler 2250 (which may be a shader compiler) into a machine-level target code 2260 that includes an 8-bit FP format conversion instruction for execution by a processing unit (e.g., VPU, FPU) of a computational block, as described herein.

[0288] The following is example pseudo code for implementing conversion of floating point data to or from 8-bit floating point format data (such as a BF8 operand) according to an embodiment.

[0289] Fig.23 is a flow chart illustrating an embodiment of a method 2300 for executing instructions for converting floating point data to 8-bit floating point format data. The method 2300 may be performed by processing logic, which may include hardware (e.g., circuits, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 2300 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. In addition, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-22B Many of the components and processes described may not be repeated or discussed below. In one implementation, a data processing system (such as Fig.14 The data processing system 1400 can execute the method 2300.

[0290] Method 2300 begins at processing block 2310, where a single instruction is fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction is decoded into decoded instructions to cause the GPGPU to perform conversion of operands to / from 8-bit floating point format. At processing block 2320, a set of commands is determined to execute the decoded vector instructions on a compute block of the GPGPU.

[0291] At processing block 2330, the group of commands is dispatched to the compute block of the GPGPU to execute the decoded instructions to perform the conversion of operands to / from 8-bit floating point format. Then, at processing block 2340, in response to the completion of the group of commands, the decoded instructions are retired.

[0292] Fig.24 is a flow chart illustrating an embodiment of a method 2400 for converting floating point data to 8-bit floating point format data. The method 2400 may be performed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions running on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 2400 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. In addition, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 23 Many of the components and processes described may not be repeated or discussed below. In one implementation, a processing unit (such as Fig.21 The processing unit 2160) can execute the method 2400.

[0293] Method 2400 begins at processing block 2410, where the source value of the instruction is fetched for execution by the computation block of the GPGPU. In one implementation, the source value is to be converted to a different data format, and the source value is at least one of the following: an 8-bit floating point format operand, or to be converted to an 8-bit floating point format operand. At decision block 2420, it is determined whether the source value is equal to 0, infinity, or non-number (NaN). If so, method 2400 proceeds to processing block 2425, where the source value is returned to the destination as a special case value (e.g., 0, infinity, etc.).

[0294] If the source value is not equal to 0, infinity or NaN at decision block 2420, method 2400 proceeds to processing block 2430, where the source value is converted to the sign-size format of the destination by rescaling, normalizing and converting the source value. Then, at processing block 2440, a round-to-even process is applied to the converted source value.

[0295] At decision block 2450, a determination is made as to whether an overflow, underflow, or denormal condition has occurred. If so, method 2400 proceeds to processing block 2460, where the converted and rounded source value is returned as a special case value (e.g., 0, infinity, etc.). On the other hand, if an overflow, underflow, or denormal condition has not occurred, method 2400 proceeds to processing block 2470, where the converted and rounded source value is returned as the destination value. Performs efficient random rounding on floating-point format data values

[0296] Embodiments provide for performing efficient random rounding on floating point format data values.

[0297] As deep learning training is moving to 8-bit floating point formats (e.g., BF8, 1s-5e-2m), numerical errors introduced due to precision loss can have a significant impact on ML model convergence. One of the ways to compensate for precision loss is to use 'rounding' when converting the FP32 or FP16 accumulated FMA output to BF8 before passing it as input to the next layer of the neural network.

[0298] However, rounding errors accumulated on long chains of dot product operations are also a problem for the numerical stability of iterative solvers used for deep neural network training. The problem is exacerbated at lower precision because the machine 'ε' of BF8 (=0.125) is larger than that of FP16 (=4.88e-04) and BF16 (=3.90e-03).

[0299] When using the BF8 data format across multiple workloads, random rounding can reduce the accumulation of rounding errors and aid convergence. Random rounding refers to a rounding process that is non-deterministic and rounds a real number to the next larger or smaller floating point number with probability 1 minus the relative distance to those numbers. Full hardware support for random rounding would include a floating point pseudo-random number generator, which is expensive to build and verify.

[0300] However, in the context of deep neural network learning, deep learning training has fewer constraints on random number generators, and random numbers can be reused frequently without affecting the numerical stability of the solver. Based on the reduced random number generator constraints, an embodiment provides a combination of hardware and instructions to accelerate random rounding using low-precision random bits (e.g., 8 bits for FP16→BF8 and 16 bits for FP32→FP16) generated and managed in software.

[0301] Embodiments herein provide one or more instructions for applying a random rounding operation when a higher precision output of an arithmetic operation is converted to a lower precision format (e.g., BF8 (1s-5e-2m), HF8 (1s4e3m), FP16, and BF16 floating point formats). These instructions may include one or two source operands having a higher precision and include a third input operand that includes an integer random number generated by a software-based pseudo-random number generator (PRNG). In some implementations, the PRNG software may use an inexpensive PSNR algorithm such as xoroshiro128++ or an equivalent algorithm. The output is stored in a destination data format specified in the instruction.

[0302] The instructions and hardware of the embodiments herein provide the following technical advantages: replacing a wide series of instructions with a single instruction that can be used by a programmer to obtain improved speed and efficiency of execution of neural network training. The embodiments also decouple the PRNG from the rounding operation to reduce the complexity of the hardware while allowing the programmer to use an algorithm to generate and manage (cache and reuse) random numbers. In addition, the embodiments accelerate the back propagation of BFLOAT8 mixed precision training to obtain improved speed and efficiency of neural network training.

[0303] Fig.25 25 is a block diagram illustrating an 8-bit FP format conversion operation 2510 with random rounding performed by an instruction pipeline 2500 according to an embodiment. The instruction pipeline 2500 may be configured to perform the 8-bit FP format conversion operation 2510 with random rounding. The instruction pipeline 2500 for accelerating hardware instructions may include: an instruction fetch and decode unit 1421, which may fetch and decode hardware instructions; and a controller unit 2520 (such as a scheduler controller 1422), which may schedule the decoded instructions to one or more execution units within a computation block 1424A-1424N (collectively referred to as a computation block 1424) and / or a matrix accelerator 1423. The instruction pipeline 2500 may also include a selection circuit 2530, such as a set of multiplexers (mux), for routing input data to the computation block 1424 and / or the matrix accelerator 1423 according to the 8-bit FP format encoded in the hardware instruction of the 8-bit FP format conversion operation 2510 with random rounding.

[0304] In one embodiment, the hardware instructions may be dispatched to the computation block 1424 and / or may be transferred to the matrix accelerator 1423 (e.g., for computation using the systolic array circuit 2540). One or more hardware instructions and associated data for performing the 8-bit FP format conversion operation with random rounding 2510 may be stored in the memory 2550. The output of the hardware instructions may also be stored in the memory 2550. The memory 2550 may be any of the memories described herein, including, for example, Fig.14 The system memory 1412, GPGPU memory 1418 or one or more cache memories 1427, 1430.

[0305] In one embodiment, the computation block 1424 may use a processing unit 2560 to execute one or more hardware instructions to perform an 8-bit FP format conversion operation 2510 with random rounding. The processing unit 2560 may include a combination of programmable hardware and fixed-function hardware that can be configured to perform an 8-bit FP format conversion operation with random rounding. In some implementations, the processing unit 2560 may be a vector processing unit (VPU). In some implementations, the processing unit 2560 may be a floating point unit (FPU). The processing unit 2560 may include a conversion circuit 2562, a random rounding circuit 2564, and a dedicated processing circuit 2566.

[0306] In an embodiment, an instruction for performing an 8-bit FP format conversion operation with random rounding may perform random rounding during conversion from a higher precision floating point to a lower precision floating point. The instruction may take the following format:

[0307] srnd dest,src0,src1

[0308] In this instruction, src0 is the source operand containing the high-precision floating-point input, and src1 contains the random integer used by the rounding hardware. The random integer is generated by software using a PRNG algorithm (such as xoroshiro128++). The output of the rounding operation is returned to dst in the low-precision floating-point format specified by the instruction opcode.

[0309] During the conversion performed by the conversion circuit 2562, a normalized sign-magnitude representation of src0 is generated. The conversion circuit 2562 may include programmable and fixed-function hardware for performing the conversion process. Then, the random rounding circuit 2564 uses a fixed-point adder 2565 to add a random integer from src1 to the normalized sign-magnitude representation of src0 to generate an intermediate result. The random integer is a PRNG 2570 generated by software using a PRNG algorithm. Then the random rounding circuit 2564 truncates the intermediate result to the size of the destination mantissa format after performing any exponent adjustment. The random rounding circuit 2564 may include programmable and fixed-function hardware for performing the random rounding process. The dedicated processing circuit 2566 may include programmable and fixed-function hardware for solving boundary conditions (such as, for example, underflow, overflow, or denormal) encountered when converting and / or rounding data.

[0310] In some embodiments, the number of random bits used for rounding operations may depend on the input and output data formats defined in the instruction opcode. Table 1 below provides a list of supported example input and output formats and the number of random bits used to perform rounding operations. Table 1

[0311] In some embodiments, the width of the random number may vary depending on the source and destination data formats. Assuming the source data format has an N-bit mantissa and the destination data format has a K-bit mantissa, then a (NK)-bit random number may be used to perform rounding at the random rounding circuit 2564 .

[0312] Fig.26 2600 is a block diagram illustrating a fixed-point addition 2600 of a sign-magnitude representation of a mantissa and a random number according to an embodiment. A source mantissa 2601 (with a leading 1) and a random number 2605 are depicted as being added to generate an addition result 2610. The source mantissa includes a mantissa of N bits 2602, where a mantissa of K bits 2604 represents the number of mantissa bits used in the destination format. Prior to the addition, the bits of the random number 2605 are aligned to the (NK) least significant bits of the source mantissa 2601. The addition result 2610 depicts the result of the addition, where there are two leading bits (X) and the remaining addition of the mantissa bits (x).

[0313] Fig.27A Illustrated are instructions 2700 executable by a processing unit according to embodiments described herein. Fig.27A The fields of an instruction for converting a floating point format input operand using random rounding are illustrated. The instruction may be executed by a processing unit (such as a VPU or FPU) provided by an embodiment. Fig.27A The fields of instruction 2700 are shown, which, when executed, causes the processing unit to execute instructions for converting floating point format input operands using random rounding. In one embodiment, instruction 2700 includes an opcode field 2702 and operand fields for specifying a destination 2704, a zeroth source (src0) 2706, and a first source (src1) 2708.

[0314] Opcode field 2702 may specify an opcode that identifies instruction 2700 to execution logic. In one embodiment, opcode field 2702 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a computation block (eg, computation block 1424).

[0315] The destination 2704, the zeroth source 2706 (src0), and the first source 2708 (src1) may be used to specify a destination to which computations are written and a location from which source data may be retrieved. In one embodiment, the destination 2704 may specify a register to which data is to be written. In one embodiment, the destination 2704 may be a scalar register, but in some embodiments, the destination may also be a vector register storing outputs from multiple channels. The zeroth source (src0) 2706 and the first source (src1) 2708 may be registers or immediate values ​​that include source data for one or more channels.

[0316] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0317] Fig.27B The program code compilation process 2715 according to an embodiment is illustrated. In one embodiment, the source code level description 2720 of the software program is compiled at the compiler 2730 (the compiler 2730 may include multiple levels of compilation) to a level with an operation 2740, which includes or specifies an FP format conversion instruction using random rounding for execution by the processing logic. The operation 2740 may be an operation specified in an intermediate language, or may be a program code that references a primitive of a computational framework, such as a primitive provided by a machine learning framework. The operation 2740 that includes or specifies an FP format conversion instruction using random rounding may then be further compiled by an additional compiler 2750 (which may be a shader compiler) into a machine-level target code 2760 that includes an FP format conversion instruction using random rounding for execution by a processing unit (e.g., VPU, FPU) of a computational block, as described herein.

[0318] The following is a first example of pseudo-code for implementing efficient random rounding of floating point format data values, according to an embodiment.

[0319] The following is a second simplified example of pseudo-code for implementing efficient random rounding of floating point format data values, according to an embodiment.

[0320] Fig.28 is a flow chart illustrating an embodiment of a method 2800 for executing instructions for performing efficient random rounding of floating point values. The method 2800 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 2800 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-27B Many of the components and processes described may not be repeated or discussed below. In one implementation, a data processing system (such as Fig.14 The data processing system 1400) can execute the method 2800.

[0321] Method 2800 begins at processing block 2810, where a single instruction is fetched and decoded to be executed within the GPGPU. In one implementation, the single instruction is decoded into decoded instructions to cause the GPGPU to perform a conversion to an 8-bit floating point format with random rounding. Then, at processing block 2820, a set of commands is determined to execute the decoded vector instructions on a compute block of the GPGPU.

[0322] At processing block 2830, the group of commands is dispatched to the computing block of the GPGPU to execute the decoded instructions to perform the conversion to the 8-bit floating point format with random rounding. Finally, at processing block 2840, in response to the completion of the group of commands, the decoded instructions are retired.

[0323] Fig.29 is a flow chart illustrating an embodiment of a method 2900 for performing efficient random rounding of floating point values. The method 2900 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 2900 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 28 Many of the components and processes described may not be repeated or discussed below. In one implementation, a processing unit (such as Fig.25 Processing unit 2560) can execute method 2900.

[0324] Method 2900 begins at processing block 2910, where a source value is fetched for an instruction to be executed by a computation block of a GPGPU. In one implementation, the source value is converted from a higher precision floating point to a lower precision floating point. Then, at decision block 2920, it is determined whether the source value is equal to 0, infinity, or NaN. If so, method 2900 proceeds to processing block 2925, where the source value is returned to the destination as a special case value. If the source value is not equal to 0, infinity, or NaN at decision block 2920, method 2900 proceeds to processing block 2930, where the source value is converted to the sign-size format of the destination and the converted source value is normalized.

[0325] Subsequently, at processing block 2940, the random number is added to the converted and normalized source value. In one implementation, the random number has a size determined based on the data format of the source and destination operands. In one implementation, the random number is obtained from PRNG software. At processing block 2950, ​​an exponent adjustment of the resulting sum is performed, and the resulting sum is truncated to the size of the destination operand mantissa format to generate the resulting destination value.

[0326] At decision block 2960, it is determined whether an overflow, underflow, or denormal condition has occurred. If so, method 2900 proceeds to processing block 2970, where the special case value is returned as the resulting destination value. On the other hand, if an overflow, underflow, or denormal condition has not occurred, method 2900 proceeds to processing block 2980, where the resulting destination value is returned. Hybrid floating point systolic operation

[0327] Embodiments herein provide hybrid floating point systolic operations.

[0328] Algorithmic advances in deep learning have enabled models to utilize low-precision arithmetic to train neural networks. The noise-resistant properties of deep neural networks have also enabled experiments with custom data formats that can be used for various deep learning tasks. One such custom data format that has been widely accepted in the deep learning community and adapted by hardware manufacturers is BFLOAT16.

[0329] As smaller bit widths (8 bits and lower) are used for deep learning, further customization of the data format can be achieved for efficient allocation of bits. For example, it is well known that during backpropagation, error gradients that tend to have a wider distribution take advantage of data formats with higher dynamic range (i.e., larger exponents), while the forward (or inference) path can benefit from higher numerical precision (i.e., larger mantissas) to reduce numerical errors. This behavior is more pronounced in smaller models (fewer model parameters) optimized for edge devices. For smaller bit width data formats, this leads to a trade-off between dynamic range and numerical precision.

[0330] In addition to balancing the bit allocation between the exponent and the mantissa, the floating point format can also customize the value distribution by choosing an appropriate exponent bias or zero point for the value distribution. Given the typical Gaussian data distribution (around 0) of most tensors used in deep learning applications, an exponent bias is typically chosen to maximize the number of small values ​​that can be represented by the format. This can partially compensate for having a smaller dynamic range by prioritizing the relevant parts of the value distribution.

[0331] Two 8-bit floating point representations that can be used for training deep neural networks have been introduced. One of these formats, BFLOAT8, uses the 's1.e5.m2' binary representation with a symmetrically distributed number. The other format, HFLOAT8, uses the 's1.e4.m3' format representation with an asymmetric exponent bias, where the distribution of numbers is biased towards smaller values. Improved model accuracy can be produced by using a combination of BFLOAT8 and HFLOAT8 formats together to address different parts of the training pipeline. Mixing multiple data formats into a single training process can result in mixed floating point operations between input matrices represented in different binary formats. These kinds of mixed operations will become more common as the industry moves to 8-bit and sub-8-bit data formats. However, traditional systems with floating point hardware do not support arithmetic operations between operands that use different binary encodings or use non-traditional exponent biases.

[0332] The embodiment solves this technical problem by providing an extension to the DPAS hardware to support custom binary encoding of input operands to implement hybrid floating point operations. Binary format information of the input operands, such as exponent size and / or exponent bias, can be built into the hardware or can be optionally expressed as part of the instruction encoding. The hardware extension of the embodiment can use this information to re-bias and convert the input variables to a common internal format before performing the requested arithmetic operation.

[0333] Fig.30 3000 is a block diagram illustrating two 8-bit floating point formats using different binary encodings and exponent biases according to an embodiment. The BFLOAT8 (or Brain-Float8) format 3000 on the left shows a BFLOAT8 binary format using the s1.e5.m2 format. The s1.e5.m2 format includes 1 sign bit 3002, 5 exponent bits 3004, and 2 mantissa bits 3006. The HFLOAT8 (or Hybrid-Float8) format 3010 on the right shows a HFLOAT8 binary format using the s1.e4.m3 format. The s1.e4.m3 format includes 1 sign bit 3012, 4 exponent bits 3014, and 3 mantissa bits 3016. In addition, the HFLOAT8 format 3010 uses a larger exponent bias to move the digital distribution toward smaller values. The difference between the two formats is listed in Table 2 below. Table 2

[0334] The hybrid floating point hardware of the embodiments herein provides technical advantages over the disadvantages discussed above by enabling applications to select from a list of available floating point formats that best suit different parts of the training pipeline to maximize accuracy. In addition, embodiments can support multiple data formats with incremental changes to the hardware. This improves processor performance and neural network training throughput.

[0335] Fig.31 3100 is a block diagram illustrating a mixed 8-bit FP format systolic operation 3110 performed by the instruction pipeline 3100 according to an embodiment. The instruction pipeline 3100 may be configured to perform a mixed 8-bit FP format systolic operation 3110, such as, but not limited to, a dot product operation. The dot product of two vectors is a scalar value equal to the sum of the products of the corresponding components of the vectors. The dot product may be calculated as shown in equation (1) below.

[0336] The dot product may be used in a convolution operation for a neural network, such as a convolutional neural network (CNN). The instruction pipeline 3100 for accelerating hardware instructions may include an instruction fetch and decode unit 1421 that may fetch and decode hardware instructions, and a controller unit 3120, such as a scheduler controller 1422, that may schedule the decoded instructions to one or more execution units within a computation block 1424A-1424N (collectively, a computation block 1424) and / or a matrix accelerator 1423. The instruction pipeline 3100 may also include a selection circuit 3130, such as a set of multiplexers (muxes), for routing input data to the computation block 1424 and / or the matrix accelerator 1423 according to a mixed 8-bit FP format encoded in a hardware instruction of the mixed 8-bit FP format systolic operation 3110.

[0337] In one embodiment, the hardware instructions may be scheduled to the compute block 1424 and may be transferred to the matrix accelerator 1423. One or more hardware instructions and associated data for performing the mixed 8-bit FP format systolic operation 3110 may be stored in the memory 3150. The output of the hardware instructions may also be stored in the memory 3150. The memory 3150 may be any of the memories described herein, including, for example, Fig.14 The system memory 1412, GPGPU memory 1418 or one or more cache memories 1427, 1430.

[0338] In one embodiment, the matrix accelerator 1423 may use a systolic array circuit 3140 to execute one or more hardware instructions to perform a mixed 8-bit FP format systolic operation 3110. The systolic array circuit 3140 may include a combination of programmable hardware and fixed function hardware that can be configured to perform a dot product operation. Although the functional units within the computation block 1424 may also be configured to perform a dot product operation, the systolic array circuit 3140 may be configured to perform a limited subset of dot product operations at a significantly higher throughput relative to the computation block 1424.

[0339] In some embodiments, a DPAS instruction is provided to perform a systolic dot product and accumulate operation on mixed 8-bit floating point format data (such as BF8 and HF8) source operands from the register file, accumulate the results at a selected precision (fp32, fp16, bf16), and write the final output back to the register file. This DPAS instruction for performing a mixed 8-bit FP format systolic operation 3110 accepts three input operands for computing c+=a*b, where the 'a' operand and the 'b' operand are of mixed 8-bit FP types, such as BF8 and HF8. In embodiments, other combinations and variations of the FP format types of the input operands are possible and are not limited to BF8 and HF8 formats.

[0340] Fig.32 is a block diagram illustrating a hybrid FMA unit 3200 of a systolic array circuit for performing hybrid floating-point systolic operations according to an embodiment. In one implementation, the hybrid FMA unit 3200 may be a reference Fig.31 A portion of the systolic array circuit 3140 is depicted. In one implementation, the hybrid FMA unit 3200 performs operations on DPAS instructions with hybrid FP format operands. The hybrid FMA implementation of the hybrid FMA unit 3200 can accept a custom floating point format and convert it internally to a higher precision common format before performing the arithmetic operation.

[0341] In an embodiment, information about the custom binary format (such as the number of bits allocated to the exponent and the exponent offset to use) may be provided in the instruction as an integer bitmap (shown below as "imm", "<imm.cbf> ”) is passed as the fourth variable of the FMA instruction. Several examples of hybrid DPAS instructions of an embodiment are shown below, using various combinations of input (e.g., BF8 and HF8) and output variables.

[0344] The instruction encoding can be expressed as<hdpas_xx> , where 'xx' indicates which input variables (src1, src2, or both) allow the use of custom input formats. The implementation of instruction encoding may vary depending on the encoding scheme used by the target architecture.

[0345] Reference Fig.32 , the hybrid FMA operation of the embodiment performed by hybrid FMA unit 3200 is performed on src1 operand and src2 operand expressed in HFLOAT8 and BFLOAT8 data formats, respectively. These two formats not only use different binary formats with different bit allocations for the exponent and mantissa, but also use different exponent biases (e.g., BFLOAT8 bias=15, HFLOAT8 bias=11).

[0346] Hybrid FMA unit 3200 may include multiple rebiasing and normalization units 3210a-h, multiple multipliers 3220a-d, multiple shifters 3230a-3230r, and adder 3240. In hybrid FMA unit 3200, the details of the internal bit width may vary depending on the input and output precision requirements.

[0347] The first stage of the hybrid FMA unit 3200 includes rebiasing and normalization units 3210a-3210h. The rebiasing and normalization units 3210a-3210h can convert two input operands (src1(HF8) and src2(BF8)) into a common 's1.e8.m3' binary format that can accommodate BFLOAT8 and HFLOAT8 formats and their subnormal values ​​(e.g., DAZ=0).

[0348] The second stage of hybrid FMA unit 3200 includes multipliers 3220a-3220d. Multipliers 3220a-3220d use the extended s1.e8.m3 format as input and produce an intermediate 17-bit sign-magnitude representation (s1.e8.m2.6).

[0349] The third stage of hybrid FMA unit 3200 includes shifters 3230a-3230e. Shifters 3230a-3230e may normalize the outputs of multipliers 3220a-3220d and src0 (which contains the previously accumulated sum) using, for example, 32-bit shifters.

[0350] The final stage of the hybrid FMA unit includes adder 3240. Adder 3240 includes an adder tree that produces a 27-bit mantissa as part of a result in, for example, s1.e8.m2.27 format. Adder 3240 rounds the result down to a destination result in s1.e8.23m format using round-to-even method.

[0351] Fig.33A A hybrid dot product and accumulate instruction 3300 is shown that may be executed by a systolic array circuit according to embodiments described herein. Fig.33A Illustrated are fields of a mixed dot product and accumulate instruction 3300 that operates on mixed 8-bit floating point format input operands and that may be executed by systolic matrix logic provided by embodiments. Fig.33A 10. The fields of a mixed dot product and accumulate instruction 3300 are shown, which, when executed, causes a systolic matrix accelerator to perform a dot product and accumulate on mixed 8-bit floating point format input operands (e.g., BF8 and HF8 operands). In one embodiment, instruction 3300 includes an opcode field 3302, a systolic depth 3304 (sdepth), a repeat count 3306 (rcount), an operand field for specifying a destination 3308, a zeroth source 3310 (src0), a first source 3312 (srcl), and a second source 3314 (src2), and an integer bitmap (imm) field 3316.

[0352] The opcode field 3302 may specify an opcode that identifies the instruction 3300 to the execution logic. In one embodiment, the opcode field 3302 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a matrix accelerator (e.g., matrix accelerator 1423). In one embodiment, the opcode field 3302 may also include one or more bits that specify that the instruction 3300 is to be executed by dedicated dot product logic, such as dot product logic within the matrix accelerator 1423 (e.g., systolic array circuit 3140).

[0353] The systolic depth 3304 (sdepth) may be used to specify the number of systolic layers used to process the input data. In one embodiment, the systolic depth 3304 may be provided as an immediate value. The repeat count 3306 (rcount) may be used to specify the number of dpas instructions generated if dst and src0 are advanced on consecutive registers, src1 remains unchanged, and src2 is advanced by N elements, where N is the destination format.

[0354] Destination 3308, zeroth source 3310 (src0), first source 3312 (src1), and second source 3314 (src2) may be used to specify a destination to which computations are written and a location from which source data may be retrieved. In one embodiment, destination 3308 may specify a register to which data is to be written. In one embodiment, destination 3308 may be a scalar register, but in some embodiments, the destination may also be a vector register storing outputs from multiple channels. Zeroth source 3310, first source 3312, and second source 3314 may be registers or immediate values ​​comprising source data for one or more channels, each channel having four elements for processing by the systolic array circuit.

[0355] An integer bitmap (imm) field 3316 may be used to specify information about a custom binary format for at least one of the source operands (e.g., src1 3312 and / or src2 3314), such as the number of bits allocated to the exponent and the exponent offset to be used. This information may be passed in instruction 3300 as an integer bitmap in imm field 3316.

[0356] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0357] Fig.33B The program code compilation process 3315 according to an embodiment is illustrated. In one embodiment, the source code level description 3320 of the software program is compiled at the compiler 3330 (which may include multiple levels of compilation) to a level with an operation 3340, which includes or specifies a mixed 8-bit FP dot product for execution by the processing logic. The operation 3340 can be an operation specified in an intermediate language, or can be a program code that references a primitive of a computational framework, such as a primitive provided by a machine learning framework. The operation 3340 that includes or specifies a mixed 8-bit FP dot product can then be further compiled by an additional compiler 3350 (which may be a shader compiler) into a machine-level target code 3360 that includes mixed 8-bit FP dot product instructions for execution by an accelerator for matrix operations, as described herein.

[0358] The following is an example of pseudo-code for implementing hybrid floating point systolic operations, according to an embodiment.

[0359] Fig.34 is a flow chart illustrating an embodiment of a method 3400 for executing instructions for hybrid floating-point systolic operations. The method 3400 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 3400 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 33B Many of the components and processes described may not be repeated or discussed below. In one implementation, a data processing system (such as Fig.14 The data processing system 1400 can execute the method 3400.

[0360] Method 3400 begins at processing block 3410, where a single instruction is fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction is decoded into a decoded matrix instruction that can operate on a mixed 8-bit floating point format operand to enable the GPGPU to perform a parallel dot product operation. At processing block 3420, a set of pipeline commands is determined to execute the decoded matrix instruction using one or more mixed 8-bit floating point format operands on a matrix accelerator.

[0361] Subsequently, at processing block 3430, the set of pipeline commands is dispatched to the systolic dot product pipeline to execute the decoded matrix instruction using one or more mixed 8-bit floating point format operands. Finally, at processing block 3440, in response to completion of the set of pipeline commands, the decoded matrix instruction is retired.

[0362] Fig.35 is a flow chart illustrating an embodiment of a method 3500 for hybrid floating point systolic operations. The method 3500 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 3500 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 34 Many of the components and processes described may not be repeated or discussed below. In one implementation, a systolic array (such as Fig.31 The systolic array circuit 3140) can perform method 3500.

[0363] Method 3500 begins at processing block 3510, where source values ​​and compute depth are fetched for instructions to be executed by a matrix operation accelerator of a GPGPU. In one implementation, the source values ​​are mixed 8-bit floating point format operands. At processing block 3520, the source value inputs are re-biased and normalized as part of the conversion to a common binary format.

[0364] Subsequently, at processing block 3530, a set of products is generated based on element-by-element multiplication of source input elements in a common binary format. Then, at processing block 3540, for each multiplier and for the accumulator input, the multiplier output and the accumulator input are normalized using a shifter. At processing block 3550, the sum of the set of normalized multiplier outputs is calculated, and the sum is rounded to even nearest. Finally, at processing block 3560, the sum is rounded to the destination output precision using even nearest rounding. Perform mixed-mode operations using 8-bit floating-point operands

[0365] Embodiments provide for performing mixed mode operations using 8-bit floating point format operands.

[0366] Algorithmic advances in deep learning have enabled models to utilize low-precision arithmetic to train neural networks. Traditional training platforms can support IEEE-754FP16 and BFLOAT16 data formats in high-performance systolic array implementations. However, 8-bit FP (such as BFLOAT8, 1s-5e-2m) can be used to improve training and inference performance.

[0367] While a large percentage of the core computational operations of a neural network (such as convolutional and linear layers) may be able to utilize 8-bit FP format data types, there are still parts of a deep neural network that will operate in a mixed precision regime (e.g., 8-bit FP format and 16-bit or 32-bit FP format). Some examples of these parts of a deep neural network that will operate in a mixed precision regime are BatchNorm and LayerNorm operations, which will maintain their internal statistics (such as mean and variance) in higher precision while the layer accepts 8-bit FP format inputs (e.g., BFLOAT8) from previous layers.

[0368] The current approach for traditional systems to handle this mixed precision problem is to up-convert the input tensors to a suitable higher precision format before performing the operation, and later down-convert to a lower precision for systolic or output tensors. However, these conversion operations of the traditional approach incur additional overhead for storing additional high precision copies of the input tensors and increase register bandwidth pressure and dependency.

[0369] Embodiments herein address these technical problems by providing instructions for performing mixed-mode operations on 8-bit FP format (e.g., BFLOAT8 and other IEEE-754 FP formats) input operands. Fig.15 Depicted is an example BF8 binary format, which can be used as an 8-bit FP format for an embodiment. The BFLOAT8 binary format is represented as a sign, exponent, and mantissa. The 5-bit exponent uses an offset value of 15, which can represent a normal floating point value between 6.1e-05 and 5.7344e+04. The format also supports a subnormal value that extends the dynamic range downward to the minimum representable value 1.5e-05.

[0370] For example, these instructions for performing mixed mode operations may accept at least one input operand in 8-bit FP format (e.g., BFLOAT8), while other inputs may be in standard floating point or half floating point format. Embodiments provide a set of instructions for frequently occurring operations, such as multiplication (MUL), ADD, multiply-accumulate (MAC), SEL, and subtraction (SUB), which may operate on the mixed mode operands discussed above.

[0371] The embodiments herein provide technical advantages over the above technical problems by reducing the occupancy and bandwidth requirements of register files. In addition, the embodiments improve the end-to-end training performance of networks with a large proportion of operations such as BatchNorm and LayerNorm. In addition, implementing mixed precision 8-bit FP format training can help accelerate training in neural networks in terms of training throughput.

[0372] Fig.36 36 is a block diagram illustrating a mixed mode 8-bit FP format operation 3610 performed by an instruction pipeline 3600 according to an embodiment. The instruction pipeline 3600 may be configured to perform the mixed mode 8-bit FP format operation 3610. The instruction pipeline 3600 for accelerating hardware instructions may include: an instruction fetch and decode unit 1421, which may fetch and decode hardware instructions; and a controller unit 3620 (such as a scheduler controller 1422), which may schedule the decoded instructions to one or more execution units within a computation block 1424A-1424N (collectively referred to as a computation block 1424) and / or a matrix accelerator 1423. The instruction pipeline 3600 may also include a selection circuit 3630, such as a set of multiplexers (mux), for routing input data to the computation block 1424 and / or the matrix accelerator 1423 according to the mixed mode 8-bit FP format encoded in the hardware instruction of the mixed mode 8-bit FP format operation 3610.

[0373] In one embodiment, the hardware instructions may be dispatched to the computation block 1424 and / or may be transferred to the matrix accelerator 1423 (e.g., for computation using the systolic array circuit 3640). One or more hardware instructions and associated data for performing the mixed-mode 8-bit FP format operation 3610 may be stored in the memory 3650. The output of the hardware instructions may also be stored in the memory 3650. The memory 3650 may be any of the memories described herein, including, for example, Fig.14 The system memory 1412, GPGPU memory 1418 or one or more cache memories 1427, 1430.

[0374] In one embodiment, the computation block 1424 may use a processing unit 3660 to execute one or more hardware instructions to perform a mixed mode 8-bit FP format operation 3610. The processing unit 3660 may include a combination of programmable hardware and fixed function hardware that can be configured to perform a mixed mode 8-bit FP format operation. In some implementations, the processing unit 3660 may be a vector processing unit (VPU). In some implementations, the processing unit 3660 may be a floating point unit (FPU). The processing unit 3660 may include a conversion circuit 3662, a round-to-nearest (RNE) rounding circuit 3664, and a dedicated processing circuit 3666.

[0375] In some embodiments, hardware instructions for performing mixed-mode 8-bit FP format operations 3610 provide mixed-mode operations on 8-bit FP (e.g., BFLOAT8) input operands. The instruction will accept at least one 8-bit FP format (e.g., BFLOAT8) input operand, while other input operands may have IEEE-754 floating point or half floating point data formats.

[0376] The conversion circuit 3662 may include programmable and fixed-function hardware for performing the conversion process described above. The conversion circuit 3662 may internally convert an 8-bit FP format (e.g., BF8) operand upward to a higher precision format to match the format of other input operands, and the operation is performed with higher precision. The data conversion of the conversion circuit 3662 renormalizes the 8-bit FP format input to match the dynamic range of the target precision and utilizes zero extension mantissa on the least significant bit (LSB). The subnormal value on the BFLOAT8 input is retained and normalized to the target precision. The RNE rounding circuit 3664 may include programmable and fixed-function hardware for performing RNE rounding of the converted data. The dedicated processing circuit 3666 may include programmable and fixed-function hardware for solving boundary conditions (such as, for example, underflow, overflow, or denormal) encountered when converting and / or rounding data.

[0377] In some implementations, instructions for conversion of 8-bit FP format data as described herein may take the following form:

[0378] Some of the 8-bit FP format mixed mode examples are discussed in detail below:

[0379] Instructions with two source operands (mov, add, cmp, sel, mul, etc.): one of the sources is in 8-bit FP format (e.g., BFLOAT8) and the other is a higher precision type. The destination can be either 8-bit FP format or a higher precision type.

[0380] Instructions with three source operands (mac, etc.): One or two of the sources can be in 8-bit FP format (e.g., BFLOAT8) while the others have higher precision types. The destination can be in 8-bit FP format or higher precision type.

[0381] Fig.37 An example schematic representation of a hardware circuit 3700 for performing a mixed mode MAC operation using at least one 8-bit FP format operand according to an embodiment is shown. In one implementation, the hardware circuit 3700 may be implemented in reference to Fig.36 The described processing unit is implemented in 3660.

[0382] like Fig.37 As shown in the example of FIG. 37, hardware circuit 3700 for performing mixed mode MAC operation accepts F16 (src1) 3704 and BF8 (src2) 3706 input operands and accumulates with src0 (FP16) 3702. The final output (dst (FP16) 3750) is converted to FP16 output. Conversion circuits 3710a, 3710b, 3710c internally convert src1 3704 and src2 3706 inputs up to FP32. Conversion circuits 3710a-c can be used with reference to Fig.36 The described conversion circuits 3662 are identical. In an embodiment, conversion circuits 3710a-c may preserve subnormal values ​​(eg, DAZ=0) on all inputs.

[0383] Multiplier 3720 can multiply FP32 inputs received from conversion circuits 3710b, 3710c to produce an intermediate output. The intermediate output from multiplier 3720 is normalized and accumulated at adder 3730 with src0 input 3702 (which is converted to FP32 format by conversion circuit 3710a).

[0384] Finally, another conversion circuit 3740 (which can be connected with Fig.36 The conversion circuit 3740 (same as the conversion circuit 3662 of FIG. 16 ) converts the FP32 and FP16 outputs 3750. In an embodiment, the conversion circuit 3740 preserves subnormal values ​​(eg, FTZ=0) on all output (dst) data types.

[0385] Fig.38A Illustrated is a set of instructions 3800 executable by a processing unit according to embodiments described herein. Fig.38A The fields of an instruction 3800 for performing mixed mode operations using 8-bit FP format operands are illustrated. Instructions 3800 include, but are not limited to, mixed mode mac instructions 3812, mixed mode sub instructions 3814, mixed mode add instructions 3816, and mixed mode mul instructions 3818. Other mixed mode instructions for operating on 8-bit FP format operands may also be implemented by embodiments.

[0386] Instruction 3800 may be executed by a processing unit (such as a VPU or FPU) provided by an embodiment. Fig.38A The fields of instruction 3800 are shown, which, when executed, causes the processing unit to execute an instruction for performing a mixed mode operation using an 8-bit FP format operand. In one embodiment, instruction 3800 includes an opcode field 3802 and an operand field for specifying a destination 3804, a zeroth source (src0) 3806, a first source (src1) 3808, and / or a second source (src2) 3810.

[0387] Opcode field 3802 may specify an opcode that identifies instruction 3800 to execution logic. In one embodiment, opcode field 3802 includes one or more bits that, when enabled, indicate that the instruction is to be executed by a processing unit of a computation block (eg, computation block 1424).

[0388] The destination 3804, the zeroth source 3806 (src0), the first source 3808 (src1), and the second source 3810 (src2) can be used to specify the destination to which the calculation is written and the location from which the source data can be retrieved. In one embodiment, the destination 3804 can specify the register to which the data is to be written. In one embodiment, the destination 3804 can be a scalar register, but in some embodiments, the destination can also be a vector register that stores outputs from multiple channels. The zeroth source (src0) 3806, the first source (src1) 3808, and the second source (src2) 3810 can be registers or immediate values ​​that include source data for one or more channels.

[0389] In some embodiments, there may be additional fields different from those shown. For example, in one embodiment, there is a source modifier field that specifies the value modification of the source operand. Before being passed to the execution pipeline, the value of each data element of the source operand can optionally have its absolute value taken and / or its sign reversed. The absolute value modifier can be applied before the negation modifier so that a necessary negative value can be generated. In one embodiment, there is a saturation field that can be used to control the destination saturation. When saturation is enabled, the output data going to the destination register is saturated. The specific saturation operation depends on the destination data type. Saturation is the operation of converting any data outside the saturation target range of the data type to the closest representation value within the target range.

[0390] Fig.38B The program code compilation process 3815 according to an embodiment is illustrated. In one embodiment, the source code level description 3820 of the software program is compiled at the compiler 3830 (the compiler 3830 may include multiple levels of compilation) to a level with an operation 3840, which includes or specifies an 8-bit FP mixed mode instruction for execution by the processing logic. The operation 3840 may be an operation specified in an intermediate language, or may be a program code that references a primitive of a computational framework, such as a primitive provided by a machine learning framework. The operation 3840 that includes or specifies the 8-bit FP mixed mode instruction may then be further compiled by an additional compiler 3850 (which may be a shader compiler) into a machine-level target code 3860 that includes an 8-bit FP mixed mode instruction for execution by a processing unit (e.g., VPU, FPU) of a computational block, as described herein.

[0391] The following is an example of pseudo code for implementing mixed-mode 8-bit FP format operations, according to an embodiment.

[0392] Fig.39 is a flow chart illustrating an embodiment of a method 3900 for executing instructions for performing mixed mode operations utilizing 8-bit floating point format operands. The method 3900 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 3900 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-38B Many of the components and processes described may not be repeated or discussed below. In one implementation, a data processing system (such as Fig.14 The data processing system 1400) can execute the method 3900.

[0393] Method 3900 begins at processing block 3910, where a single instruction is fetched and decoded to be executed within a GPGPU. In one implementation, the single instruction is decoded into decoded instructions to cause the GPGPU to perform 8-bit floating point format mixed mode operations. At processing block 3920, a set of commands is determined to execute the decoded vector instructions on a compute block of the GPGPU.

[0394] Subsequently, at processing block 3930, the group of commands is dispatched to the computing block of the GPGPU to execute the decoded instructions to perform 8-bit floating point format mixed mode operations. Finally, at processing block 3940, in response to the completion of the group of commands, the decoded instructions are retired.

[0395] Fig.40 is a flow chart illustrating an embodiment of a method 4000 for performing mixed mode operations utilizing 8-bit floating point format operands. The method 4000 may be performed by processing logic that may include hardware (e.g., circuitry, dedicated logic, programmable logic, etc.), software (such as instructions executed on a processing device), or a combination thereof. For simplicity and clarity of presentation, the processes of the method 4000 are illustrated in a linear sequence; however, it is contemplated that any number of the processes may be performed in parallel, asynchronously, or in a different order. Additionally, for simplicity, clarity, and ease of understanding, reference is made to Figure 1-Figure 39 Many of the components and processes described may not be repeated or discussed below. In one implementation, a processing unit (such as Fig.36 The processing unit 3660) can execute the method 4000.

[0396] Method 4000 begins at processing block 4010, where the source value of the instruction is fetched for the operation to be performed by the computation block of the GPGPU. In one implementation, the source value is a mixed mode 8-bit floating point format operand. At processing block 4020, the source value input is re-biased and normalized as part of the conversion to a common binary format. Subsequently, at processing block 4030, the operation is performed on the source input elements in the common binary format.

[0397] Subsequently, at processing block 4040, the operation output is normalized using a shifter. Then, at processing block 4050, the normalized output is converted to the destination format to generate a resulting value. Finally, at processing block 4060, the resulting value is returned to the destination operand.

[0398] The following examples relate to further embodiments. Example 1 is an apparatus for providing support for 8-bit floating point format operands in a computing architecture. In one embodiment, Example 1 is an apparatus for providing systolic dot product accumulation of 8-bit floating point format input operands. The apparatus of Example 1 includes: a processor, the processor including: a decoder for decoding instructions fetched for execution into decoded instructions, wherein the decoded instructions are matrix instructions, the matrix instructions operate on 8-bit floating point operands to cause the processor to perform parallel dot product operations; a controller for scheduling the decoded instructions and providing input data for the 8-bit floating point operands according to the 8-bit floating point data format indicated by the decoded instructions; and a systolic dot product circuit for executing the decoded instructions using systolic layers, each systolic layer including one or more groups of interconnected multipliers, shifters, and adders, each group of multipliers, shifters, and adders for generating dot products of the 8-bit floating point operands.

[0399] In Example 2, the subject matter of Example 1 may optionally include: wherein the shifter is used to normalize the output of the multiplier. In Example 3, the subject matter of any of Examples 1-2 may optionally include: wherein the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In Example 4, the subject matter of any of Examples 1-3 may optionally include: wherein the adder includes an adder tree, the adder tree being used to add products generated by the multipliers and normalized by the shifter, and wherein the adder is used to round the result of the adder tree using nearest-to-even rounding.

[0400] In Example 5, the subject matter of any of Examples 1-4 may optionally include: wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 6, the subject matter of any of Examples 1-5 may optionally include: wherein the systolic dot product circuit is used to perform a late accumulation of an accumulator source operand, the late accumulation being used to accumulate the accumulator source operand after generation of the dot product of the 8-bit floating point operand. In Example 7, the subject matter of any of Examples 1-6 may optionally include: wherein the systolic dot product circuit is used to perform an accumulation of an accumulator source operand, the accumulation being used to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuit or an intermediate stage of the systolic dot product circuit.

[0401] In Example 8, the subject matter of any of Examples 1-7 may optionally include: wherein the processor comprises a graphics processing unit (GPU). In Example 9, the subject matter of any of Examples 1-8 may optionally include: wherein the device is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.

[0402] Example 10 is a method for facilitating support of 8-bit floating point format operands in a computing architecture, the method comprising: decoding, by a processor, an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; scheduling, by the processor, the decoded instruction and providing input data for the 8-bit floating point operands according to an 8-bit floating point data format indicated by the decoded instruction; and executing, by a systolic dot product circuit of the processor, the decoded instruction using systolic layers, each systolic layer comprising one or more interconnected groups of multipliers, shifters, and adders, each group of multipliers, shifters, and adders for generating a dot product of the 8-bit floating point operands.

[0403] In Example 11, the subject matter of Example 10 may optionally include: wherein the shifter is used to normalize the output of the multiplier, wherein the adder includes an adder tree, the adder tree is used to add the products generated by the multiplier and normalized by the shifter, and wherein the adder is used to round the result of the adder tree using nearest-to-even rounding. In Example 12, the subject matter of any of Examples 10-11 may optionally include: wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 13, the subject matter of any of Examples 10-12 may optionally include: wherein the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier.

[0404] In Example 14, the subject matter of any one of Examples 10-13 may optionally include: further including: performing, by the systolic dot product circuit, a late accumulation of an accumulator source operand, the late accumulation being used to accumulate the accumulator source operand after generation of the dot product of the 8-bit floating point operand. In Example 15, the subject matter of any one of Examples 10-14 may optionally include: further including: performing, by the systolic dot product circuit, an accumulation of an accumulator source operand, the accumulation being used to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuit or an intermediate stage of the systolic dot product circuit.

[0405] Example 16 is a non-transitory computer-readable medium for facilitating support of 8-bit floating point format operands in a computing architecture. In Example 16, the non-transitory computer-readable medium may have instructions stored thereon, which, when executed by one or more processors, cause the processors to: decode, by the one or more processors, instructions fetched for execution into decoded instructions, wherein the decoded instructions are matrix instructions that operate on 8-bit floating point operands to cause the one or more processors to perform parallel dot product operations; schedule, by the one or more processors, the decoded instructions and provide input data for the 8-bit floating point operands according to an 8-bit floating point data format indicated by the decoded instructions; and execute, by systolic dot product circuitry of the one or more processors, the decoded instructions using systolic layers, each systolic layer comprising one or more interconnected groups of multipliers, shifters, and adders, each group of multipliers, shifters, and adders for generating dot products of the 8-bit floating point operands.

[0406] In Example 17, the subject matter of Example 16 can optionally include: wherein the shifter is used to normalize the output of the multiplier, wherein the adder includes an adder tree, the adder tree is used to add the products generated by the multiplier and normalized by the shifter, and wherein the adder is used to round the result of the adder tree using round-to-even. In Example 18, the subject matter of any of Examples 16-17 can optionally include: wherein the result is rounded to a destination precision indicated by the decoded instruction.

[0407] In Example 19, the subject matter of any one of Examples 16-18 may optionally include: wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuit, a late accumulation of an accumulator source operand, the late accumulation being used to accumulate the accumulator source operand after generation of the dot product of the 8-bit floating point operand. In Example 20, the subject matter of any one of Examples 16-19 may optionally include: wherein the instructions cause the one or more processors to: perform, by the systolic dot product circuit, an accumulation of an accumulator source operand, the accumulation being used to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuit or an intermediate stage of the systolic dot product circuit.

[0408] Example 21 is a system for facilitating support of 8-bit floating point format operands in a computing architecture. In Example 21, the system includes a memory and one or more processors having multiple GPUs. The one or more processors of Example 21 are communicatively coupled to the memory and include: a decoder for decoding instructions fetched for execution into decoded instructions, wherein the decoded instructions are matrix instructions that operate on 8-bit floating point operands to cause the graphics processing unit to perform parallel dot product operations; a controller for scheduling the decoded instructions and providing input data for the 8-bit floating point operands according to the 8-bit floating point data format indicated by the decoded instructions; and a systolic dot product circuit for executing the decoded instructions using a systolic layer, each systolic layer including one or more groups of interconnected multipliers, shifters, and adders, each group of multipliers, shifters, and adders for generating dot products of the 8-bit floating point operands.

[0409] In Example 22, the subject matter of Example 21 may optionally include: wherein the shifter is used to normalize the output of the multiplier. In Example 23, the subject matter of any of Examples 21-22 may optionally include: wherein the multiplier includes at least one of a 4-bit multiplier, an 8-bit multiplier, a 16-bit multiplier, or a 32-bit multiplier. In Example 24, the subject matter of any of Examples 21-23 may optionally include: wherein the adder includes an adder tree, the adder tree is used to add the products generated by the multiplier and normalized by the shifter, and wherein the adder is used to round the result of the adder tree using nearest-to-even rounding.

[0410] In Example 25, the subject matter of any of Examples 21-24 may optionally include: wherein the result is rounded to a destination precision indicated by the decoded instruction. In Example 26, the subject matter of any of Examples 21-25 may optionally include: wherein the systolic dot product circuit is used to perform a late accumulation of an accumulator source operand, the late accumulation being used to accumulate the accumulator source operand after generation of the dot product of the 8-bit floating point operand. In Example 27, the subject matter of any of Examples 21-26 may optionally include: wherein the systolic dot product circuit is used to perform an accumulation of an accumulator source operand, the accumulation being used to accumulate the accumulator source operand at one of a first stage of the systolic dot product circuit or an intermediate stage of the systolic dot product circuit.

[0411] In Example 28, the subject matter of any of Examples 21-27 may optionally include: wherein the processor comprises a graphics processing unit (GPU). In Example 29, the subject matter of any of Examples 21-28 may optionally include: wherein the device is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine.

[0412] Example 30 is a device for facilitating support of 8-bit floating point format operands in a computing architecture, comprising: means for decoding instructions fetched for execution into decoded instructions, wherein the decoded instructions are matrix instructions that operate on 8-bit floating point operands to cause a processor to perform parallel dot product operations; means for scheduling the decoded instructions and providing input data for the 8-bit floating point operands according to an 8-bit floating point data format indicated by the decoded instructions; and means for executing the decoded instructions using systolic layers, each systolic layer comprising one or more groups of interconnected multipliers, shifters, and adders, each group of multipliers, shifters, and adders for generating dot products of the 8-bit floating point operands. In Example 31, the subject matter of Example 30 may optionally include a device further configured to perform a method as in any one of Examples 11 to 15.

[0413] Example 32 is at least one machine-readable medium, comprising a plurality of instructions, which in response to being executed on a computing device, cause the computing device to perform a method according to any one of Examples 10-15. Example 33 is a device for facilitating support of 8-bit floating point format operands in a computing architecture, configured to perform a method as in any one of Examples 10-15. Example 34 is a device for facilitating support of 8-bit floating point format operands in a computing architecture, comprising means for performing a method as in any one of Examples 10 to 15. The details in the examples may be used anywhere in one or more embodiments.

[0414] Example 35 is a device for facilitating support of 8-bit floating point format operands in a computing architecture, and is specifically used to facilitate conversion of floating point data to or from 8-bit floating point format data. The device of Example 35 includes: a processor having multiple graphics processing units (GPUs), the processor being used to: fetch a source value for an instruction executed by a computing block of the processor, wherein the source value is converted to a different data format, and the source value is at least one of the following: an 8-bit floating point format operand, or is to be converted to the 8-bit floating point operand; converting the source value to a destination's sign-magnitude format by rescaling, normalizing, and converting the source value; applying nearest-to-even rounding to the converted source value; and returning the converted and rounded source value as a destination value.

[0415] Example 36 is an apparatus for facilitating support of 8-bit floating point format operands in a computing architecture, and specifically for facilitating efficient random rounding of floating point format data values. The apparatus of Example 36 includes: a processor having a plurality of graphics processing units (GPUs), the processor being configured to: fetch a source value for an instruction executed by a computing block of the processor, wherein the source value is converted from a higher precision floating point to a lower precision floating point; convert the source value to a sign-size format of a destination and normalize the converted source value; add a random number to the converted and normalized source value, the random number having a size determined based on the data format of the source operand and the destination operand, and wherein the random number is obtained from a PRNG; perform an exponent adjustment on a resulting sum and truncate the resulting sum to a size of a destination operand mantissa format to generate a resulting destination value; and return the resulting destination value.

[0416] Example 37 is an apparatus for facilitating support of 8-bit floating point format operands in a computing architecture, and is particularly used to facilitate mixed floating point systolic operations. The apparatus of Example 37 includes: a processor having multiple graphics processing units (GPUs), the processor being configured to: fetch source values ​​and computation depths for instructions executed by a matrix operation accelerator of the processor, wherein the source values ​​include mixed 8-bit floating point format operands; rebias and normalize the source values ​​as part of conversion to a common binary format; generate a set of products based on element-by-element multiplication of the rebiased and normalized source values ​​in the common binary format; normalize the multiplier outputs and the accumulator inputs using a shifter for each multiplier and for an accumulator input; compute a sum of a set of normalized multiplier outputs and round the sum to the nearest even number; and round the computed sum to a destination output precision using nearest-to-even rounding.

[0417] Example 38 is an apparatus for facilitating support of 8-bit floating point format operands in a computing architecture, and specifically for facilitating mixed mode operations utilizing 8-bit floating point format operands. The apparatus of Example 38 includes: a processor having a plurality of graphics processing units (GPUs), the processor being configured to: fetch source values ​​for instructions for operations to be performed by a computing block of the processor, wherein the source values ​​include mixed mode 8-bit floating point format operands; rebias and normalize the source values ​​as part of a conversion to a common binary format; perform the operation on the rebiased and normalized source values ​​in the common binary format; normalize the output using a shifter; convert the normalized output to a destination format to generate a resulting value; and return the resulting value to a destination operand.

[0418] The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. It will be appreciated by those skilled in the art that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features as set forth in the appended claims. < / fp16> < / fp32> < / bf8> < / bf8>

Claims

1. A device comprising: Integrated circuit chips, including: a plurality of registers for storing a plurality of data elements, including 8-bit floating point data elements and 32-bit floating point data elements; a decoding circuit for decoding a single matrix instruction having a field for indicating an opcode and a position of a first source matrix, a second source matrix, and a third source matrix, the first source matrix comprising a first plurality of 8-bit floating point data elements encoded in a first 8-bit floating point format, the second source matrix comprising a second plurality of 8-bit floating point data elements encoded in a second 8-bit floating point format, the third source matrix comprising a plurality of 32-bit floating point data elements, wherein the first 8-bit floating point format includes a sign bit, a 5-bit exponent value, and a 2-bit mantissa value, and the second 8-bit floating point format includes a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and An execution circuit includes a matrix accelerator for accelerating matrix operations, wherein, in response to the single matrix instruction, the execution circuit is used to generate a plurality of products based on the first plurality of 8-bit floating-point data elements of the first source matrix and the second plurality of 8-bit floating-point data elements of the second source matrix, and accumulate each of the plurality of products with a corresponding 32-bit floating-point data element of the third source matrix to generate a corresponding 32-bit floating-point result data element of a result matrix.

2. The apparatus of claim 1, further comprising: Package components, including: The integrated circuit chip includes a graphics processor chiplet; The first basic chiplet includes: The first structure, and a first global cache coupled to the first structure; wherein the graphics processor chiplet is stacked on the first base chiplet; wherein a first interconnect structure couples the graphics processor chiplet to the first junction structure; A second basic chiplet coupled to the first basic chiplet via a second interconnect structure, the second basic chiplet comprising: The second structure, and a second global cache coupled to the second structure; A processor core chiplet, stacked on the second base chiplet, the processor core chiplet comprising a plurality of processor cores, Wherein a third interconnect structure couples the processor core chiplet to the second structure.

3. The device as claimed in claim 2, wherein: The graphics processor chiplet is fabricated using a different process technology than that used to fabricate the first base chiplet and the second base chiplet.

4. The device according to claim 2 or 3, further comprising: One or more memory controllers for coupling the graphics processor chiplet and the processor core chiplet to a unified memory, the graphics processor chiplet and the processor core chiplet for accessing the unified memory and sharing a unified virtual address space.

5. The device according to any one of claims 1 to 4, further comprising: A scheduler is used to schedule a group of commands for execution by the execution circuit according to the single matrix instruction.

6. The device according to any one of claims 1 to 5, wherein: The execution circuit is used to execute the single matrix instruction on multiple SIMD channels.

7. The device according to claim 6, wherein: The execution circuit is to multiply groups of 8-bit floating point data elements of the first plurality of 8-bit floating point data elements of the first source matrix with corresponding groups of 8-bit floating point data elements of the second plurality of 8-bit floating point data elements of the second source matrix in separate single instruction multiple data channels of the plurality of single instruction multiple data channels.

8. The device according to claim 6 or 7, wherein: The single instruction multiple data channel includes a 32-bit single instruction multiple data channel.

9. The device of claim 8, wherein: A group of four of the first plurality of 8-bit floating point data elements of the first source matrix is ​​used to be multiplied with a corresponding group of four of the second plurality of 8-bit floating point data elements of the second source matrix within one of the 32-bit single instruction multiple data paths.

10. The apparatus of claim 4, further comprising: Multiple memory management units for providing virtual to physical address mapping.

11. The device of claim 10, wherein: The plurality of memory management units include a first memory management unit associated with the processor core chiplet and a second memory management unit associated with the graphics processor chiplet.

12. The device of claim 11, wherein: The first memory management unit and the second memory management unit are synchronized according to the unified virtual address space.

13. The device according to any one of claims 10 to 12, wherein: The plurality of memory management units include an input-output memory management unit for managing page tables for mapping virtual addresses to multiple sets of physical addresses, including virtual addresses of the unified virtual address space shared by the graphics processor chiplet and the processor core chiplet.

14. A method comprising: decoding a single matrix instruction having a field for indicating an opcode and a location of a first source matrix, a second source matrix, and a third source matrix, the first source matrix comprising a first plurality of 8-bit floating point data elements encoded in a first 8-bit floating point format, the second source matrix comprising a second plurality of 8-bit floating point data elements encoded in a second 8-bit floating point format, the third source matrix comprising a plurality of 32-bit floating point data elements, wherein the first 8-bit floating point format includes a sign bit, a 5-bit exponent value, and a 2-bit mantissa value, and the second 8-bit floating point format includes a sign bit, a 4-bit exponent value, and a 3-bit mantissa value; and In response to the single matrix instruction, a plurality of products are generated based on the first plurality of 8-bit floating-point data elements of the first source matrix and the second plurality of 8-bit floating-point data elements of the second source matrix, and each of the plurality of products is accumulated with a corresponding 32-bit floating-point data element of the third source matrix to generate a corresponding 32-bit floating-point result data element of a result matrix.

15. The method of claim 14, further comprising: A group of commands are scheduled for execution according to the single matrix instruction.

16. The method of claim 14 or 15, further comprising: The single matrix instruction is executed on multiple SIMD paths.

17. The method of claim 16, further comprising: Groups of 8-bit floating point data elements of the first plurality of 8-bit floating point data elements of the first source matrix are multiplied in separate single instruction multiple data channels of the plurality of single instruction multiple data channels with corresponding groups of 8-bit floating point data elements of the second plurality of 8-bit floating point data elements of the second source matrix.

18. The method according to claim 16 or 17, wherein: The single instruction multiple data channel includes a 32-bit single instruction multiple data channel.

19. The method of claim 18, further comprising: A group of four of the first plurality of 8-bit floating point data elements of the first source matrix is ​​multiplied within one of the 32-bit single instruction multiple data paths with a corresponding group of four of the second plurality of 8-bit floating point data elements of the second source matrix.

20. A machine-readable medium comprising instructions which, in response to being executed on a computing device, cause the computing device to perform the method of any one of claims 14 to 19.

21. A method comprising: Performing a pipeline flush to allow the active graphics pipeline to complete any pending commands; Execution pipeline selection; configuring a graphics pipeline for operation and programming the pipeline; Configure a set of return buffers for corresponding pipelines to write data; Determine whether the selected pipeline is a 3D pipeline or a media pipeline; as well as Executes the commands associated with the selected pipeline.

22. A graphics processor, comprising: Vertex processor, used to execute vertex shader programs; The fragment processor is used to perform fragment shading operations; A memory management unit for providing virtual to physical address mapping; Cache; as well as The circuits are interconnected so that the graphics processor can interface with other IP cores in the system on chip.

23. A method comprising: compiling, at a compiler, a source code level description of a software program to a level having operations including FP format conversion instructions with random rounding for execution by processing logic; as well as The operations are compiled into machine-level object codes by an additional compiler, the machine-level object codes including FP format conversion instructions with random rounding for execution by a processing unit of a computation block.

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