Operation management method and device for multi-core computing system

Abstract

The invention provides an operation management method of a multi-core particle computing system. The method comprises the steps that a chip of the multi-core particle computing system comprises a general processor and a plurality of functional core particles; the universal processor distributes tasks to each functional core particle, and the functional core particles report the working state and the current working site to the universal processor; the universal processor judges whether the functional core particles are normal or not according to the working state, and if yes, the current working site corresponding to the functional core particles is stored; and otherwise, judging that the functional core particle has a fault, distributing the task currently executed by the functional core particle with the fault to the functional core particle with the same function and normal working state, and restarting the task distributed to the functional core particle with the fault from the stored working site by the functional core particle with the normal working state to obtain a task execution result.

Description

Technical Field

[0001] The present invention relates to the technical fields of integrated circuits, chip design and chip operating systems, and in particular to an operating system management method for a multi-chip computing system. Background Art

[0002] With the continuous development of semiconductor technology, Moore's Law has gradually become invalid in recent years. On the one hand, as the size of transistors continues to shrink, quantum effects have an increasingly greater impact on the performance of transistors, and the improvement of manufacturing processes has become more difficult due to physical limitations. Integrating more transistors will also bring power consumption and heat dissipation problems; on the other hand, as the chip area increases, the chip yield continues to decrease, and the resulting cost issues are gradually becoming unacceptable. In current emerging fields such as deep learning, high-performance computing, and cloud computing, the demand for processor computing power is growing exponentially. Since 2018, the demand for computing power has doubled about every two months, and insufficient computing power has become an important bottleneck affecting the development of science and technology. A single processor is difficult to meet the needs of large-scale data processing and high memory bandwidth. Therefore, using many small chips to form a multi-chip module has become a mainstream solution. Each chip in a multi-chip module can be designed and implemented on an independent die, which can be manufactured using different process nodes. Therefore, the multi-chip module has significant advantages in design time and manufacturing cost, but it requires dense interconnection between chips to ensure the bandwidth of data transmission, and also requires advanced packaging technology to reduce its operating power consumption.

[0003] A multi-chip computing system is a complex and compact system that contains a large number of chips, power supplies, memory and other modules, and these components need to be integrated into a complete wafer substrate. How the operating system manages these components to make them work together is an important issue. Generally speaking, the management of a multi-chip computing system needs to consider factors such as task scheduling, concurrency and synchronization between chips, power management, memory management, interrupt handling and fault tolerance.

[0004] Existing multi-chip system operating systems often focus on improving the efficiency of task scheduling and solving the problems of concurrency and synchronization between chips to improve the efficiency of the entire system. At the same time, some work is also devoted to optimizing memory management and power management in multi-chip systems. Work on improving the fault tolerance of multi-chip systems is relatively rare. Existing work focuses more on the error correction capability of data transmission in the link between chips, and there is no good solution for catastrophic errors caused by damage to a chip.

[0005] Since multi-chip computing systems are very different from traditional computer architectures, when a chip is damaged, the multi-chip system cannot be repaired by replacing the chip, and the entire module needs to be replaced. Summary of the invention

[0006] The present invention application aims to enhance the fault tolerance of a multi-chip computing system and proposes a multi-chip system operating system management method. The invention enables the entire module to continue to operate while shielding the damaged chip, thereby avoiding data corruption caused by downtime. The goal of the present invention is to provide an effective and reliable multi-chip system operating system management solution to meet the needs of improving system stability and fault tolerance.

[0007] Specifically, if Figure 4 As shown, the present invention proposes an operation management method for a multi-chip computing system, which includes:

[0008] Monitoring step S1, the chip of the multi-chip computing system includes a general processor and multiple functional chips; the general processor assigns tasks to each of the functional chips, and the functional chips report the working status and current working scene to the general processor;

[0009] In the fault-tolerant step S2, the general processor determines whether the functional core particle is normal according to the working state. If normal, the corresponding current working scene is saved; otherwise, the functional core particle is determined to be faulty, and the task currently executed by the faulty functional core particle is assigned to the functional core particle with the same function and normal working state. The functional core particle with normal working state restarts the task assigned to the faulty functional core particle from the restored and saved working scene to obtain the task execution result.

[0010] The operation management method of the multi-chip computing system, wherein the fault tolerance step comprises:

[0011] If the general processor times out without receiving the working status of the functional chip, it is determined that the functional chip has failed, and the task currently executed by the failed functional chip is assigned to a functional chip with the same function and normal working status. The functional chip with normal working status restarts the task assigned to the failed functional chip from the restored and saved work site to obtain the task execution result.

[0012] The operation management method of the multi-chip computing system, wherein the fault-tolerance step includes: cutting off the power input of the failed functional chip.

[0013] The operation management method of the multi-chip computing system, wherein the working status is a signal generated by the functional chip according to the self-check mechanism representing whether it is currently working normally, or the working status information is a signal sent periodically by the functional chip representing its survival status.

[0014] like Figure 5 As shown, the present invention also proposes an operation management device for a multi-chip computing system, which includes:

[0015] Monitoring module M1, the chip of the multi-chip computing system includes a general processor and multiple functional chips; the general processor assigns tasks to each of the functional chips, and the functional chips report the working status and current working site to the general processor;

[0016] Fault-tolerant module M2, the general processor determines whether the functional core is normal according to the working status. If it is normal, the corresponding current working scene is saved; otherwise, it is determined that the functional core is faulty, and the task currently executed by the faulty functional core is assigned to the functional core with the same function and normal working status. The functional core with normal working status restarts the task assigned to the faulty functional core from the restored and saved working scene to obtain the task execution result.

[0017] The operation management device of the multi-core computing system, wherein the fault-tolerant module comprises:

[0018] If the general processor times out without receiving the working status of the functional chip, it is determined that the functional chip has failed, and the task currently executed by the failed functional chip is assigned to a functional chip with the same function and normal working status. The functional chip with normal working status restarts the task assigned to the failed functional chip from the restored and saved work site to obtain the task execution result.

[0019] The operation management device of the multi-chip computing system, wherein the fault-tolerant module includes: cutting off the power input of the failed functional chip.

[0020] The operation management device of the multi-chip computing system, wherein the working status is a signal generated by the functional chip according to the self-check mechanism representing whether it is currently working normally, or the working status information is a signal sent periodically by the functional chip representing its survival status.

[0021] The present invention also proposes an electronic device, which includes an operation management device of a multi-core computing system, and the electronic device is connected to an information display device, which is used to display the task execution result according to the display parameters and attributes set by the user or through an artificial intelligence model.

[0022] The present invention also proposes a storage medium for storing a computer program for executing the operation management method of the multi-chip computing system.

[0023] It can be seen from the above scheme that the advantages of the present invention are:

[0024] The present invention proposes an operation management method for a multi-chip system and provides a matching inter-chip communication structure. Through this operating system management solution, the fault tolerance of the overall module is significantly improved, the risk of data damage and loss caused by downtime due to chip damage is reduced, and the cost of maintaining the system is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of a 3×3 multi-core module provided by the present invention;

[0026] Figure 2 It is the necessary data path required for increasing fault tolerance in this example;

[0027] Figure 3 This is a schematic diagram of the power input control of the slave node by the master node in this example;

[0028] Figure 4 is a flow chart of the method of the present invention;

[0029] Figure 5 It is a module diagram of the device of the present invention;

[0030] Figure 6 This is a schematic diagram of the structure of a first electronic device of the present invention;

[0031] Figure 7 This is a schematic diagram of the application environment structure of the first electronic device of the present invention;

[0032] Figure 8 It is a schematic diagram of the structure of a second electronic device of the present invention.

[0033] Reference numerals:

[0034] A-First electronic device;

[0035] B-operation management device of multi-chip computing system;

[0036] C-data acquisition equipment;

[0037] D-information display device;

[0038] 1000 - second electronic device;

[0039] Ⅰ-computational unit;

[0040] II-ROM;

[0041] III-RAM;

[0042] IV-bus;

[0043] V-interface;

[0044] VI - input unit;

[0045] VII-output unit;

[0046] VIII- Storage medium;

[0047] Ⅸ-Communication unit. DETAILED DESCRIPTION

[0048] It should be noted that the processor described in the present invention is the control center of the electronic device, which can be a processor or a general term for multiple processing elements. For example, it can be one or more central processing units (CPUs), or application specific integrated circuits (ASICs), or one or more integrated circuits configured to implement the embodiments of the present invention, such as one or more microprocessors (digital signal processors, DSPs), or one or more field programmable gate arrays (FPGAs).

[0049] Optionally, the processor can perform various functions of the electronic device by running or executing a software program stored in the memory, and calling data stored in the memory.

[0050] In a specific implementation, as an embodiment, the processor may include one or more CPUs. Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions). Electronic devices may include: servers, desktop computers, laptops, smart phones, tablet computers, embedded computers, etc., wherein the embedded computers include vehicles and robots, etc.

[0051] The memory is used to store the software program for executing the solution of the present invention, and the execution is controlled by the processor. The specific implementation method can refer to the above method embodiment, which will not be repeated here.

[0052] It should be noted that the structure of the electronic device shown in the drawings of the present invention does not constitute a limitation thereto, and the actual knowledge structure recognition device may include more or fewer components than shown in the drawings, or a combination of certain components, or a different arrangement of components.

[0053] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0054] It should also be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0055] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0056] It should also be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0057] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0058] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0059] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0060] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0061] When the inventor was conducting research on the multi-chip system, he found that in order to improve the concurrency of the multi-chip system, there are often multiple key chips in the multi-chip system. When one of the chips is damaged (for example, the chip cannot work properly and cannot calculate the correct output), in theory, the module can still continue to operate at a lower efficiency. This fault tolerance can effectively reduce costs and avoid data loss caused by downtime when certain catastrophic errors occur.

[0062] Therefore, the difficulty of the technology of the present invention lies in how to discover and shield damaged core particles, and perform on-site recovery after a system error. After studying the operating system of a multi-core system, the inventor found that these capabilities can be achieved with support at the operating system level. The operating system can periodically save the scene and check the working status of each core particle, and shield the problem core particle and restore the scene after discovering that the core particle is damaged. In addition to support at the operating system level, it is also necessary to design a specific communication path between core particles to support operations such as core particle state transmission and core particle shielding.

[0063] In view of the shortcomings of the prior art, the present invention provides a multi-chip operating system that can improve the fault tolerance of the system, and designs an inter-chip communication structure that matches the operating system. The technical solution used by the present invention to improve the fault tolerance of the system is as follows:

[0064] 1. At the operating system level, a method is proposed to regularly detect the working status of each chip, restore the working scene when one of the chips is damaged, and try to continue execution after blocking it. It can also cut off the data path to the damaged chip and cut off the power supply of the damaged chip to avoid damage to the power module and other chips due to internal short circuits and other faults of the damaged chip.

[0065] 2. At the inter-chiplet communication level, the general processor chiplet serves as the master node, and other functional chiplets serve as slave nodes. The slave node can periodically send working status information to the master node, and the master node can decide whether to continue exchanging data with the slave node. Among them, the other functional chiplets can be chiplets responsible for certain dedicated tasks in a multi-chiplet system. The tasks input to different functional chiplets can be operations such as calculating fast number theoretic transformations (NTT), performing certain encryption operations on the input, or performing simple image processing. If the slave node has some self-checking mechanisms, the working status information can be a signal sent to represent whether it is currently working normally. Otherwise, the working status information can be a signal sent periodically to represent its survival status. When the master node does not receive the signal, it will be considered to be abnormal.

[0066] In general, the present invention improves the fault tolerance of the overall system by designing a multi-chiplet system operating system and corresponding inter-chiplet communication paths, and using the collaborative working method of software and hardware.

[0067] In order to make the above features and effects of the present invention more clearly and understandably described, embodiments are given below and described in detail with reference to the accompanying drawings. This specification discloses one or more embodiments that include the features of the present invention. The disclosed embodiments are only for illustration. The scope of protection of the present invention is not limited to the disclosed embodiments, and the present invention is defined by the attached claims.

[0068] like Figure 1As shown in the figure, a 3×3 module consisting of a general-purpose processor, functional components, memory, and IO nodes is taken as an example. The general-purpose processor, as the main node, has functions such as allocating scheduling tasks and performing power management. The central power module is responsible for supplying power to the surrounding nodes, and the memory node and I / O node play the role of main memory and exchanging information with the outside respectively. In addition, the entire system also contains two types of functional nodes, which are used to execute function 1 and function 2 respectively. In order to speed up the execution speed, the system contains two independent function 1 nodes.

[0069] In the above example, if one of the function 1 nodes is damaged, the above 3×3 modules can theoretically still continue to work at a relatively low efficiency and complete a certain stage of the task before being repaired and replaced. To achieve this goal, there needs to be a Figure 2 As shown in the connection path, the two functional nodes regularly report their working status to the master node, and the master node needs to regularly save the current working scene to the memory node. Figure 3 As shown, the master node can also control the power input of the two function 1 nodes respectively.

[0070] When the module is working normally, the master node saves the current working scene to the memory each time it receives the correct working status reported by the two function 1 nodes. At this time, if one of the function nodes is damaged, the master node receives the damage signal reported by the damaged node or does not receive the report signal of the damaged node after timeout, the master node considers that the function node has failed, sends a signal to cut off the power input of the function node, modifies the task allocation algorithm to allocate the current and subsequent tasks of the node to another intact node, restores the working scene when the node is not damaged from the memory, and then restarts the work to continue running, and sends the error report to the external controller through the I / O node.

[0071] The above process ensures the correctness of the data after the restart work, and will not cause downtime to affect the entire workflow. The module can be replaced after this part of the work is completed.

[0072] The following is a system embodiment corresponding to the above method embodiment. This embodiment can be implemented in conjunction with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0073] like Figure 5 As shown, the present invention also proposes an operation management device for a multi-chip computing system, which includes:

[0074] Monitoring module M1, the chip of the multi-chip computing system includes a general processor and multiple functional chips; the general processor assigns tasks to each of the functional chips, and the functional chips report the working status and current working site to the general processor;

[0075] Fault-tolerant module M2, the general processor determines whether the functional core is normal according to the working status. If it is normal, the corresponding current working scene is saved; otherwise, it is determined that the functional core is faulty, and the task currently executed by the faulty functional core is assigned to the functional core with the same function and normal working status. The functional core with normal working status restarts the task assigned to the faulty functional core from the restored and saved working scene to obtain the task execution result.

[0076] The operation management device of the multi-core computing system, wherein the fault-tolerant module comprises:

[0077] If the general processor times out without receiving the working status of the functional chip, it is determined that the functional chip has failed, and the task currently executed by the failed functional chip is assigned to a functional chip with the same function and normal working status. The functional chip with normal working status restarts the task assigned to the failed functional chip from the restored and saved work site to obtain the task execution result.

[0078] The operation management device of the multi-chip computing system, wherein the fault-tolerant module includes: cutting off the power input of the failed functional chip.

[0079] The operation management device of the multi-chip computing system, wherein the working status is a signal generated by the functional chip according to the self-check mechanism representing whether it is currently working normally, or the working status information is a signal sent periodically by the functional chip representing its survival status.

[0080] like Figure 6 As shown, the present invention further proposes a first electronic device A in another embodiment, which includes the operation management device of the multi-chip computing system.

[0081] like Figure 7 As shown, the first electronic device A can also be connected to the data acquisition device C and the information display device D through a wired or wireless information transmission scheme. The data acquisition device C is used to collect and obtain videos to be identified and classified, such as the sorting videos described in the embodiment of the present invention, and the information display device D is used to display the video classification results obtained by the analysis of the present invention.

[0082] The information display device D can sort and process the data output by the first electronic device A based on the information display mechanism to improve the readability of the data output by the first electronic device A. The information display mechanism can be manually preset, for example, the data output by the first electronic device A is visually displayed, which can be based on the display parameters and / or attributes set by the user. The display parameters can be, for example, the display data range, and the display attributes can be, for example, the display font, color, whether to scroll and play, etc. The key information specified by the task execution results and task execution status is presented to the user, and the user can understand this information more timely without having to access the secondary page or scroll the page, saving the user's operation. Or the information display mechanism can be an artificial intelligence AI display model, which can learn the user's key information based on the user's previous usage habits, such as viewing time, number of clicks, number of edits, etc., and then automatically present rich and necessary key information to the user.

[0083] The present invention also proposes a storage medium VIII in another embodiment for storing a computer program for executing the operation management method of the multi-chip computing system. It should be understood that the storage medium in the embodiment of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DRRAM).

[0084] Figure 8A schematic block diagram of a second electronic device 1000 that can be used to implement an embodiment of the present invention is shown. The second electronic device 1000 electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The second electronic device 1000 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples, and are not intended to limit the implementation of the present invention described and / or required herein. The second electronic device 1000 may be the same or different from the first electronic device A.

[0085] The second electronic device 1000 includes a computing unit I, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory II (ROM) or a computer program loaded from a storage medium VIII into a random access memory (RAM) III. In RAM III, various programs and data required for the operation of the device 1000 can also be stored. The computing unit I, ROM II, and RAM III are connected to each other via a bus IV. An input / output (I / O) interface V is also connected to the bus IV.

[0086] A plurality of components in the second electronic device 1000 are connected to the I / O interface V, including: an input unit VI, such as a keyboard, a mouse, etc.; an output unit VII, such as various types of displays, speakers, etc.; a storage medium VIII, such as a disk, an optical disk, etc.; and a communication unit IX, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit IX allows the second electronic device 1000 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0087] The computing unit I may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit I include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit I performs the various methods and processes described above, such as method steps S1 and S2. For example, in some embodiments, the method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage medium VIII. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 1000 via ROM II and / or communication unit IX. When the computer program is loaded into RAM III and executed by the computing unit I, one or more steps of the method described above may be performed. Alternatively, in other embodiments, the computing unit I may be configured to execute the method in any other appropriate manner (e.g., by means of firmware).

[0088] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A method for operating and managing a multi-chip computing system, characterized in that: include: Monitoring step, the chip of the multi-chip computing system includes a general processor and a plurality of functional chips; the general processor assigns tasks to each of the functional chips, and the functional chips report the working status and current working scene to the general processor; In the fault-tolerant step, the general processor determines whether the functional core particle is normal according to the working status. If normal, the corresponding current working scene is saved; otherwise, the functional core particle is determined to be faulty, and the task currently executed by the faulty functional core particle is assigned to the functional core particle with the same function and normal working status. The functional core particle with normal working status restarts the task assigned to the faulty functional core particle from the restored and saved working scene to obtain the task execution result.

2. The operation management method of a multi-chip computing system according to claim 1, characterized in that: The fault tolerance steps include: If the general processor times out without receiving the working status of the functional chip, it is determined that the functional chip has failed, and the task currently executed by the failed functional chip is assigned to a functional chip with the same function and normal working status. The functional chip with normal working status restarts the task assigned to the failed functional chip from the restored and saved work site to obtain the task execution result.

3. The operation management method of a multi-chip computing system according to claim 1 or 2, characterized in that: The fault-tolerance step includes: cutting off the power input of the failed functional core.

4. The operation management method of a multi-chip computing system according to claim 1 or 2, characterized in that: The working status is a signal generated by the functional core according to a self-checking mechanism, representing whether it is currently working normally, or the working status information is a signal periodically sent by the functional core to represent its survival status.

5. An operation management device for a multi-chip computing system, characterized in that: include: Monitoring module, the chip of the multi-chip computing system includes a general processor and multiple functional chips; the general processor assigns tasks to each of the functional chips, and the functional chips report the working status and current working scene to the general processor; A fault-tolerant module is a general-purpose processor that determines whether a functional core particle is normal according to the working status. If normal, the corresponding current working scene is saved; otherwise, the functional core particle is determined to be faulty, and the task currently executed by the faulty functional core particle is assigned to a functional core particle with the same function and normal working status. The functional core particle with normal working status restarts the task assigned to the faulty functional core particle from the restored and saved working scene to obtain the task execution result.

6. The operation management device of the multi-chip computing system according to claim 5, characterized in that: The fault-tolerant module includes: If the general processor times out without receiving the working status of the functional chip, it is determined that the functional chip has failed, and the task currently executed by the failed functional chip is assigned to a functional chip with the same function and normal working status. The functional chip with normal working status restarts the task assigned to the failed functional chip from the restored and saved work site to obtain the task execution result.

7. The operation management device of a multi-chip computing system according to claim 5 or 6, characterized in that: The fault-tolerant module includes: cutting off the power input of the functional core particle that fails.

8. The operation management device of a multi-chip computing system according to claim 5 or 6, characterized in that: The working status is a signal generated by the functional core according to a self-checking mechanism, representing whether it is currently working normally, or the working status information is a signal periodically sent by the functional core to represent its survival status.

9. An electronic device, characterized in that: An operation management device for a multi-core computing system comprising the electronic device described in claims 5-8, wherein the electronic device is connected to an information display device, and the information display device is used to display the task execution result according to the display parameters and attributes set by the user or through an artificial intelligence model.

10. A storage medium for storing a computer program for executing the operation management method of the multi-chip computing system according to claims 1-4.

Images