SOI semiconductor structure of integrated longitudinal device and manufacturing method of SOI semiconductor structure

Abstract

The invention relates to an SOI semiconductor structure integrated with a longitudinal device and a manufacturing method thereof, and the method comprises the steps: obtaining a wafer which comprises a substrate, a buried dielectric layer on the substrate, a first conductive type region on the buried dielectric layer, and a first electrode doping region formed at the bottom of the first conductive type region and on the buried dielectric layer; forming an isolation structure on the buried dielectric layer, wherein the isolation structure divides the first conductive type region into a longitudinal device region and a first device region; forming a CMOS device main body in the first device region through a CMOS process, and forming a longitudinal device main body in the longitudinal device region; forming a leading-out groove of which the bottom reaches the first electrode doping region in the longitudinal device region; and filling the lead-out groove with a conductive material to form a conductive structure for leading out the first electrode doped region to the front surface of the device. The first electrode doped region of the longitudinal device is led out from the front surface of the device by utilizing the longitudinal conductive structure, so that the longitudinal device can be integrated in a process platform by adopting a process compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to an SOI semiconductor structure integrating vertical devices, and also to a manufacturing method of the SOI semiconductor structure integrating vertical devices. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process technology that can produce Bipolar (bipolar transistors), CMOS (metal oxide semiconductor field effect transistors) and DMOS devices (double diffused metal oxide semiconductor field effect transistors) on the same chip. The devices prepared by this process combine the advantages of high transconductance and strong load driving capability of bipolar devices and high integration and low power consumption of CMOS; at the same time, DMOS can carry a larger voltage and has extremely low power consumption when working in switching mode, and can transfer high power to the load without expensive packaging and cooling systems. This technology has been widely used in automotive electronics, power management, lighting, and radio frequency communications. Among them, DMOS, which is responsible for the power part, is the core of this type of circuit. Because it needs to carry relatively large current and voltage, the area often occupies 30%-90% of the entire area, and is the key to the entire integrated circuit.

[0003] In the exemplary BCD process, DMOS uses lateral channel LDMOS (lateral double diffused metal oxide semiconductor field effect transistor). For LDMOS, the drift region needs to bear the withstand voltage, so for devices with higher withstand voltage requirements, the drift region needs to be long enough to bear the withstand voltage, and the size of the device is larger. Summary of the invention

[0004] Based on this, it is necessary to provide an SOI semiconductor structure with integrated vertical devices.

[0005] A SOI semiconductor structure for an integrated vertical device comprises: a substrate; a buried dielectric layer, arranged on the substrate; a first device body, arranged on the buried dielectric layer; a vertical device body, arranged on the buried dielectric layer, comprising a first electrode doping region arranged at the bottom of the vertical device body; a first electrode doping region lead-out structure, comprising a conductive structure arranged in a lead-out groove, the bottom of the conductive structure being electrically connected to the first electrode doping region, the first electrode doping region lead-out structure being used to lead the first electrode doping region to the front side of the device, the inner wall of the lead-out groove having an insulating layer surrounding the conductive structure; a first isolation structure, located between the first device body and the vertical device body, and having a bottom reaching the buried dielectric layer, the first isolation structure being used to isolate the vertical device body from the first device body.

[0006] The SOI semiconductor structure with integrated vertical devices, through the first electrode doping region lead-out structure, leads the first electrode doping region of the vertical device from the front of the device, so that the relatively small vertical device (for reference, the area of ​​VDMOS is smaller than that of LDMOS) can be integrated in the process platform, making the complex circuit more miniaturized, and the device process compatibility is high. And the vertical device is isolated from other devices by using the characteristics of SOI, which can make the entire circuit safer and more reliable.

[0007] In one of the embodiments, the withstand voltage of the vertical device is greater than the withstand voltage of the first device.

[0008] In one embodiment, the vertical device is a high voltage device and the first device is a low voltage device.

[0009] In one embodiment, the vertical device is a VDMOS device, the first electrode doping region is a drain doping region of the VDMOS and has a first conductivity type, and the vertical device body also includes: a VDMOS well region, having a second conductivity type, disposed above the drain doping region, the first conductivity type and the second conductivity type being opposite conductivity types; a drift region, having a first conductivity type, disposed between the drain doping region and the VDMOS well region; a VDMOS source region, having a first conductivity type, disposed in the VDMOS well region; and a VDMOS gate, disposed on the drift region.

[0010] In one embodiment, the first device body includes: a CMOS well region having a second conductivity type, disposed above the buried dielectric layer; a first conductivity type region, disposed between the CMOS well region and the buried dielectric layer; a CMOS source region having a first conductivity type, disposed in the CMOS well region; a CMOS drain region having a first conductivity type, disposed in the CMOS well region; and a CMOS gate, disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

[0011] In one embodiment, the VDMOS source region, the CMOS source region and the CMOS drain region are located at the same level in the SOI semiconductor structure.

[0012] In one embodiment, the SOI semiconductor structure further includes: a second isolation structure, connected to the first isolation structure, and the bottom of which reaches the buried dielectric layer, and the second isolation structure and the first isolation structure together surround the first device body; a third isolation structure, connected to the first isolation structure, and the bottom of which reaches the buried dielectric layer, and the third isolation structure and the first isolation structure together surround the vertical device body.

[0013] In one embodiment, the conductive structure is a closed ring structure located inside a region surrounded by the first isolation structure and the third isolation structure.

[0014] In one of the embodiments, the conductive structure includes metal and / or alloy.

[0015] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0016] It is also necessary to provide a method for manufacturing an SOI semiconductor structure with integrated vertical devices.

[0017] A method for manufacturing an SOI semiconductor structure with integrated vertical devices, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, a first conductive type region on the buried dielectric layer, and a first electrode doping region formed at the bottom of the first conductive type region and on the buried dielectric layer; the first electrode doping region has a first conductive type; forming a first isolation structure on the buried dielectric layer to separate the first conductive type region into a vertical device region and a first device region, the bottom of the first isolation structure reaches the buried dielectric layer, and the first electrode doping region is located in the vertical device region; forming a first device body in the first device region and forming the remaining vertical device body in the vertical device region; forming an extraction groove in the vertical device region by photolithography and etching, the bottom of the extraction groove reaches the first electrode doping region; forming an insulating layer on the inner wall of the extraction groove; filling the extraction groove with conductive material to form a conductive structure for extracting the first electrode doping region to the front side of the device.

[0018] The manufacturing method of the SOI semiconductor structure with integrated vertical devices uses the conductive structure in the lead-out groove to lead the first electrode doping region of the vertical device from the front of the device, so that a process compatible with CMOS can be used to integrate a relatively small vertical device in a process platform, making the complex circuit more miniaturized and having higher economic benefits. In addition, the vertical device is isolated from other devices by using the characteristics of SOI, making the entire circuit safer and more reliable.

[0019] In one of the embodiments, forming the first device body in the first device area includes: forming a CMOS well region, a CMOS source region, a CMOS drain region and a CMOS gate in the first device area by a CMOS process; forming the remaining vertical device bodies in the vertical device area includes: forming a VDMOS well region, a VDMOS source region and a VDMOS gate in the vertical device area by a CMOS process at the same time; the VDMOS well region has a second conductivity type and is formed in the first conductivity type region and above the first electrode doping region, the VDMOS source region has a first conductivity type and is formed in the VDMOS well region, and the VDMOS gate is formed on the first conductivity type region; the CMOS well region has a second conductivity type and is formed in the first conductivity type region and above the buried dielectric layer, the CMOS source region and the CMOS drain region have a first conductivity type and are formed in the CMOS well region, and the CMOS gate is formed on the CMOS well region between the CMOS source region and the CMOS drain region; the first conductivity type and the second conductivity type are opposite conductivity types.

[0020] In one embodiment, the step of obtaining a wafer includes: obtaining a wafer having the substrate, a buried dielectric layer and a semiconductor layer on the buried dielectric layer, the semiconductor layer having a first conductivity type; forming the first electrode doping region in the semiconductor layer by photolithography and implantation, the doping concentration of the first electrode doping region being greater than the doping concentration of the semiconductor layer; forming the first conductivity type region having a concentration gradient by multiple epitaxy, the doping concentration of the first conductivity type region changing from high to low from bottom to top.

[0021] In one of the embodiments, in the step of forming the lead-out groove in the vertical device region by photolithography and etching, the critical dimension of the lead-out groove is 0.5 micrometers to 2 micrometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0023] Figure 1 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in one embodiment of the present application;

[0024] Figure 2a to Figure 2g is based on Figure 1 A schematic cross-sectional view of a device during manufacturing by the method shown;

[0025] Figure 3 It is a schematic cross-sectional structure diagram of an SOI semiconductor structure integrating a vertical device in one embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0028] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0029] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0030] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0032] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0033] With the wide application of ultra-large-scale integrated circuits in various fields, the system has higher and higher requirements for the development of high-voltage and high-power semiconductor devices. Integrated high-voltage devices using silicon on insulator (SOI) technology have the advantages of SOI technology and the device itself, with fast operating speed, low parasitic effects, high breakdown voltage, simple process preparation, and convenient integration, so they have been widely studied and applied. This application proposes a process method for integrating a vertical channel VDMOS (vertical double diffused metal oxide semiconductor field effect transistor) device on an SOI substrate, which can integrate a VDMOS with low on-resistance, small area, and high withstand voltage into a BCD process platform to obtain a DMOS with higher power density. At the same time, because VDMOS can be packaged together with integrated CMOS, complex circuits can be miniaturized.

[0034] Figure 1 1 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in an embodiment of the present application, comprising the following steps:

[0035] S110, obtaining a wafer.

[0036] See also Figure 2b The obtained wafer includes a substrate 10, a buried dielectric layer 20 on the substrate 10, a first conductive type region 22 on the buried dielectric layer 20, and a first electrode doping region 42 formed at the bottom of the first conductive type region 22 and on the buried dielectric layer 20. The first electrode doping region 42 has a first conductive type. In one embodiment of the present application, the first conductive type is N-type and the second conductive type is P-type. The first conductive type region 22 is correspondingly an N-type region, and the first electrode doping region 42 is an N+ region. In other embodiments of the present application, the first conductive type may also be P-type and the second conductive type may be N-type.

[0037] exist Figure 2b In the embodiment shown, the substrate 10 is a P-type silicon substrate. The buried dielectric layer 20 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide. In one embodiment of the present application, the buried dielectric layer 20 has a thickness of 1 micron to 8 microns.

[0038] The doping concentration of the first electrode doping region 42 is greater than the doping concentration of the first conductive type region 22 .

[0039] In one embodiment of the present application, step S110 first obtains a wafer having a substrate 10, a buried dielectric layer 20, and a semiconductor layer 21 on the buried dielectric layer 20, and then forms a photoresist layer 92 on the upper surface of the semiconductor layer 21 by photolithography, exposing a position where the first electrode doping region 42 is to be formed, and then injects first conductive type ions to form the first electrode doping region 42, see Figure 2a The semiconductor layer 21 has a first conductivity type. In one embodiment of the present application, the thickness of the semiconductor layer 21 is 0.5 micrometers to 2 micrometers.

[0040] In one embodiment of the present application, after removing the photoresist layer 92, an epitaxial layer of the first conductivity type having a concentration gradient can be formed on the semiconductor layer 21 and the first electrode doping region 42 by multiple epitaxy, thereby obtaining the first conductivity type region 22. The doping concentration of the first conductivity type region 22 (the doping concentration of the first conductivity type ions) changes from high to low from bottom to top. In one embodiment of the present application, the thickness of the epitaxial layer on the semiconductor layer 21 and the first electrode doping region 42 is 2 microns to 8 microns, and the specific epitaxial thickness is determined according to the designed withstand voltage of the device.

[0041] S120 , forming a first isolation structure that separates the first conductive type region into a vertical device region and a first device region.

[0042] A first isolation structure 32 is formed on the buried dielectric layer 20 to separate the first conductive type region 22 into a vertical device region and a first device region. The bottom of the first isolation structure 32 reaches the buried dielectric layer 20, and the first electrode doping region 42 is located in the vertical device region. In one embodiment of the present application, an isolation groove is formed by photolithography and etching, and then an insulating material is deposited in the isolation groove to form the first isolation structure 32.

[0043] exist Figure 2c In the illustrated embodiment, while forming the first isolation structure 32, a second isolation structure 34 and a third isolation structure 36 are also formed. The second isolation structure 34 is connected to the first isolation structure 32, and the bottom reaches the buried dielectric layer 20. The second isolation structure 34 and the first isolation structure 32 together surround the first device region in the horizontal direction. The third isolation structure 36 is connected to the first isolation structure 32, and the bottom reaches the buried dielectric layer 20. The third isolation structure 36 and the first isolation structure 32 together surround the vertical device region in the horizontal direction.

[0044] S130, forming a CMOS device body in the first device region and a vertical device body in the vertical device region by using a CMOS process.

[0045] In one embodiment of the present application, the vertical device is a VDMOS device. Figure 2d , a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564 and a CMOS gate 58 can be formed in the first device region by conventional CMOS processes, and a VDMOS well region 44, a VDMOS source region 46 and a VDMOS gate 48 are formed in the vertical device region. The first electrode doping region 42 is a drain doping region of the VDMOS. The VDMOS well region 44 has a second conductivity type and is formed in the first conductivity type region 22 in the vertical device region and above the first electrode doping region 42. The VDMOS source region 46 has a first conductivity type and is formed in the VDMOS well region 44. The VDMOS gate 48 is formed on the first conductivity type region 22 in the vertical device region. The CMOS well region 54 has a second conductivity type and is formed in the first conductivity type region 22 in the first device region and above the buried dielectric layer 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564 .

[0046] S140, forming a lead-out groove in the vertical device region by photolithography and etching.

[0047] In one embodiment of the present application, after forming an interlayer dielectric (ILD) layer 60 by deposition, a photoresist layer 94 is formed by photolithography to expose the position where the lead-out groove 49 is to be formed. Figure 2e Then, an extraction groove 49 is formed by etching, and the bottom of the extraction groove 49 reaches the first electrode doping region 42. The interlayer dielectric layer 60 covers the CMOS well region 54, the CMOS source region 562, the CMOS drain region 564, the CMOS gate 58, the VDMOS well region 44, the VDMOS source region 46 and the VDMOS gate 48.

[0048] In one embodiment of the present application, the critical dimension (CD) of the lead-out groove 49 is 0.5 microns to 2 microns. The critical dimension is the size of the groove opening. In one embodiment of the present application, the lead-out groove 49 is a closed ring structure located inside the area surrounded by the first isolation structure 32 and the third isolation structure 36. The ring structure can be a circular ring, a square ring, or a closed ring of other shapes.

[0049] S150, forming an insulating layer on the inner wall of the lead-out groove.

[0050] In one embodiment of the present application, after removing the photoresist layer 94, the lead-out groove 49 may be filled with 0.2 micron to 0.8 micron thick silicon dioxide as an insulating layer 492 by SACVD (sub-atmospheric pressure chemical vapor deposition) or low pressure chemical vapor deposition (LPCVD) using TEOS (tetraethyl orthosilicate) as a reactant. Then, the insulating layer 492 at the bottom of the lead-out groove 49 is removed by etching, thereby exposing the first electrode doping region 42. Figure 2f .

[0051] S160, filling the lead-out groove with a conductive material to form a longitudinal conductive structure that leads the first electrode doping region to the front side of the device.

[0052] The conductive material may be a metal and / or alloy. In one embodiment of the present application, the longitudinal conductive structure 494 is a tungsten plug. Figure 2g .

[0053] After step S160 is completed, through holes / contact holes of each electrode of the device are made. Figure 3 , forming a first contact hole 62 for leading out the CMOS source region 562, a second contact hole 64 for leading out the CMOS drain region 564, a third contact hole 63 for leading out the CMOS gate 58, a fourth contact hole 66 for leading out the VDMOS source region 46, and a fifth contact hole 68 for leading out the VDMOS gate 48.

[0054] In one embodiment of the present application, Figure 2g A layer of silicon oxynitride is deposited on the obtained structure, that is, a layer of silicon oxynitride is deposited on the interlayer dielectric 60, and then the contact holes are photolithographically etched, and small holes are also etched above the conductive structure 494, and then the contact holes and the small holes above the conductive structure 494 are filled with conductive materials (such as metals and / or alloys), and finally the silicon oxynitride layer (and the conductive materials at the corresponding positions) are removed by CMP (chemical mechanical polishing). The deposition of the silicon oxynitride layer can prevent the photoresist from being left in the lead-out groove 49. In one embodiment of the present application, the thickness of the deposited silicon oxynitride layer is to .

[0055] The manufacturing method of the SOI semiconductor structure with integrated vertical devices described above uses the conductive structure 494 in the lead-out groove 49 to lead the first electrode doping region 42 of the vertical device (for example, when the vertical device is VDMOS, the first electrode doping region 42 is a drain doping region, and when the vertical device is IGBT, it is an emitter doping region) from the front of the device, so that a process compatible with CMOS can be used to integrate a relatively small vertical device in a process platform, making the complex circuit more miniaturized and having higher economic benefits. And by using the characteristics of SOI to isolate the vertical device from other devices, the entire circuit can be made safer and more reliable.

[0056] In one embodiment of the present application, the aforementioned SOI semiconductor structure is a BCD process platform. In one embodiment of the present application, the vertical device body formed in step S130 can also be an IGBT (insulated gate bipolar transistor) device, an SGT (Shielded Gate Trench) device, etc. The multiple epitaxial formation of the first conductive type region 22 with a concentration difference in step S110 is conducive to obtaining a higher device withstand voltage, so that vertical power devices such as IGBT and SGT can be introduced into the SOIBCD process.

[0057] The present application accordingly provides an SOI semiconductor structure with integrated vertical devices. Figure 3 The process platform includes a substrate 10, a buried dielectric layer 20, a first device body ( Figure 3 Not marked), vertical device body ( Figure 3 Not marked), the first electrode doping region lead-out structure ( Figure 3 The buried dielectric layer 20 is disposed on the substrate 10. The first device body and the vertical device body are disposed on the buried dielectric layer 20. The vertical device body includes a first electrode doping region 42 disposed at the bottom of the vertical device body. The first electrode doping region lead-out structure includes a lead-out groove ( Figure 3 The bottom of the conductive structure 494 is electrically connected to the first electrode doping region 42. The first electrode doping region lead-out structure is used to lead the first electrode doping region 42 to the front side of the device. The inner wall of the lead-out groove is provided with an insulating layer 492 surrounding the conductive structure 494.

[0058] The SOI semiconductor structure with integrated vertical devices described above leads the first electrode doping region 42 of the vertical device from the front side of the device through the first electrode doping region lead-out structure, so that the vertical device with a relatively small area can be integrated into the process platform, making the complex circuit more miniaturized, and the device process compatibility is high. In addition, the vertical device is isolated from other devices by utilizing the characteristics of SOI, which can make the entire circuit safer and more reliable.

[0059] exist Figure 3In the embodiment shown, the substrate 10 is a P-type silicon substrate. The buried dielectric layer 20 is a buried oxide layer, and its material can be silicon oxide, such as silicon dioxide. In one embodiment of the present application, the thickness of the buried dielectric layer 20 is 1 micron to 8 microns. The first electrode doping region 42 is an N+ region.

[0060] In one embodiment of the present application, the first device is a low voltage device (eg, a CMOS device), the vertical device is a high voltage device (eg, a VDMOS device), and the low voltage device is isolated from the high voltage device by a first isolation structure 32 .

[0061] exist Figure 3 In the illustrated embodiment, the vertical device is a VDMOS device, the first electrode doping region 42 is a drain doping region and has a first conductivity type, and the vertical device body further includes a VDMOS well region 44, a drift region 22a, a VDMOS source region 46, and a VDMOS gate 48. The VDMOS well region 44 has a second conductivity type and is disposed above the first electrode doping region 42. The drift region 22a has a first conductivity type and is disposed between the first electrode doping region 42 and the VDMOS well region 44. The VDMOS source region 46 has a first conductivity type and is disposed in the VDMOS well region 44. The VDMOS gate 48 is disposed on the drift region 22a.

[0062] In one embodiment of the present application, the aforementioned SOI semiconductor structure is a BCD process platform. In one embodiment of the present application, the vertical device may also be an IGBT device, a SGT device, and the like.

[0063] In one embodiment of the present application, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments of the present application, the first conductivity type may be P-type, and the second conductivity type may be N-type.

[0064] exist Figure 3 In the illustrated embodiment, the first device is a CMOS device, and the first device body includes a CMOS well region 54, a first conductive type region 22, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has a second conductive type and is disposed above the buried dielectric layer 20. The first conductive type region 22 is disposed between the CMOS well region 54 and the buried dielectric layer 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductive type and are disposed in the CMOS well region 54. The CMOS gate 58 is disposed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0065] exist Figure 3In the illustrated embodiment, the VDMOS source region 46 , the CMOS source region 562 , and the CMOS drain region 564 are located at the same level in the SOI semiconductor structure.

[0066] exist Figure 3 In the illustrated embodiment, the SOI semiconductor structure further includes a second isolation structure 34 and a third isolation structure 36. The second isolation structure 34 is connected to the first isolation structure 32, and the bottom reaches the buried dielectric layer 20. The second isolation structure 34, together with the first isolation structure 32, surrounds the first device body in the lateral direction, thereby isolating the first device from other devices of the SOI platform together with the buried dielectric layer 20. The third isolation structure 36 is connected to the first isolation structure 32, and the bottom reaches the buried dielectric layer 20. The third isolation structure 36, together with the first isolation structure 32, surrounds the vertical device body in the lateral direction, thereby isolating the vertical device from other devices of the SOI platform together with the buried dielectric layer 20.

[0067] exist Figure 3 In the illustrated embodiment, the conductive structure 494 passes through the interlayer dielectric layer 60 to lead the first electrode doping region 42 to the front side of the device.

[0068] In one embodiment of the present application, the conductive structure 494 is a closed ring structure located inside the region surrounded by the first isolation structure 32 and the third isolation structure 36. In one embodiment of the present application, the conductive structure 494 includes a metal and / or an alloy. The conductive structure 494 can act as a field plate to reduce the surface electric field (RESURF), thereby increasing the withstand voltage of the vertical device. In one embodiment of the present application, the conductive structure 494 is a tungsten plug.

[0069] In one embodiment of the present application, the thickness of the insulating layer 492 is 0.2 micrometers to 0.8 micrometers.

[0070] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0071] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An SOI semiconductor structure with integrated vertical devices, characterized in that: include: substrate; A buried dielectric layer is disposed on the substrate; A first device body, disposed on the buried dielectric layer; A vertical device body, disposed on the buried dielectric layer, comprising a first electrode doping region disposed at the bottom of the vertical device body; A first electrode doping region lead-out structure, comprising a conductive structure disposed in a lead-out groove, wherein the bottom of the conductive structure is electrically connected to the first electrode doping region, the first electrode doping region lead-out structure is used to lead the first electrode doping region to the front side of the device, and an insulating layer surrounding the conductive structure is disposed on the inner wall of the lead-out groove; The first isolation structure is located between the first device body and the vertical device body, and the bottom of the structure reaches the buried dielectric layer. The first isolation structure is used to isolate the vertical device body from the first device body.

2. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: The vertical device is a VDMOS device, the first electrode doping region is a drain doping region of the VDMOS and has a first conductivity type, and the vertical device body further includes: A VDMOS well region, having a second conductivity type, is disposed above the drain doping region, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a drift region, having a first conductivity type, disposed between the drain doping region and the VDMOS well region; A VDMOS source region, having a first conductivity type, disposed in the VDMOS well region; The VDMOS gate is disposed on the drift region.

3. The SOI semiconductor structure with integrated vertical devices according to claim 2, characterized in that: The first device body comprises: A CMOS well region, having a second conductivity type, disposed above the buried dielectric layer; A first conductive type region, disposed between the CMOS well region and the buried dielectric layer; A CMOS source region, having a first conductivity type, disposed in the CMOS well region; A CMOS drain region, having a first conductivity type, disposed in the CMOS well region; The CMOS gate is disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

4. The SOI semiconductor structure with integrated vertical devices according to claim 3, characterized in that: The VDMOS source region, the CMOS source region and the CMOS drain region are located at the same horizontal plane in the SOI semiconductor structure.

5. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: Also includes: a second isolation structure connected to the first isolation structure, with the bottom thereof reaching the buried dielectric layer, wherein the second isolation structure and the first isolation structure together surround the first device body; The third isolation structure is connected to the first isolation structure, and the bottom of the third isolation structure reaches the buried dielectric layer. The third isolation structure and the first isolation structure together surround the vertical device body.

6. The SOI semiconductor structure with integrated vertical devices according to claim 5, characterized in that: The conductive structure is a closed ring structure located inside the region surrounded by the first isolation structure and the third isolation structure; and / or The conductive structure includes metal and / or alloy.

7. A method for manufacturing a SOI semiconductor structure with an integrated vertical device, comprising: Obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, a first conductive type region on the buried dielectric layer, and a first electrode doping region formed at the bottom of the first conductive type region and on the buried dielectric layer; the first electrode doping region has a first conductive type; forming a first isolation structure on the buried dielectric layer to separate the first conductive type region into a vertical device region and a first device region, wherein the bottom of the first isolation structure reaches the buried dielectric layer, and the first electrode doping region is located in the vertical device region; forming a first device body in the first device region and forming a remaining vertical device body in the vertical device region; Forming a lead-out groove in the vertical device region by photolithography and etching, wherein the bottom of the lead-out groove reaches the first electrode doping region; forming an insulating layer on the inner wall of the lead-out groove; A conductive material is filled into the lead-out groove to form a conductive structure for leading the first electrode doping region to the front side of the device.

8. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: The forming of the first device body in the first device region comprises: forming a CMOS well region, a CMOS source region, a CMOS drain region and a CMOS gate in the first device region by a CMOS process; The forming of the remaining vertical device body in the vertical device area includes: forming a VDMOS well area, a VDMOS source area and a VDMOS gate in the vertical device area by CMOS process at the same time; the VDMOS well area has a second conductivity type and is formed in the first conductivity type area and above the first electrode doping area, the VDMOS source area has a first conductivity type and is formed in the VDMOS well area, and the VDMOS gate is formed on the first conductivity type area; the CMOS well area has a second conductivity type and is formed in the first conductivity type area and above the buried dielectric layer, the CMOS source area and the CMOS drain area have a first conductivity type and are formed in the CMOS well area, and the CMOS gate is formed on the CMOS well area between the CMOS source area and the CMOS drain area; the first conductivity type and the second conductivity type are opposite conductivity types.

9. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: The step of obtaining a wafer comprises: Obtaining a wafer having the substrate, a buried dielectric layer, and a semiconductor layer on the buried dielectric layer, wherein the semiconductor layer has a first conductivity type; forming the first electrode doping region in the semiconductor layer by photolithography and implantation, wherein the doping concentration of the first electrode doping region is greater than the doping concentration of the semiconductor layer; Through multiple epitaxy, the first conductive type region with a concentration gradient is formed, and the doping concentration of the first conductive type region decreases from high to low from bottom to top.

10. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: In the step of forming the lead-out groove in the vertical device region by photolithography and etching, the critical dimension of the lead-out groove is 0.5 micrometers to 2 micrometers.

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