Semiconductor chip capable of reducing low-clamping transient voltage

Abstract

The invention discloses a semiconductor chip capable of reducing low-clamping transient voltage, which relates to the technical field of semiconductor chips and comprises back metal, a substrate layer is arranged at the upper end of the back metal, a first P + isolation region and a second P + isolation region are arranged on two sides of the upper end of the substrate layer respectively, and an epitaxial layer is arranged in the middle of the upper end of the substrate layer. The two ends of the epitaxial layer are communicated with the first P + isolation region and the second P + isolation region respectively, a first doping region, a third P + isolation region, a second doping region, a third doping region and a fourth doping region are arranged in the epitaxial layer, and a first heat dissipation layer and a second heat dissipation layer are arranged in the epitaxial layer. According to the semiconductor chip capable of reducing the low-clamping transient voltage, the electromagnetic intensity is slowed down in time, so that the transient response speed of a transient voltage suppressor is increased, the semiconductor chip can perform continuous heat dissipation through heat dissipation coatings with different densities, and the current control accuracy of the semiconductor chip is improved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor chips, and in particular to a semiconductor chip capable of reducing low clamping transient voltage. Background Art

[0002] A semiconductor chip is a high-tech product that integrates thousands or even millions of microelectronic components, such as transistors, resistors and capacitors, on a small piece of semiconductor material. Semiconductor chips are an indispensable core component in modern electronic devices. They are mainly made of semiconductor materials (such as silicon, germanium or gallium arsenide), and electronic components are integrated into a small piece of material through complex manufacturing processes. This technology has greatly promoted the development of information technology and the electronics industry, and is widely used in computers, communication equipment, home appliances and various smart products.

[0003] Patent No. CN201510516444.5 discloses a transient voltage suppressor, which has a signal terminal and a ground terminal, and includes: a capacitive diode component and a first Zener diode connected in series with each other, wherein the capacitive diode component includes a first diode and a second diode formed in the same semiconductor chip and connected in reverse parallel in the semiconductor chip. The transient voltage suppressor uses the capacitive diode component as a non-polarity capacitor element, thereby improving the transient response speed of the transient voltage suppressor.

[0004] After searching the above patents, it was found that the semiconductor chip still has the following deficiencies: 1. Since the clamping voltage is directly related to the surge current, the larger the surge current, the larger the clamping voltage will be. Although the above patents can improve the transient response speed of the transient voltage suppressor, it is impossible to reduce the electromagnetic intensity in time while improving the transient response speed of the transient voltage suppressor, resulting in a weak transient response speed of the transient voltage suppressor, affecting the efficiency of reducing the low clamping transient voltage; 2. Since the electric field strength of the semiconductor chip is too high when the power is turned on and off, the transient voltage in the conductive part of the circuit rises rapidly, resulting in excessive current, affecting the stability and reliability of the semiconductor chip. At the same time, the voltage of the semiconductor chip will generate high temperature during transmission, and the high temperature cannot be reduced during the transmission process, which makes the semiconductor chip have weak accuracy in current control.

[0005] Therefore, a semiconductor chip capable of reducing the low clamping transient voltage is proposed to solve the above problems. Summary of the invention

[0006] The main object of the present invention is to provide a semiconductor chip capable of reducing low clamping transient voltage to solve the problems raised in the above background.

[0007] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a semiconductor chip capable of reducing low clamping transient voltage, comprising a back metal, a substrate layer is arranged at the upper end of the back metal, a No. 1 P+ isolation region and a No. 2 P+ isolation region are arranged on both sides of the upper end of the substrate layer, an epitaxial layer is arranged in the middle of the upper end of the substrate layer, the two ends of the epitaxial layer are respectively connected with the No. 1 P+ isolation region and the No. 2 P+ isolation region, a group of insulating layers are arranged together at the No. 1 P+ isolation region, the No. 2 P+ isolation region and the upper end of the epitaxial layer, a No. 1 interconnection lead and a No. 2 interconnection lead are arranged on the insulating layer, a No. 1 doping region, a No. 3 P+ isolation region, a No. 2 doping region, a No. 3 doping region and a No. 4 doping region are arranged in the epitaxial layer, a P+ groove and a P- groove are arranged in the No. 1 doping region and the No. 2 doping region, respectively, a No. 1 buffer groove and a No. 2 buffer groove are opened on both sides of the interior of the No. 3 P+ isolation region, and a No. 1 heat dissipation layer and a No. 2 heat dissipation layer are arranged in the epitaxial layer.

[0008] The third P+ isolation region is connected to the fourth doping region; The doping densities of the first doping region and the second doping region are different; Through the above technical solution, by arranging P+ trenches and P- trenches in the first doping region and the second doping region, the semiconductor chip can improve the transient response speed of the transient voltage suppressor.

[0009] The doping concentration range of the first doping region is 1.0E12cm -3 To 1.0E16cm -3 ; The doping concentration range of the second doping region is 1.0E8cm -3 To 1.0E12cm -3 ; Through the above technical solution, after the semiconductor chip is turned on, the transmitted voltage can be buffered by the P+ groove and the P- groove.

[0010] The first P+ isolation region, the second P+ isolation region and the third P+ isolation region include a peripheral portion surrounding the conductive source region and a middle portion separating the conductive source regions from each other; Through the above technical solution, the semiconductor chip can reduce the electromagnetic intensity in time while improving the transient response speed of the transient voltage suppressor.

[0011] The third doping region spans the interface between the conductive power region and the peripheral portions of the first P+ isolation region, the second P+ isolation region, and the third P+ isolation region; Through the above technical solution, the transient response speed of the transient voltage suppressor is enhanced, and the reduction efficiency of the low-clamp transient voltage is improved.

[0012] A PN junction of a first diode is formed between the first doped region and the epitaxial layer; A PN junction of a second diode is formed between the substrate layer and the epitaxial layer; Through the above technical solution, the voltage peak can be reduced through the continuous electric field buffering of the No. 1 buffer groove and the No. 2 buffer groove, avoiding the rapid rise of transient voltage in the circuit conduction part and preventing excessive current.

[0013] The third doping region surrounds the first doping region; The fourth doping region surrounds the second doping region; Through the above technical solution, the rapid rise of transient voltage in the circuit conduction part can be avoided, excessive current can be prevented, and the stability and reliability of the semiconductor chip can be increased.

[0014] The doping concentration range of the fourth doping region is 1.0E4cm -3 To 1.0E8cm -3 ; The doping concentration range of the third doping region is 1.0E4cm -3 To 1.0E8cm -3 ; The above technical solution makes it easier to control the current and increase the stability and reliability of the semiconductor chip.

[0015] The first heat dissipation layer and the second heat dissipation layer are both provided with heat dissipation coatings; The heat dissipation coating includes one of high thermal conductivity nano carbon ball coating and MIL-101 (Cr); Through the above technical solution, the coating densities of the high thermal conductivity nano-carbon ball coating and MIL-101 (Cr) are different, so that the electric field intensity and high temperature generated when the power of the semiconductor chip is turned on and off can be dissipated through the heat dissipation coating.

[0016] The coating densities of the first heat dissipation layer and the second heat dissipation layer are different; Through the above technical solution, continuous heat dissipation can be achieved through heat dissipation coatings of different densities, with good heat dissipation effect, thereby improving the accuracy of current control of semiconductor chips.

[0017] The present invention has the following beneficial effects: 1. In the present invention, by arranging P+ grooves and P- grooves in the first doping region and the second doping region, the semiconductor chip can improve the transient response speed of the transient voltage suppressor. At the same time, after the semiconductor chip is turned on, the transmitted voltage can be buffered by the P+ grooves and the P- grooves, so that the semiconductor chip can timely reduce the electromagnetic intensity while improving the transient response speed of the transient voltage suppressor, thereby enhancing the transient response speed of the transient voltage suppressor and improving the reduction efficiency of the low clamping transient voltage.

[0018] 2. In the present invention, by setting a No. 1 buffer groove and a No. 2 buffer groove in the No. 3 P+ isolation area, the No. 1 buffer groove and the No. 2 buffer groove, through the continuous electric field buffering of the No. 1 buffer groove and the No. 2 buffer groove, the voltage peak can be reduced, the rapid rise of the transient voltage in the circuit conduction part can be avoided, the current is prevented from being too large, and the stability and reliability of the semiconductor chip are increased. At the same time, a No. 1 heat dissipation layer and a No. 2 heat dissipation layer are set in the epitaxial layer, and the No. 1 heat dissipation layer and the No. 2 heat dissipation layer are both provided with heat dissipation coatings, and the two heat dissipation coatings include one of high thermal conductivity nano-carbon ball coating and MIL-101 (Cr), wherein the coating densities of the high thermal conductivity nano-carbon ball coating and MIL-101 (Cr) are different, so that when the power of the semiconductor chip is turned on and off, the electric field intensity and high temperature that appear can be dissipated through the heat dissipation coating, so that the semiconductor chip can be continuously dissipated through the heat dissipation coatings of different densities, the heat dissipation effect is good, and the accuracy of the semiconductor chip to control the current is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The figure is a schematic diagram of the overall structure of a semiconductor chip capable of reducing low clamping transient voltage according to the present invention.

[0020] In the figure: 1. back metal layer; 2. substrate layer; 3. P+ isolation region No. 1; 4. P+ isolation region No. 2; 5. epitaxial layer; 6. doping region No. 1; 7. P+ isolation region No. 3; 8. doping region No. 2; 9. doping region No. 3; 10. doping region No. 4; 11. P+ trench; 12. P- trench; 13. buffer trench No. 1; 14. insulating layer; 15. interconnection lead No. 1; 16. interconnection lead No. 2; 17. heat dissipation layer No. 1; 131. buffer trench No. 2; 171. heat dissipation layer No. 2. DETAILED DESCRIPTION

[0021] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further explained below in conjunction with specific implementation methods.

[0022] Example 1

[0023] Please refer to Figure 1As shown: A semiconductor chip capable of reducing low clamping transient voltage comprises a back metal 1, a substrate layer 2 is arranged on the upper end of the back metal 1, a No. 1 P+ isolation region 3 and a No. 2 P+ isolation region 4 are arranged on both sides of the upper end of the substrate layer 2, an epitaxial layer 5 is arranged in the middle of the upper end of the substrate layer 2, and the two ends of the epitaxial layer 5 are respectively connected to the No. 1 P+ isolation region 3 and the No. 2 P+ isolation region 4, and a group of insulating layers 14 are arranged on the upper ends of the No. 1 P+ isolation region 3, the No. 2 P+ isolation region 4 and the epitaxial layer 5. A No. 1 interconnection lead 15 and a No. 2 interconnection lead 16 are arranged on the insulating layer 14, a No. 1 doping region 6, a No. 3 P+ isolation region 7, a No. 2 doping region 8, a No. 3 doping region 9 and a No. 4 doping region 10 are arranged in the epitaxial layer 5, a P+ groove 11 and a P- groove 12 are respectively arranged in the No. 1 doping region 6 and the No. 2 doping region 8, a No. 1 buffer groove 13 and a No. 2 buffer groove 131 are respectively opened on both sides of the interior of the No. 3 P+ isolation region 7, and a No. 1 heat dissipation layer 17 and a No. 2 heat dissipation layer 171 are arranged in the epitaxial layer 5.

[0024] The third P+ isolation region 7 is connected to the fourth doping region 10; The doping densities of the first doping region 6 and the second doping region 8 are different.

[0025] The doping concentration of the first doping region 6 is in the range of 1.0E12cm -3 To 1.0E16cm -3 ; The doping concentration range of the second doping region 8 is 1.0E8cm -3 To 1.0E12cm -3 .

[0026] The first P+ isolation region 3, the second P+ isolation region 4 and the third P+ isolation region 7 include peripheral portions surrounding the conductive source regions and middle portions separating the conductive source regions from each other.

[0027] The third doped region 9 spans the interface between the conductive power region and the peripheral portions of the first P+ isolation region 3, the second P+ isolation region 4 and the third P+ isolation region 7, thereby avoiding a rapid rise in transient voltage at the circuit conduction portion, preventing excessive current, and increasing the stability and reliability of the semiconductor chip.

[0028] A PN junction of a first diode is formed between the first doped region 6 and the epitaxial layer 5; A PN junction of a second diode is formed between the substrate layer 2 and the epitaxial layer 5. After the semiconductor chip is turned on, the transmitted voltage can be buffered through the P+ trench and the P- trench.

[0029] The third doping region 9 surrounds the first doping region 6; The fourth doping region 10 surrounds the second doping region 8 to improve the transient response speed of the transient voltage suppressor.

[0030] The doping concentration range of the fourth doping region 10 is 1.0E4cm -3 To 1.0E8cm -3 ; The doping concentration range of the third doping region 9 is 1.0E4cm -3 To 1.0E8cm, the transient response speed of the transient voltage suppressor is enhanced and the reduction efficiency of the low clamping transient voltage is improved.

[0031] When the semiconductor chip is in use, by setting P+ grooves 11 and P- grooves 12 in the first doping region 6 and the second doping region 8, the semiconductor chip can improve the transient response speed of the transient voltage suppressor. At the same time, after the semiconductor chip is turned on, the transmitted voltage can be buffered by the P+ grooves 11 and the P- grooves 12, so that the semiconductor chip can reduce the electromagnetic intensity in time while improving the transient response speed of the transient voltage suppressor, thereby enhancing the transient response speed of the transient voltage suppressor and improving the reduction efficiency of the low clamping transient voltage.

[0032] Example 2

[0033] Please refer to Figure 1 As shown: an integrated gate-controlled carbonized MOSFET capable of improving the surge current resistance capability, comprising a back metal 1, a substrate layer 2 is arranged on the upper end of the back metal 1, a No. 1 P+ isolation region 3 and a No. 2 P+ isolation region 4 are arranged on both sides of the upper end of the substrate layer 2, an epitaxial layer 5 is arranged in the middle of the upper end of the substrate layer 2, and the two ends of the epitaxial layer 5 are respectively connected to the No. 1 P+ isolation region 3 and the No. 2 P+ isolation region 4, and a group of insulating layers are arranged together at the upper ends of the No. 1 P+ isolation region 3, the No. 2 P+ isolation region 4 and the epitaxial layer 5. 14, a No. 1 interconnection lead 15 and a No. 2 interconnection lead 16 are arranged on the insulating layer 14, a No. 1 doping region 6, a No. 3 P+ isolation region 7, a No. 2 doping region 8, a No. 3 doping region 9 and a No. 4 doping region 10 are arranged in the epitaxial layer 5, a P+ groove 11 and a P- groove 12 are respectively arranged in the No. 1 doping region 6 and the No. 2 doping region 8, a No. 1 buffer groove 13 and a No. 2 buffer groove 131 are respectively opened on both sides of the interior of the No. 3 P+ isolation region 7, and a No. 1 heat dissipation layer 17 and a No. 2 heat dissipation layer 171 are arranged in the epitaxial layer 5.

[0034] Heat dissipation coatings are provided in both the first heat dissipation layer 17 and the second heat dissipation layer 171; The heat dissipation coating includes one of high thermal conductivity nano-carbon ball coating and MIL-101 (Cr). The coating densities of the high thermal conductivity nano-carbon ball coating and MIL-101 (Cr) are different. Among them, the high thermal conductivity nano-carbon ball coating is preferably ZS-411, so that the electric field strength and high temperature generated when the power of the semiconductor chip is turned on and off can be dissipated through the heat dissipation coating.

[0035] The coating densities of the first heat dissipation layer 17 and the second heat dissipation layer 171 are different, and heat dissipation can be continuously performed through heat dissipation coatings of different densities, so that the heat dissipation effect is good and the accuracy of current control of the semiconductor chip is improved.

[0036] When the semiconductor chip is in use, by setting the first buffer groove 13 and the second buffer groove 131 in the third P+ isolation area 7, the first buffer groove 13 and the second buffer groove 131 can reduce the voltage peak through the continuous electric field buffering of the first buffer groove 13 and the second buffer groove 131, avoid the rapid rise of the transient voltage in the circuit conduction part, prevent the current from being too large, and increase the stability and reliability of the semiconductor chip. At the same time, the first heat dissipation layer 17 and the second heat dissipation layer 171 are set in the epitaxial layer 5. Layer 17 and the second heat dissipation layer 171 are both provided with heat dissipation coatings, and the two heat dissipation coatings include one of high thermal conductivity nano-carbon ball coating and MIL-101 (Cr), wherein the coating densities of the high thermal conductivity nano-carbon ball coating and MIL-101 (Cr) are different, so that when the power of the semiconductor chip is turned on and off, the electric field intensity and high temperature generated can be dissipated through the heat dissipation coating, so that the semiconductor chip can be continuously dissipated through the heat dissipation coatings of different densities, the heat dissipation effect is good, and the accuracy of the semiconductor chip's current control is improved.

[0037] In the present invention, a semiconductor chip capable of reducing low clamping transient voltage is provided. When the system is in operation, a first buffer groove 13 and a second buffer groove 131 are provided in a third P+ isolation region 7. The first buffer groove 13 and the second buffer groove 131 can reduce the voltage peak value through continuous electric field buffering of the first buffer groove 13 and the second buffer groove 131, avoid the occurrence of a rapid rise in transient voltage at the circuit conduction part, prevent excessive current, and increase the stability and reliability of the semiconductor chip. At the same time, a first heat dissipation layer 17 and a second heat dissipation layer 17 are provided in the epitaxial layer 5. Layer 171, the first heat dissipation layer 17 and the second heat dissipation layer 171 are both provided with heat dissipation coatings, and the two heat dissipation coatings include one of high thermal conductivity nano carbon ball coating and MIL-101 (Cr), wherein the coating densities of the high thermal conductivity nano carbon ball coating and MIL-101 (Cr) are different, so that when the power of the semiconductor chip is turned on and off, the electric field intensity and high temperature that appear can be dissipated through the heat dissipation coating, so that the semiconductor chip can be continuously dissipated through the heat dissipation coatings of different densities, the heat dissipation effect is good, and the accuracy of the semiconductor chip to control the current is improved; by A first buffer groove 13 and a second buffer groove 131 are arranged in the P+ isolation region 7. The first buffer groove 13 and the second buffer groove 131 can reduce the voltage peak through the continuous electric field buffering of the first buffer groove 13 and the second buffer groove 131, avoid the rapid rise of transient voltage in the circuit conduction part, prevent excessive current, and increase the stability and reliability of the semiconductor chip. At the same time, a first heat dissipation layer 17 and a second heat dissipation layer 171 are arranged in the epitaxial layer 5. The first heat dissipation layer 17 and the second heat dissipation layer 171 are both provided with heat dissipation coatings. The two heat dissipation coatings are The layer includes one of high thermal conductivity nano-carbon ball coating and MIL-101 (Cr), wherein the coating densities of the high thermal conductivity nano-carbon ball coating and MIL-101 (Cr) are different, so that the electric field strength and high temperature generated when the power of the semiconductor chip is turned on and off can be dissipated through the heat dissipation coating, so that the semiconductor chip can be continuously dissipated through the heat dissipation coatings of different densities, with good heat dissipation effect, improving the accuracy of the semiconductor chip's current control, thereby better reducing the low clamping transient voltage, and is suitable for the use and preparation of semiconductor chips that can reduce the low clamping transient voltage.

[0038] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A semiconductor chip capable of reducing low clamping transient voltage, comprising a back metal (1), characterized in that: A substrate layer (2) is arranged at the upper end of the back metal (1), and a No. 1 P+ isolation region (3) and a No. 2 P+ isolation region (4) are arranged on both sides of the upper end of the substrate layer (2), and an epitaxial layer (5) is arranged in the middle of the upper end of the substrate layer (2), and the two ends of the epitaxial layer (5) are respectively connected to the No. 1 P+ isolation region (3) and the No. 2 P+ isolation region (4), and a group of insulating layers (14) are arranged on the upper ends of the No. 1 P+ isolation region (3), the No. 2 P+ isolation region (4) and the epitaxial layer (5), and a No. 1 interconnection lead (14) is arranged on the insulating layer (14). 5) and a No. 2 interconnection lead (16), a No. 1 doping region (6), a No. 3 P+ isolation region (7), a No. 2 doping region (8), a No. 3 doping region (9) and a No. 4 doping region (10) are provided in the epitaxial layer (5), a P+ groove (11) and a P- groove (12) are provided in the No. 1 doping region (6) and the No. 2 doping region (8), respectively, a No. 1 buffer groove (13) and a No. 2 buffer groove (131) are provided on both sides of the interior of the No. 3 P+ isolation region (7), and a No. 1 heat dissipation layer (17) and a No. 2 heat dissipation layer (171) are provided in the epitaxial layer (5).

2. The semiconductor chip according to claim 1, characterized in that The third P+ isolation region (7) and the fourth doping region (10) are connected; The doping density of the first doping region (6) and the second doping region (8) is different.

3. The semiconductor chip according to claim 1, characterized in that The doping concentration range of the first doping region (6) is 1.0E12cm -3 To 1.0E16cm -3 The doping concentration of the second doping region (8) is in the range of 1.0E8cm -3 To 1.0E12cm -3 .

4. The semiconductor chip according to claim 1, characterized in that The first P+ isolation region (3), the second P+ isolation region (4) and the third P+ isolation region (7) include a peripheral portion surrounding the conductive source region and a middle portion separating the conductive source regions from each other.

5. The semiconductor chip according to claim 1, characterized in that The third doping region (9) spans across the interface between the conductive power region and the peripheral portions of the first P+ isolation region (3), the second P+ isolation region (4) and the third P+ isolation region (7).

6. The semiconductor chip according to claim 1, characterized in that A PN junction of a first diode is formed between the first doped region (6) and the epitaxial layer (5); and a PN junction of a second diode is formed between the substrate layer (2) and the epitaxial layer (5).

7. The semiconductor chip according to claim 1, characterized in that The third doping region (9) surrounds the first doping region (6); and the fourth doping region (10) surrounds the second doping region (8).

8. The semiconductor chip according to claim 1, characterized in that The doping concentration range of the fourth doping region (10) is 1.0E4cm -3 To 1.0E8cm -3 The doping concentration of the third doping region (9) is in the range of 1.0E4cm -3 To 1.0E8cm -3 .

9. The semiconductor chip according to claim 1, characterized in that The first heat dissipation layer (17) and the second heat dissipation layer (171) are both provided with a heat dissipation coating; the heat dissipation coating comprises one of a high thermal conductivity nano-carbon ball coating and MIL-101 (Cr).

10. The semiconductor chip according to claim 1, characterized in that The first heat dissipation layer (17) and the second heat dissipation layer (171) have different coating densities.

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