Chip testing method and device and electronic equipment

Abstract

The invention provides a chip testing method and device and electronic equipment, and relates to the technical field of chip testing, and the method comprises the steps: obtaining the application demand information of a target test chip; determining a test period and a parallel distributed test layout structure by the parallel test, and determining a first coverage degree set; determining a test depth and a cross distributed test layout structure through cross testing, and determining a second coverage degree set; and through the test period, the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, simulating a test environment according to the first coverage degree set and the second coverage degree set, and performing an iterative test on the target test chip. Through the chip testing method and device, the technical problem that in the prior art, the chip testing efficiency is poor due to the fact that the complexity of a chip is increased and the requirement for testing the coverage rate is improved can be solved, and the coverage rate and efficiency of chip testing are improved by establishing two coverage degree sets and combining parallel and cross testing layouts.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip testing method, device and electronic equipment. Background Art

[0002] With the continuous development of science and technology, chip technology plays an increasingly important role in various fields. As the core of modern electronic devices, it undertakes extremely complex computing and control tasks. With the improvement of integration, the structure of chips is becoming more and more complex, and advanced technologies such as multi-core, 3D packaging, and heterogeneous computing are adopted. With the continuous advancement of process technology, the size of chips is gradually reduced, entering the nanoscale process, so that a single chip can accommodate more functions and higher performance. Existing chip testing methods usually use functional testing, scan chain testing, parameter testing, and automated testing. Although they can effectively detect some common functional failures and parameter anomalies, as the complexity of chips increases, existing testing methods face many challenges. As the complexity of chips increases, the interaction between functional modules becomes more complex. Existing testing methods are difficult to fully cover all functions and interaction modes, and are prone to overlooking some boundary conditions or low-probability failure modes. In addition, as the complexity of chip functions and structures increases, the number of test cases increases dramatically, and each possible failure mode needs to be verified, resulting in long testing time and low efficiency.

[0003] To sum up, the prior art has technical problems in that due to the increasing complexity of chips and the higher test coverage requirements, chip testing is difficult to fully cover all functions and potential failure modes, and some boundary conditions or low-probability failures are easily ignored, resulting in poor chip testing efficiency. Summary of the invention

[0004] The purpose of this application is to provide a chip testing method, device and electronic equipment to solve the technical problems in the prior art that due to the increased complexity of chips and the higher test coverage requirements, chip testing is difficult to fully cover all functions and potential failure modes, and some boundary conditions or low-probability failures are easily ignored, resulting in poor chip testing efficiency.

[0005] In view of the above problems, the present application provides a chip testing method, device and electronic device.

[0006] In a first aspect, the present application provides a chip testing method, which is implemented by a chip testing device, wherein the chip testing method includes: obtaining application requirement information of a target test chip, setting multiple test cases, and the multiple test cases including multiple test mark points; determining a test cycle and a parallel distributed test layout structure in a parallel testing manner according to the test mark points; determining a test depth and a cross-distributed test layout structure in a cross-test manner according to the test mark points; determining a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure; determining a second coverage set based on the multiple test cases through the test depth and the cross-distributed test layout structure; simulating a test environment based on the first coverage set and the second coverage set through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, and iteratively testing the target test chip.

[0007] In a second aspect, the present application further provides a chip testing device for executing a chip testing method as described in the first aspect, wherein the chip testing device comprises: a test case setting module, the test case setting module is used to obtain application requirement information of a target test chip and set multiple test cases, wherein the multiple test cases include multiple test mark points; a parallel test module, the parallel test module is used to determine a test cycle and a parallel distributed test layout structure in a parallel test manner according to the test mark points; a cross test module, the cross test module is used to determine a test depth and a cross distributed test layout structure in a cross test manner according to the test mark points; a first coverage module, the first coverage module is used to determine a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure; a second coverage module, the second coverage module is used to determine a second coverage set based on the multiple test cases through the test depth and the cross distributed test layout structure; a simulation test module, the simulation test module is used to simulate a test environment according to the first coverage set and the second coverage set through the test cycle and the parallel distributed test layout structure, the test depth and the cross distributed test layout structure, and iteratively test the target test chip.

[0008] In a third aspect, the present application also provides an electronic device comprising: at least one processor; a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the steps of a chip testing method described in any one of the first aspects above.

[0009] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0010] By acquiring the application requirement information of the target test chip, multiple test cases are set, and the multiple test cases include multiple test mark points; according to the test mark points, the test cycle and the parallel distributed test layout structure are determined in a parallel test manner; according to the test mark points, the test depth and the cross-distributed test layout structure are determined in a cross-test manner; based on the multiple test cases, the first coverage set is determined through the test cycle and the parallel distributed test layout structure; based on the multiple test cases, the second coverage set is determined through the test depth and the cross-distributed test layout structure; through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, according to the first coverage set and the second coverage set, the test environment is simulated, and the target test chip is iteratively tested. In other words, multiple test cases are determined through the application requirement information of the target test chip, and a distributed layout design combining parallel testing and cross testing is introduced. Combined with the evaluation of the coverage set and the iterative test of the simulation environment, the problems of low test efficiency and insufficient coverage caused by the increase in chip complexity are solved, and the coverage and efficiency of chip testing are improved.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented according to the contents of the specification, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are specifically cited below. It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present application, nor is it intended to limit the scope of the present application. Other features of the present application will become easy to understand through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the present application or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of a chip testing method for this application;

[0014] Figure 2 A schematic diagram of the structure of a chip testing device for this application;

[0015] Figure 3This is a schematic diagram of the structure of an exemplary electronic device of the present application.

[0016] Explanation of the accompanying drawings: test case setting module 11, parallel testing module 12, cross testing module 13, first coverage module 14, second coverage module 15, simulation testing module 16, bus 300, receiver 301, processor 302, transmitter 303, memory 304, bus interface 305. DETAILED DESCRIPTION

[0017] The present application provides a chip testing method, device and electronic device to solve the technical problems in the prior art that due to the increased complexity of the chip and the increased test coverage requirements, the chip test is difficult to fully cover all functions and potential failure modes, and some boundary conditions or low-probability failures are easily ignored, resulting in poor efficiency of chip testing. Through the application requirement information of the target test chip, multiple test cases are determined, and a distributed layout design combining parallel testing and cross testing is introduced. Combined with the evaluation of the coverage set and the iterative testing of the simulation environment, the problems of low test efficiency and insufficient coverage caused by the increase in chip complexity are solved, and the coverage and efficiency of chip testing are improved.

[0018] Below, the technical solutions in the present application will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments of the present application. It should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present application. It should also be noted that, for the convenience of description, only the parts related to the present application are shown in the accompanying drawings, rather than all of them.

[0019] For example, please refer to the attached Figure 1 The present application provides a chip testing method, wherein the chip testing method is applied to a chip testing device, and the chip testing method specifically includes the following steps:

[0020] Step 1: Obtain application requirement information of the target test chip and set a plurality of test cases, wherein the plurality of test cases include a plurality of test marking points.

[0021] Specifically, by analyzing product specifications, user requirements documents and communicating with the chip design team, the application requirements information of the target test chip is obtained, that is, various performance and functional requirements information related to the actual application scenarios of the target chip, including the working environment of the chip in a specific device, the required speed, power consumption, stability and other requirements. The target test chip refers to the chip that needs to be tested during the chip design, production or functional verification process, including microprocessors, sensors, communication modules, etc., which are usually core components in product development. According to the application requirements information of the target chip, multiple test cases are designed, including functional tests, performance tests, environmental tests, etc., to ensure that the performance of the chip in various aspects in actual applications can be verified. In each test case, several test mark points are set to identify the parts or stages that need special attention, which are usually the key nodes for the realization of chip functions, to ensure that the various parameters of the chip can be monitored in real time during the test process. By obtaining application requirements, it is ensured that the test cases and test mark points can fully cover the application requirements of the chip, providing a clear direction and measurement standard for subsequent testing work.

[0022] Step 2: According to the test marking points, determine the test cycle and the parallel distributed test layout structure in a parallel testing manner.

[0023] Specifically, in chip testing, due to the complexity and diversity of chips, the number and types of test mark points are usually large. In order to improve test efficiency and ensure the comprehensiveness of the test, parallel testing can be used for testing. Parallel testing refers to performing multiple test tasks simultaneously instead of serially, thereby saving time and improving efficiency. Test mark points refer to specific test locations or test functions that need to be verified in chip design or function. The parallel testing method means that each mark point is no longer tested in sequence, but multiple test tasks are assigned to different test resources or test units, allowing multiple test tasks to be performed simultaneously, significantly improving test efficiency and shortening the test cycle. For example, assuming there are five test mark points A, B, C, D, and E, if the serial test method is used, each test mark point needs to be performed in sequence, assuming that each test takes 30 minutes, then the total test time is 150 minutes. Using the parallel test method, different test tasks are assigned to different test resources, such as A and B are tested simultaneously using one device, and C, D, and E are tested simultaneously using another device, reducing the total test time.

[0024] The test cycle refers to the time required to complete a complete round of testing. In parallel testing mode, the test cycle is determined by the slowest test task because all test tasks need to be completed within the same time window. If there are more test equipment and more efficient test processes, the test cycle can be significantly shortened. Suppose that testing point A takes 10 minutes, B takes 20 minutes, and C takes 30 minutes. If these tasks are performed simultaneously, the total time for the parallel test cycle is 30 minutes (that is, the longest test task). In the process of parallel testing, it is necessary to reasonably configure the test resources and time required for each test mark point to ensure that the test is completed in the shortest time. The duration of each test task is predicted based on the complexity and required resources of each test mark point, and the overall test cycle is determined by comprehensively considering the longest time required for the parallel test tasks.

[0025] In parallel test mode, in order to improve resource utilization and test efficiency, test tasks are assigned to multiple test devices or test units to form a distributed test structure, and each test unit can perform different test tasks in parallel. For example, suppose there are five test markers A, B, C, D, and E, and there are three test devices: X, Y, and Z. The test markers are assigned as follows: Device X: A, B, Device Y: C, D, Device Z: E, and each device performs different test tasks in parallel. In the end, the test tasks of devices X, Y, and Z will be completed in the same time period, saving the overall test time. The parallel distributed layout of test markers needs to be optimized to ensure full utilization of resources. Test resources include hardware devices (such as test instruments, simulators, etc.) and software tools (such as automated test frameworks). In order to achieve an efficient test process, different types and quantities of resources are allocated according to the needs of different test markers.

[0026] The parallel distributed test layout structure refers to how to allocate test tasks to different test resources, and factors such as the performance of test resources, the dependencies of test tasks, and communication delays need to be considered. In parallel testing, since multiple test tasks are carried out at the same time, resource competition may occur, resulting in loss of test accuracy. Therefore, it is necessary to first evaluate the accuracy loss based on the test mark points. In order to ensure the accuracy of the test results, an acceptable accuracy loss threshold is set according to the application requirements and test objectives of the chip. In parallel testing, the progress of each test task needs to be synchronized to ensure the coordination and consistency of the test. This is usually achieved through test management software, which can monitor the execution of each test task and make adjustments when the task progress deviates. According to the accuracy loss threshold and the progress of the test task, it may be necessary to reallocate the parallel test tasks and update the parallel distributed test layout structure to ensure efficient use of test resources and balanced distribution of test tasks.

[0027] Analyze the functional requirements of each test mark point, determine its test time, required resources and difficulty, and evaluate the complexity of each test mark point. According to the complexity of each test mark point, assign different tasks to different parallel test equipment. According to the allocation structure of parallel testing, calculate the slowest task completion time, which is the test cycle. Optimize resource allocation in real time according to the actual progress and task completion status. For example, if a task is progressing slowly, allocate more resources to this task to ensure that the entire test process proceeds as planned. Through parallel testing, the time of the entire chip test is greatly shortened, especially when there are many test mark points, the parallel execution of multiple test tasks can be carried out simultaneously, thereby reducing the overall test cycle.

[0028] Step 3: Determine the test depth and cross-distributed test layout structure in a cross-test manner according to the test marking points.

[0029] Specifically, in the chip testing process, cross-testing is a complex testing strategy that can more comprehensively evaluate the functions and performance of the chip by cross-executing test tasks between different test mark points. The purpose is to dig deeper into the potential problems of the chip under different working conditions and loads to ensure higher test coverage and lower omission probability. During the testing process, some test mark points may involve multiple inputs or conditions. Cross-testing is to combine these conditions with the conditions of other mark points to simulate more complex application scenarios. By crossing different test points, conditions or parameters, potential errors and failure modes can be discovered.

[0030] Test depth refers to the levels and combinations of test conditions and parameters involved in cross-testing. The greater the test depth, the more scenarios and combinations the test covers, and the more potential failure modes can be discovered. For example, if the chip may perform differently in different environments (such as temperature, voltage, clock frequency, etc.), then the depth of cross-testing is the combination of these environmental conditions. In cross-testing, the test depth is usually selected based on the functional complexity of the chip, test objectives, resources, and time constraints. Each combination needs to be tested separately, and the test depth of each combination will be determined based on the characteristics of the chip.

[0031] The cross-distributed test layout structure refers to the distribution of test tasks to multiple resource units or test devices according to the needs of cross-testing to form a distributed test system. During the cross-testing process, different combinations of test mark points will be distributed to different devices and tested at the same time. The cross-distributed test layout structure not only requires the reasonable distribution of test tasks, but also ensures that each combination of test mark points can be completed within a reasonable time range. The rationality of the layout directly affects the efficiency and coverage of the test, and the layout can be optimized through resource allocation, load balancing, parallel execution, etc.

[0032] Analyze which combinations of markers need to be cross-tested, which markers are independent, and which combinations may lead to higher failure rates or errors, and evaluate the combination relationship of each test marker. According to the functional complexity, test objectives, and resource constraints of the chip, determine the test depth and the combination of test markers required, and determine the test conditions for each test marker combination, that is, the depth of cross-test. Assign test tasks to different test equipment and ensure load balancing and optimal use of resources. Design a reasonable test layout to ensure the smooth progress of parallel and cross-testing. Through the designed cross-test layout structure, perform tests and collect test results of each test marker combination. According to the results of the cross-test, analyze the performance of the chip under different combination conditions, and optimize the test strategy according to the test results. By cross-combining different test conditions, some low-probability failure modes are revealed. These failures may not be easy to find when tested alone. Combining tests with multiple test markers can efficiently evaluate chip performance under different conditions, while avoiding repeated tests and improving resource utilization efficiency.

[0033] Step 4: Based on the multiple test cases, determine a first coverage set through the test cycle and the parallel distributed test layout structure.

[0034] Specifically, multiple test cases target different chip functions, working conditions, and potential failure modes to verify whether specific functions of the chip or system work as expected. Through the set of multiple test cases, test cycles, and parallel distributed test layout structures, the first coverage set is determined, that is, the set of chip functions or failure modes actually covered during the test process. The first coverage set reflects all the test cases executed in parallel, and ultimately covers all the functions and potential failure modes of the chip.

[0035] According to the application requirements of the target chip, select multiple representative test cases, covering multiple aspects of chip functions, such as power consumption, stability, electromagnetic compatibility, etc. Through parallel testing, multiple test cases are executed simultaneously on multiple test resources, shortening the test time and improving test efficiency. According to the test cycle requirements, adjust the execution order of each test case and the resource allocation of the test equipment. If the test cycle is short, choose to test more critical functions first, and other minor functions can be carried out in subsequent stages. After executing all parallel test tasks, summarize the functions or failure modes covered by each test case to form the first coverage set, which includes the chip functions covered by all test cases.

[0036] The process of determining the first coverage set involves analyzing and prioritizing the test cases. Test cases for key functions and high-risk areas are usually given priority. Then, the set of test cases that can be executed is determined based on the test cycle and the availability of test resources. By determining the first coverage set, it is ensured that the coverage of the test is maximized under limited time and resource constraints. Through the parallel distributed test layout structure, the test efficiency can be improved while ensuring the test coverage of key functions.

[0037] Step 5: Based on the multiple test cases, determine a second coverage set through the test depth and the cross-distributed test layout structure.

[0038] Specifically, according to the test depth requirements, each test case is analyzed in depth to ensure that the test can cover all important functions and performance boundaries of the chip. Using the cross-distributed test layout structure, test cases are tested in different orders and combinations to simulate various situations that may be encountered in actual use and achieve cross-testing. Different test cases, test conditions or working states can be cross-executed on different devices to ensure the comprehensiveness and diversity of the test.

[0039] Determine multiple test cases to cover different functions of the chip, including the power consumption, stability, voltage and temperature adaptability of the chip. For each test case, set a different test depth. Design a cross-test scheme based on the working environment that the chip may face. Perform in-depth tests at multiple cross-test points to evaluate the performance of the chip under complex conditions. After executing all deep tests and cross-tests, summarize the covered chip functions and failure modes to form a second coverage set, which includes the performance of the chip under multiple extreme conditions to further ensure the comprehensiveness of the test. The second coverage set refers to a set of chip functions, failure modes or performance issues covered on the basis of cross-tests and test depths, usually involving more fine-grained tests, especially the performance of the chip under extreme conditions or complex working modes. By setting multiple test depths and cross-tests, the performance of the chip under various extreme conditions can be fully covered, especially the long-term stability of the chip and the performance under extreme conditions can be deeply analyzed, covering the potential failures of the chip under various environmental conditions, especially low-probability failure modes, which may not be discovered under a single condition, ensuring the comprehensiveness and efficiency of the test, thereby improving the quality and reliability of the chip.

[0040] Step six: through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, simulate the test environment according to the first coverage set and the second coverage set, and iteratively test the target test chip.

[0041] Specifically, in complex chip testing, multiple factors (such as test cycle, test layout, coverage, etc.) need to work in coordination to ensure comprehensive testing of the chip. That is to say, through reasonable test cycles and layout structures, combined with coverage sets, efficient simulation of the test environment and iterative testing, the performance and reliability of the chip under different conditions can be verified. The first coverage set obtained by the parallel distributed test layout structure is combined with the test cycle and the parallel distributed test layout structure. The second coverage set obtained by the cross-distributed test layout structure is combined with the test depth and the cross-distributed test layout structure to build a simulated test environment, that is, to create a test environment similar to the actual operating environment through virtualization or simulation technology. It allows multiple rounds of testing to be performed under controlled conditions to evaluate the performance, stability and reliability of the chip. Iterative testing refers to the process of adjusting and continuously improving the test plan according to the results of the previous round of testing during the testing process. It is a cyclic process in which analysis and feedback are performed after each round of testing to improve the comprehensiveness and accuracy of the test. Through iterative testing, potential problems that may exist in the chip can be gradually discovered, and the stability and reliability of the chip can be gradually improved. By rationally arranging the test cycle, parallel distributed test layout, test depth and cross-distributed test layout structure, efficient and comprehensive chip testing can be achieved. Combining the first coverage set and the second coverage set, iterative testing is performed in a simulated test environment to ensure the performance stability of the chip under complex conditions, significantly improve test efficiency, comprehensiveness and accuracy, and thus provide reliable quality assurance for chip R&D and production.

[0042] Furthermore, step one of this application includes:

[0043] A class of key requirement indicators in the application requirement information is obtained, wherein the class of key requirement indicators is associated with the reliability of the target test chip, and the class of key requirement indicators includes vibration resistance requirements and electromagnetic compatibility requirements; a reliability verification link is set according to the vibration resistance requirements and electromagnetic compatibility requirements in the class of key requirement indicators; under the constraints of the resource synchronization monitoring mechanism, the reliability verification link is seamlessly integrated into the test operation phase to perform resource balancing scheduling.

[0044] Specifically, according to the actual application scenarios of the chip, obtain specific requirements for the chip in terms of function, performance, environmental adaptability, etc. Among the many application requirements, key demand indicators refer to requirements that are crucial to the performance of the chip and determine whether it can operate normally in actual applications. They are crucial to the reliability, stability, safety, etc. of the chip. A class of key demand indicators related to reliability is obtained from the application demand information, including vibration resistance requirements and electromagnetic compatibility requirements. Vibration resistance requirements mean that the chip needs to be able to maintain normal operation without failure or performance degradation when it is affected by mechanical forces such as vibration or shock. Electromagnetic compatibility requirements mean that the chip must be able to operate normally in an electromagnetic environment, not be affected by electromagnetic interference (EMI), and not generate excessive electromagnetic radiation (EMC) to interfere with other devices. A class of key demand indicators is related to the reliability of the target test chip, which directly affects the performance and stability of the chip in actual applications.

[0045] According to the vibration resistance requirements and electromagnetic compatibility requirements in a category of key demand indicators, a reliability verification link, that is, a series of test links, is set up to verify the performance and stability of the chip under these specific conditions. The reliability verification link refers to the test process and steps designed to verify the reliability of the chip, focusing on whether the chip can maintain normal operation under environments such as vibration and electromagnetic interference. Reliability verification not only tests the performance of the chip under normal working conditions, but also includes the performance of the chip under harsh conditions, such as stability when running in environments such as high temperature, high humidity, vibration, and electromagnetic interference. For example, vibration testing is combined with electromagnetic compatibility testing to ensure that the chip can operate stably under complex environmental conditions.

[0046] The purpose of reliability verification is to ensure that the chip operates stably in the expected working environment, prevent potential failure modes, ensure the stability of the chip in long-term use, optimize product design, etc. The chip's tolerance is tested by simulating the working state of the chip under different environmental conditions, including high temperature test, low temperature test, humidity test, etc.; the chip's performance in a vibration environment is simulated, and the impact of falling during transportation or use is checked to check whether the physical structure and electronic functions of the chip are affected. The chip is quickly converted from an extremely high or extremely low temperature environment to another environment in a short period of time to detect the chip's resistance to thermal stress and thermal expansion. The working stability of the chip in an electromagnetic interference environment is tested, while ensuring that the electromagnetic radiation of the chip itself does not affect other devices. The power consumption of the chip is tested by high-load operation and long-term operation to ensure that the chip will not overheat or fail when running at high power. The chip's response to overvoltage or overcurrent is tested to ensure that it has sufficient overload resistance. By exposing the chip to extreme environmental conditions (such as high temperature, high humidity, strong electromagnetic interference, etc.), the long-term use of the chip is simulated so that the chip life prediction data can be obtained in a shorter time; the reliability of the chip in long-term use is evaluated, such as the number of times the connector is plugged in and out, the number of times the chip is switched on and off, etc., to determine the mechanical life.

[0047] Before reliability verification, it is necessary to clarify the reliability standards required for the chip, which are usually determined by the chip design requirements, industry standards (such as ISO9001, MIL-STD, etc.) and customer needs. According to the application scenario and key requirements of the chip, select the appropriate test method. For example, for communication chips, EMC testing and power consumption testing are more important. According to the application and test requirements of the chip, formulate a detailed test plan, and clarify the test conditions, test time and test objectives of each test link. Use professional test equipment and environment to perform each test link as planned. During the test, the test data should be recorded in real time, and fault analysis should be performed based on the test results. After the test is completed, the test data is analyzed to find out the possible failure mode or performance deviation, and the chip design or manufacturing process is adjusted based on the test results.

[0048] In the actual chip testing process, multiple test links (such as vibration resistance test, electromagnetic compatibility test, functional test, etc.) may need to be carried out simultaneously. In order to avoid waste of resources or test conflicts, the test tasks must be reasonably scheduled. Suppose that multiple test equipment needs to be used at the same time, such as a vibration table and an EMC tester. Through the scheduling system, the execution order and required resources of each test task are reasonably arranged according to the priority and time requirements of each test link. The resource synchronization monitoring mechanism refers to the real-time monitoring and coordination of the use of all test resources (such as test equipment, testers, computing power, etc.) during the chip testing process to ensure efficient collaboration of each test link and reasonable allocation of resources.

[0049] Under the constraint of resource synchronization monitoring mechanism, the reliability verification link is integrated into the test operation phase, that is, the reliability verification link (such as vibration resistance test, electromagnetic compatibility test) is seamlessly integrated with other functional test, performance test and other links. Through a unified resource scheduling platform, the operation and monitoring links of the test equipment can be coordinated to avoid resource conflicts and ensure that all test links can be executed smoothly. Resource balance scheduling refers to the reasonable allocation of test resources when multiple test links are carried out simultaneously, avoiding excessive concentration or waste of resources, ensuring that each test case can get appropriate resource support, and will not affect the normal operation of other test links. The test operation phase refers to the various links in the chip testing process, from test design, execution to result analysis. The test operation phase involves multiple stages and different types of tests, such as functional verification, performance verification, environmental adaptability test, reliability test, etc. Through reasonable scheduling and resource synchronization monitoring, the smooth progress of different test links is ensured, resource conflicts and test delays are reduced, and the overall test efficiency is improved.

[0050] Furthermore, the present application also includes the following steps:

[0051] Obtain two types of key demand indicators in the application demand information, wherein the two types of key demand indicators are associated with the stability of the target test chip, and the two types of key demand indicators include signal reception sensitivity requirements, transmission power requirements, and spectrum efficiency requirements; set a stability verification link through the signal reception sensitivity requirements, transmission power requirements, and spectrum efficiency requirements in the two types of key demand indicators; and seamlessly integrate the stability verification link into the test operation phase under the constraints of the resource synchronization monitoring mechanism to perform resource balancing scheduling.

[0052] Specifically, according to the application scenario and expected use environment of the chip, two types of key demand indicators related to stability are obtained, including signal reception sensitivity requirements, transmission power requirements and spectrum efficiency requirements. Signal reception sensitivity requirements refer to the minimum signal strength that the chip can detect when receiving a signal, which is used to evaluate the receiving capability of wireless communication devices or modules under low signal strength. Transmission power requirements refer to the output power of the chip when transmitting a signal, which usually affects the coverage and transmission distance of the communication. Too low transmission power may result in insufficient communication distance, while too high transmission power may cause energy waste or electromagnetic interference. Spectral efficiency requirements refer to the ability of a chip or device to efficiently transmit data within a certain bandwidth. High spectrum efficiency means that more information can be transmitted with limited spectrum resources. Spectral efficiency is usually measured in bits per hertz (bps / Hz) and is an important indicator of communication system performance.

[0053] Determine the corresponding stability verification link for each of the two types of key demand indicators. Signal reception sensitivity verification verifies whether the chip can stably receive the expected minimum signal strength by simulating environments with different signal strengths; transmit power verification controls the transmit power and tests the performance of the chip under different power outputs to ensure that it can maintain stable signal transmission under different environmental conditions; spectrum efficiency verification tests the maximum data transmission rate of the chip within a certain bandwidth to evaluate whether its spectrum efficiency meets the design requirements.

[0054] Similarly, under the constraints of the resource synchronization monitoring mechanism, the stability verification link is also seamlessly integrated into the test operation phase to perform resource balancing scheduling. When performing stability verification tests, multiple test equipment (such as signal generators, spectrum analyzers, oscilloscopes, etc.) need to work in coordination. The resource synchronization monitoring mechanism ensures that the operating status of each test device is fed back to the system in real time and adjusted to avoid resource conflicts or long idle time of the test equipment. For example, when verifying the signal reception sensitivity, the received signal strength needs to be measured by the spectrum analyzer, and the signal generator provides signal sources of different strengths. Through the synchronization monitoring mechanism, these devices are scheduled in real time to ensure that the test is carried out as planned. During the chip stability verification process, the test links and resource requirements may be carried out in parallel. Through resource balancing scheduling, it is ensured that each test link obtains appropriate resource support and avoids excessive equipment load or delays in the test link. By verifying the signal reception sensitivity, transmission power and spectrum efficiency, it is ensured that the chip can work stably in different environments, which improves the overall stability of the chip.

[0055] Furthermore, the present application also includes the following steps:

[0056] Based on the reliability verification link and the stability verification link, a resource configuration optimization function is established; the total number of the test mark points is recorded as K, and the resource configuration optimization function Among them, R opt is the optimal resource allocation, R k is the actual resource configuration corresponding to the kth test mark point, D k is the resource requirement corresponding to the kth test mark point, λ is the coefficient between the trade-off between resource allocation and comprehensive evaluation value, and the comprehensive evaluation value Among them, w reliability,i is the test result of the i-th reliability verification link, R stability,j is the test result of the jth stability verification link, w reliability,i and w stability,j It is the weight corresponding to the reliability verification link and the stability verification link.

[0057] Specifically, based on the reliability and stability requirements of chip testing, a resource allocation optimization function is established to optimize the allocation of test resources to ensure that each verification link (reliability verification and stability verification) is completed as efficiently as possible under limited resources. The total number of test mark points is recorded as K, which represents the different functional points or performance indicators that need to be verified in the test task. The resource allocation optimization function Among them, R opt is the optimal resource configuration, that is, the resources allocated to each test point. k It is the actual resource configuration corresponding to the kth test mark point, which can be test equipment, time or other resource-related quantities. k is the resource requirement corresponding to the kth test mark point. Each test mark point requires different amounts of resources depending on the complexity of the test and the verification process. (R k -D k ) 2 represents the resource allocation error of the kth test mark point. The two are as close as possible to reduce resource waste and improve the accuracy of the test. λ is a coefficient that weighs resource allocation and comprehensive evaluation value, which is used to balance the weight between resource allocation accuracy and comprehensive evaluation value. By adjusting λ, the optimal balance between resource allocation error and comprehensive evaluation value can be found. (1-V integrated ) 2 is a term that reflects the difference between the comprehensive evaluation value and the target value. The comprehensive evaluation value V integrated It measures the overall effect or quality of the testing process and is required to be close to 1, indicating the efficiency and quality of the testing process.

[0058] Next, the expression of the comprehensive evaluation value is: Among them, V integrated It is a comprehensive evaluation value, indicating the overall performance or quality of the test process, which depends on the test results of all reliability verification links and stability verification links. reliability,i is the test result of the i-th reliability verification link, R stability,j is the test result of the jth stability verification link, w reliability,i and w stability,j It is the weight corresponding to the reliability verification link and the stability verification link. It represents the weighted sum of all reliability verification links, reflecting the impact of reliability verification on the overall evaluation. It is the weighted sum of all stability verification links, reflecting the impact of stability verification on the overall evaluation.

[0059] Resource allocation error means that for each test mark point, the resource allocation is as close as possible to the required resources, effectively reducing resource waste and ensuring the comprehensiveness of the test. The comprehensive evaluation value reflects the overall performance of all test links (reliability and stability verification links). The test link not only requires resource support, but also high-quality verification results. The comprehensive evaluation value will weigh the test effects of these links. The reliability verification link may involve electromagnetic compatibility and vibration resistance tests, while the stability verification link focuses on signal reception sensitivity, etc. Each link has its corresponding weight. By optimizing the comprehensive evaluation value, the effectiveness and test quality of these verification links are ensured. The λ coefficient controls the balance between resource allocation error and comprehensive evaluation value. If the value of λ is large, the optimization process will be more inclined to reduce resource allocation error, that is, more focused on accurately allocating resources. If the value of λ is small, the optimization process will pay more attention to improving the comprehensive evaluation value, that is, ensuring the quality of test results. By solving this resource configuration optimization function, an optimal resource configuration R will eventually be obtained. opt , which means that under given resource constraints and test requirements, the most efficient resource allocation and optimal test quality can be achieved. Through the resource configuration optimization function, each link of the test task (such as reliability verification and stability verification) can be executed with the optimal resource configuration, avoiding resource waste or unreasonable resource allocation.

[0060] Further, step 2 of this application includes:

[0061] Based on the test mark points, the accuracy loss is evaluated and an accuracy loss threshold is set; in a parallel test mode, the progress of the test tasks is synchronized; through the accuracy loss threshold and the progress of the test tasks, the parallel test tasks are reallocated and the parallel distributed test layout structure is updated.

[0062] Specifically, in chip testing, the performance indicators corresponding to the test mark points (such as power consumption, voltage, current, signal transmission speed, etc.) may deviate due to different test methods. The purpose of precision loss assessment is to detect the degree of this deviation and ensure that the test results do not exceed the set tolerance range. When the load of the test equipment is high, the test accuracy may be reduced. For example, if the computing power of the test equipment is not sufficient to process multiple test mark points at the same time, the results will be inaccurate. Precision loss assessment is to analyze this error and make adjustments within an acceptable range. In order to ensure that the accuracy of parallel testing meets the requirements, it is necessary to set a precision loss threshold, which is a predefined tolerance range. When the precision loss of the test exceeds this threshold, measures need to be taken to adjust the test strategy.

[0063] In parallel testing, each test task will be carried out in parallel, but since the test order of the test mark points may affect the progress of the entire test process, the progress of each test task must be synchronized to ensure the efficient operation of the entire test system. During parallel testing, some test mark points may complete the test ahead of time, while other mark points may progress slowly due to resource allocation issues or tasks with higher complexity. In order to ensure that all tasks can be completed within a reasonable time, the test system needs to monitor the progress of each task and adjust the test strategy in time to ensure that all tasks can be completed within a reasonable time window to avoid affecting the overall test progress due to the lag of a single test mark point. Reallocate parallel test tasks based on the accuracy loss threshold and the progress of the test tasks. In other words, when the accuracy loss of some mark points in the test process exceeds the set threshold, or the progress of the test tasks is uneven, it is necessary to readjust the resource allocation of the test tasks to optimize the test efficiency.

[0064] If the accuracy loss of a test mark exceeds the set threshold (such as test interruption or device resource overload), ensure that the accuracy meets the requirements by reallocating other resources. For example, allocate more powerful computing resources to the mark or extend its test time to compensate for the accuracy loss. When some tasks progress slowly, ensure the balance of test progress by adding resources or adjusting the order of tasks. For example, when the test progress of a test mark lags behind due to equipment failure or insufficient resources, other idle devices can be dynamically scheduled to supplement it.

[0065] The layout structure of parallel testing refers to the distribution of test tasks on multiple test devices. During the test process, as the task progress changes and the accuracy loss is evaluated, the layout structure of the test tasks needs to be continuously adjusted and updated. For example, if the task progress of a test mark point lags behind, assign the task to a device with relatively idle resources, or split it into smaller subtasks and distribute it to multiple devices; if the resources of some test devices are already fully loaded, migrate part of the test tasks to other devices to maintain load balancing and test progress synchronization. Through accuracy loss evaluation and adjustment, the accuracy and reliability of the test are ensured, and test result errors caused by insufficient resources or excessive equipment load are avoided. While ensuring test coverage, high-precision test results are maintained.

[0066] Furthermore, step six of this application includes:

[0067] Obtain basic power consumption parameters of the target test chip; based on the basic power consumption parameters, initialize the test environment and establish an initialization test environment, wherein the initialization test environment has an overvoltage protection mechanism and an overcurrent protection mechanism; based on the initialization test environment, set the test operation phase through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure.

[0068] Specifically, the basic power consumption parameters of the target test chip are obtained through data sheets, design documents or by measuring the power consumption of the chip, that is, the power consumed by the target test chip under different working states, including static power consumption, dynamic power consumption, peak power consumption, average power consumption, etc. For example, in laboratory testing, a power analyzer is used to monitor the power consumption of the chip under different workloads. According to the basic power consumption parameters, the test environment is initialized and configured to set up an environment containing necessary protection mechanisms, that is, the initialization test environment, to ensure that the chip is not damaged due to power consumption problems during the test. The initialization test environment has an overvoltage protection mechanism and an overcurrent protection mechanism. The overvoltage protection mechanism is used to protect the chip from voltage input exceeding its maximum rated voltage. The overvoltage protection mechanism can detect that the voltage exceeds the threshold and cut off the power supply to protect the chip from damage; the overcurrent protection mechanism is used to protect the chip from excessive current. Excessive current may cause short circuit or overheating of the internal circuit of the chip, or even burn the chip. The overcurrent protection mechanism immediately cuts off or limits the current when it exceeds the rated value of the chip to protect the chip from damage.

[0069] Initializing the test environment requires combining the aforementioned power consumption parameters with the protection mechanism to ensure that the voltage and current during the test are within the safe operating range of the chip. The purpose of initializing the test environment is to ensure that the chip will not be damaged due to overvoltage, overcurrent, etc. before other tests are performed. According to the previously defined test cycle, parallel distributed test layout structure, test depth, etc., set the test run phase and arrange specific test tasks. The test run phase is the phase in which the test tasks are actually executed during the chip test process. According to the test plan and resources, arrange the execution of test cases to ensure that all test tasks are completed within the specified test cycle. Ensure the security and stability of the test environment while improving the efficiency and quality of the test. Through reasonable test run phase settings, the test coverage can be maximized while minimizing the test cycle and resource consumption.

[0070] Furthermore, the present application also includes the following steps:

[0071] Based on the target test chip, the rated computing efficiency is added at the test mark point; the rated computing efficiency is used as a boundary condition to adjust the resource configuration corresponding to the test running phase, and the resource configuration indicators include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; according to the resource configuration indicators, a resource synchronization monitoring mechanism is introduced, and the resource synchronization monitoring mechanism is used to match the resource demand changes corresponding to the test running phase.

[0072] Specifically, during the test process of the target test chip, by setting the computing efficiency as a boundary condition, adjusting the resource configuration, and monitoring and adjusting the changes in resource demand in real time through the resource synchronization monitoring mechanism. Rated computing efficiency refers to the computing power of the chip under a specific workload, usually expressed as the amount of computing tasks that can be completed per unit time, measured in operations per second (OPS) or other performance indicators. The rated computing efficiency is usually determined by factors such as the chip's architectural design, clock frequency, number of cores, and parallel computing capabilities. Adding the rated computing efficiency to the test mark means that during the test process, in addition to verifying functionality and stability, it is also necessary to evaluate whether the chip's performance meets expectations. The rated computing efficiency is usually expressed as the amount of tasks that can be completed per second (for example: floating-point operations per second or instructions per second), reflecting the computing performance of the chip under ideal conditions, and as a boundary condition, expectations for chip performance can be set during testing.

[0073] By using the rated computing efficiency as a boundary condition, it can be ensured that during the test process, the resources allocated to the chip will not be lower than the minimum resource requirements required for its rated computing efficiency. Otherwise, the test results may not accurately reflect the actual performance of the chip or may cause the test time to be too long. In the test run phase, resource allocation refers to the reasonable allocation of computing resources required for chip testing, including processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints, ensuring that the use of resources during the test process will not exceed the chip's capabilities, thereby avoiding potential performance bottlenecks or resource conflicts. The resource synchronization monitoring mechanism is used to monitor the use of various resources during the test in real time, and dynamically adjust the resource configuration according to changes in resource requirements, ensuring that during the test process, resources can be adjusted in time according to the real-time needs of the test task to avoid resource overload or waste. As the test task proceeds, the demand for processor, memory, and I / O resources will change at different stages. The use of various resources is tracked in real time through monitoring tools (such as hardware monitoring sensors and operating system resource monitoring tools). Based on the monitored changes in resource requirements, the scheduler will dynamically adjust the resource configuration to meet the needs of the test task.

[0074] By setting boundary conditions based on the rated computing efficiency of the target test chip and dynamically adjusting the resource configuration during the test run phase, we can ensure the optimal use of resources and avoid resource waste and bottleneck problems. The resource synchronization monitoring mechanism ensures real-time response to changes in resource requirements during the test process, further improving test efficiency and stability, making the chip test process more accurate and efficient, and ultimately improving the test coverage and test quality of the chip.

[0075] In summary, the chip testing method provided by this application has the following technical effects:

[0076] By acquiring the application requirement information of the target test chip, multiple test cases are set, and the multiple test cases include multiple test mark points; according to the test mark points, the test cycle and the parallel distributed test layout structure are determined in a parallel test manner; according to the test mark points, the test depth and the cross-distributed test layout structure are determined in a cross-test manner; based on the multiple test cases, the first coverage set is determined through the test cycle and the parallel distributed test layout structure; based on the multiple test cases, the second coverage set is determined through the test depth and the cross-distributed test layout structure; through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, according to the first coverage set and the second coverage set, the test environment is simulated, and the target test chip is iteratively tested. In other words, multiple test cases are determined through the application requirement information of the target test chip, and a distributed layout design combining parallel testing and cross testing is introduced. Combined with the evaluation of the coverage set and the iterative test of the simulation environment, the problems of low test efficiency and insufficient coverage caused by the increase in chip complexity are solved, and the coverage and efficiency of chip testing are improved.

[0077] Embodiment 2: Based on the same inventive concept as the chip testing method in the aforementioned embodiment 1, the present application also provides a chip testing device, see the attached Figure 2 , the chip testing device comprises:

[0078] The test case setting module 11 is used to obtain application requirement information of the target test chip and set a plurality of test cases, wherein the plurality of test cases include a plurality of test marking points.

[0079] The parallel testing module 12 is used to determine the test cycle and the parallel distributed test layout structure in a parallel testing manner according to the test marking points.

[0080] The cross-test module 13 is used to determine the test depth and the cross-distributed test layout structure in a cross-test manner according to the test mark points.

[0081] The first coverage module 14 is used to determine a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure.

[0082] The second coverage module 15 is used to determine a second coverage set based on the multiple test cases through the test depth and the cross-distributed test layout structure.

[0083] The simulation test module 16 is used to simulate the test environment according to the first coverage set and the second coverage set through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, and perform iterative testing on the target test chip.

[0084] Further, the test case setting module 11 in the chip testing device is also used for:

[0085] A class of key requirement indicators in the application requirement information is obtained, wherein the class of key requirement indicators is associated with the reliability of the target test chip, and the class of key requirement indicators includes vibration resistance requirements and electromagnetic compatibility requirements; a reliability verification link is set according to the vibration resistance requirements and electromagnetic compatibility requirements in the class of key requirement indicators; under the constraints of the resource synchronization monitoring mechanism, the reliability verification link is seamlessly integrated into the test operation phase to perform resource balancing scheduling.

[0086] Further, the test case setting module 11 in the chip testing device is also used for:

[0087] Obtain two types of key demand indicators in the application demand information, wherein the two types of key demand indicators are associated with the stability of the target test chip, and the two types of key demand indicators include signal reception sensitivity requirements, transmission power requirements, and spectrum efficiency requirements; set a stability verification link through the signal reception sensitivity requirements, transmission power requirements, and spectrum efficiency requirements in the two types of key demand indicators; and seamlessly integrate the stability verification link into the test operation phase under the constraints of the resource synchronization monitoring mechanism to perform resource balancing scheduling.

[0088] Further, the test case setting module 11 in the chip testing device is also used for:

[0089] Based on the reliability verification link and the stability verification link, a resource configuration optimization function is established; the total number of the test mark points is recorded as K, and the resource configuration optimization function Among them, R opt is the optimal resource allocation, R k is the actual resource configuration corresponding to the kth test mark point, D k is the resource requirement corresponding to the kth test mark point, λ is the coefficient between the trade-off between resource allocation and comprehensive evaluation value, and the comprehensive evaluation value Among them, w reliability,i is the test result of the i-th reliability verification link, R stability,j is the test result of the jth stability verification link, w reliability,i and wstability,j It is the weight corresponding to the reliability verification link and the stability verification link.

[0090] Furthermore, the parallel testing module 12 in the chip testing device is also used for:

[0091] Based on the test mark points, the accuracy loss is evaluated and an accuracy loss threshold is set; in a parallel test mode, the progress of the test tasks is synchronized; through the accuracy loss threshold and the progress of the test tasks, the parallel test tasks are reallocated and the parallel distributed test layout structure is updated.

[0092] Furthermore, the simulation test module 16 in the chip testing device is also used for:

[0093] Obtain basic power consumption parameters of the target test chip; based on the basic power consumption parameters, initialize the test environment and establish an initialization test environment, wherein the initialization test environment has an overvoltage protection mechanism and an overcurrent protection mechanism; based on the initialization test environment, set the test operation phase through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure.

[0094] Furthermore, the simulation test module 16 in the chip testing device is also used for:

[0095] Based on the target test chip, the rated computing efficiency is added at the test mark point; the rated computing efficiency is used as a boundary condition to adjust the resource configuration corresponding to the test running phase, and the resource configuration indicators include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; according to the resource configuration indicators, a resource synchronization monitoring mechanism is introduced, and the resource synchronization monitoring mechanism is used to match the resource demand changes corresponding to the test running phase.

[0096] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. Figure 1 The chip testing method and specific examples in the first embodiment are also applicable to a chip testing device in the present embodiment. Through the above detailed description of a chip testing method, those skilled in the art can clearly understand a chip testing device in the present embodiment, so for the sake of brevity of the specification, it will not be described in detail here. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0097] Embodiment three, based on the inventive concept of a chip testing method in the aforementioned embodiment one, the present application also provides an electronic device, comprising: at least one processor; a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the steps of a chip testing method described in any one of the aforementioned embodiments one.

[0098] Attached Figure 3 This is a schematic diagram of the structure of an exemplary electronic device of this application. Figure 3 In the embodiment, the bus architecture is represented by bus 300, which may include any number of interconnected buses and bridges, and bus 300 connects various circuits including one or more processors represented by processor 302 and memory represented by memory 304. Bus 300 may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. Bus interface 305 provides an interface between bus 300 and receiver 301 and transmitter 303. Receiver 301 and transmitter 303 may be the same element, namely a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 302 is responsible for managing bus 300 and general processing, while memory 304 may be used to store data used by processor 302 when performing operations.

[0099] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the present application and its equivalent technology, the present application is also intended to include these modifications and variations.

Claims

1. A chip testing method, characterized in that: include: Acquire application requirement information of a target test chip, and set a plurality of test cases, wherein the plurality of test cases include a plurality of test marking points; According to the test marking points, determining the test cycle and the parallel distributed test layout structure in a parallel testing manner; Determine the test depth and the cross-distributed test layout structure in a cross-test manner according to the test marking points; Based on the multiple test cases, determining a first coverage set through the test cycle and the parallel distributed test layout structure; Based on the multiple test cases, determining a second coverage set through the test depth and the cross-distributed test layout structure; Through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, the target test chip is iteratively tested according to the first coverage set and the second coverage set to simulate the test environment.

2. A chip testing method according to claim 1, characterized in that: By using the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, simulating the test environment according to the first coverage set and the second coverage set, including: Obtain the basic power consumption parameters of the target test chip; Based on the basic power consumption parameters, the test environment is initialized and configured to establish an initialization test environment, wherein the initialization test environment has an overvoltage protection mechanism and an overcurrent protection mechanism; Based on the initialization test environment, the test running phase is set through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure.

3. A chip testing method as claimed in claim 2, characterized in that: Based on the initialization test environment, the test running phase is set through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure, including: Based on the target test chip, at the test mark point, adding a rated computing efficiency; Taking the rated computing efficiency as a boundary condition, adjusting the resource configuration corresponding to the test running phase, the resource configuration indicators include processor resource allocation constraints, memory resource allocation constraints, and I / O resource allocation constraints; According to the resource configuration index, a resource synchronization monitoring mechanism is introduced, and the resource synchronization monitoring mechanism is used to match the resource demand changes corresponding to the test running stage.

4. A chip testing method as claimed in claim 3, characterized in that: Obtain application requirement information of the target test chip, set up multiple test cases, and also include: Acquire a class of key requirement indicators in the application requirement information, wherein the class of key requirement indicators is associated with the reliability of the target test chip, and the class of key requirement indicators includes vibration resistance requirements and electromagnetic compatibility requirements; According to the vibration resistance requirements and electromagnetic compatibility requirements in the first category of key demand indicators, a reliability verification link is set; Under the constraints of the resource synchronization monitoring mechanism, the reliability verification link is seamlessly integrated into the test operation phase to perform resource balancing scheduling.

5. A chip testing method as claimed in claim 4, characterized in that: Obtain a class of key demand indicators in application demand information, including: Obtaining two types of key demand indicators in the application demand information, wherein the two types of key demand indicators are associated with the stability of the target test chip, and the two types of key demand indicators include signal receiving sensitivity requirements, transmission power requirements, and spectrum efficiency requirements; According to the signal receiving sensitivity requirements, transmission power requirements and spectrum efficiency requirements in the two types of key demand indicators, a stability verification link is set; Under the constraints of the resource synchronization monitoring mechanism, the stability verification link is seamlessly integrated into the test operation phase to perform resource balancing scheduling.

6. A chip testing method as claimed in claim 5, characterized in that: Also includes: Based on the reliability verification link and the stability verification link, a resource configuration optimization function is established; The total number of the test mark points is recorded as K, and the resource allocation optimization function Among them, R opt is the optimal resource allocation, R k is the actual resource configuration corresponding to the kth test mark point, D k is the resource requirement corresponding to the kth test mark point, λ is the coefficient between the trade-off between resource allocation and comprehensive evaluation value, and the comprehensive evaluation value Among them, w reliability,u is the test result of the i-th reliability verification link, R stability,j is the test result of the jth stability verification link, w reliability,i and w stability,j It is the weight corresponding to the reliability verification link and the stability verification link.

7. A chip testing method as claimed in claim 6, characterized in that: According to the test mark points, a test cycle and a parallel distributed test layout structure are determined in a parallel testing manner, including: Performing precision loss assessment based on the test mark points and setting a precision loss threshold; In parallel testing mode, synchronize the progress of test tasks; The parallel test tasks are reallocated according to the accuracy loss threshold and the test task progress, and the parallel distributed test layout structure is updated.

8. A chip testing device, characterized in that: The chip testing device is used to implement the steps of the chip testing method according to any one of claims 1 to 7, comprising: A test case setting module, the test case setting module is used to obtain application requirement information of the target test chip and set a plurality of test cases, wherein the plurality of test cases include a plurality of test marking points; A parallel test module, the parallel test module is used to determine the test cycle and the parallel distributed test layout structure in a parallel test manner according to the test mark points; A cross-test module, the cross-test module is used to determine the test depth and the cross-distributed test layout structure in a cross-test manner according to the test mark points; A first coverage module, the first coverage module is used to determine a first coverage set based on the multiple test cases through the test cycle and the parallel distributed test layout structure; A second coverage module, the second coverage module is used to determine a second coverage set based on the multiple test cases through the test depth and the cross-distributed test layout structure; A simulation test module, wherein the simulation test module is used to perform iterative testing on the target test chip by simulating the test environment according to the first coverage set and the second coverage set through the test cycle and the parallel distributed test layout structure, the test depth and the cross-distributed test layout structure.

9. An electronic device, comprising: at least one processor; a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the steps of a chip testing method described in any one of claims 1 to 7.

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