Solid state disk power consumption control method, solid state disk and storage medium

Abstract

The invention discloses a solid-state disk power consumption control method, a solid-state disk and a storage medium. The method comprises the steps of determining an updated value of an idle timeout duration corresponding to at least one low-power-consumption state level according to a current running state parameter of the solid state disk based on a set initial value of the idle timeout duration corresponding to the at least one low-power-consumption state level; according to the update value of the idle timeout duration corresponding to the at least one low-power-consumption state level, controlling the solid state disk to enter a corresponding low-power-consumption state; wherein the running state parameters comprise at least two of the following parameters: data throughput, host instruction quantity, cache data volume in a buffer management unit, flash memory queue instruction quantity, flash memory programming operation quantity and flash memory erasure state. According to the solid state disk power consumption control scheme provided by the embodiment of the invention, the idle timeout duration is dynamically adjusted based on the running state of the solid state disk, the low-power-consumption state management scheme of the solid state disk is optimized, and the overall performance is improved on the premise of reducing the power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a solid state hard disk power consumption control method, a solid state hard disk, and a storage medium. Background Art

[0002] The power consumption and heat generated by the migration and movement of electrons are problems that semiconductor memory devices must face and solve. Solid-state drives are widely used in computer systems, and reducing their power consumption and heat generation is particularly important for solid-state drives, which has a decisive impact on device endurance, system stability, and overall performance. Summary of the invention

[0003] The present application provides a solid-state hard disk power consumption control method, a solid-state hard disk and a storage medium. Based on the set initial values ​​of the idle timeout durations of each level and according to the current operating state parameters of the solid-state hard disk, the idle timeout duration update values ​​corresponding to each low-power state level are dynamically determined, and based on this, the solid-state hard disk is controlled to enter the corresponding low-power state. The idle timeout duration can be dynamically adjusted based on the operating status of the solid-state hard disk, the low-power state management scheme of the solid-state hard disk is optimized, and the overall performance is improved while reducing power consumption.

[0004] The present application provides a method for controlling power consumption of a solid state drive, including: Based on the set initial value of the idle timeout duration corresponding to at least one low power consumption state level, and according to the current operating state parameters of the solid state drive, determining an updated value of the idle timeout duration corresponding to the at least one low power consumption state level; According to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level, controlling the solid state drive to enter a corresponding low power consumption state; The operating status parameters include at least two of the following: data throughput, host instruction quantity, cache data quantity in a buffer management unit, flash memory queue instruction quantity, flash memory programming operation quantity, and flash memory erase status.

[0005] The present application also provides a solid state drive, including: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the solid-state hard disk power consumption control method as described in any embodiment of the present application.

[0006] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the solid-state hard disk power consumption control method as described in any embodiment of the present application is implemented.

[0007] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0009] Figure 1 This is a flow chart of a solid state hard disk security protection method in an embodiment of the present application; Figure 2 This is a flow chart of another solid state hard disk security protection method in an embodiment of the present application; Figure 3 This is another schematic diagram of the relationship between the power consumption states of a solid state drive in an embodiment of the present application; Figure 4 This is a schematic diagram of the structure of a solid state hard disk in an embodiment of the present application. DETAILED DESCRIPTION

[0010] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0011] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0012] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0013] Solid-state drives are widely used in computer systems as storage disks or system disks due to their higher stability, lower power consumption, and faster speed. Solid-state drives with lower power consumption and shorter wake-up time play a key role in ensuring the overall performance of computer systems. Some realizable solid-state drives support the ASPM (Active State Power Management) function of PCIe's L1.1 and L1.2. The solid-state drive determines the current low-power state through the ASPM function of the PCIe physical layer adaptive power consumption, allowing it to switch to a low-power state when needed, thereby effectively reducing the power consumption of the entire link. Usually based on the PCIe link detection results, when the link is in an idle state, the PCIe link level is actively reduced to achieve reduced power consumption of the solid-state drive.

[0014] The present application embodiment provides a method for controlling power consumption of a solid state drive. Figure 1 As shown, including: Step 130, based on the set initial value of the idle timeout duration corresponding to at least one low power consumption state level, and according to the current operating state parameters of the solid state drive, determining an updated value of the idle timeout duration corresponding to the at least one low power consumption state level; Step 140, controlling the solid state drive to enter a corresponding low power consumption state according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level; The operating status parameters include at least two of the following: data throughput, host command quantity, BMU buffer data size, NAND queue command quantity, NAND program operation quantity, and NAND erase state.

[0015] The data throughput indicates the data throughput between the solid-state drive and an external system per unit time, and the external system includes a host, that is, the amount of data transmitted between the solid-state drive and the host per unit time; the number of host instructions indicates the number of host instructions processed by the solid-state drive per unit time, including read instructions and / or write instructions; the amount of cached data in the buffer management unit indicates the amount of cached data in the buffer management unit BMU in the solid-state drive; the number of flash memory queue instructions indicates the number of instructions in the flash memory operation instruction queue in the solid-state drive; the number of flash memory programming operations indicates the number of flash memory programming operations in the solid-state drive per unit time, also known as the number of flash memory write operations per unit time; the flash memory erase status indicates the status of the flash memory in the solid-state drive being in progress or having completed an erase operation.

[0016] In some exemplary embodiments, the at least one low power consumption state level has M levels, the operating state parameters include n, M and n are both integers greater than 0; and the update value of the idle supermarket duration corresponding to each low power consumption state level is determined according to the following method: in, is the updated value of the idle timeout duration of the i-th level, is the initial value of the idle timeout period of the i-th level, The weight of the jth operating status parameter at the i-th level, is the parameter value of the j-th operating status parameter; i is less than or equal to M, and j is less than or equal to n.

[0017] In some exemplary embodiments, is the calculated participation value corresponding to the (actual) parameter value of the jth operating state parameter, according to the actual parameter value of each operating state parameter And the corresponding calculation coefficient For example, All calculation coefficients are 1 / 1000, Optionally, the (actual) parameter values ​​of the various operating state parameters can also be used in the calculation without calculating the coefficients Participate and set appropriate weights The calculation coefficients of different operating state parameters may be the same or different, and are not limited to specific aspects.

[0018] Among them, the weight values ​​of different operating parameters at the same level can be the same or different, and the weight values ​​of different levels of the same operating parameter can be the same or different. They can be flexibly set according to needs and are not limited to specific aspects.

[0019] It can be understood that low power consumption in the embodiment of the present application refers to a power consumption state compared to the normal power consumption of the solid-state hard disk under normal working conditions. In some exemplary embodiments, the power consumption is reduced by turning off the power supply of some hardware modules in the solid-state hard disk and / or changing the working mode of some hardware modules. Among them, different types of hardware modules change the working mode in different specific ways, not limited to specific aspects. For example, the flash memory module, the working mode outside the power off (power off) includes: normal power operation mode (power on) and standby mode (standby); the CPU clock module, the working mode outside the power off (power off) includes: normal power operation mode (power on) and clock gating mode (clockgating); the PCIe module, the working mode outside the power off (power off) includes: normal power operation mode (power on) and lower frequency mode (lower frequency); DDR (module), the working mode outside the power off (power off) includes: normal power operation mode (power on), self-refresh mode (self-refresh) and deep sleep mode (deep sleep); and so on.

[0020] In some exemplary embodiments, the idle timeout duration is also referred to as an idle time processing timeout duration (ITPT).

[0021] Among them, according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level, controlling the solid state drive to enter the corresponding low power consumption state includes: According to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level, controlling the solid state drive to enter the corresponding low power consumption state, and determining the target low power consumption state level corresponding to the current idle time duration of the solid state drive; Control the solid state drive to switch to the target low power consumption state level.

[0022] In some exemplary embodiments, controlling the solid state drive to switch to the target low power consumption state level includes: The operation of each hardware module is controlled according to the power switch and / or working mode configuration of each hardware module corresponding to the target low power consumption state level.

[0023] In some exemplary embodiments, the solid-state drive includes five power consumption state levels, wherein PS0 is a normal power consumption state level, and PS1-PS4 are low power consumption state levels. In multiple low power consumption states, the power switches and / or working modes of the corresponding multiple hardware modules are configured differently to correspond to different operating power consumptions. For example, in the normal power consumption state level PS0, each hardware module is powered on normally, and in the low power consumption state levels PS1-PS4, each hardware module has a corresponding power supply and / or working mode configuration as follows: Figure 2 As shown. It can be seen that PS4 is at the first power consumption state level, PS3 is at the second power consumption state level, the power consumption of PS4 level is higher than that of PS3 level, the power consumption of PS3 level is higher than that of PS2 level, and the power consumption of PS2 level is higher than that of PS1 level. It should be noted that Figure 2 The hardware modules in the solid-state drive shown include: CPU clock module (CPU CLOCK), system clock module (SYSTEM CLOCK), non-volatile memory protocol (NVME) module, PCIe module (PCIE), flash memory module (NAND), DDR module, phase-locked loop (Autonomous Power State Transition, PLL) module, Advanced Encryption Standard / Advanced Encryption Standard , AES / SHA module. In some exemplary embodiments, the hardware modules also include: General Purpose Input / Output (GPIO) module, Power Management Unit (Power Management Unit, PMU), Static Random-Access Memory (Static Random-Access Memory, SRAM), etc. Different solid-state drives contain different hardware modules, not limited to Figure 2 Or aspects recorded in the embodiments of the present application.

[0024] Accordingly, an idle timeout duration is set for each low power state level PS1-PS4, which is recorded as T1, T2, T3, and T4. The power consumption levels are from low to high: PS4, PS3, PS2, and PS1, and the corresponding idle timeout durations are from large to small: T4, T3, T2, and T1. In some exemplary embodiments, when the idle time of the solid state drive reaches T1, it enters the low power state of the PS1 level, reaches T2, enters the low power state of the PS2 level, reaches T3, enters the low power state of the PS3 level, and reaches T4, enters the first power consumption state of the PS4 level. Accordingly, the initial value of the idle timeout duration is recorded as: , , , , the updated value is recorded as: , , , .

[0025] It is understandable that, according to the need for low power consumption control, a low power consumption state level can be set, or multiple low power consumption state levels can be set, without limitation to specific aspects. Execution of step 130 determines the idle timeout duration corresponding to one or more low power consumption state levels, and after the idle time of the solid state drive exceeds the idle timeout duration, the solid state drive enters the corresponding low power consumption state. For example, two low power consumption levels are determined: a first low power consumption level and a second low power consumption level, and the corresponding idle timeout durations are a first timeout duration and a second timeout duration, respectively.

[0026] In some exemplary embodiments, the method further comprises: Step 110, receiving an Autonomous Power State Transition Enable (APSTE) instruction from the host, and starting an Autonomous Power State Transition (APST) function; Accordingly, step 140 includes: executing the APST function to control the solid-state hard disk to sequentially enter the corresponding low power consumption level according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level.

[0027] It can be seen that the method is applied to a solid-state drive that supports the APST function, that is, the local firmware of the solid-state drive sets the autonomous power state transition attributes (APSTA). Upon receiving an APSTE instruction from the host, the local APST function is started, and the APST function is executed, so that the idle timeout duration corresponding to at least one low power state level is updated according to the determined updated value, so that when the solid-state drive timeout duration reaches the idle timeout duration, the low power state is entered accordingly.

[0028] In some exemplary embodiments, the method further comprises: Step 120, receiving a set feature instruction from a host, and controlling the solid state drive to enter a corresponding low power consumption state according to the low power consumption level indicated in the set feature instruction.

[0029] It can be understood that in some exemplary embodiments, the host can directly instruct the solid-state drive to enter a certain low-power state through the set feature instruction. The timing of sending the set feature is determined by the host, and the target low-power state level indicated in the instruction is determined by the host; the solid-state drive responds to the instruction and controls the power supply and / or working mode of one or more local hardware modules according to the indicated low-power state level to achieve the indicated low-power target and enter the corresponding low-power level.

[0030] In some exemplary embodiments, the host obtains the current operating status parameters of the solid-state drive, determines the updated value of the idle timeout period corresponding to each low-power state level based on the initial value of the idle timeout period corresponding to each low-power state level, and according to the current operating status parameters; then determines the corresponding target low-power state level based on the current idle time of the solid-state drive, and sends a set feature command to control the solid-state drive to enter the corresponding target low-power state.

[0031] Optionally, the host may also determine the target power consumption state level in other ways and then send the set feature command.

[0032] In some exemplary embodiments, the set feature instruction format may be determined according to the NVME specification, and the specific instruction format will not be discussed in detail herein.

[0033] In some exemplary embodiments, step 140 further includes: When neither the APSTE instruction nor the set feature instruction is received, a local Auto Power Extend (Auto PX) function module is started to control the solid-state drive to enter a corresponding low power state according to an updated value of an idle timeout duration corresponding to at least one low power state level.

[0034] In some exemplary embodiments, the Auto PX functional module determines an updated value of the idle timeout period corresponding to at least one low power consumption state level based on the initial value of the idle timeout period corresponding to at least one low power consumption state level and according to the current operating state parameters of the solid state drive, so as to control the solid state drive to enter the corresponding low power consumption state.

[0035] Optionally, in some exemplary embodiments, the APST function module determines an update value of the idle timeout duration corresponding to at least one low power consumption state level based on an initial value of the idle timeout duration corresponding to at least one low power consumption state level set according to a current operating state parameter of the solid state drive, so as to control the solid state drive to enter a corresponding low power consumption state; Alternatively, other functional modules on the solid-state drive use this method to determine the update value of the idle timeout duration corresponding to the at least one low-power state level, and the Auto PX functional module or the APST functional module controls the low-power state switching according to the determined update value. The specific implementation form is not limited to the aspects of the examples of the embodiments of the present application. In some exemplary embodiments, the Auto PX functional module or the APST functional module controls the power switch and / or operation / power of each module through the PMU, and the implementation scheme of the PMU is not discussed in detail here.

[0036] Among them, the levels included in the at least one low power consumption state level used by the Auto PX functional module or the APST functional module may be the same or different; the initial values ​​of the idle timeout durations corresponding to each level may be the same or different, and the corresponding weight values ​​when determining the update value may be the same or different. In the absence of conflict, they can be flexibly determined and are not limited to specific aspects.

[0037] For example, there are four low-power state levels: PS1, PS2, PS3, and PS4. The weight values ​​of the four levels of the same operating state parameter are the same, and the initial value of the idle timeout duration is 500ms, 1000ms, 2000ms, 3000ms, 6 operating status parameters: data throughput , host command number (host command,) , the amount of cached data in the buffer management unit (BMU buffer data size) 、Number of flash queue commands (number of cmds in NADN queue) 、NAND program number , NAND erase state , the weight value of each parameter , , Set to 3, 6, 9, 12, 15, 18, where the weight values ​​of the four levels of the same operating status parameter are the same, that is , ,… The updated value is calculated as follows: get: It should be noted that the weight values ​​of the four levels of the same operating status parameter may also be different, or partially different, and can be flexibly set according to needs.

[0038] In some exemplary embodiments, the at least one low power consumption state level includes: a first power consumption state level; in the first power consumption state level, the solid state drive keeps the following hardware modules powered and cuts off the power supply of other hardware modules: GPIO module, power management control PMU module and SRAM.

[0039] In some exemplary embodiments, before controlling the solid state drive to enter the first power consumption state level, the method further includes: The data in one or more registers in other hardware modules in the solid state drive that will be cut off from power supply are saved in the SRAM.

[0040] The one or more registers include: a first type of register and / or a second type of register.

[0041] It can be seen that before entering the first power consumption state, the data in the registers of the set type in other hardware modules in the solid-state hard disk that will be cut off from power supply are saved in the SRAM that still maintains power supply in the first power consumption state, thereby improving the data storage efficiency. When necessary, the data saved in the SRAM can be quickly read and the first power consumption state can be exited to wake up the solid-state hard disk, thereby improving the entry / exit speed of the lowest power consumption state.

[0042] In some exemplary embodiments, before controlling the solid state drive to enter the first power consumption state level, the method further includes: Saving data in one or more first-category registers in other hardware modules in the solid-state drive that will be cut off from power supply into the SRAM; and / or, The data in one or more second-category registers in other hardware modules in the solid-state drive that will be cut off from power supply are saved in the flash memory.

[0043] In some exemplary embodiments, the at least one low power consumption state level includes: a second power consumption state level; in the second power consumption state level, the solid state drive keeps the following hardware modules powered and cuts off the power supply of other hardware modules: General purpose input and output port GPIO module, power management control PMU module, double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR) and SRAM.

[0044] In some exemplary embodiments, before controlling the solid state drive to enter the second power consumption state level, the method further includes: The data in one or more second-category registers in other hardware modules in the solid-state drive that will be cut off from power supply are saved in the flash memory.

[0045] It can be seen that in the second power consumption state, more hardware modules maintain power supply than in the first power consumption state, and the power consumption of the solid state drive after entering the second power consumption state is greater than the power consumption after entering the first power consumption state.

[0046] In some exemplary embodiments, the at least one low power consumption state level includes: a first power consumption state level and a second power consumption state level.

[0047] In some exemplary embodiments, the at least one low power consumption state level includes: a first power consumption state level and a third power consumption state level; or, includes: a second power consumption state level and a third power consumption state level; or, includes: a first power consumption state level, a second power consumption state level and a third power consumption state level; and so on. More examples are not listed here one by one.

[0048] In some exemplary embodiments, the first type of registers includes: one or more registers in DDR. In some exemplary embodiments, the data in the first type of registers includes one or more of the following: self-monitoring analysis and reporting information (Smart info, Self-Monitoring, Analysis and Reporting Technology), non-volatile memory host controller interface specification registration information (NVME reg, Non-Volatile Memory express) and host information (host info).

[0049] In some exemplary embodiments, the data in the second type of registers includes one or more of the following: address mapping table (L2P table, solid state drive physical information (vb list info), cache data in the cache management unit (BMU buf) It can be seen that in the first power consumption state level, the solid state drive maintains the power supply of the most basic hardware modules, and these most basic hardware modules maintain power supply so that the solid state drive can receive and respond to signals from the host, so as to exit the first power consumption state. Compared with the second power consumption state level, when entering the first power consumption state, the DDR power supply will be disconnected, while the SRAM still maintains power supply. Therefore, before entering the first power consumption state, the data in the second type of register is saved in the flash memory, and the data in the first type of register in the DDR is saved in the SRAM; that is, before entering the first power consumption state, it is necessary to move the DDR register data to the SRAM, and when exiting the first power consumption state, it is necessary to restore the data from the SRAM to the DDR, which delays the switching time to a certain extent. Therefore, considering the switching time and the power consumption after switching, in some exemplary embodiments, the lowest power consumption state level included in the at least one low power consumption state level is the second power consumption state level (PS3), and the DDR and SRAM are both powered, so that before the final control enters the lowest power consumption state, there is no need to move the register data in the DDR to the SRAM, which not only ensures the switching efficiency of entering / exiting the second power consumption state, but also ensures lower power consumption in the second power consumption state.

[0050] In some exemplary embodiments, the initial value of the idle timeout duration corresponding to the at least one low power consumption state level is pre-set in the host, or pre-set in the solid state drive, and can be selected accordingly according to the specific embodiment.

[0051] In some exemplary embodiments, the solid state drive includes five power consumption state levels, PS0 is a normal power consumption state level, PS1-PS4 are four low power consumption state levels from low to high, and the power consumption state transition is as follows: Figure 3 As shown, after the host (operating system, OS) is started, the SSD enters the normal power consumption state PS0, and the host sends an APSTE instruction to the SSD. If the SSD supports the APST function, the host determines the update value of the idle timeout duration corresponding to the four low power consumption state levels in response to the instruction. , , , , and then enter PS1, PS2, PS3 and PS4 in turn according to the idle time. Among them, PS1 is the fourth low power state (highest power consumption), at least including changing the CPU clock to gating mode; PS2 is the third low power state (second highest power consumption), at least including changing DDR to deep sleep mode; PS3 is the second low power state (second lowest power consumption), at least including changing NVME to power off; PS4 is the first low power level (lowest power consumption), at least including changing NAND to power off; more hardware modules power supply status and / or working mode, not one by one example. In the case that the solid-state drive does not support the APST function, the set feature instruction of the host (OS) is received, corresponding to the level PSx indicated in the instruction. Among them, the PS4 level only retains GIPO, PMU, and SRAM power supply, and the PS3 level only retains GIPO, PMU, DDR, and SRAM power supply. It can be seen that under PS4, only SRAM remains powered, and data in other volatile storage in the SSD needs to be saved in flash memory and / or SRAM. For example, data in DDR needs to be moved to SRAM, and then restored from SRAM to DDR when exiting PS4. Under PS3, DDR remains powered, so there is no need to move related data, and the time required to recover from this low-power state to normal working state is shorter.

[0052] In some exemplary embodiments, the solid-state drive also starts the Auto PX function module, which selects three low-power state levels, PS1, PS2, and PS3, and determines the update value of the idle timeout duration corresponding to the three low-power state levels used by this function module. , , . In the case that the solid state drive does not support the APST function and does not support the set feature instruction, the solid state drive starts the Auto PX function module, and controls itself to enter the corresponding low power state according to the determined three low power state levels and the updated value of the corresponding idle timeout duration. It can be seen that, considering that in PS4, except for the SRAM power supply, other storage modules are all cut off from power supply, so before switching to PS4, the data in the DDR needs to be moved to the SRAM for storage, and the switching in / out time of this state is relatively long. In this embodiment, the Auto PX function module determines that the lowest power state level is PS3, that is, in the lowest power state controlled by the Auto PX function module, the power supply of the general input and output port GPIO module, the power management unit PMU, the double rate synchronous dynamic random access memory DDR and the static random access memory SRAM are all maintained, taking into account the balance between reducing power consumption and quickly waking up / exiting the low power state, which is conducive to improving the application scope of the solid state drive.

[0053] It should be noted that Figure 3 Only some of the switching between power consumption state levels are illustrated, including exiting PS4 and returning to PS3, exiting PS3 and returning to PS2, exiting PS4 and returning to PS0, exiting PS3 and returning to PS0, ... etc., which are not shown.

[0054] In some exemplary embodiments, the method further includes: controlling the solid-state drive to exit the current low power consumption state and restore to the normal power consumption state according to a preset wake-up event; or switching to another low power consumption state. In the absence of conflicts, the switching relationship between the states, the wake-up event, and the entry / exit conditions can be flexibly set according to relevant specifications or application needs.

[0055] In some exemplary embodiments, the method further includes: executing step 130 again according to a preset time interval or event trigger, determining an updated value of the idle timeout duration corresponding to the at least one low power consumption state level according to the latest operating state parameters, and executing step 140 again.

[0056] The present application also provides a solid state drive, including: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the solid-state hard disk power consumption control method as described in any embodiment of the present application.

[0057] In some exemplary embodiments, the solid state drive further comprises: a GPIO module, a power management unit PMU and an SRAM; The GPIO module is configured to maintain power supply and receive IO instructions from the outside at each low power consumption state level; The PMU module is configured to maintain power supply at each low power consumption state level, and is used to control the power switch of other hardware modules; The SRAM is configured to maintain power supply in a first power consumption state level to save one or more register values ​​in the solid state drive.

[0058] In some exemplary embodiments, the solid state drive further includes: DDR.

[0059] In some exemplary embodiments, the processor executes the one or program to save the data in one or more first-class registers in the DDR into the SRAM before controlling the solid-state drive to enter the first power consumption state; after controlling the solid-state drive to exit the first power consumption state, the data saved by the previous generation is read out from the SRAM and restored to one or more first-class registers in the DDR.

[0060] In some exemplary embodiments, the solid state drive further includes: a system clock SYS CLK module, a CPU clock module, a flash memory module, an error detection and correction ECC (Error Correction Code) module, a low-density parity-check code LDPC (Low Density Parity-Check Code) module, a buffer management unit BMU (Buffer Management Unit), and a phase-locked loop PLL (Phase Locked Loop) module.

[0061] In some exemplary embodiments, the solid state drive further includes: an NVME module, a PCIe module, a flash memory module, and an AES / SHA module.

[0062] For example, the solid state drive Figure 4 As shown, including: CPU, PCIE, NWME, GPIO, PMU, SRAM, NAND, DDR, BMU, SYS PLL, AES / SHA, ECC / LDPC.

[0063] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the solid-state hard disk power consumption control method as described in any embodiment of the present application is implemented.

[0064] By adopting the power consumption control scheme provided in the embodiment of the present application, the idle timeout duration corresponding to each low power consumption state can be dynamically determined to more accurately control the timing of the solid state drive switching to a low power consumption state level, thereby further improving the power consumption control effect. In some exemplary embodiments, the low power consumption control behavior compatible with the host operating system, when APSTE and set feature are not supported, the local automatic power extension function module is used as the main control module for the basic switching of the low power consumption state, providing a complete low power consumption state management, and ensuring the effectiveness of the low power consumption control of the solid state drive.

[0065] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

Claims

1. A method for controlling power consumption of a solid state drive, characterized in that: include: Based on the set initial value of the idle timeout duration corresponding to at least one low power consumption state level, and according to the current operating state parameters of the solid state drive, determining an updated value of the idle timeout duration corresponding to the at least one low power consumption state level; According to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level, controlling the solid state drive to enter a corresponding low power consumption state; The operating status parameters include at least two of the following: data throughput, host instruction quantity, cache data quantity in a buffer management unit, flash memory queue instruction quantity, flash memory programming operation quantity, and flash memory erase status.

2. The method for controlling power consumption of a solid state drive according to claim 1, wherein: The method also includes: receiving an automatic power state transition enable APSTE instruction from a host and starting an automatic power state transition APST function; The controlling the solid state drive to enter a corresponding low power consumption level according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level comprises: The APST function is executed to control the solid-state hard disk to enter the corresponding low power consumption level in sequence according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level.

3. The method for controlling power consumption of a solid state drive according to claim 1, wherein: The method also includes: receiving a set feature instruction from a host, and controlling the solid state drive to enter a corresponding low power consumption state according to the low power consumption level indicated in the set feature instruction.

4. The method for controlling power consumption of a solid state hard disk according to claim 2 or 3, characterized in that: The controlling the solid state drive to enter a corresponding low power consumption level according to the updated value of the idle timeout duration corresponding to the at least one low power consumption state level further includes: When neither the APSTE instruction nor the set feature instruction is received, the local automatic power extension function module is started to control the solid-state drive to enter the corresponding low power state according to the updated value of the idle timeout duration corresponding to the at least one low power state level.

5. The method for controlling power consumption of a solid state drive according to claim 1, wherein: The at least one low power consumption state level includes: a first power consumption state level; in the first power consumption state level, the solid state drive keeps the following hardware modules powered and cuts off the power supply of other hardware modules: General purpose input and output port GPIO module, power management unit PMU and static random access memory SRAM.

6. The method for controlling power consumption of a solid state drive according to claim 5, characterized in that: Before controlling the solid state drive to enter the first power consumption state level, the method further includes: The data in one or more registers in other hardware modules in the solid state drive that will be cut off from power supply are saved in the SRAM.

7. The method for controlling power consumption of a solid state drive according to claim 5 or 6, characterized in that: The at least one low power consumption state level includes: a second power consumption state level; in the second power consumption state level, the solid state drive keeps the following hardware modules powered and cuts off the power supply of other hardware modules: General purpose input and output port GPIO module, power management unit PMU, double rate synchronous dynamic random access memory DDR and static random access memory SRAM.

8. A solid state hard disk, characterized in that: include: one or more processors; a storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the solid-state hard disk power consumption control method as described in any one of claims 1-7.

9. The solid state drive according to claim 8, characterized in that: It also includes: a general purpose input and output port GPIO module, a power management unit PMU and a static random access memory SRAM; The GPIO module is configured to maintain power supply and receive input and output IO instructions from the outside at each low power consumption state level; The PMU module is configured to maintain power supply at each low power consumption state level, and is used to control the power switch of other hardware modules; The SRAM is configured to maintain power supply at each low power consumption state level; wherein, the SRAM maintains power supply at the first power consumption state level to save one or more register values ​​of other registers in the solid state drive that have been cut off from power supply.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the solid-state hard disk power consumption control method as described in any one of claims 1 to 7 is implemented.

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