FPGA fault diagnosis accelerator design method and system

Abstract

The invention belongs to the technical field of artificial intelligence, and discloses an FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix, and the method comprises the steps: taking GHOSTNETV2 as a backbone network, carrying out the standard 3 * 3 two-dimensional convolution operation of an input content through a first main convolution layer of the network, so as to extract features, and carrying out the calculation of the features; then inputting the features into a subsequent layer for further feature extraction, and independently optimizing the layer; the influence of quantization and data packaging on delay is analyzed, and different quantization methods of different data formats from 32 bits to 8 bits are compared; different quantization strategies are selected for different network layers; an advanced synthesis tool HLS of the Xilinx FPGA is selected; each Xilinx DSP48E1 is decomposed into two 8 * 8 multiplying units, so that computing resources are maximized. According to the method, an optimal mixing precision quantification strategy is obtained through theoretical analysis and experiments, and knowledge distillation is decided to be used for keeping precision, so that the use of hardware resources is remarkably reduced.

Description

Technical Field

[0001] The present invention belongs to the field of artificial intelligence technology, and in particular relates to a method and system for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix. Background Art

[0002] Advances in deep learning have driven rapid progress in various interdisciplinary fields, including fault diagnosis, and this progress has not only pushed up the stock prices of GPU manufacturers, but also triggered new discussions. Despite their many advantages, GPUs are not widely used due to their high cost and power consumption, making them unsuitable in most practical industrial environments. Therefore, in order to seek more effective deployment solutions, many researchers have been looking for alternatives in recent months.

[0003] It is widely acknowledged that a more efficient and low-power accelerator is urgently needed. However, identifying the hardware that can achieve this goal remains a key issue. Some companies have started the chip manufacturing process directly (such as Google's TPU, Amazon's Inferentia, and Microsoft's newly released Maia), but challenges such as long chip manufacturing cycles and difficulty keeping up with rapidly evolving model environments (such as Maia's limited memory bandwidth) pose a huge obstacle. Between general-purpose processors (CPU / GPU) and dedicated accelerators (ASICs), there is another hardware option: field-programmable gate arrays (FPGAs). FPGAs achieve a better balance between programmability and performance than general-purpose processors. However, supporting unprecedented scale with FPGAs brings huge challenges, especially in terms of computing and memory resources. At the same time, it is also crucial to design hardware accelerators that can achieve low latency and high energy efficiency, and it is crucial to identify suitable application scenarios for FPGAs. In order to fully realize the potential of FPGAs, their reconfigurability must be considered. Previous studies have attempted to build instruction set architectures (or overlays) on FPGAs, but in fact, this approach abuses FPGAs. Once a particular instruction set is implemented as a dedicated circuit, it is often more efficient to convert it to an ASIC than to use an FPGA, which makes the FPGA a mere experimental prototype and unable to fully utilize its reconfigurable features. Instruction set architectures such as those used in CPUs often have significant performance and energy overhead due to instruction decoding and multiple levels of memory access. Eliminating these additional overheads can greatly improve hardware efficiency. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a method and system for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix.

[0005] The present invention is implemented in this way: a method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix, the method specifically comprising:

[0006] S1: GHOSTNETV2 is used as the backbone network. The first main convolutional layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into subsequent layers for further feature extraction. This layer is optimized separately;

[0007] S2: Analyzed the impact of quantization and data packing on latency, and compared different quantization methods for different data formats from 32-bit to 8-bit; selected different quantization strategies for different network layers, including data format selection and quantization configuration;

[0008] S3: To achieve FPGA deployment at the edge, we selected the high-level synthesis tool HLS of Xilinx FPGA. We decomposed each Xilinx DSP48E1 into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share an input channel, encapsulating two INT8 operations in one DSP48E.

[0009] Furthermore, the optimization of this layer alone specifically includes:

[0010] The Winograd-based CNN accelerator is used to reduce the computational load of the convolutional layer. The challenge of applying the Winograd algorithm to DNNs is to maintain the sparsity obtained by pruning the convolutional layers in the spatial domain. The avgpool is replaced by maxpool to improve the feature extraction efficiency, thereby maximally preserving texture features and reducing the impact of the shift module on accuracy.

[0011] The Winograd algorithm specifically includes:

[0012] Use k to represent the size of the FIR filter, and calculate the result of n outputs, recorded as G = (n, k); the traditional algorithm requires 2*3 = 6 multiplications when G = (2, 3); now, only 4 multiplications are needed; the number of multiplications required by the Winograd algorithm is equal to the input size. The above one-dimensional algorithm can be further nested to form a two-dimensional minimum algorithm G (n × n, k × k). The Winograd algorithm for two-dimensional convolution is expressed as follows:

[0013]

[0014] Furthermore, the impact of the quantization and data packaging on delay specifically includes:

[0015] Weight quantization is critical for FPGA deployment; on the one hand, it reduces the consumption of BRAM resources; on the other hand, it relieves the bandwidth pressure of off-chip DRAM access; however, since the fully unfolded dataflow architecture basically eliminates the need to store intermediate activation values, activation quantization has a negligible impact on memory usage; data packing is critical to reducing the number of BRAM ports and lowering resource consumption, which also helps with the layout and routing of back-end circuits.

[0016] Furthermore, the comparison of different quantization methods for different data formats from 32 bits to 8 bits specifically includes:

[0017] Assuming that the convolution calculation formula is as follows, the above quantization strategy is theoretically analyzed: ⊕ represents the convolution operation, En represents the input feature map of the n-th layer of convolution, En+1 represents the output feature map of the n-th layer of convolution, Wn represents the convolution kernel weight of the n-th layer of convolution, and Fn represents the bias of the n-th layer of convolution;

[0018]

[0019] According to the integer quantization method used, the corresponding quantization factor is S; in order to combine the bias and INT8 convolution without loss of generality, the convolution calculation is replaced by the following calculation process:

[0020]

[0021] S x =2 x

[0022] Replace the above quantization factors with exponential operations:

[0023]

[0024] In hardware logic, the exponential operation of 2 can be further simplified to a shift operation:

[0025]

[0026] Further, the S3 specifically includes:

[0027] (1) A system-on-chip (SoC) architecture consisting of programmable logic (PL) and processing system (PS) is used to design a hardware accelerator based on a dataflow architecture. First, processing functions are extracted from the main operations, including pwconv (point-by-point convolution), dwconv (depthwise convolution), maxpooling, FPGA-shift, and memory loading. Different computing units of different operators are connected in a pipeline dataflow architecture using blocking and non-blocking FIFOs. All processing functions run in parallel, and functions are triggered when data arrives to ensure that task-level parallelism is maximized.

[0028] (2) When accelerating neural networks, the PL-side accelerator can control the reasoning and training of the neural network; the processor core can handle the formatting and preprocessing of feature maps and weight data; all feature maps and weights are stored in off-chip memory, waiting to be retrieved; the bottleneck of accelerator computing is often not the insufficient number of computing units or their insufficient speed, but the memory bandwidth - that is, the insufficient data reading and writing speed, resulting in the computing unit being unable to obtain enough data; naturally, the most efficient computing method is to make full use of the on-chip high-speed memory to ensure that the computing unit never has to wait for data and minimize the read and write operations of the external DDR, thereby reducing power consumption;

[0029] (3) An AXI cross matrix and a core-to-core cross matrix module are proposed to achieve high-speed communication between processor cores; the cross network of the AXI bus connects the cores to the on-chip peripherals, realizes data transmission between multiple master and slave devices, and facilitates arbitration of 16 read and write requests on the AXI bus; this reduces a lot of time to access memory from off-chip DRAM; in FPGA, there is no need for instruction decoding and data selection; in work, the cross matrix uses on-chip memory to cache the image data of the first h-1 rows (where h is the operand height); when the data of the hth row arrives, it can directly read the data stored in the previous rows from the on-chip memory without getting all the data from the external DDR, thus achieving the highest real-time performance (for 16 layers of 3x3 convolution, the delay is 32 rows, i.e. 1 / 16fps); this ensures that any size of convolution can be calculated after reading the image data only once; in addition, the DDR is divided into four different memory areas and treated as FIFO transmission to reduce memory access time;

[0030] (4) A balanced resource allocation strategy is adopted to effectively utilize different precisions by using LUTs, DSPs, and on-chip memory and to maximize resource utilization. The design is optimized specifically for the Xilinx platform because the DSP48E DSP core on the Xilinx platform can only perform one 16-bit multiplication per cycle, which is half the DSP capability on the Arria 10 and Stratix 5 platforms. Only 8-bit precision data is used to reflect the characteristics of the Xilinx platform, and two sets of INT8 multiplication calculations with the same coefficients are spatially arranged and combined to perform multiplication and accumulation operations, thereby achieving a 1.75x performance improvement using a single DSP. Using this approach, the Xilinx DSP can perform two multiplications per cycle, and considering the precision difference, the two DSPs can be considered equivalent, thereby maintaining the meaningfulness of the measurement. In addition, the frames per second (fps) value of each DSP can be increased by increasing the clock speed.

[0031] Another object of the present invention is to provide an FPGA fault diagnosis accelerator design system based on a shift module and an AXI cross matrix for implementing the FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix, the system comprising:

[0032] Network structure design module: GHOSTNETV2 is used as the backbone network. The first main convolution layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into the subsequent layers for further feature extraction. This layer is optimized separately;

[0033] Quantization analysis module: Analyzes the impact of quantization and data packing on latency, compares different quantization methods for different data formats from 32 bits to 8 bits; selects different quantization strategies for different network layers, including data format selection and quantization configuration;

[0034] Hardware design module: In order to realize the deployment of FPGA at the edge, the high-level synthesis tool HLS of Xilinx FPGA was selected; each Xilinx DSP48E1 was decomposed into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share an input channel, encapsulating two INT8 operations in one DSP48E.

[0035] Another object of the present invention is to provide a computer device, which includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix.

[0036] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to execute the steps of the FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix.

[0037] Another object of the present invention is to provide an information data processing terminal, which is used to implement the FPGA fault diagnosis accelerator design system based on the shift module and the AXI cross matrix.

[0038] In combination with the above technical solutions and the technical problems solved, please analyze the advantages and positive effects of the technical solutions to be protected by the present invention from the following aspects:

[0039] In combination with the above technical solutions and the technical problems solved, the advantages and positive effects of the technical solutions to be protected by the present invention are as follows:

[0040] First, the present invention proposes an FPGA-based fault diagnosis edge AI accelerator to achieve effective classification of fault signal time-frequency diagrams. In order to realize efficient parallel processing of DNN models in FPGA applications, the present invention obtains the optimal mixed precision quantization strategy through theoretical analysis and experiments, and decides to use knowledge distillation to maintain accuracy, thereby significantly reducing the use of hardware resources. By inserting displacement modules and Winograd algorithms, redundant connections are reduced, the network model is made more unified, and a hardware-friendly network is constructed. Finally, the present invention innovatively proposes a multi-channel parallel processing method and an AXI cross-computing matrix acceleration architecture to maximize throughput and DDR (dynamic random access memory) bandwidth utilization.

[0041] The present invention also uses double buffering, Ifmap multiplexing and weight repetition to accelerate convolution and depthwise separable convolution. Actual test results show that the network model designed by the present invention has the best performance and lower energy consumption on the accelerator.

[0042] Second, with the widespread application of deep learning in the field of fault diagnosis, the requirements for computing performance are increasing. Traditional computing platforms such as CPUs and GPUs face problems such as limited resources and high power consumption when processing large-scale neural networks. FPGA (field programmable gate array) has become a powerful tool for accelerating deep learning models due to its high degree of parallelization, low power consumption and programmability. However, FPGA accelerator design still faces many challenges in resource optimization, delay control and quantization strategy. The present invention proposes a FPGA fault diagnosis accelerator design method based on shift module and AXI cross matrix, which aims to solve these technical problems.

[0043] The present invention uses GHOSTNETV2 as the backbone network, especially optimizes the first main convolution layer, and uses the Winograd algorithm to reduce the computational load of the convolution layer. Through theoretical analysis and experimental verification, different quantization methods from 32 bits to 8 bits are selected, and different quantization strategies are implemented for different network layers, including data format selection and quantization configuration. This optimization not only reduces the consumption of BRAM resources, but also alleviates the bandwidth pressure of off-chip DRAM access. At the same time, the AXI cross matrix is ​​used to achieve efficient data transmission, further improving the overall performance.

[0044] In terms of quantization strategy, the present invention adopts integer quantization method to simplify the multiplication operation in convolution calculation into shift operation, which greatly reduces the computational complexity. By comparing the quantization effects under different data formats, the optimal quantization scheme is selected to balance the computational accuracy and resource consumption. In addition, the present invention also analyzes in detail the impact of data packaging on delay, reduces the number of BRAM ports and resource consumption through a reasonable data packaging strategy, and optimizes the layout and wiring of the back-end circuit.

[0045] The present invention significantly improves the performance of FPGA in fault diagnosis accelerator by comprehensively applying Winograd algorithm, quantization optimization and AXI cross matrix technology. On the one hand, computing resources are efficiently utilized and power consumption is greatly reduced; on the other hand, delay is effectively controlled, which improves the real-time performance of fault diagnosis. In addition, the method of the present invention has strong versatility and scalability, and is applicable to a variety of deep learning models and fault diagnosis scenarios. In general, the present invention has achieved significant technical progress and application results while solving the problems of the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a flow chart of a method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix provided by an embodiment of the present invention;

[0047] Figure 2 is a network structure diagram provided by an embodiment of the present invention;

[0048] Figure 3 It is a Winograd two-dimensional convolution calculation method provided by an embodiment of the present invention;

[0049] Figure 4 Different quantization strategies for different networks provided by the embodiments of the present invention;

[0050] Figure 5 is the precision of different bit widths provided by the embodiments of the present invention: (a) the number of bits of each effective weight in all fully connected layers, (b) the number of bits of each effective weight in all convolutional layers;

[0051] Figure 6The model training and validation curves provided by the embodiment of the present invention are: (a) training and validation accuracy curves, (b) training and validation loss curves;

[0052] Figure 7 It is a visual analysis of the test results and features provided by the embodiments of the present invention;

[0053] Figure 8 It is the overall hardware architecture provided by the embodiment of the present invention;

[0054] Fig. 9 is an AXI cross matrix provided by an embodiment of the present invention;

[0055] Fig.10 It is a DSP package provided by an embodiment of the present invention;

[0056] Fig.11 Different quantization strategies for different networks provided by the embodiments of the present invention;

[0057] Fig.12 It is the data stream provided by the embodiment of the present invention (version or iteration is II). DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0059] like Figure 1 As shown, an embodiment of the present invention provides a method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix, and the method specifically includes:

[0060] S1: GHOSTNETV2 is used as the backbone network. The first main convolutional layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into subsequent layers for further feature extraction. This layer is optimized separately;

[0061] S2: Analyzed the impact of quantization and data packing on latency, and compared different quantization methods for different data formats from 32-bit to 8-bit; selected different quantization strategies for different network layers, including data format selection and quantization configuration;

[0062] S3: To achieve FPGA deployment at the edge, we selected the high-level synthesis tool HLS of Xilinx FPGA. We decomposed each Xilinx DSP48E1 into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share an input channel, encapsulating two INT8 operations in one DSP48E.

[0063] Furthermore, the optimization of this layer alone specifically includes:

[0064] The challenge of applying the Winograd algorithm to DNNs is to maintain the sparsity obtained by pruning the convolutional layers in the spatial domain. The avgpool is replaced by maxpool to improve the feature extraction efficiency, thereby maximally preserving texture features and reducing the impact of the shift module on accuracy. Figure 2 The overall structure of the network is shown.

[0065] The Winograd algorithm specifically includes: using k to represent the size of the FIR filter, and calculating the result of n outputs, recorded as G = (n, k); the traditional algorithm requires 2*3 = 6 multiplications when G = (2, 3); but now, only 4 multiplications are needed; the number of multiplications required by the Winograd algorithm is equal to the input size. The above one-dimensional algorithm can be further nested to form a two-dimensional minimum algorithm G (n × n, k × k), Figure 3 and two The Winograd algorithm for dimensional convolution is expressed as follows:

[0066]

[0067] Furthermore, the impact of the quantization and data packaging on delay specifically includes:

[0068] Weight quantization is critical for FPGA deployment; on the one hand, it reduces the consumption of BRAM resources; on the other hand, it relieves the bandwidth pressure of off-chip DRAM access; however, since the fully unfolded dataflow architecture basically eliminates the need to store intermediate activation values, activation quantization has a negligible impact on memory usage; data packing is critical to reducing the number of BRAM ports and lowering resource consumption, which also helps with the layout and routing of back-end circuits. Figure 4 These are different quantization strategies for different networks provided by the embodiments of the present invention.

[0069] Furthermore, the comparison of different quantization methods for different data formats from 32 bits to 8 bits specifically includes:

[0070] Assuming that the convolution calculation formula is as follows, the above quantization strategy is theoretically analyzed: ⊕ represents the convolution operation, En represents the input feature map of the n-th layer of convolution, En+1 represents the output feature map of the n-th layer of convolution, Wn represents the convolution kernel weight of the n-th layer of convolution, and Fn represents the bias of the n-th layer of convolution;

[0071]

[0072] According to the integer quantization method used, the corresponding quantization factor is S; in order to combine the bias and INT8 convolution without loss of generality, the convolution calculation is replaced by the following calculation process:

[0073]

[0074] S x =2 x

[0075] Replace the above quantization factors with exponential operations:

[0076]

[0077] In hardware logic, the exponential operation of 2 can be further simplified to a shift operation:

[0078]

[0079] Figure 5 is the precision of different bit widths provided by the embodiments of the present invention: (a) the number of bits of each effective weight in all fully connected layers, (b) the number of bits of each effective weight in all convolutional layers;

[0080] Shows how the accuracy of convolutional layers (right) and fully connected layers (left) decreases as the number of bits in each connection decreases, and the impact of knowledge distillation. Each chart reports the top-1 and top-5 accuracy. Figure 6 It shows that the test accuracy of the optimized and fine-tuned network can reach 99%.

[0081] After testing, it was found that the original samples were distributed chaotically and irregularly. After model training, the following Figure 7 The samples within a class are clustered and the samples between classes are separated.

[0082] Further, the S3 specifically includes:

[0083] (1) A system-on-chip (SoC) architecture consisting of programmable logic (PL) and processing system (PS) is used to design a hardware accelerator based on a dataflow architecture. First, processing functions are extracted from the main operations, including pwconv (point-by-point convolution), dwconv (depthwise convolution), maxpooling, FPGA-shift, and memory loading. Different computing units of different operators are connected in a pipeline dataflow architecture using blocking and non-blocking FIFOs. All processing functions run in parallel, and functions are triggered when data arrives to ensure that task-level parallelism is maximized. Figure 8 It is the overall hardware architecture provided by the embodiment of the present invention;

[0084] (2) When accelerating neural networks, the PL-side accelerator can control the reasoning and training of the neural network; the processor core can handle the formatting and preprocessing of feature maps and weight data; all feature maps and weights are stored in off-chip memory, waiting to be retrieved; the bottleneck of accelerator computing is often not the insufficient number of computing units or their insufficient speed, but the memory bandwidth - that is, the insufficient data reading and writing speed, resulting in the computing unit being unable to obtain enough data; naturally, the most efficient computing method is to make full use of the on-chip high-speed memory to ensure that the computing unit never has to wait for data and minimize the read and write operations of the external DDR, thereby reducing power consumption;

[0085] (3) An AXI cross matrix and a core-to-core cross matrix module are proposed to achieve high-speed communication between processor cores; the cross network of the AXI bus connects the cores to the on-chip peripherals, realizes data transmission between multiple master and slave devices, and facilitates arbitration of 16 read and write requests on the AXI bus; this reduces a lot of time to access memory from off-chip DRAM; in FPGA, there is no need for instruction decoding and data selection; in work, the cross matrix uses on-chip memory to cache the image data of the first h-1 rows (where h is the operand height); when the data of the hth row arrives, it can directly read the data stored in the previous rows from the on-chip memory without getting all the data from the external DDR, thus achieving the highest real-time performance (for 16 layers of 3x3 convolution, the delay is 32 rows, i.e. 1 / 16fps); this ensures that any size of convolution can be calculated after reading the image data only once; in addition, the DDR is divided into four different memory areas and treated as FIFO transmission to reduce memory access time; Fig. 9 is an AXI cross matrix provided by an embodiment of the present invention;

[0086] (4) A balanced resource allocation strategy is adopted to effectively utilize different precisions by using LUTs, DSPs, and on-chip memory and to maximize resource utilization. The design is optimized specifically for the Xilinx platform because the DSP48E DSP core on the Xilinx platform can only perform one 16-bit multiplication per cycle, which is half the DSP capability on the Arria 10 and Stratix 5 platforms. Only 8-bit precision data is used to reflect the characteristics of the Xilinx platform, and two sets of INT8 multiplication calculations with the same coefficients are spatially arranged and combined to perform multiplication and accumulation operations, thereby achieving a 1.75x performance improvement using a single DSP. Using this approach, the Xilinx DSP can perform two multiplications per cycle, and considering the precision difference, the two DSPs can be considered equivalent, thereby maintaining the meaningfulness of the measurement. In addition, the frames per second (fps) value of each DSP can be increased by increasing the clock speed.

[0087] Increasing the number of DSPs by 25% only increases the throughput by 9%. Therefore, in order to make full use of the limited resources and area of ​​FPGA, this paper decomposes each Xilinx DSP48E1 into two 8×8 multipliers to maximize the computing resources. Fig.10 However, due to the device characteristics, the two decomposed multipliers need to share one input channel and encapsulate two INT8 operations in one DSP48E. The resource consumption after processing is shown in Fig.11 shown.

[0088] The embodiment of the present invention provides an FPGA fault diagnosis accelerator design system based on a shift module and an AXI cross matrix for implementing the FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix, the system comprising:

[0089] Network structure design module: GHOSTNETV2 is used as the backbone network. The first main convolution layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into the subsequent layers for further feature extraction. This layer is optimized separately;

[0090] Quantization analysis module: Analyzes the impact of quantization and data packing on latency, compares different quantization methods for different data formats from 32 bits to 8 bits; selects different quantization strategies for different network layers, including data format selection and quantization configuration;

[0091] Hardware design module: In order to realize the deployment of FPGA at the edge, the high-level synthesis tool HLS of Xilinx FPGA was selected; each Xilinx DSP48E1 was decomposed into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share an input channel, encapsulating two INT8 operations in one DSP48E.

[0092] An embodiment of the present invention provides a computer device, which includes a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the processor executes the steps of the FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix.

[0093] An embodiment of the present invention provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the steps of the method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix.

[0094] An embodiment of the present invention provides an information data processing terminal, which is used to implement the FPGA fault diagnosis accelerator design system based on the shift module and the AXI cross matrix.

[0095] To maximize the performance of the custom hardware and ensure that each computation can be completed efficiently within one hardware cycle via integer multiplication and addition, we calculated (1) the computational power requirement:

[0096] ∑M i C <M tot , i∈{w,c 1 , c 2 ,f}

[0097] Among them, (w): Winograd layer; (c1, c2): Matmul1, Matmul2; (f): fully connected layer (fc layer).

[0098] The upper limit of computing power is the maximum computing power that the hardware can provide, that is, the number of DSPs on the FPGA, where (C) is the number of convolutional layers deployed on one FPGA, and (M_{tot}) is the total number of equivalent DSPs on the FPGA.

[0099] (2) Memory capacity limitation: The total storage capacity required for all parameters must not exceed the total DRAM and BRAM capacity of the FPGA. We store the parameters on DRAM, and the number of all parameters needs to be smaller than the DRAM capacity:

[0100] S param C <DRAMtot

[0101] The on-chip memory mainly stores the intermediate activation value parameters after sharding, caching and FIFO, which can be obtained:

[0102] ∑S i C <SRAM tot ,i∈{title,FIFO,cache}

[0103] (3) Memory port limitation: Since different computing units need to read data at the same time, in order to avoid memory access conflicts, we need to allocate the corresponding data to different ports. Assuming that the number of parameters of the linear layer (i) is (si), and there are (Mi) MAC computing units executing in parallel, where (ri) computing units share the same load parameters, the weight cache needs to be divided into (M_i / ri) slices. If the weight cache is stored on the slices and each element has a (bw) bit width, then the number of elements obtained from each slice is (si / (Mi / ri)).

[0104] In addition, since (bw) cannot occupy all the bit widths of BRAM, we introduce (b_{BRAM}) as the minimum legal BRAM bit width greater than (bw), and (S_{BRAM}) is the total capacity of a memory unit (we use a 36kb AMD FPGA and obtain the result by packing (k) data). The new memory requirement is:

[0105]

[0106] (4) Memory bandwidth limitation: Since (M_i / r_i) parameters need to be loaded from DRAM in each cycle to supply (Mi) computing units, the required bandwidth is (where freq is the frequency of the FPGA):

[0107] B i =b W ×M i / r i ×freq

[0108] The final designed accelerator has been experimentally verified and compared with other accelerators, and it can be found that our core parameters all perform well. Under the same resource usage, the implemented data flow is very efficient, and most operations can be overlapped. Fig.12 As shown in Figure 1, we do not need to wait for the result of the previous operation to be fully output before proceeding to the next operation, nor do we need to write it back to memory. The only thing that needs to wait is the Winograd layer and the subsequent DFC module.

[0109] Power consumption and efficiency are key characteristics, as FPGA systems are usually power-constrained and heat-dissipating. Data related to power consumption and throughput are obtained after FPGA synthesis results, while throughput information is calculated by multiplying the clock frequency by the number of operations to be counted in one clock cycle. Since FPGAs have different form factors, different training accelerators will certainly show different performance. For comparison, the evaluation metric is energy efficiency (GOPS / W). In this case, performance refers to throughput, measured in the number of images classified per second (FPS). We also compare the throughput (GOPS) of different accelerators.

[0110] It can be seen that the parameters such as GOPS / W, GOPS, FPS in the present invention are currently quite excellent, and all of the above parameters meet the requirements.

[0111] It should be noted that the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware. The hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. It can be understood by a person of ordinary skill in the art that the above-mentioned devices and methods can be implemented using computer executable instructions and / or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium. The device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.

[0112] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix, characterized in that: The method specifically includes: S1: GHOSTNETV2 is used as the backbone network. The first main convolutional layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into subsequent layers for further feature extraction. This layer is optimized separately; S2: Analyzed the impact of quantization and data packing on latency, and compared different quantization methods for different data formats from 32-bit to 8-bit; selected different quantization strategies for different network layers, including data format selection and quantization configuration; S3: To achieve FPGA deployment at the edge, we selected the high-level synthesis tool HLS of Xilinx FPGA. We decomposed each Xilinx DSP48E1 into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share one input channel, encapsulating two INT8 operations in one DSP48E.

2. The FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix as claimed in claim 1, characterized in that: The optimization of this layer alone specifically includes: The Winograd-based CNN accelerator is used to reduce the computational load of the convolutional layer. The challenge of applying the Winograd algorithm to DNNs is to maintain the sparsity obtained by pruning the convolutional layers in the spatial domain. The avgpool is replaced by maxpool to improve the feature extraction efficiency, thereby maximally preserving texture features and reducing the impact of the shift module on accuracy. The Winograd algorithm specifically includes: Use k to represent the size of the FIR filter, and calculate the result of n outputs, recorded as G = (n, k); the traditional algorithm requires 2*3 = 6 multiplications when G = (2, 3); now, only 4 multiplications are needed; the number of multiplications required by the Winograd algorithm is equal to the input size. The above one-dimensional algorithm can be further nested to form a two-dimensional minimum algorithm G (n × n, k × k). The Winograd algorithm for two-dimensional convolution is expressed as follows:

3. The FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix as claimed in claim 1, characterized in that: The impact of quantization and data packaging on latency specifically includes: Weight quantization is critical for FPGA deployment; on the one hand, it reduces the consumption of BRAM resources; on the other hand, it relieves the bandwidth pressure of off-chip DRAM access; however, since the fully unfolded dataflow architecture basically eliminates the need to store intermediate activation values, activation quantization has a negligible impact on memory usage; data packing is critical to reducing the number of BRAM ports and lowering resource consumption, which also helps with the layout and routing of back-end circuits.

4. The FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix as claimed in claim 1, characterized in that: The comparison of different quantization methods for different data formats from 32 bits to 8 bits includes: Assuming the convolution calculation formula is as follows, the above quantization strategy is theoretically analyzed: Represents the convolution operation, En represents the input feature map of the n-th layer of convolution, En+1 represents the output feature map of the n-th layer of convolution, Wn represents the convolution kernel weight of the n-th layer of convolution, and Fn represents the bias of the n-th layer of convolution; According to the integer quantization method used, the corresponding quantization factor is S; in order to combine the bias and INT8 convolution without loss of generality, the convolution calculation is replaced by the following calculation process: S x ＝2 x Replace the above quantization factors with exponential operations: In hardware logic, the exponential operation of 2 can be further simplified to a shift operation:

5. The FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix as claimed in claim 1, characterized in that: The S3 specifically includes: A system-on-chip (SoC) architecture including programmable logic (PL) and processing system (PS) is adopted to design a hardware accelerator, which is based on a dataflow architecture. The processing functions are extracted from the main operations, and different computing units of different operators are connected into a pipelined dataflow architecture by using blocking and non-blocking FIFOs. High-speed communication between processor cores is achieved through AXI crossbar matrix and core-to-core crossbar matrix modules. A balanced resource allocation strategy is used to effectively utilize different precisions through LUT, DSP and on-chip memory while maximizing resource utilization.

6. The FPGA fault diagnosis accelerator design method based on the shift module and the AXI cross matrix as claimed in claim 5, characterized in that: The PL-side accelerator can control the reasoning and training of the neural network, and the processor core handles the formatting and preprocessing of feature maps and weight data. It is proposed to use the cross-network of the AXI bus to realize data transmission between multiple master and slave devices, facilitate arbitration of multiple read and write requests on the AXI bus, and reduce the time to access memory from off-chip DRAM. By dividing DDR into multiple different memory areas and treating them as FIFO transmissions, the memory access time can be further reduced and the real-time performance of the accelerator can be improved.

7. An FPGA fault diagnosis accelerator design system based on a shift module and an AXI cross matrix that implements the FPGA fault diagnosis accelerator design method based on a shift module and an AXI cross matrix as described in any one of claims 1 to 6, characterized in that: The system includes: Network structure design module: GHOSTNETV2 is used as the backbone network. The first main convolution layer of the network performs a standard 3x3 two-dimensional convolution operation on the input content to extract features, and then inputs these features into the subsequent layers for further feature extraction. This layer is optimized separately; Quantization analysis module: Analyzes the impact of quantization and data packing on latency, compares different quantization methods for different data formats from 32 bits to 8 bits; selects different quantization strategies for different network layers, including data format selection and quantization configuration; Hardware design module: In order to realize the deployment of FPGA at the edge, the high-level synthesis tool HLS of Xilinx FPGA was selected; each Xilinx DSP48E1 was decomposed into two 8×8 multipliers to maximize computing resources. However, due to the characteristics of the device, the two decomposed multipliers need to share an input channel, encapsulating two INT8 operations in one DSP48E.

8. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the FPGA fault diagnosis accelerator design method based on the shift module and AXI cross matrix as described in any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the method for designing an FPGA fault diagnosis accelerator based on a shift module and an AXI cross matrix as described in any one of claims 1 to 6.

10. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the FPGA fault diagnosis accelerator design system based on the shift module and AXI cross matrix as described in claim 7.

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