Pixel control circuit and method and display panel

Abstract

The invention belongs to the technical field of display panels, and provides a pixel control circuit and method and a display panel, the display panel comprises a plurality of pixel units, each pixel unit comprises a first sub-pixel unit and a second sub-pixel unit, and the pixel control circuit comprises a first control module, a second control module and a third control module. The third control module is used for connecting the corresponding second sub-pixel unit into the circuit in a specified state, so that the second sub-pixel unit is controlled by a line scanning signal and / or a data signal to be in an activated state; wherein the specified state comprises at least one of the fault of the first sub-pixel unit and the sawtooth phenomenon of the display picture. The second sub-pixel unit can be connected when the first sub-pixel unit breaks down, and the phenomenon of cross bright lines is eliminated. In addition, when a sawtooth phenomenon occurs in a display picture, smooth transition can be carried out on the sawtooth state by accessing the second sub-pixel units, and the sawtooth phenomenon is weakened.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in particular, relates to a pixel control circuit, method and display panel. Background Art

[0002] Sub-millimeter light emitting diode (Miniature Light Emitting Diode, Mini LED) backlight uses MiniLED as the backlight source of liquid crystal display (Liquid Crystal Display, LCD) panel, which has the advantages of ultra-high contrast, high color gamut, and high dynamic range (High-Dynamic Range, HDR), thereby greatly improving the display effect. Compared with traditional backlight, Mini LED backlight can achieve better brightness uniformity within a smaller mixing distance, and because of the local dimming design, it has more refined HDR partitions and greatly improves the contrast of LCD display. However, due to the characteristics of Mini LED, when the Mini LED lamp bead has an open circuit problem, a cross bright line phenomenon will appear, affecting the product display effect. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a pixel control circuit, method and display panel to solve the problem that when the MiniLED lamp bead has an open circuit problem, a cross bright line phenomenon will appear, which affects the display effect of the product.

[0004] A first aspect of an embodiment of the present application provides a pixel control circuit of a display panel, wherein the display panel includes a plurality of pixel units, the pixel units are arranged in an array in the form of n rows and m columns, the pixel units include a first sub-pixel unit and a second sub-pixel unit, and the pixel control circuit includes a first control module, a second control module, a third control module, n row signal lines, and m column signal lines;

[0005] The first control module is connected to the row signal line, the second control module is connected to the column signal line, and the pixel units in the i-th row and j-th column are respectively connected to the i-th row signal line and the j-th column signal line;

[0006] The first control module is used to output a row scanning signal to the row signal line;

[0007] The second control module is used to output a data signal to the column signal line;

[0008] The first sub-pixel unit is used to be controlled by the row scanning signal and / or the data signal to be in an activated or inactivated state;

[0009] The third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal to be in an activated state;

[0010] The specified state includes at least one of a first sub-pixel unit failure and a aliasing phenomenon on a display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m].

[0011] A second aspect of an embodiment of the present application provides a pixel control method, which is applied to a pixel control circuit of a display panel provided in the first aspect of an embodiment of the present application, comprising:

[0012] Determine the working status of the display panel;

[0013] If the working state is a designated state, the corresponding second sub-pixel unit is connected to the circuit, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal and is in an activated state.

[0014] The third aspect of the embodiments of the present application provides a display panel, including the pixel control circuit of the display panel provided by the first aspect of the embodiments of the present application, the pixel control circuit including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the pixel control method provided by the second aspect of the embodiments of the present application when executing the computer program.

[0015] A first aspect of an embodiment of the present application provides a pixel control circuit of a display panel, wherein the display panel includes a plurality of pixel units, the pixel units are arranged in an array in the form of n rows and m columns, the pixel units include a first sub-pixel unit and a second sub-pixel unit, and the pixel control circuit includes a first control module, a second control module, a third control module, n row signal lines and m column signal lines; the first control module is connected to the row signal line, the second control module is connected to the column signal line, the pixel units in the i-th row and j-th column are respectively connected to the i-th row signal line and the j-th column signal line; the first control module is used to control the row signal line to the first row signal line and the second sub-pixel unit to the second sub-pixel unit; The signal line outputs a row scan signal; the second control module is used to output a data signal to the column signal line; the first sub-pixel unit is used to be controlled by the row scan signal and / or the data signal to be in an activated or inactivated state; the third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by the row scan signal and / or the data signal to be in an activated state; wherein the specified state includes at least one of a failure of the first sub-pixel unit and a jagged phenomenon on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m]. The present application can connect the second sub-pixel unit when the first sub-pixel unit fails, eliminating the cross bright line phenomenon. In addition, when a jagged phenomenon appears on the display screen, connecting the second sub-pixel unit can also make a smooth transition of the jagged state and reduce the jagged phenomenon.

[0016] It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 is a structural schematic diagram of a pixel control circuit provided by an embodiment of the present application;

[0019] Figure 2 is a structural schematic diagram of a pixel control circuit provided by another embodiment of the present application;

[0020] Figure 3 is a structural schematic diagram of a pixel control circuit provided by another embodiment of the present application;

[0021] Figure 4is a structural schematic diagram of a pixel control circuit provided by another embodiment of the present application;

[0022] Figure 5 is a schematic diagram of pixel unit distribution of a pixel control circuit provided in an embodiment of the present application;

[0023] Figure 6 This is a flowchart of a pixel control method provided by an embodiment of the present application;

[0024] Figure 7 is a flowchart of a pixel control method provided by another embodiment of the present application;

[0025] Figure 8 This is a schematic diagram of a sawtooth screen provided by an embodiment of the present application;

[0026] Fig. 9 is a structural schematic diagram of a pixel control circuit provided in an embodiment of the present application.

[0027] In the figure:

[0028] 1-pixel unit, 11-first sub-pixel unit, 12-second sub-pixel unit,

[0029] 2-pixel control circuit, 21-first control module, 22-second control module, 221-second feedback signal processing module, 23-third control module, 24-column signal line, 25-row signal line, 26-switch module, 27-first feedback signal processing module. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0034] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] Embodiment 1

[0037] The pixel control circuit of the display panel provided in the embodiment of the present application comprises a plurality of pixel units 1 through the display panel, the pixel units 1 are arranged in an array in the form of n rows and m columns, the pixel units 1 comprise a first sub-pixel unit 11 and a second sub-pixel unit 12, the pixel control circuit comprises a first control module 21, a second control module 22, a third control module 23, n row signal lines 25 and m column signal lines 24; the first control module 21 is connected to the row signal line 25, the second control module 22 is connected to the column signal line 24, the pixel unit 1 of the i-th row and the j-th column is respectively connected to the i-th row signal line 25 and the j-th column signal line 24; the first control module 21 is connected to the row signal line 25, the second control module 22 is connected to the column signal line 24, the pixel unit 1 of the i-th row and the j-th column is respectively connected to the i-th row signal line 25 and the j-th column signal line 24; 1 is used to output a row scan signal to the row signal line 25; the second control module 22 is used to output a data signal to the column signal line 24; the first sub-pixel unit 11 is used to be controlled by the row scan signal and / or the data signal to be in an activated or inactivated state; the third control module 23 is used to connect the corresponding second sub-pixel unit 12 to the circuit in a specified state, so that the second sub-pixel unit 12 is controlled by the row scan signal and / or the data signal to be in an activated state; wherein the specified state includes at least one of the failure of the first sub-pixel unit 11 and the appearance of a sawtooth phenomenon on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m]. The present application can connect the second sub-pixel unit 12 when the first sub-pixel unit 11 fails, eliminating the cross bright line phenomenon. In addition, when the sawtooth phenomenon appears on the display screen, connecting the second sub-pixel unit 12 can also make a smooth transition of the sawtooth state and reduce the sawtooth phenomenon.

[0038] In application, the pixels of the display panel are designed to have a special grid-like "island" structure. Pixel unit 1 is used in a multicolor display panel and is used to refer to any part of a pixel that can be independently addressed to emit a specific color. For example, a blue pixel unit 1 is a part of a pixel that can be addressed to emit blue light. In a full-color display, a pixel typically includes three primary color pixel units 1, i.e., blue, green and red. Optionally, pixel unit 1 refers to a single light-emitting element.

[0039] In application, the row scan signal is used to select a row of pixels on the display panel so that it can receive the data signal from the column signal line 24. When the row scan signal is activated, it turns on the switches of all pixels on a specific row, so that these pixels can receive the data voltage transmitted on the data line. When the row scan signal is at a low level, the corresponding pixel row is turned off and does not receive the data voltage. The row scan signal is activated row by row in a certain periodic order to ensure that each row of pixels has the opportunity to receive the data voltage. For example, if the display panel has 10 rows of pixels, the row scan signal will activate row 1, row 2, ..., row 10 in sequence, and then start the cycle from row 1 again.

[0040] In application, the data signal output by the column signal line 24 is used to control the brightness or color of each pixel. The data signal carries the brightness or color information that each pixel needs to display. When a pixel in a column is selected by a row scan signal, the data signal of the column will be loaded onto the pixel.

[0041] like Figure 1 and 2 As shown, the pixel control circuit of the display panel provided in the embodiment of the present application includes a first control module 21, a second control module 22, a third control module 23, n row signal lines 25 and m column signal lines 24; the first control module 21 is connected to the row signal line 25, the second control module 22 is connected to the column signal line 24, and the pixel unit 1 of the i-th row and j-th column is respectively connected to the i-th row signal line 25 and the j-th column signal line 24; the display panel includes a plurality of pixel units 1, the pixel units 1 are arranged in an array in the form of n rows and m columns, and the pixel unit 1 includes a first sub-pixel unit 11 and a second sub-pixel unit 12;

[0042] The first control module 21 is used to output a row scanning signal to the row signal line 25;

[0043] The second control module 22 is used to output a data signal to the column signal line 24;

[0044] The first sub-pixel unit 11 is used to be controlled by a row scanning signal and / or a data signal to be in an activated or inactivated state;

[0045] The third control module 23 is used to connect the corresponding second sub-pixel unit 12 to the circuit under a specified state, so that the second sub-pixel unit 12 is controlled by the row scanning signal and / or the data signal to be in an activated state;

[0046] The specified state includes at least one of a failure of the first sub-pixel unit 11 and a aliasing phenomenon on the display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m].

[0047] In application, the first control module 21 and the third control module 23 can be hardware modules for realizing the above functions, or virtual modules in a certain integrated circuit. The first control module 21 and the third control module 23 can be integrated in a scanning integrated circuit (Scanning Integrated Circuit, Scan IC), and the functions of the first control module 21 and the third control module 23 are directly realized by the scanning integrated circuit. Alternatively, the control circuits of the first control module 21 and the third control module 23 are routed on the left and right edges of the display panel, and at the same time, the control signal is generated by other ICs such as the timing controller integrated circuit (Timing Controller IC, Tcon IC) on the PCBA board, and is routed to the gate drive line (GDL) area in the plane through the bypass pin (by pass pin) of the driver IC (driver IC), and then the on-off of the switch module 26 is controlled. The present application does not limit the specific form of the first control module 21 and the third control module 23, as long as the hardware module or software module that can realize the above functions can be applied to the embodiments of the present application.

[0048] In application, the scheme of the embodiment of the present application is explained by taking 3 rows and 3 columns of pixel units 1 as an example. The first control module 21 scans the pixel units 1 in each row in the pixel array through the row signal line 25. Among them, the first row signal line 25 is connected to all the pixel units 1 in the first row, so as to output a row scanning signal to all the pixel units 1 in the first row. Similarly, the second row signal line 25 is connected to all the pixel units 1 in the second row, so as to output a row scanning signal to all the pixel units 1 in the second row. The third row signal line 25 is connected to all the pixel units 1 in the third row, so as to output a row scanning signal to all the pixel units 1 in the third row.

[0049] In application, a second sub-pixel unit 12 is disposed at each first sub-pixel unit 11, the cathodes of the first sub-pixel unit 11 and the second sub-pixel unit 12 are connected to the same column signal line 24, and the anode of the first sub-pixel unit 11 is connected to the row signal line 25 of the corresponding row, and the anode of the second sub-pixel unit 12 is connected to the same row signal line 25 as the first sub-pixel unit 11, or is connected to the third control module 23 through the switch module 26. The second sub-pixel unit 12 can be connected or disconnected by controlling the on and off of the switch module 26 by the third control module 23.

[0050] In the application, the failure of the first sub-pixel unit 11 includes the first sub-pixel unit 11 being open. Take the row scan start voltage of 5V and the shut-off voltage of 3V as an example for explanation. When the high level of the row scan signal comes, the data signal (data signal) adjusts the display grayscale by controlling the low pulse duty cycle, and the data signal is valid at a low level and is 0V. When the first sub-pixel unit 11 is turned on, the scan voltage of the row data line is transmitted to the column data line, so that the low level of the data signal is about 1V. If a first sub-pixel unit 11 is open, the low level of the data signal cannot be pulled up from 0V to about 1V through the open first sub-pixel unit 11, resulting in micro-conduction in the column where the open first sub-pixel unit 11 is located, resulting in a cross bright line phenomenon. When the first sub-pixel unit 11 is open, the access circuit of the second sub-pixel unit 12 set at the open first sub-pixel unit 11 is connected through the third control module 23, and the low level of the data signal can be pulled up from 0V to about 1V through the second sub-pixel unit 12, thereby avoiding the cross bright line phenomenon.

[0051] In one embodiment, Figure 3 As shown, it also includes a first feedback signal processing module 27;

[0052] The jth input terminal of the second control module 22 is connected to the jth column signal line 24, the jth output terminal of the second control module 22 is connected to the jth input terminal of the first feedback signal processing module 27, and the jth output terminal of the first feedback signal processing module 27 is connected to the jth input terminal of the third control module 23;

[0053] The first feedback signal processing module 27 is used to determine the state of the first sub-pixel unit 11 being in failure according to the voltage of the column signal line 24 obtained, and locate the column coordinates of the failed pixel unit 1, and send them to the third control module 23;

[0054] The third control module 23 is further used to connect the corresponding second sub-pixel unit 12 to the circuit according to the row and column coordinates of the faulty pixel unit 1 .

[0055] In application, a feedback circuit can be set in the second module to collect the feedback voltage of each column signal line 24 and transmit it to the first feedback signal processing module 27. The first feedback signal processing module 27 can be an independently set physical module, such as a hardware circuit, or a physical module or a virtual module set inside a physical module (such as a scanning integrated circuit). Each column signal line 24 has an independent number. Therefore, in addition to receiving the voltage value of the column signal line 24, the first feedback signal processing module 27 can also identify the correspondence between the column signal line 24 and the voltage value according to the number of the column signal line 24, so as to judge the relevant state of the column corresponding to the column signal line 24 according to the size of the voltage value. For example, the first sub-pixel unit 11 of the first row and the first column is open, and the first sub-pixel unit 11 of the first row and the second column is normal. At this time, the feedback voltage value of the first column signal line 24 is 0V, and the feedback voltage value of the second column signal line 24 is 1V. After receiving the voltage value data, the first feedback signal processing module 27 can determine that the column where the column signal line 24 corresponding to 0V is located is the first column, that is, the first sub-pixel unit 11 of the first column is open, and the first feedback signal processing module 27 sends the column coordinates of the open first sub-pixel unit 11 to the third control module 23. Since the current row scan signal is the first row, the coordinate position of the open first sub-pixel unit 11 is determined to be the first row and the second column. The third control module 23 turns on the switch module 26 of the first row and the first column according to the row and column coordinates of the open first sub-pixel unit 11. At this time, the second sub-pixel unit 12 of the same row and column is connected to the circuit, and can be displayed at a specified brightness under the action of the row scan signal and the data signal.

[0056] In one embodiment, a switch module 26 corresponding to each second sub-pixel unit 12 is further included;

[0057] The controlled end of the switch module 26 in the i-th row and j-th column is connected to the third control module 23, the input end is connected to the first control module 21, the output end is connected to one end of the second sub-pixel unit 12 in the i-th row and j-th column, one end of the first sub-pixel unit 11 in the i-th row and j-th column is connected to the i-th row signal line 25, and the other ends of the first sub-pixel unit 11 in the i-th row and j-th column and the second sub-pixel unit 12 in the i-th row and j-th column are connected to the j-th column signal line 24; the third control module 23 is also used to turn on the corresponding switch module 26 in a specified state so that the corresponding second sub-pixel unit 12 is connected to the circuit.

[0058] In application, the switch module 26 can be a switch tube, or a switch unit including a switch tube and other components. When the switch module 26 includes a switch tube, the controlled end of the switch tube is connected to the third control module 23, and the controlled end of the switch tube is controlled by the third control module 23, so that the on and off of the switch module 26 can be controlled by the third control module 23, thereby realizing the access of the second sub-pixel unit 12 when necessary. For example, the first sub-pixel unit 11 can be accessed when it is open, and it can also be accessed when the picture has a sawtooth phenomenon. The input end of the switch module 26 in the i-th row and the j-th column is connected to the first control module 21, and the connection can be a direct connection or an indirect connection.

[0059] In one embodiment, the input end of the switch module 26 in the i-th row and j-th column is connected to the first control module 21 through the i-th row signal line 25, or the input end of the switch module 26 in the i-th row and j-th column is directly connected to the first control module 21, and the first control module 21 is used to send a row scanning signal to the corresponding second sub-pixel unit 12 through the switch module 26 in the i-th row and j-th column.

[0060] In applications, such as Figure 1 As shown, the input end of the switch module 26 of the i-th row and j-th column is connected to the first control module 21 through the i-th row signal line 25. When the third control module 23 controls the switch module 26 to be turned on, the i-th row signal line 25 can output a row scanning signal to the first sub-pixel unit 11, and can also output a row scanning signal to the second sub-pixel unit 12. For example, when the first sub-pixel unit 11 of the 1st row and the 1st column is open, the third control module 23 controls the switch module 26 of the 1st row and the 1st column to be turned on, then when the first control module 21 outputs a row scanning signal to the 1st row signal line 25, the signal can act on the second sub-pixel unit 12, and since the second sub-pixel unit 12 can be used as a compensation for the first sub-pixel unit 11, the cross bright line problem can be solved.

[0061] In applications, such as Figure 2 As shown, the input end of the switch module 26 in the i-th row and j-th column is directly connected to the first control module 21, rather than being connected to the row signal line 25 of the corresponding row, so as to realize the time-sharing drive of the first sub-pixel unit 11 and the second sub-pixel unit 12, which is particularly suitable for the case where the sizes of the first sub-pixel unit 11 and the second sub-pixel unit 12 are different.

[0062] In one embodiment, the size of the second sub-pixel unit 12 is smaller than the first sub-pixel unit 11, and the first sub-pixel unit 11 and the second sub-pixel unit 12 are staggered;

[0063] The third control module 23 is also used for:

[0064] When the first sub-pixel unit 11 in the i-th row and the j-th column is in an activated state, sending a first data signal to the first sub-pixel unit 11 in the i-th row and the j-th column;

[0065] When the second sub-pixel unit 12 in the i-th row and the j-th column is in an activated state, sending a second data signal to the second sub-pixel unit 12 in the i-th row and the j-th column;

[0066] The duty cycle of the first data signal is greater than that of the second data signal.

[0067] In application, the size of the second sub-pixel unit 12 can be made smaller than the first sub-pixel unit 11 to eliminate the jagged phenomenon. For example, if the area of ​​the ordinary pixel unit 1 is 1, the area of ​​the first sub-pixel unit 11 can be made 2 / 3, the area of ​​the second sub-pixel unit 12 can be made 1 / 3, and the first sub-pixel unit 11 and the second sub-pixel unit 12 can be staggered. When a jagged picture appears, the second sub-pixel unit 12 can make a smooth transition of the jagged state of the entire picture to reduce the jagged phenomenon.

[0068] In application, since the size of the second sub-pixel unit 12 is smaller than the first sub-pixel unit 11, if the data signal inputs the same duty cycle to the first sub-pixel unit 11 and the second sub-pixel unit 12, the brightness of the second sub-pixel unit 12 will be lower than that of the first sub-pixel unit 11. Therefore, in order to make the brightness of the second sub-pixel unit 12 consistent with that of the first sub-pixel unit 11 when enabled, the duty cycle of the data signal output to the second sub-pixel unit 12 can be adjusted. For example: assuming that the duty cycle of the data signal of the first sub-pixel unit 11 is set to 40%, the duty cycle of the data signal of the second sub-pixel unit 12 can be set to 60%. This means that in a complete pulse cycle, the proportion of the time when the second sub-pixel unit 12 emits light is 60%, while the proportion of the time when the first sub-pixel unit 11 emits light is 40%. Since the input end of the switch module 26 is directly connected to the first control module 21, rather than connected to the row signal line 25 of the corresponding row, the time-sharing drive of the first sub-pixel unit 11 and the second sub-pixel unit 12 can be realized. When the row scan signal points to the first sub-pixel unit 11, the duty cycle of the data signal is set to 40%. Under this duty cycle, the first sub-pixel unit 11 will be in a high level state for 40% of the time in a complete cycle. When the row scan signal points to the second sub-pixel unit 12, the duty cycle of the data signal is set to 60%. Under this duty cycle, the second sub-pixel unit 12 will be in a high level state for 60% of the time in a complete cycle, so that even if the size of the second sub-pixel unit 12 is smaller than the first sub-pixel unit 11, it can emit light with the same brightness as the first sub-pixel unit 11.

[0069] In one embodiment, the third control module 23 further includes a second feedback signal processing module 221, and the third control module 23 is further used for:

[0070] Obtaining a line scan feedback signal;

[0071] Acquire grayscale data of the corresponding row according to the row scanning feedback signal;

[0072] Obtaining a preset compensation duty cycle according to the grayscale data of the corresponding row;

[0073] Duty cycle compensation is performed on the data signal of the corresponding second sub-pixel unit 12 according to the preset compensation duty cycle, so that the gray scale of the corresponding second sub-pixel unit 12 in the activated state is consistent with the acquired gray scale of the corresponding row.

[0074] In application, the area of ​​the first sub-pixel unit 11 can be set to 2 / 3, the area of ​​the second sub-pixel unit 12 can be set to 1 / 3, and the output grayscale brightness can be set to 0, 5, 10, 15...255. The actual output brightness of the first sub-pixel unit 11 and the second sub-pixel unit 12 can be measured, the brightness difference can be confirmed, and the respective brightness values ​​can be recorded. For example, a brightness measuring instrument can be used for measurement. Then the data signal is adjusted to lengthen the output duty cycle of the data signal of the second sub-pixel unit 12, and the initial duty cycle and the final duty cycle are recorded until it is confirmed that the brightness value actually output by the second sub-pixel unit 12 is consistent with the grayscale (i.e., the set grayscale) of the first sub-pixel unit 11. It can be obtained that the duty ratio (i.e., the final duty ratio) corresponding to the gray scales 0, 5, 10, ... 255 is D0', D5', D10' ... D255', and the compensation duty ratio under different gray scales is ΔD0, ΔD5 ... ΔD255, and the compensation duty ratio is the difference between the final duty ratio and the initial duty ratio. When the feedback voltage received is 0v and it is confirmed that a lamp bead (i.e., the first sub-pixel unit 11) is open, the row scanning signal of the row where the open lamp bead is located is also synchronously fed back to the second feedback signal processing module 221 in the third control module 23 through the first control module 21. Whenever the row is output, the third control module 23 will automatically read the grayscale of the current row output through the timing control integrated circuit (Tcon IC), and then call the compensation duty cycle of the current grayscale to compensate the initial duty cycle to obtain the final duty cycle to be output, and use the compensated duty cycle to compensate the brightness of the second sub-pixel unit 12, so that the second sub-pixel unit 12 and the first sub-pixel unit 11 output the same brightness.

[0075] In application, after the column signal line 24 with a corresponding number from the third control module 23 is fed back to the scan IC, the row scanning voltage output by the scan IC is increased to compensate for the brightness.

[0076] In one embodiment, the lamp beads of the second sub-pixel unit 12 can be designed to have the same appearance as the lamp beads of the first sub-pixel unit 11, with only a size difference. The appearance of the lamp beads of the second sub-pixel unit 12 can also be designed to be different from that of the first sub-pixel unit 11 according to different application scenarios.

[0077] In applications, such as Figure 5 As shown, the second sub-pixel unit 12 is arranged at the lower right part of the first sub-pixel unit 11. The second sub-pixel unit 12 can also be arranged at any position such as the lower left part, the left middle part, the right middle part, the upper left part, and the upper right part of the first sub-pixel unit 11. When designing the appearance of the second sub-pixel unit 12, the goal is to ensure the PPI of the display screen and reduce the pitch between the first sub-pixel unit 11 and the second sub-pixel unit 12, without limiting its specific form.

[0078] Embodiment 2

[0079] The pixel control method provided in the embodiment of the present application can be executed by the processor 201 of the pixel control circuit when running a computer program 203 with corresponding functions, by determining the working state of the display panel; if the working state is a specified state, the corresponding second sub-pixel unit 12 is connected to the circuit so that the second sub-pixel unit 12 is controlled by the row scanning signal and / or the data signal and is in an activated state. The second sub-pixel unit 12 can be connected when the first sub-pixel unit 11 fails, eliminating the cross bright line phenomenon. In addition, when the jagged phenomenon appears on the display screen, the second sub-pixel unit 12 can also be connected to make a smooth transition of the jagged state and reduce the jagged phenomenon.

[0080] like Figure 6 As shown, the pixel control method provided in the embodiment of the present application includes the following steps S101 and S102:

[0081] Step S101: Determine the working state of the display panel.

[0082] In one embodiment, determining the working state of the display panel includes:

[0083] Obtaining the voltage of the column signal line 24, if the voltage is the first voltage, determining that the working state is that the first sub-pixel unit 11 of the corresponding column is normal, if the voltage is the second voltage, determining that the working state is that the first sub-pixel unit 11 of the corresponding column is faulty; and / or

[0084] Based on the received display picture analysis result, it is determined that a jaggies phenomenon occurs on the display picture.

[0085] In application, the first voltage is the output voltage of the column signal line 24 when the first sub-pixel unit 11 is normal, such as 1V. The second voltage is the output voltage of the column signal line 24 when the first sub-pixel unit 11 is open, such as 0V. By measuring the output voltage value of the column signal line 24, it can be determined whether the first sub-pixel unit 11 is in a normal state or an open state. In addition, if the first sub-pixel unit 11 has other faults such as a short circuit, it can also be reflected by the output voltage of the column signal line 24.

[0086] In the application, the display screen analysis result can be obtained by the graphics processing unit (GPU) to collect the display screen, and after the screen analysis is performed using the built-in algorithm, the display screen analysis result obtained by the analysis is output to the pixel control circuit. For example, when the screen analysis module of the graphics processor analyzes that the image screen has jagged edges, the jagged edge phenomenon can be reflected in the display screen analysis result, and can be known by the pixel control circuit.

[0087] In applications, the graphics processor can perform jagged image detection based on the Sobel operator or the Canny edge detection algorithm. The graphics processor uses a convolution kernel to detect the location where the grayscale value changes sharply in the image, that is, the edge. For jagged edges, since the grayscale value in its local area changes greatly, after applying the Sobel operator, the gradient intensity at these locations will increase significantly and be identified. The graphics processor can apply one or more predefined convolution kernels (such as the horizontal and vertical templates in the Sobel operator) to each pixel of the image, and calculate the gradient intensity by differencing the grayscale values ​​of adjacent pixels. If the gradient intensity of a pixel point and its neighborhood exceeds a certain threshold, it is considered that there is an edge at this location. At this time, the display screen analysis result can be used to feedback the jagged phenomenon of the display screen, and the corresponding area of ​​the jaggedness in the screen can also be fed back.

[0088] Step S102: If the working state is the designated state, the corresponding second sub-pixel unit 12 is connected to the circuit, so that the second sub-pixel unit 12 is controlled by the row scanning signal and / or the data signal and is in an activated state.

[0089] In one embodiment, Figure 7 As shown, step S102 includes the following steps S201 and S202:

[0090] Step S201: If the first sub-pixel unit 11 is in a faulty state, the second sub-pixel unit 12 in the same row and column as the faulty pixel unit 1 is connected to the circuit.

[0091] In application, if the first sub-pixel unit 11 is open, the switch modules 26 in the same row and column are driven to conduct according to the row and column coordinates of the open first sub-pixel unit 11, so that the second sub-pixel unit 12 is connected to the circuit.

[0092] Step S202: If the aliasing phenomenon occurs on the display screen, all the second sub-pixel units 12 are connected to the circuit, or the second sub-pixel units 12 in the area corresponding to the aliasing phenomenon are connected to the circuit.

[0093] In applications, such as Figure 8 As shown, when the display image analysis result indicates that the image has a aliasing phenomenon, all second sub-pixel units 12 of the entire display panel can be connected to the circuit to reduce the aliasing phenomenon of the entire image. Based on the aliasing area indicated in the display image analysis result, the second sub-pixel units 12 in the aliasing area can also be connected to the circuit to reduce the aliasing phenomenon of the aliasing area.

[0094] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0095] Embodiment 3

[0096] like Fig. 9 As shown, an embodiment of the present application also provides a display panel, including a pixel control circuit 2 of the display panel provided in the first embodiment of the present application, the pixel control circuit 2 includes a memory 202, a processor 201, and a computer program 203 stored in the memory 202 and executable on the processor 201, and when the processor 201 executes the computer program 203, the steps of the pixel control method provided in the second embodiment of the present application are implemented.

[0097] In applications, the display panel may include, but is not limited to, a processor and a memory. Those skilled in the art will appreciate that Fig. 9 This is merely an example of a display panel and does not constitute a limitation on the display panel. The display panel may include more or fewer components than shown in the figure, or a combination of certain components, or different components.

[0098] In applications, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0099] In application, the memory may be an internal storage unit of the display panel in some embodiments, such as a hard disk or memory of the display panel. The memory may also be an external storage device of the display panel in other embodiments, such as a plug-in hard disk equipped on the display panel, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. Further, the memory may also include both an internal storage unit of the display panel and an external storage device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as program code of a computer program, etc. The memory may also be used to temporarily store data that has been output or is to be output.

[0100] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0101] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0102] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program 203. When the computer program 203 is executed by the processor 201, the steps in the above-mentioned method embodiments can be implemented.

[0103] The embodiment of the present application provides a computer program 203 product. When the computer program 203 product runs on a display panel, the display panel can implement the steps in the above-mentioned method embodiments when executing the computer program 203 product.

[0104] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / display panel, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0107] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0108] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0109] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A pixel control circuit for a display panel, characterized in that: The display panel includes a plurality of pixel units, the pixel units are arranged in an array in the form of n rows and m columns, the pixel units include a first sub-pixel unit and a second sub-pixel unit, and the pixel control circuit includes a first control module, a second control module, a third control module, n row signal lines and m column signal lines; The first control module is connected to the row signal line, the second control module is connected to the column signal line, and the pixel units in the i-th row and j-th column are respectively connected to the i-th row signal line and the j-th column signal line; The first control module is used to output a row scanning signal to the row signal line; The second control module is used to output a data signal to the column signal line; The first sub-pixel unit is used to be controlled by the row scanning signal and / or the data signal to be in an activated or inactivated state; The third control module is used to connect the corresponding second sub-pixel unit to the circuit under a specified state, so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal to be in an activated state; The specified state includes at least one of a first sub-pixel unit failure and a aliasing phenomenon on a display screen; i is an integer, and i∈[1,n]; j is an integer, and j∈[1,m].

2. The pixel control circuit according to claim 1, characterized in that: Also included are switch modules corresponding one to one with each second sub-pixel unit; The controlled end of the switch module in the i-th row and j-th column is connected to the third control module, the input end is connected to the first control module, the output end is connected to one end of the second sub-pixel unit in the i-th row and j-th column, one end of the first sub-pixel unit in the i-th row and j-th column is connected to the i-th row signal line, and the other ends of the first sub-pixel unit in the i-th row and j-th column and the second sub-pixel unit in the i-th row and j-th column are connected to the j-th column signal line; The third control module is further used to turn on the corresponding switch module in a specified state so that the corresponding second sub-pixel unit is connected to the circuit.

3. The pixel control circuit according to claim 2, characterized in that: The input end of the switch module in the i-th row and j-th column is connected to the first control module via the i-th row signal line, or The input end of the switch module in the i-th row and j-th column is directly connected to the first control module, and the first control module is used to send a row scanning signal to the corresponding second sub-pixel unit through the switch module in the i-th row and j-th column.

4. The pixel control circuit according to claim 1, characterized in that: Also includes a first feedback signal processing module; The jth input terminal of the second control module is connected to the jth column signal line, the jth output terminal of the second control module is connected to the jth input terminal of the first feedback signal processing module, and the jth output terminal of the first feedback signal processing module is connected to the jth input terminal of the third control module; The first feedback signal processing module is used to determine the state of the first sub-pixel unit failure according to the voltage of the column signal line obtained, and locate the column coordinates of the failed pixel unit and send them to the third control module; The third control module is further used to connect the corresponding second sub-pixel unit to the circuit according to the row and column coordinates of the faulty pixel unit.

5. The pixel control circuit according to claim 1, characterized in that: The size of the second sub-pixel unit is smaller than that of the first sub-pixel unit, and the first sub-pixel unit and the second sub-pixel unit are staggered; The third control module is also used for: When the first sub-pixel unit in the i-th row and the j-th column is in an activated state, sending a first data signal to the first sub-pixel unit in the i-th row and the j-th column; When the second sub-pixel unit in the i-th row and the j-th column is in an activated state, sending a second data signal to the second sub-pixel unit in the i-th row and the j-th column; The duty cycle of the first data signal is greater than that of the first data signal.

6. The pixel control circuit according to any one of claims 1 to 5, characterized in that: The third control module is also used for: Obtaining a line scan feedback signal; Acquiring grayscale data of a corresponding row according to the row scanning feedback signal; Acquire a preset compensation duty cycle according to the grayscale data of the corresponding row; Duty cycle compensation is performed on the data signal of the corresponding second sub-pixel unit according to the preset compensation duty cycle, so that the gray scale of the corresponding second sub-pixel unit in an activated state is consistent with the acquired gray scale of the corresponding row.

7. A pixel control method, applied to the pixel control circuit according to any one of claims 1 to 6, characterized in that: include: Determine the working status of the display panel; If the working state is a designated state, the corresponding second sub-pixel unit is connected to the circuit so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal and is in an activated state.

8. The pixel control method according to claim 7, characterized in that: The determining the working state of the display panel includes: Obtaining a voltage of a column signal line, and if the voltage is a first voltage, determining that the working state is that the first sub-pixel unit of the corresponding column is normal, and if the voltage is a second voltage, determining that the working state is that the first sub-pixel unit of the corresponding column is faulty; and / or Based on the received display picture analysis result, it is determined that a jaggies phenomenon occurs on the display picture.

9. The pixel control method according to claim 7, characterized in that: If the working state is the specified state, the corresponding second sub-pixel unit is connected to the circuit so that the second sub-pixel unit is controlled by the row scanning signal and / or the data signal and is in an activated state, including: If the first sub-pixel unit is in a faulty state, a second sub-pixel unit in the same row and column as the faulty pixel unit is connected to the circuit; If the display screen is in a state where the aliasing phenomenon occurs, all the second sub-pixel units are connected to the circuit, or the second sub-pixel units in the area corresponding to the aliasing phenomenon are connected to the circuit.

10. A display panel, characterized in that: The method comprises a pixel control circuit as claimed in any one of claims 1 to 6, wherein the pixel control circuit comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the pixel control method as claimed in any one of claims 7 to 9 when executing the computer program.

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