Double-grid-based GaN high-electron-mobility transistor structure and preparation method

Abstract

The invention discloses a double-grid-based GaN high-electron-mobility transistor structure and a preparation method of the double-grid-based GaN high-electron-mobility transistor structure. The transistor structure comprises a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer and a dielectric layer from bottom to top. Two sides of the dielectric layer are respectively provided with a source trench and a drain trench, and a gate structure is arranged between the source trench and the drain trench. The gate structure comprises a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left gate structure and the right gate structure are isolated through a dielectric substance. According to the structure, the electric field of the right grid electrode can be adjusted by the left grid electrode under the same grid voltage of the transistor, distribution is more uniform, and grid electrode electric leakage is improved. Meanwhile, the energy band change of the left side grid is small, hole dissipation and electron capture are reduced, and therefore the dynamic threshold value of the device is improved. On the premise of losing certain on resistance and gate capacitance, the saturation source and drain current of the device is improved, the gate electric leakage is reduced, and the gate reliability is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a reliability reinforcement technology for nitride power semiconductor devices, and in particular to a dual-gate based GaN high electron mobility transistor structure and a preparation method. Background Art

[0002] In order to control power conversion and energy consumption in power electronic systems and improve energy utilization efficiency, enhanced power switching transistors with higher energy transmission efficiency have come into the public eye. Wide bandgap materials have greater advantages in electrical properties, thermal properties and energy utilization efficiency compared to low bandgap materials represented by traditional silicon materials. Among them, GaN materials have the advantages of higher mobility carriers and large breakdown electric fields.

[0003] Schottky-type p-GaN gate high electron mobility transistors show extremely high commercial prospects compared to other enhancement-mode device structures. The p-type cap layer structure above the gate barrier layer raises the conduction band of the heterojunction below the gate to above the Fermi level, depleting the electrons below the gate and shifting the threshold in the positive direction. In order to reduce device leakage and increase gate swing, the use of Schottky contacts instead of ohmic contacts can improve gate reliability, but its gate reliability is still a key issue for p-GaN gate hemts. There is a large voltage drop and electric field in the Schottky-type p-GaN gate structure, which will show time-dependent degradation, resulting in a strong increase in gate leakage. The safe gate bias voltage is generally around 6V. Most people believe that the cause of gate breakdown may be Schottky tunneling, leakage in the passivation layer, and trap-assisted tunneling in the barrier layer. The same gate geometry and changes in the defect mechanism of the p-type cap layer will also lead to reduced reliability. Summary of the invention

[0004] In view of the deficiencies in the existing reliability reinforcement technology of nitride power semiconductor devices, the present invention proposes a GaN high electron mobility transistor structure and preparation method based on a dual gate, improves the gate leakage and dynamic threshold problems of the device by redesigning the gate structure and improving the p-type cap and field plate structure.

[0005] The GaN high electron mobility transistor structure based on dual gates includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first dielectric layer, and a second dielectric layer from bottom to top. A source trench and a drain trench are provided on both sides of the dielectric layer, respectively. The source trench and the drain trench pass through the dielectric layer and the barrier layer and contact the upper surface of the channel layer. A source metal is provided in the source trench, and a drain metal is provided in the drain trench. A gate structure is provided between the source trench and the drain trench in the dielectric layer.

[0006] The gate structure includes a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric. The right gate structure is composed of a right p-type cap layer and a right gate metal from bottom to top, the right gate metal is higher than the first dielectric layer, and the right gate field plate is located on the upper surface of the first dielectric layer and extends from the side of the right gate metal toward the drain trench. The left gate structure is composed of a left p-type cap layer, a left gate metal and a left gate field plate from bottom to top, the left gate field plate is located above the right gate structure, the upper surface is higher than the upper surface of the second dielectric layer, and the right end of the left gate field plate is located between the right gate field plate and the drain trench in the second dielectric layer.

[0007] Preferably, the p-type cap layer is in direct contact with the gate metal. The gate metal is a Schottky contact, the width of the left and right p-type cap layers is 0.6µm, the thickness is 110nm, there is a 0.2µm dielectric layer between the left and right p-type cap layers, and the p-type cap layer is doped with Mg at a concentration of 2e19 cm-3.

[0008] Preferably, the height of the left gate field plate is 0.4µm, the length is 4µm, and a groove structure with a height of 0.2µm and a width of 1.9µm is provided at one end close to the drain trench. The height of the right gate field plate is 0.2µm, and the length is 1.8µm.

[0009] Preferably, the thickness of the nucleation layer AlN is 0.05 μm; the buffer layer Al 0.05 Ga 0.95 The thickness of N is 2µm and the doping concentration is 1e14 cm-3; the channel layer is non-intentionally doped GaN with a thickness of 0.2µm; the barrier layer is non-intentionally doped Al 0.23 Ga 0.77 N, thickness is 0.015µm.

[0010] Preferably, the etching width of the source trench and the drain trench is 0.5µm and the depth is 0.45µm. The spacing between the source trench and the gate structure is 1µm, and the spacing between the gate structure and the drain trench is 10µm.

[0011] The preparation method of a GaN high electron mobility transistor based on a dual gate specifically comprises the following steps: Step 1: Prepare the silicon substrate region of the power semiconductor device, add C impurities in the silicon substrate region by metal organic chemical vapor deposition (MOCVD), and sequentially epitaxially grow an AlN nucleation layer and an AlGaN buffer layer. On the AlGaN buffer layer, sequentially grow an epitaxial non-intentionally doped GaN channel layer and a non-intentionally doped AlGaN barrier layer by metal organic chemical vapor deposition. Then, deposit the first dielectric layer on the AlGaN barrier layer by plasma enhanced chemical vapor deposition (PECVD).

[0012] Step 2: After the right gate window is opened by etching the first dielectric layer by inductively coupled plasma (ICP), the etching is continued by a digital etching process using low-damage oxidized HCL immersion until the AlGaN barrier layer is exposed to obtain a right gate groove.

[0013] Step 3: On the right gate groove, Mg is used as the P-type doping and epitaxial growth is performed by metal organic chemical vapor deposition to obtain a right p-type cap layer. Then, Ni / Au is deposited on the right p-type cap layer to a level higher than the first dielectric layer by low pressure chemical vapor deposition (LPCVD) to form a right gate metal.

[0014] Step 4: Deposit aluminum metal on the first dielectric layer on the right side of the right gate metal to obtain the right gate field plate. Step 5: Deposit a 0.2µm second dielectric layer on the first dielectric layer by plasma enhanced chemical vapor deposition (PECVD). Repeat the above steps 2 to 4 to etch the left gate groove, and deposit the left p-type cap layer, left gate metal and left gate field plate in sequence.

[0015] Step 6: Use a digital etching process with low-damage oxidation HCL immersion on both sides of the second dielectric layer until the GaN channel layer is exposed, and continue etching to 0.05µm below the upper surface of the channel layer to obtain source and drain trenches. Use electron beam evaporation to plate Ti, Al, Ni, and Au with thicknesses of 20 nm, 130 nm, 50 nm, and 150 nm in sequence, and then anneal at 890°C for 30s in a nitrogen environment to form metal contacts for the source and drain electrodes.

[0016] The beneficial effects of the present invention are: A GaN high electron mobility transistor structure based on dual gates is proposed. The structure is designed to be split into two gate structures in the gate p-type cap layer region. The discrete gates are separated by a dielectric layer, and two field plates with different heights and widths are grown on the dual gates. The simulation results of Sentaurus TCAD show that under the same gate voltage, the electric field of the right gate can be adjusted by the left gate, making the electric field more uniform, and its defect influence is also reduced to a certain extent, improving the gate leakage. The same gate is modulated by the double-layer field plate by the leakage measurement electric field, so that the device maintains a relatively consistent breakdown voltage at a higher source-drain current. In the dual-gate structure, the left gate energy band changes less, reducing the hole escape and electron capture of the pgain structure, thereby improving the dynamic threshold of the device and other problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a schematic diagram of the structure of a traditional GaN high electron mobility transistor; Figure 2It is a schematic diagram of the structure of the GaN high electron mobility transistor proposed in this application; Figure 3 is a schematic diagram of depositing a first dielectric layer in an embodiment; Figure 4 is a schematic diagram of etching a right gate groove in an embodiment; Figure 5 is a schematic diagram of depositing a right p-type cap in an embodiment; Figure 6 is a schematic diagram of preparing a right gate structure in an embodiment; Figure 7 is a schematic diagram of preparing a left gate structure in an embodiment; Figure 8 is a graph showing the change in gate leakage of different transistors with gate forward voltage bias in the embodiments.

[0018] Fig. 9 is a threshold drift variation curve diagram of different transistors under different gate biases in the embodiment.

[0019] Among them, substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, barrier layer 105, dielectric layer 106, first dielectric layer 106a, second dielectric layer 106b, 2DEG region 107, p-type cap layer 108, left p-type cap layer 108a, right p-type cap layer 108b, source metal 109, drain metal 110, gate metal 111, left gate metal 111a, right gate metal 111b, field plate 112, left field plate 112a, right field plate 112b. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings.

[0021] Figure 1 It is a traditional GaN high electron mobility transistor structure, which includes a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and a dielectric layer 106 from bottom to top. The thickness of the nucleation layer 102 is 0.05µm; the thickness of the buffer layer 103 is 2µm; the channel layer 104 is non-intentionally doped GaN, with a thickness of 0.2µm; the barrier layer 105 is non-intentionally doped Al 0.23 Ga 0.77 N, thickness is 0.015µm.

[0022] A source trench and a drain trench are provided on both sides of the dielectric layer 106. The source trench and the drain trench pass through the dielectric layer 106 and the barrier layer 105 to the upper surface of the channel layer 104. A source metal 109 is provided in the source trench, and a drain metal 110 is provided in the drain trench. The etching width of the source trench and the drain trench is 0.5µm and the depth is 0.45µm. A gate structure is provided between the source trench and the drain trench. The spacing distance between the source trench and the gate structure is 1µm, and the spacing distance between the gate structure and the drain trench is 10µm.

[0023] Figure 2 The GaN high electron mobility transistor structure based on dual gate proposed in this application is divided into a second dielectric layer 106b and a first dielectric layer 106a of upper and lower layers. The gate structure is divided into a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric. The right gate structure is a right p-type cap layer 108b and a right gate metal 111b from bottom to top, the right gate metal 111b is higher than the first dielectric layer 106a, and the right gate field plate 112a is located on the upper surface of the first dielectric layer 106a, extending from the side of the right gate metal 111b to the drain trench. The left gate structure comprises, from bottom to top, a left p-type cap layer 108a, a left gate metal 111a and a left gate field plate 112b. The left gate field plate 112b is located above the right gate structure, and its upper surface is higher than the upper surface of the second dielectric layer 106b. The right end of the left gate field plate 112b is located between the right gate field plate 112a and the drain trench in the second dielectric layer 106b.

[0024] The p-type cap layer is doped with Mg at a concentration of 2e19 cm-3 and is in direct contact with the gate metal. The left and right gate cap layers 108a and 108b are controlled by the same potential, and the cross sections are isolated by a 0.2µm wide dielectric layer 106. The width of the left and right p-type cap layers is 0.6µm and the thickness is 110nm.

[0025] The height of the left gate field plate is 0.4µm and the length is 4µm, and a groove structure with a height of 0.2µm and a width of 1.9µm is provided at one end close to the drain trench. The height of the right gate field plate is 0.2µm and the length is 1.8µm.

[0026] The preparation method of a GaN high electron mobility transistor based on a dual gate specifically comprises the following steps: Step 1: Prepare the silicon substrate region of the power semiconductor device, add C impurities in the silicon substrate region by metal organic chemical vapor deposition (MOCVD), and sequentially epitaxially grow an AlN nucleation layer and an AlGaN buffer layer. On the AlGaN buffer layer, sequentially grow an epitaxial non-intentionally doped GaN channel layer and a non-intentionally doped AlGaN barrier layer by metal organic chemical vapor deposition. Then, deposit a first dielectric layer on the AlGaN barrier layer by plasma enhanced chemical vapor deposition (PECVD), such as Figure 3 shown.

[0027] Step 2: After the right gate window is opened by etching the first dielectric layer through inductively coupled plasma (ICP), the etching is continued by a digital etching process using low-damage oxidized HCL immersion until the AlGaN barrier layer is exposed to obtain the right gate groove, as shown in FIG. Figure 4 shown.

[0028] Step 3: On the right gate groove, a right p-type cap layer is obtained by metal organic chemical vapor deposition, using Mg as a P-type dopant and epitaxial growth, such as Figure 5 Then, Ni / Au is deposited on the right p-type cap layer to a level higher than the first dielectric layer by low pressure chemical vapor deposition (LPCVD) to form a right gate metal.

[0029] Step 4: Deposit aluminum metal on the first dielectric layer on the right side of the right gate metal to obtain the right gate field plate, such as Figure 6 shown.

[0030] Step 5: Deposit a 0.2µm second dielectric layer on the first dielectric layer by plasma enhanced chemical vapor deposition (PECVD). Repeat the above steps 2 to 4 to etch out the left gate groove, and deposit the left p-type cap layer, left gate metal and left gate field plate in sequence. Figure 7 shown.

[0031] Step 6: Use a digital etching process with low-damage oxidation HCL immersion on both sides of the second dielectric layer until the GaN channel layer is exposed, and continue etching to 0.05µm below the upper surface of the channel layer to obtain source and drain trenches. Use electron beam evaporation to plate Ti, Al, Ni, and Au with thicknesses of 20 nm, 130 nm, 50 nm, and 150 nm in sequence, and then anneal at 890°C for 30 seconds in a nitrogen environment to form metal contacts for the source and drain electrodes, as shown below. Figure 2 The GaN high electron mobility transistor structure shown.

[0032] The following uses Sentaurus TCAD simulation verification method to compare Figure 1 , Figure 2 The performance of the two transistor structures is shown in Figure 2. Figure 8 , 9 shown.

[0033] When the source-drain voltage is biased to 0V, a positive gate voltage bias is applied to the gate. Figure 2 The transistor structure shown in the figure has a relaxed electric field inside the p-type cap layer, which allows it to withstand higher voltages. Figure 1 The 8.6V breakdown voltage of the conventional transistor structure shown in the figure, the new structure proposed in this application can achieve a gate breakdown of 11.4V, which is an increase of about 32%. When the device is placed under a 10V source-drain voltage bias and subjected to different gate stress times, compared with the conventional transistor structure, the threshold drift of the transistor structure proposed in this application under the stress time can be reduced by 0.1V~0.3V in general, and the gate-drain electric field is significantly reduced, and the frequency of its electron scattering is reduced. The intensity of defect capture increases with time, resulting in a decrease in the electron concentration below the gate, so the threshold drifts positively in the initial stage. The electrons at the interface of the metal and the p-type cap layer are gradually depleted, and gradually increase at the interface of the barrier layer and the p-type cap layer. The hole depletion at the metal interface enters the barrier layer, resulting in a lower energy level, which in turn causes a negative drift in the threshold. The two work together to affect the threshold drift.

[0034] Static under different source-drain voltage bias (V DSQ =10V / 20V / 50V) is subjected to gate bias. The double-gate double-field plate structure proposed in this application can effectively reduce the threshold drift problem. DSQ =20V, the improvement is best. In the off state with high drain voltage, the gate metal / p-type cap Schottky junction is slightly forward biased, causing the gate-drain capacitance to charge and some holes to escape from the p-type cap, resulting in hole losses. Higher V DSQ This will cause more holes to flow out of the gate stack, making the gate stack more negatively charged. The electric field of the gate leakage test aggravates the influence of the defect mechanism, thereby changing its threshold and affecting stability.

[0035] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. It should be noted that the above description is only a specific embodiment of the present invention and does not limit the present invention. All modulations and optimizations made within the spirit and principle of the present invention should fall within the scope of the claims of the present invention.

Claims

1. A dual-gate GaN high electron mobility transistor structure, comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a dielectric layer, wherein a source trench and a drain trench are respectively provided on both sides of the dielectric layer, wherein the source trench and the drain trench pass through the dielectric layer and the barrier layer and contact the upper surface of the channel layer; a source metal is provided in the source trench, and a drain metal is provided in the drain trench; a gate structure is provided between the source trench and the drain trench in the dielectric layer; and the characteristics are as follows: The dielectric layer is divided into a second dielectric layer and a first dielectric layer stacked up and down; The gate structure includes a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric; The right gate structure is composed of a right p-type cap layer and a right gate metal from bottom to top, the right gate metal is higher than the first dielectric layer, the right gate field plate is located on the upper surface of the first dielectric layer, and extends from the side of the right gate metal toward the drain trench; the left gate structure is composed of a left p-type cap layer, a left gate metal and a left gate field plate from bottom to top, the left gate field plate is located above the right gate structure, the upper surface is higher than the upper surface of the second dielectric layer, and the right end of the left gate field plate is located between the right gate field plate and the drain trench in the second dielectric layer.

2. The dual-gate GaN high electron mobility transistor structure according to claim 1, characterized in that: The p-type cap layer is in direct contact with the gate metal; the gate metal is a Schottky contact, the width of the left and right p-type cap layers is 0.6µm, the thickness is 110nm, there is a 0.2µm dielectric layer between the left and right p-type cap layers, and the p-type cap layer is doped with Mg with a concentration of 2e19cm-3.

3. The dual-gate GaN high electron mobility transistor structure according to claim 1, characterized in that: The height of the left gate field plate is 0.4µm and the length is 4µm. A groove structure with a height of 0.2µm and a width of 1.9µm is provided at one end close to the drain trench. The height of the right gate field plate is 0.2µm and the length is 1.8µm.

4. The dual-gate GaN high electron mobility transistor structure according to claim 1, characterized in that: The thickness of the nucleation layer AlN is 0.05 μm; the buffer layer Al 0.05 Ga 0.95 The thickness of N is 2µm and the doping concentration is 1e14 cm-3; the channel layer is non-intentionally doped GaN with a thickness of 0.2µm; the barrier layer is non-intentionally doped Al 0.23 Ga 0.77 N, thickness is 0.015µm.

5. The dual-gate GaN high electron mobility transistor structure according to claim 1, characterized in that: The etching width of the source trench and the drain trench is 0.5µm and the depth is 0.45µm; the spacing distance between the source trench and the gate structure is 1µm, and the spacing distance between the gate structure and the drain trench is 10µm.

6. A method for preparing a dual-gate GaN high electron mobility transistor, characterized in that: The specific steps include: Step 1, preparing a silicon substrate region of a power semiconductor device, adding C impurities in the silicon substrate region by metal organic chemical vapor deposition, and sequentially growing an AlN nucleation layer and an AlGaN buffer layer by epitaxial growth; sequentially growing an epitaxial non-intentionally doped GaN channel layer and a non-intentionally doped AlGaN barrier layer by metal organic chemical vapor deposition on the AlGaN buffer layer; and then depositing a first dielectric layer on the AlGaN barrier layer by plasma enhanced chemical vapor deposition; Step 2: After the right gate window is opened by etching the first dielectric layer through inductively coupled plasma, the etching is continued by a digital etching process of low-damage oxidized HCL immersion until the AlGaN barrier layer is exposed to obtain a right gate groove; Step 3: On the right gate groove, Mg is used as a P-type dopant and epitaxially grown by metal organic chemical vapor deposition to obtain a right p-type cap layer; Ni / Au is then deposited on the right p-type cap layer to a level higher than the first dielectric layer by low pressure chemical vapor deposition to form a right gate metal; Step 4, depositing aluminum metal on the first dielectric layer on the right side of the right gate metal to obtain a right gate field plate; Step 5, depositing a 0.2µm second dielectric layer on the first dielectric layer by plasma enhanced chemical vapor deposition; Repeat the above steps 2 to 4 to etch a left gate groove, and deposit a left p-type cap layer, a left gate metal and a left gate field plate in sequence; Step 6: Use a digital etching process of low-damage oxidation HCL immersion on both sides of the second dielectric layer until the GaN channel layer is exposed, and continue etching to 0.05µm below the upper surface of the channel layer to obtain source and drain trenches; use electron beam evaporation to plate Ti, Al, Ni, and Au with thicknesses of 20 nm, 130 nm, 50 nm, and 150 nm in sequence, and then anneal at 890°C for 30s in a nitrogen environment to form metal contacts for the source and drain electrodes.

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