Network-on-chip simulation method and device, equipment and storage medium

Abstract

The invention provides a network-on-chip simulation method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of computers, and the method comprises the steps: determining each hardware unit for forming a network-on-chip, and determining an execution action included in the hardware unit in each execution cycle; constructing an execution code snippet of each hardware unit in an execution cycle through a preset compiling language according to execution actions included in the hardware units; constructing an on-chip network design file according to the respective execution code snippets of all the hardware units; and performing simulation operation on the network-on-chip design file to obtain a simulation operation result. According to the method, all execution actions of the hardware unit in each execution cycle are simulated, migration of the execution actions occurs as time goes on, and therefore circulation of the execution actions of the hardware unit in the execution cycle is simulated through scheduling of the simulation process, and a design file of the whole network-on-chip can be constructed more meticulously.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a network-on-chip simulation method, device, electronic device, and computer-readable storage medium. Background Art

[0002] Circuit design files are files written in high-level languages ​​that describe the internal structure and characteristics of a circuit.

[0003] At present, in the field of on-chip networks, a state machine can be constructed for each network layer data packet using the transmitted network layer data packet as an index, thereby realizing logical modeling and obtaining on-chip network design files.

[0004] However, the on-chip network design file constructed in a way that the transmitted network layer packets are indexed has poor precision. Summary of the invention

[0005] The embodiments of the present application provide a network on chip simulation method, device, electronic device and computer-readable storage medium to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides an on-chip network simulation method, the method comprising: Determine each hardware unit used to constitute the on-chip network, and determine the execution actions included in the hardware unit in each execution cycle; According to the execution actions included in the hardware units, constructing the execution code fragments of each hardware unit in the execution cycle by using a preset compilation language; Constructing a network-on-chip design file according to the respective execution code snippets of all the hardware units; The on-chip network design file is simulated and run to obtain a simulation result.

[0007] In a second aspect, an embodiment of the present application provides an on-chip network simulation device, the device comprising: A determination module, used to determine various hardware units used to constitute the on-chip network, and to determine execution actions included in the hardware units in each execution cycle; A first construction module is used to construct an execution code segment of each hardware unit in the execution cycle by using a preset compilation language according to the execution actions included in the hardware unit; A second construction module is used to construct a network-on-chip design file according to the respective execution code fragments of all the hardware units; The running module is used to simulate the on-chip network design file to obtain the simulation running result.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0010] In an embodiment of the present application, the execution code snippet of each hardware unit in the execution cycle can be constructed by a preset compilation language according to the execution actions included in the hardware unit in the on-chip network, and the on-chip network design file can be constructed according to the respective execution code snippets of all hardware units, so as to simulate and run the on-chip network design file to obtain the simulation operation result. The embodiment of the present application can use the execution cycle as an index to simulate all the execution actions of the hardware unit in each execution cycle, and the migration of the execution actions occurs over time, so as to simulate the flow of the execution actions of the hardware unit in the execution cycle through the scheduling of the simulation process, so that the design file of the entire on-chip network can be constructed more meticulously.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 is a flowchart of a method for emulating a network on chip provided by an embodiment of the present application; Figure 2 It is a flowchart of the specific steps of an on-chip network simulation method provided by an embodiment of the present application; Figure 3 It is a timing logic diagram of a routing module in a network on chip provided by an embodiment of the present application; Figure 4 It is a code structure diagram of a routing module in a network on chip provided by an embodiment of the present application; Figure 5is a structural diagram of a node of an on-chip network provided in an embodiment of the present application; Figure 6 It is a schematic diagram of a connection method between nodes of a network on chip provided in an embodiment of the present application; Figure 7 It is a structure of a network on chip provided by an embodiment of the present application; Figure 8 This is a block diagram of a network-on-chip simulation device provided in an embodiment of the present application; Fig. 9 is a block diagram of an electronic device provided by an embodiment of the present invention; Fig.10 is a block diagram of another electronic device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0016] Figure 1 , is a flowchart of a method for emulating a network on chip provided by an embodiment of the present application, such as Figure 1 As shown, the method may include: Step 101: determine various hardware units used to constitute an on-chip network, and determine execution actions included in the hardware units in each execution cycle.

[0017] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0018] Therefore, the network-on-chip (NOC) is a key technology of the multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for the collaborative work of processors. The network-on-chip aims to solve the communication problem within the multi-core processor. The network-on-chip is an integrated circuit on a network-based communication subsystem. The network-on-chip is a packet switching network based on routers between systems-on-chip. The network-on-chip technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The message communication mechanism is used between the processor cores, and the on-chip bus of the related technology is replaced by routers and packet switching technology to complete the communication task, thereby solving the various bottleneck problems caused by bus interconnection in the related technology.

[0019] The network on chip may include multiple hardware units, which may include: routing modules, access devices, consistency modules, processor cores, buffers, etc. Among them, the routing module is an important component of the network on chip, and the routing module is used to implement important functions in the network on chip such as routing calculation and data arbitration. In addition, the number of routing modules can be multiple, and multiple routing modules can be connected to each other. The routing module can also be connected to other access devices. For example, the access device connected to the injection port of the routing module may include external devices such as memory, graphics card, network card, etc., that is, through a rich selection of additional access devices, the function realization of the multi-core processor architecture is improved.

[0020] In this step, when the on-chip network is working, the hardware unit implements related functions by executing the same execution action in each execution cycle. Different hardware units in the on-chip network each include different execution actions. For example, each execution cycle of the routing module may include execution actions such as routing path calculation, data packet arbitration, and routing strategy selection. Each execution cycle of the buffer may include execution actions such as push, pop, empty check, and full check.

[0021] Step 102: construct an execution code segment of each hardware unit in the execution cycle by using a preset compilation language according to the execution actions included in the hardware unit.

[0022] In a related technology, a state machine can be constructed for each network layer data packet using the transmitted network layer data packet as an index, and the delay and other parameters of the network layer data packet in the routing module can be calculated based on the time overlap between the current network layer data packet and other network layer data packets in the same routing module or buffer. However, the on-chip network design file constructed in this way cannot describe the hardware details in a detailed manner to meet the requirements of further design.

[0023] Therefore, the embodiment of the present application aims to construct all states of the hardware units within each execution cycle with the time cycle as the index, and the state migration occurs over time. Compared with the related technology, this method can achieve a very free topology and real-time simulation of the hardware units through hardware unit-oriented modeling and highly hardware-simulated topology construction, and simulate the execution actions of the hardware units within the execution cycle through the scheduling of the simulation process, so as to carefully construct the design files of the entire on-chip network.

[0024] Specifically, the embodiment of the present application can use a high-level language (such as Python) to write the design file of the on-chip network. The embodiment of the present application can use a single-step simulator model (Network on Chip) to construct the design file of the on-chip network. The single-step simulator model supports the configuration of a large number of parameters such as the size of the on-chip network, the number and location of processing units (PE, Processing Element), the structural function of the routing module, and the injection rate (injection rate, the probability of PE injecting a message per cycle).

[0025] In addition, the single-step simulator model is highly extensible and can add any new routing algorithm, arbitration algorithm, topology network structure, modify any bus protocol, modify any hardware unit, modify the execution action of the hardware unit, modify to any discrete clock domain, etc. PE mounting can be modified to any form of load, such as the master node, request node, etc. in the bus consistency protocol (CHI, Coherent Hub Interface), or directly mount the simulated processor core. In addition, based on Python 3.10, the single-step simulator model can introduce a large number of new dynamic routing methods including machine learning.

[0026] In this step, the execution code snippet of each hardware unit in the execution cycle can be first constructed by a preset compiled language according to the execution actions included in the hardware unit, and the execution code snippet is used to control the corresponding hardware unit to execute a fixed plurality of execution actions in each execution cycle. In the process of constructing the execution code snippet, the writing order of the execution actions in the execution code snippet can be determined according to the dependencies between the execution actions. Thus, the embodiment of the present application constructs a network on chip with the execution actions of the hardware unit in the execution cycle as the dimension. Such a design can be indexed by the time cycle to determine all states of the hardware unit in each execution cycle, and state migration occurs over time. The execution actions of the hardware unit in the execution cycle are simulated by the scheduling of the simulation process, and the design file of the entire network on chip can be carefully constructed.

[0027] For example, suppose a hardware unit A of the network on chip includes execution actions a, b, and c. For the hardware unit A, the execution statements of the execution actions a, b, and c can be written in a compiled language, and the writing order of the execution actions a, b, and c in the execution code fragment can be determined according to the dependency relationship between the execution actions a, b, and c, so as to construct the execution code fragment of the hardware unit A. The execution code fragment of the hardware unit A can control the hardware unit A to execute the execution actions a, b, and c in sequence in each execution cycle according to the execution order.

[0028] Step 103: construct a network-on-chip design file according to the respective execution code snippets of all the hardware units.

[0029] In an embodiment of the present application, after independently constructing the execution code snippets of each hardware unit, the execution code snippets of all hardware units can be summarized into a set of on-chip network design files. In the process of summarizing the execution code snippets of all hardware units into a set of on-chip network design files, the result assignment code snippets between the hardware units can be written according to the input-output relationship between the hardware units, thereby meeting the data interaction requirements between the hardware units in the on-chip network.

[0030] For example, the embodiment of the present application can provide a channel for managing the operating status of each hardware unit and a connection port for all access devices at the top layer (network layer) of a set of network-on-chip design files after aggregation. Subsequently, the network-on-chip design file can be imported into a simulated operating environment for simulation and verification, or the verified network-on-chip design file can be written into the board for operation.

[0031] Step 104: simulate the network on chip design file to obtain simulation results.

[0032] In the embodiment of the present application, during the verification of the on-chip network design file, the on-chip network design file can be imported into the constructed verification platform for compilation and operation to obtain the measured operation result, and then the measured operation result can be compared with the preset reference operation result. If the two are consistent, the verification result can be output as passed. If the two are inconsistent, the verification result can be output as failed.

[0033] In addition, if the verification is passed, the on-chip network design file can be burned to the board for operation, thereby completing the implementation of the on-chip network design.

[0034] In summary, in the embodiment of the present application, the execution code snippets of each hardware unit in the execution cycle can be constructed by a preset compilation language according to the execution actions included in the hardware unit in the on-chip network, and the on-chip network design file can be constructed according to the respective execution code snippets of all hardware units, so as to simulate and run the on-chip network design file to obtain the simulation operation result. The embodiment of the present application can use the execution cycle as an index to simulate all the execution actions of the hardware unit in each execution cycle, and the migration of the execution actions occurs over time, so as to simulate the flow of the execution actions of the hardware unit in the execution cycle through the scheduling of the simulation process, so that the design file of the entire on-chip network can be constructed more meticulously.

[0035] Figure 2 , is a flowchart of specific steps of an on-chip network simulation method provided by an embodiment of the present application, such as Figure 2 As shown, the method may include: Step 201: determine various hardware units used to constitute the on-chip network, and determine the execution actions included in the hardware units in each execution cycle.

[0036] This step may specifically refer to the above step 101, which will not be described in detail here.

[0037] Step 202: Determine the dependency relationship between the execution actions.

[0038] Step 203: construct an execution code segment of each hardware unit in the execution cycle by using a preset compilation language according to the dependency relationship.

[0039] In the embodiment of the present application, for steps 202-203, the dependency relationship reflects the constraint relationship and flow order between the execution actions. For example, if one execution action needs to wait for another execution action to be completed before it can be executed, then there is a dependency relationship between the two execution actions. Or if one execution action needs to obtain the output result of another execution action before it can be executed, then there is also a dependency relationship between the two execution actions.

[0040] Specifically, according to the dependency relationship, the writing order of the execution statements corresponding to the execution actions in the execution code fragment can be determined. Therefore, the embodiment of the present application can specifically construct the execution code fragment of each hardware unit in the execution cycle through a preset compilation language according to the dependency relationship.

[0041] Optionally, the execution action includes a first execution action and a second execution action having a dependency relationship; step 203 may specifically include: Sub-step 2031: in the execution code snippet, write a first execution statement corresponding to the first execution action and a second execution statement corresponding to the second execution action in the preset compilation language.

[0042] Sub-step 2032: Determine the writing order of the first execution statement and the second execution statement in the execution code fragment according to the dependency relationship, so as to construct the execution code fragment of the hardware unit in the execution cycle.

[0043] In an embodiment of the present application, for sub-steps 2031-2032, if the execution action includes a first execution action and a second execution action with a dependency relationship, the embodiment of the present application can determine the writing order of the first execution statement and the second execution statement in the execution code fragment according to the dependency relationship, thereby constructing an execution code fragment of the hardware unit in the execution cycle. When the on-chip network is subsequently run, the execution code fragment can control the first execution statement of the first execution action and the second execution statement of the second execution action, and execute them in the correct execution order, thereby meeting the requirements of the dependency relationship between the first execution action and the second execution action. Thus, the embodiment of the present application can use the time cycle as an index to construct all states (execution actions) of the hardware unit in each execution cycle, and the state (execution action) migration occurs over time. Compared with the related art, this method can achieve a very free topology and real-time simulation of the hardware unit through modeling for the hardware unit and topology construction of highly simulated hardware, and simulate the execution actions of the hardware unit in the execution cycle through the scheduling of the simulation process, and can carefully construct the design file of the entire on-chip network.

[0044] Optionally, the dependency relationship is: the first execution action is used to complete execution after obtaining the execution result of the second execution action; sub-step 2031 may specifically include: Sub-step 20311: In the execution code snippet, write the first execution statement before the second execution statement.

[0045] In the embodiment of the present application, the dependency relationship can be specifically refined into the relationship between the producer and the consumer, that is, the consumer needs the producer to produce the product before consuming it. In the embodiment of the present application, if the first execution action is used to complete the execution after obtaining the execution result of the second execution action, the first execution action can be the consumer role, and the second execution action can be the producer role.

[0046] When specifically determining the order in which the first execution statement of the first execution action and the second execution statement of the second execution action are written in the execution code snippet, the first execution statement can be written before the second execution statement. The purpose of this is that in an execution cycle 1, the first execution statement written earlier is not executed because it does not obtain the execution result of the second execution statement, while the second execution statement written later can be executed and generate an execution result. Then, in the next execution cycle 2, the first execution statement can obtain the execution result of the second execution statement in the execution cycle 1 and execute. For another example, in an execution cycle 1, the first execution statement written earlier can obtain the execution result of the second execution statement in the previous execution cycle 0 and execute it, while the second execution statement written later can be executed and generate the execution result of the execution cycle 1. Then, in the next execution cycle 2, the first execution statement can obtain the execution result of the second execution statement in the execution cycle 2 and execute it, while the second execution statement can be executed and generate the execution result of the execution cycle 2… If the hardware unit has a large number (greater than 2) of execution actions in the execution cycle, it is possible to find out the execution actions that have dependencies between each other, determine the roles corresponding to each execution action, and write code according to the rule that the execution statement of the consumer role is written before the execution statement of the producer role.

[0047] For example, suppose that hardware unit A includes execution actions a, b, and c, where there is a dependency relationship between execution actions a and b, and there is also a dependency relationship between execution actions b and c. Execution action a needs to obtain the running result of execution action b before it can be executed, and execution action b needs to obtain the running result of execution action c before it can be executed. When writing the execution code snippet of hardware unit A, the execution statement of execution action a is written before the execution statement of execution action b, and the execution statement of execution action b is written before the execution statement of execution action c, that is, the writing order of execution statement a—execution statement b—execution statement c is obtained.

[0048] Step 204: construct a network-on-chip design file based on the execution code snippets of all the hardware units.

[0049] This step may be specifically referred to as the above step 103, which will not be described in detail here.

[0050] Optionally, in one implementation, step 204 may specifically include: Sub-step 2041: Determine the input-output relationship between the hardware units.

[0051] Sub-step 2042: According to the input-output relationship, write result assignment code fragments between the hardware units using the preset compilation language.

[0052] Sub-step 2043: construct the on-chip network design file according to the result assignment code fragment and the execution code fragments of each of the hardware units.

[0053] In the embodiment of the present application, for sub-steps 2041-2043, the network on chip is composed of hardware units. In order to realize data transmission within the network on chip, data interaction is required between the hardware units of the network on chip. Therefore, when constructing the network on chip design file, in addition to writing the execution code snippets of each hardware unit, the result assignment code snippets between the hardware units can also be written in a preset compiled language. The result assignment code snippets are used to control the data interaction between the hardware units in the network on chip. The result assignment code snippets can be specifically written based on the input-output relationship between the hardware units.

[0054] The input-output relationship between hardware units is used to control the data flow between hardware units. For example, assuming there are hardware 1 and hardware 2, if hardware 2 needs the output result of hardware 1, the output value of hardware 2 can be assigned to hardware 1 for use. That is, there is an input-output relationship between hardware 1 and 2. The result assignment code snippet written for hardware 1 and hardware 2 is a code snippet used to implement the process of assigning the output value of hardware 2 to hardware 1 for use.

[0055] Optionally, in another implementation, step 204 may specifically include: Sub-step 2044: construct a calculation code fragment for simulating and calculating the power consumption of the on-chip network according to the static power consumption calculation rule and the dynamic power consumption calculation rule.

[0056] Sub-step 2045: constructing a network-on-chip design file according to the computing code snippet and the respective execution code snippets of all the hardware units.

[0057] In the embodiment of the present application, for sub-steps 2044-2045, the on-chip network design file of the embodiment of the present application also supports simulation calculation of the on-chip network power consumption, and this model can be used to perform accurate performance / power consumption analysis of the on-chip network later.

[0058] Specifically, the simulation calculation of power consumption can be divided into the processes of static power consumption calculation and dynamic power consumption calculation chain. The embodiment of the present application can construct a calculation code snippet for simulating the calculation of the power consumption of the on-chip network according to the static power consumption calculation rules and the dynamic power consumption calculation rules, and add the calculation code snippet to the on-chip network design file.

[0059] Optionally, the static power consumption calculation rule is used to calculate the static power consumption of the hardware unit based on the data bit width of the hardware unit and the corresponding relationship between the preset data bit width and power consumption; the dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit based on the execution actions included in the hardware unit and the action power consumption corresponding to each of the execution actions; the total power consumption of the hardware unit is the sum of the static power consumption and dynamic power consumption of the hardware unit.

[0060] In the embodiment of the present application, the static power consumption calculation is realized by judging which components are in the on-chip network. In hardware, these components are constructed by circuits, and the circuits have leakage current losses, so all components have their own power consumption. In the software simulation of the on-chip network, it can be simplified into several parts: the power consumption of the buffer, the power consumption of the routing module, the power consumption of the direction selection module (selection), and the power consumption of the output module (Crossbar). These power consumptions have a corresponding relationship with the configured data bit width and other data, and the corresponding relationship can be constructed as a mapping table obtained after mathematical calculation. For example, when executing XY routing (a choice of routing module) in the simulation, the static power consumption is 1.20e-4 joules, and if WEST_FIRST routing (another routing module) is selected, the static power consumption is 1.28e-4 joules. For example, if you choose a fifo with a depth of 2 and an entry width of 128 bits (a buffer that follows first-in, first-out), the static power consumption is 5.0e-3 joules. If you choose a fifo with a depth of 4 and an entry width of 256 bits, the static power consumption is 1.64e-2 joules. These power consumption values ​​are known and can be called directly according to the selection.

[0061] Dynamic power consumption is calculated by analyzing the operations performed by all components, including the power consumption of push and pop operations of the buffer, the power consumption of push and pop operations of transferring buffer to tile, the power consumption of push and pop operations of transferring tile to buffer, the power consumption of routing module (power consumption required for each execution), the power consumption of selection module, the power consumption of the cross switch output module, and the power consumption of line transmission (power consumption of transferring flit from a to b). These power consumptions are counted every time the program executes a specific operation to simulate the power consumed by the hardware to perform a specific operation. The calculation of dynamic power consumption is also calculated based on the simulated power consumption calculated in advance. For example, if a fifo with a depth of 2 and an entry bit width of 128 bits is selected (buffer that follows the first-in, first-out principle), the energy consumed when performing a push operation is 2.25e-12 joules, and the energy consumed when performing a pop operation is 1.25e-12 joules. When simulating the on-chip network, this operation will be performed multiple times, and each time it needs to be counted.

[0062] Step 205: simulate the network on chip design file to obtain simulation results.

[0063] This step may specifically refer to the above step 104, which will not be described in detail here.

[0064] In an example, the execution code snippet is written for the hardware unit buffer. The hardware unit buffer can be written into a class, which includes various execution actions, such as push, pop, empty check, full check, etc.

[0065] Assume that according to the dependency between the execution actions, the order of writing the hardware unit buffer is determined as follows: the clock cycle update action is written before the action of setting the buffer capacity, the action of setting the buffer capacity is before the action of checking the maximum capacity of the buffer, the action of checking the maximum capacity of the buffer is before the action of checking how much capacity is left in the buffer, the action of checking how much capacity is left in the buffer is before the action of checking whether the buffer is full, the action of checking whether the buffer is full is before the action of checking whether the buffer capacity is empty, the action of checking whether the buffer capacity is empty is before the action of reporting an error if continuing to push when the buffer is full, and the action of reporting an error if continuing to push when the buffer is full is before the action of reporting an error if continuing to pop when the buffer is empty. The execution code snippets of the hardware unit buffer written include: def Update_cycle(self, clock): self.clock = clock #Clock cycle update function; def SetMaxBufferSize(self,bms): #Set Buffer max size (in flits) assert bms>0 self.max_buffer_size = bms #Function to set the capacity of this buffer; def GetMaxBufferSize(self): #Get max buffer size return self.max_buffer_size #Function to check the maximum capacity of this buffer; def getCurrentFreeSlots(self): #free buffer slots return self.max_buffer_size-len(self.buffer) #A function to check how much capacity is left in this buffer; def IsFull(self): #Returns true if buffer is full return len(self.buffer) == self.max_buffer_size #Check if the buffer is full; def IsEmpty(self): #Returns true if buffer is empty return len(self.buffer) == 0 #Check whether the capacity of this buffer is empty; def Drop(self, flit): #Called by Push() when buffer is full assert False #When the buffer is full, if you continue to push, an error will be reported; def Empty(self): #Called by Pop() when buffer is empty assert False #If you continue to pop when the buffer is empty, an error will be reported.

[0066] Reference Figure 3, which shows the timing logic of the routing module in the on-chip network, wherein the execution actions of the routing module include: input cache action, arbitration action, and distribution action. When writing the execution code snippet of the routing module, the distribution action can be written before the arbitration action based on the dependency relationship between the above actions, and the arbitration action can be written before the input cache action. Specifically, a data packet is selected by the routing strategy, and the routing transmission path based on the routing strategy is calculated, and then it is transmitted from the virtual channel indicated by the routing transmission path. After that, the data packet is arbitrated based on the selected arbitration strategy, and the output distribution channel is used for data distribution, realizing the processing of a data packet by the routing module.

[0067] Further references Figure 4 , which shows the code structure of the routing module in the on-chip network, including: arbitration submodule, input / output queue, local routing table, routing submodule, data verification submodule, switch allocation submodule, and distribution submodule.

[0068] Further references Figure 5 , which shows the structure of a node of the on-chip network, including: a routing module and a processing unit, and the routing module and the processing unit are connected via a transmission protocol.

[0069] Further references Figure 6 , which shows the connection mode between nodes of the on-chip network, wherein the nodes are connected to each other through a transmission protocol and a judgment module, and the judgment module is used to judge whether the current destination routing module has idle positions to process data.

[0070] Final reference Figure 7 , which shows the structure of the on-chip network. It can be seen that the on-chip network consists of an array structure consisting of multiple nodes ( Figure 7 The 4×4 specification is used in the figure), which enables the horizontal and vertical (X / Y direction) transmission of data within the on-chip network.

[0071] In summary, in the embodiment of the present application, the execution code snippets of each hardware unit in the execution cycle can be constructed by a preset compilation language according to the execution actions included in the hardware unit in the on-chip network, and the on-chip network design file can be constructed according to the respective execution code snippets of all hardware units, so as to simulate and run the on-chip network design file to obtain the simulation operation result. The embodiment of the present application can use the execution cycle as an index to simulate all the execution actions of the hardware unit in each execution cycle, and the migration of the execution actions occurs over time, so as to simulate the flow of the execution actions of the hardware unit in the execution cycle through the scheduling of the simulation process, so that the design file of the entire on-chip network can be constructed more meticulously.

[0072] Figure 8: is a block diagram of an on-chip network simulation device provided by an embodiment of the present application, the device comprising: A determination module 301 is used to determine various hardware units used to constitute the on-chip network, and to determine the execution actions included in the hardware units in each execution cycle; A first construction module 302 is used to construct an execution code segment of each hardware unit in the execution cycle by using a preset compilation language according to the execution actions included in the hardware unit; A second construction module 303 is used to construct a network on chip design file according to the execution code fragments of all the hardware units; The operation module 304 is used to perform simulation operation on the on-chip network design file to obtain simulation operation results.

[0073] Optionally, the first building module 302 includes: A dependency determination submodule, used to determine the dependency relationship between the execution actions; The first writing submodule is used to construct the execution code fragment of each hardware unit in the execution cycle through a preset compilation language according to the dependency relationship.

[0074] Optionally, the execution action includes a first execution action and a second execution action having a dependency relationship; The first writing submodule includes: A first writing unit is used to write, in the execution code fragment, a first execution statement corresponding to the first execution action and a second execution statement corresponding to the second execution action by using the preset compilation language; The second writing unit is used to determine the writing order of the first execution statement and the second execution statement in the execution code fragment according to the dependency relationship, so as to construct the execution code fragment of the hardware unit in the execution cycle.

[0075] Optionally, the dependency relationship is: the first execution action is used to complete execution after obtaining the execution result of the second execution action; The second writing unit includes: The writing subunit writes the first execution statement before the second execution statement in the execution code fragment.

[0076] Optionally, the second building block 303 includes: A determination submodule, used to determine the input-output relationship between the hardware units; A third writing submodule is used to write the result assignment code fragments between the hardware units in the preset compilation language according to the input-output relationship; The first construction submodule is used to construct the on-chip network design file according to the result assignment code fragment and the execution code fragments of each of the hardware units.

[0077] Optionally, the second building module 303 includes: A second construction submodule is used to construct a calculation code fragment for simulating and calculating the power consumption of the on-chip network according to a static power consumption calculation rule and a dynamic power consumption calculation rule; The third construction submodule is used to construct an on-chip network design file according to the computing code fragment and the execution code fragments of all the hardware units.

[0078] Optionally, the static power consumption calculation rule is used to calculate the static power consumption of the hardware unit according to the data bit width of the hardware unit and the corresponding relationship between the preset data bit width and power consumption; The dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit according to the execution actions included in the hardware unit and the action power consumption corresponding to each of the execution actions; The total power consumption of the hardware unit is the sum of the static power consumption and the dynamic power consumption of the hardware unit.

[0079] In summary, in the embodiment of the present application, the execution code snippets of each hardware unit in the execution cycle can be constructed by a preset compilation language according to the execution actions included in the hardware unit in the on-chip network, and the on-chip network design file can be constructed according to the respective execution code snippets of all hardware units, so as to simulate and run the on-chip network design file to obtain the simulation operation result. The embodiment of the present application can use the execution cycle as an index to simulate all the execution actions of the hardware unit in each execution cycle, and the migration of the execution actions occurs over time, so as to simulate the flow of the execution actions of the hardware unit in the execution cycle through the scheduling of the simulation process, so that the design file of the entire on-chip network can be constructed more meticulously.

[0080] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0081] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0082] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0083] An embodiment of the present application provides an on-chip network simulation device, including a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to include methods for performing one or more of the above embodiments.

[0084] Fig. 9 is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0085] Reference Fig. 9 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0086] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 602 may include one or more modules to facilitate the interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate the interaction between the multimedia component 608 and the processing component 602.

[0087] The memory 604 is used to store various types of data to support the operation of the electronic device 600. Examples of such data include instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, multimedia, etc. The memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0088] The power supply component 606 provides power to the various components of the electronic device 600. The power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0089] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0090] The audio component 610 is used to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), and when the electronic device 600 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 604 or sent via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0091] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0092] The sensor assembly 614 includes one or more sensors for providing various aspects of status assessment for the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of the components, such as the display and keypad of the electronic device 600, and the sensor assembly 614 can also detect the position change of the electronic device 600 or a component of the electronic device 600, the presence or absence of contact between the user and the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and the temperature change of the electronic device 600. The sensor assembly 614 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 614 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0093] The communication component 616 is used to facilitate wired or wireless communication between the electronic device 600 and other devices. The electronic device 600 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0094] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement the methods provided in the embodiments of the present application.

[0095] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, and the instructions can be executed by a processor 620 of an electronic device 600 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0096] Fig.10 is a block diagram of an electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be provided as a server. Fig.10 The electronic device 700 includes a processing component 722, which further includes one or more processors, and a memory resource represented by a memory 732 for storing instructions that can be executed by the processing component 722, such as an application. The application stored in the memory 732 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 722 is configured to execute instructions to perform the method provided in the embodiment of the present application.

[0097] The electronic device 700 may also include a power supply component 726 configured to perform power management of the electronic device 700, a wired or wireless network interface 750 configured to connect the electronic device 700 to a network, and an input / output (I / O) interface 758. The electronic device 700 may operate based on an operating system stored in the memory 732, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, FreeBSD TM or the like.

[0098] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0099] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0100] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A network-on-chip simulation method, characterized in that: The method comprises: Determine each hardware unit used to constitute the on-chip network, and determine the execution actions included in the hardware unit in each execution cycle; According to the execution actions included in the hardware units, constructing the execution code fragments of each hardware unit in the execution cycle by using a preset compilation language; Constructing a network-on-chip design file according to the respective execution code snippets of all the hardware units; The on-chip network design file is simulated and run to obtain a simulation result.

2. The on-chip network simulation method according to claim 1, characterized in that: The step of constructing the execution code fragment of each hardware unit in the execution cycle by using a preset compilation language according to the execution actions included in the hardware unit includes: Determining dependencies between the execution actions; According to the dependency relationship, an execution code segment of each hardware unit in the execution cycle is constructed by using a preset compilation language.

3. The on-chip network simulation method according to claim 2, characterized in that: The execution action includes a first execution action and a second execution action having a dependency relationship; The step of constructing the execution code fragment of each hardware unit in the execution cycle by using a preset compilation language according to the dependency relationship includes: In the execution code snippet, a first execution statement corresponding to the first execution action and a second execution statement corresponding to the second execution action are written in the preset compilation language; According to the dependency relationship, the writing order of the first execution statement and the second execution statement in the execution code fragment is determined, so as to construct the execution code fragment of the hardware unit in the execution cycle.

4. The on-chip network simulation method according to claim 3, characterized in that: The dependency relationship is: the first execution action is used to complete execution after obtaining the execution result of the second execution action; The step of determining the writing order of the first execution statement and the second execution statement in the execution code fragment according to the dependency relationship includes: In the execution code snippet, the first execution statement is written before the second execution statement.

5. The on-chip network simulation method according to claim 1, characterized in that: The on-chip network design file is constructed based on the respective execution code fragments of all the hardware units, including: Determining input-output relationships between the hardware units; According to the input-output relationship, writing result assignment code fragments between the hardware units by using the preset compilation language; The on-chip network design file is constructed based on the result assignment code fragment and the execution code fragments of each of the hardware units.

6. The on-chip network simulation method according to claim 1, characterized in that: The on-chip network design file is constructed based on the respective execution code fragments of all the hardware units, including: According to the static power consumption calculation rule and the dynamic power consumption calculation rule, construct a calculation code fragment for simulating and calculating the power consumption of the on-chip network; An on-chip network design file is constructed based on the computing code snippet and the respective execution code snippets of all the hardware units.

7. The on-chip network simulation method according to claim 6, characterized in that: The static power consumption calculation rule is used to calculate the static power consumption of the hardware unit according to the data bit width of the hardware unit and the corresponding relationship between the preset data bit width and power consumption; The dynamic power consumption calculation rule is used to calculate the dynamic power consumption of the hardware unit according to the execution actions included in the hardware unit and the action power consumption corresponding to each of the execution actions; The total power consumption of the hardware unit is the sum of the static power consumption and the dynamic power consumption of the hardware unit.

8. A network-on-chip simulation device, characterized in that: The device comprises: A determination module, used to determine various hardware units used to constitute the on-chip network, and to determine execution actions included in the hardware units in each execution cycle; A first construction module is used to construct an execution code segment of each hardware unit in the execution cycle by using a preset compilation language according to the execution actions included in the hardware unit; A second construction module is used to construct a network-on-chip design file according to the respective execution code fragments of all the hardware units; The running module is used to simulate the on-chip network design file to obtain the simulation running result.

9. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 7.

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