Synchronous circuit driven by multiple power tubes in parallel

Abstract

The invention discloses a multi-power tube parallel driving synchronous circuit, which relates to the technical field of driving circuits, and comprises a plurality of driving branches connected with a plurality of power tubes in a one-to-one correspondence manner; the common resistor is connected with each driving branch in series; the first differential sampling circuit is used for collecting the terminal voltage of the common resistor; each driving branch comprises a discrete resistor which is connected in series between the corresponding power tube and the common resistor. The second differential sampling circuit is used for collecting the terminal voltage of the discrete resistor; the comparator circuit is used for comparing the terminal voltage of the common resistor with the terminal voltage of the discrete resistor and outputting a positive level when a preset condition is met, otherwise, outputting a negative level; the equalization triodes are used for being turned on when receiving the positive level so as to enable the corresponding power tubes to discharge reversely; when receiving the negative level, the power tube is turned off, and current flows through the discrete resistor to charge the corresponding power tube; according to the invention, the consistency of a plurality of power tube parallel switches can be improved, and asynchronous driving is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of drive circuits, and in particular to a multi-power tube parallel drive synchronous circuit. Background Art

[0002] With the increase of power level, the parallel use of power MOS tubes has increased in consideration of cost and power density requirements. However, there is little research in this area. For power imbalance and other situations, most of them use large margin devices and connect 2-3 MOS tubes in parallel, and the number of parallel connections is small. When the number of parallel connections is large, there will be problems of asynchronous triggering and drive oscillation. When multiple MOS tubes are connected in parallel, due to the differences in the MOS tubes themselves and the differences in parasitic parameters caused by PCB wiring, multiple MOS tubes cannot be turned on synchronously when multiple tubes are connected in parallel, resulting in time delay.

[0003] At present, in the existing parallel schemes, the parallel drive circuit solves the problem of drive asynchrony and drive oscillation mainly in two directions: 1. Isolate the parallel drive. This method is mainly aimed at the oscillation direct pass caused by the consistency difference of MOS tubes during the parallel opening process. Generally, a larger power device is selected. The selected power tube (MOS tube) has a larger margin to overcome the transient voltage stress caused by its asynchrony. The focus is on solving the parallel balanced current after opening and reducing its thermal stress risk. The requirements for the peak stress caused by the switch asynchrony are not high and no optimization is made; 2. The drive is not isolated. The multi-channel drive is uniformly driven by the drive chip. Devices such as inductors are connected in series in the drive circuit to suppress the problem of drive asynchrony. When a MOS tube is quickly turned on, its inductor suppresses the current mutation, reduces its switching speed, and thus suppresses the inconsistency of the parallel power tube opening.

[0004] However, the above-mentioned parallel scheme cannot effectively suppress the problems of drive asynchrony and drive oscillation when more devices are connected in parallel. It is still necessary to rely on the consistency of the power tube itself and its own high-quality parameters to overcome the impact during the parallel opening process, which is bound to increase costs; especially when the production consistency of the selected power tube is poor, it is easy to cause drive resonance and bridge arm direct connection, which poses a challenge to the reliability of the product. Summary of the invention

[0005] In order to solve the problems existing in the prior art, the present invention provides a multi-power tube parallel drive synchronization circuit, which can improve the consistency of multiple power tube parallel switches, avoid drive asynchrony and drive oscillation, thereby reducing device stress and improving product reliability.

[0006] To achieve the above object, the present invention provides a multi-power tube parallel drive synchronization circuit, which is arranged at the input end of multiple power tubes in parallel, and the multi-power tube parallel drive synchronization circuit includes: A plurality of driving branches are connected to the plurality of power tubes in a one-to-one correspondence; A common resistor connected in series with each of the driving branches; A first differential sampling circuit, used for collecting the terminal voltage of the common resistor; Wherein, any of the driving branches comprises: A discrete resistor is arranged in series between the corresponding power tube and the common resistor; A second differential sampling circuit, used for collecting the terminal voltage of the discrete resistor; A comparator circuit, used for comparing the terminal voltage of the common resistor with the terminal voltage of the discrete resistor, and outputting a positive level when a preset condition is met, otherwise outputting a negative level; the preset condition includes that the terminal voltage of the discrete resistor is greater than the terminal voltage of the common resistor; The balancing transistor is used to turn on when receiving the positive level to make the corresponding power tube discharge in reverse; and turn off when receiving the negative level to make the current flow through the discrete resistor to charge the corresponding power tube.

[0007] Optionally, the preset condition further includes: a difference between a terminal voltage of the discrete resistor and a terminal voltage of the common resistor is greater than a preset margin.

[0008] Optionally, the first differential sampling circuit includes a first resistor and a first operational amplifier; One end of the first resistor is connected to the negative input terminal of the first operational amplifier, and the other end is connected to the output terminal of the first operational amplifier; the negative input terminal of the first operational amplifier is connected to the voltage input terminal and one end of the common resistor, the positive input terminal is connected to the other end of the common resistor and one end of the discrete resistor, and the output terminal is connected to the negative input terminal of the comparator circuit.

[0009] Optionally, the second differential sampling circuit includes a second resistor and a second operational amplifier; One end of the second resistor is connected to the negative input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier; the negative input terminal of the second operational amplifier is connected to the other end of the common resistor and one end of the discrete resistor, the positive input terminal is connected to the other end of the discrete resistor, and the output terminal is connected to the positive input terminal of the comparator circuit.

[0010] Optionally, the gate of the power tube is connected to the other end of the corresponding discrete resistor, the source is connected to one end of the parallel capacitor, and the drain is connected to the other end of the parallel capacitor through a third resistor.

[0011] Optionally, the base of the balancing transistor is connected to the output end of the comparator circuit, the collector is connected to one end of the discrete resistor, and the emitter is connected to one end of the parallel capacitor.

[0012] The present invention also provides a multi-power tube parallel drive synchronization circuit, which is arranged at the input end of a plurality of power tubes connected in parallel, and the multi-power tube parallel drive synchronization circuit comprises: A plurality of branch resistors are connected to the plurality of power tubes in a one-to-one correspondence; The common-circuit resistor has one end connected to the voltage input terminal and the other end connected in series with each of the branch resistors.

[0013] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects: The multi-power tube parallel drive synchronous circuit provided by the present invention not only divides the driving resistance of the power tube into a common resistance and a discrete resistance, and uses an open-loop method to suppress the difference in the parallel opening of the power tubes, but also uses a differential sampling circuit, a comparator circuit and a balancing transistor to form a negative feedback loop, so that the power tube that is first turned on triggers the bypass, and the power tube will be intermittently closed and reopened during the entire opening process. Finally, after all the switch differences caused by the consistency of peripheral devices and routing are overcome, wait for other power tubes to be turned on synchronously, thereby reducing the opening difference, so that the parallel power tubes maintain a high consistency when turned on, avoid driving oscillation caused by the opening timing difference, and even the phenomenon of upper and lower bridge arms passing through and stress imbalance, thereby improving the reliability of the overall product. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0015] Figure 1 The hardware topology diagram of the power tube parallel drive synchronous circuit shown in the embodiment of the present invention; Figure 2 Schematic diagram of a differential sampling circuit according to an embodiment of the present invention; wherein FIG. (2a) is a schematic diagram of a first differential sampling circuit, and FIG. (2b) is a schematic diagram of a second differential sampling circuit; Figure 3 An equivalent circuit diagram of multi-channel MOS tube parallel driving shown in an embodiment of the present invention; Figure 4 This is a simulation waveform diagram of multiple MOS tubes connected in parallel without a shared resistor shown in an embodiment of the present invention; Figure 5 This is a simulation waveform diagram of turning on and off of a multi-channel MOS tube without a shared resistor shown in an embodiment of the present invention; Figure 6 This is a simulation waveform diagram of multiple MOS tubes connected in parallel and turned on with a common resistance of 4.5Ω shown in an embodiment of the present invention; Figure 7 This is a simulation waveform diagram of the parallel shutdown of multiple MOS tubes with a common resistance of 4.5Ω shown in an embodiment of the present invention. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Currently, many products have a small number of power tubes connected in parallel, with 2-3 being the most common. As product grades improve, device manufacturers are also gradually launching large-package, high-power devices. However, there is relatively little research on power tube paralleling. Instead, there is more research on reasonable PCB layout based on experience, and on device consistency when purchasing devices. Currently, there is no solution that can achieve synchronous switching of multiple parallel power tubes through fine control in principle.

[0018] In addition, the existing power tube parallel connection scheme is not perfect. When the number of parallel connections is large, it is easy to cause driving oscillation and over-reliance on the manufacturing consistency of the power tube itself. Especially when there are devices with small usage within certain specification ranges, their own consistency is poor, which can easily further amplify the parallel defects, causing the parallel power tube to oscillate and even increase the risk of bridge arm direct conduction.

[0019] In order to solve the problem that when multiple power tubes are connected in parallel, the tubes cannot be turned on synchronously and there is a time delay due to the differences in parasitic parameters caused by the differences in the power tubes themselves and PCB wiring. The present invention provides a multi-power tube parallel drive synchronization circuit, which can improve the consistency of the parallel opening of multiple power tubes and avoid drive asynchronism and drive oscillation.

[0020] See also Figure 1 , Figure 1 This is the hardware topology diagram of the power tube parallel drive synchronous circuit.

[0021] The above-mentioned multi-power tube parallel driving synchronous circuit is arranged at the input end of the plurality of power tubes connected in parallel, and the multi-power tube parallel driving synchronous circuit comprises: Multiple driving branches are connected to multiple power tubes in a one-to-one correspondence; A common resistor is connected in series with each driving branch; A first differential sampling circuit, used for collecting the terminal voltage of the shared resistor; Wherein, any driving branch includes: Discrete resistors are arranged in series between the corresponding power tubes and the common resistor; A second differential sampling circuit, used for collecting the terminal voltage of the discrete resistor; A comparator circuit, used for comparing the terminal voltage of the common resistor with the terminal voltage of the discrete resistor, and outputting a positive level when a preset condition is met, otherwise outputting a negative level; the preset condition includes that the terminal voltage of the discrete resistor is greater than the terminal voltage of the common resistor; The balancing transistor is used to turn on when receiving a positive level to make the corresponding power tube discharge in reverse; and turn off when receiving a negative level to allow current to flow through a discrete resistor to charge the corresponding power tube.

[0022] like Figure 1 As shown, Figure 1 Six parallel power tubes (MOS1 to MOS6) are shown in the figure. Multiple parallel power tubes are provided with multiple differential sampling drive branches, and each drive branch supplies power to the corresponding power tube. The present invention divides the drive resistor of the previous parallel drive circuit into a common drive resistor R_com (common resistor) and discrete resistors in each drive branch. The common resistor is connected in series with multiple parallel drive branches. The first differential sampling circuit is used to perform differential sampling to obtain the terminal voltage of the common resistor; the second differential sampling circuit in the drive branch obtains the terminal voltage of the discrete resistor through differential sampling; the comparator circuit outputs the corresponding positive and negative levels according to the voltage difference between the common resistor and the discrete resistor, and the balancing transistor (hereinafter referred to as the transistor) is opened and closed according to the positive and negative levels, so that the corresponding drive branch is bypassed and turned on, and the power tube is reversely discharged and charged accordingly.

[0023] Figure 1 The structure of the parallel drive synchronous circuit is embodied in Figure 2 for Figure 1 2 is a partial enlarged schematic diagram, wherein FIG (2a) corresponds to the first differential sampling circuit, and FIG (2b) corresponds to the second differential sampling circuit of the discrete resistor R1. In the application, the specific differential sampling circuit construction configuration can be designed in detail according to the sampling parameters; in addition, Figure 1 The number of parallel power tubes is 6, which is an exemplary description. The number of power tubes in actual applications is not limited to this.

[0024] In one embodiment, the first differential sampling circuit includes a first resistor and a first operational amplifier; one end of the first resistor is connected to the negative input terminal of the first operational amplifier, and the other end is connected to the output terminal of the first operational amplifier; the negative input terminal of the first operational amplifier is connected to the voltage input terminal and one end of the common resistor, the positive input terminal is connected to the other end of the common resistor and one end of the discrete resistor, and the output terminal is connected to the negative input terminal of the comparator circuit.

[0025] The second differential sampling circuit includes a second resistor and a second operational amplifier; one end of the second resistor is connected to the negative input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier; the negative input terminal of the second operational amplifier is connected to the other end of the common resistor and one end of the discrete resistor, the positive input terminal is connected to the other end of the discrete resistor, and the output terminal is connected to the positive input terminal of the comparator circuit.

[0026] The gate of the power tube is connected to the other end of the corresponding discrete resistor, the source is connected to one end of the parallel capacitor, and the drain is connected to the other end of the parallel capacitor through the third resistor.

[0027] The base of the balancing transistor is connected to the output end of the comparator circuit, the collector is connected to one end of the discrete resistor, and the emitter is connected to one end of the parallel capacitor.

[0028] In one embodiment, the preset condition includes not only that the terminal voltage of the discrete resistor is greater than the terminal voltage of the common resistor, but also that the difference between the terminal voltage of the discrete resistor and the terminal voltage of the common resistor is greater than a preset margin.

[0029] For example, assuming that the driving resistance of each power tube is 7Ω according to the driving parameter selection, if the common resistance R_com is set to 2Ω, then the discrete resistance in a branch is R1=5Ω. Figure 1 A 6-tube parallel driving method is adopted. If the current is equalized, the terminal voltage sampling value of R_com and the terminal voltage sampling ratio of R1 are: VR_com:VR1=2 / (5 / 6)=12:5. If there is a completely synchronous opening in a strict sense, the terminal voltage result of the differential sampling satisfies 12:5. Therefore, when configuring the differential sampling circuit, the sampling voltages of R_com and R1 are proportionally scaled so that their final ratio after scaling satisfies 1:1, and then the DC bias is superimposed to ensure that the sampling result is still positive when it is turned off (this circuit will not be repeated).

[0030] Among them, the ratio of 1:1 is the theoretical ratio. In actual design, there may be a margin, such as designing according to 120%, etc., and retaining a certain margin. If the sampling voltage of the driving branch (the terminal voltage of the discrete resistor) exceeds 120% of the theoretical value, the comparator circuit will trigger the action again, and the actual margin (preset margin) can be flexibly set according to the debugging results. The input superimposed DC bias is because the op amp sampling circuit has requirements for the input signal, and the input voltage must be positive. Based on this, a bias circuit is added to the op amp input to make its input voltage meet the sampling requirements.

[0031] Combine the following Figure 1 The operating principle of the above parallel drive synchronous circuit is further explained: If the drive is turned on due to device consistency differences, such as the power tube MOS2 is turned on first (or its turn-on speed is better than others), the current flowing through it is very large, which will inevitably cause the sampled voltages at both ends of R_com and R2 to deviate greatly from the theoretical values. At this time, the sampled voltage at the R2 end (the terminal voltage of the discrete resistor) will seriously exceed the standard; then, the sampled voltage at the R2 end is compared with the terminal voltage after sampling and conditioning by R_com, the comparator circuit outputs a positive level, the transistor is turned on, and the entire drive circuit is bypassed (the drive branch where R2 is located is bypassed); at the same time, the charged voltage of MOS2 is also discharged in the reverse direction, but the process lasts for a very short time. Once no current flows through R2, the sampled voltage at the R2 end will inevitably be 0, the comparator circuit level is reversed and outputs a negative level, the transistor is turned off, and MOS2 continues to charge, and this reciprocating balance forms a closed-loop feedback. If the number of MOS tubes reaches 6 in parallel, when 3 to 4 power tubes are turned on first, whether the driver branch bypass will continue to be triggered depends on the preset margin set when the sampling ratio is designed. Whether the bypass will be triggered is determined based on the margin left for each driver branch. In this process, there are repeated bypasses and recharging until all power tubes are turned on synchronously within the margin range.

[0032] In addition, even if MOS2 is still turned on faster due to the margin left by the design and the power tube itself is turned on first, its charging current will inevitably decrease. Because of the existence of the split resistor, the open-loop effect will also inhibit its subsequent turning on and gradually slow down (this will be explained in detail later), further reducing the difference and making the power tube switch drive synchronous.

[0033] The present invention optimizes the conventional driving circuit, adds a switch suppression function, samples the driving signal for the current difference flowing through the driving resistor when turned on, and builds a negative feedback loop at the operational amplifier end, so that the power tube that is turned on first triggers the bypass. During the entire turning-on process of the power tube, the driver will intermittently bypass the MOS tube driver that is turned on faster according to the actual turning-on difference of the MOS, and finally turn it back on. Finally, after all the switch differences caused by the consistency of peripheral devices and routing are overcome, wait for other power tubes to be turned on synchronously, thereby reducing the turning-on difference, so that the parallel power tubes maintain a high consistency when turned on, avoid driving oscillation caused by the turning-on timing difference, and even the phenomenon of direct connection of the upper and lower bridge arms and stress imbalance, thereby improving the reliability of the overall product.

[0034] In the design, in addition to the closed-loop op amp sampling and transistors that will synchronize the switching of the switch tube in the closed loop, the driving resistance division idea itself shares the resistance (R_com), and the branch resistance (R1, R2, etc.) itself will promote the driving synchronous switching in an open-loop manner.

[0035] Correspondingly, the present invention also provides a multi-power tube parallel drive synchronization circuit, which is arranged at the input end of multiple power tubes in parallel, and the multi-power tube parallel drive synchronization circuit includes: Multiple branch resistors are connected to multiple power tubes in a one-to-one correspondence; The common-circuit resistor has one end connected to the voltage input terminal and the other end connected in series with each branch resistor.

[0036] The following is an explanation of the principle of using open-loop action to improve the driving consistency of parallel power tubes: In the application, although there is no closed-loop feedback to synchronize the drive, it is also effective for the synchronous opening of multi-tube parallel drives by relying on the hardware-driven resistance division method.

[0037] For details, please see Figure 3 , Figure 3 The equivalent circuit diagram of multi-channel MOS tube parallel driving (the figure shows 6 groups of parallel driving power tubes by way of example). When there is no shared driving resistor, that is, R15=0, the model is established to simulate the parasitic parameters of MOS when multiple tubes are connected in parallel in the form of capacitance parameter differences, and the simulation is performed through circuit simulation software. The actual simulation results show that when R15=0, each branch resistance such as R14 is set to 40Ω, if the Vgs=4V of MOS is used as the turn-on voltage, under the same difference (consistent parasitic capacitance parameter difference), when the Vgs=4V of the typical value (11nF) tube, the maximum and minimum Vgs of the remaining MOS tubes when turned on are: 5.2V and 3.2V respectively (such as Figure 4The non-synchronous phenomenon of the drive is very obvious. Similarly, when the device and simulation model parameters remain unchanged, when the typical value (11nF) tube Vgs = 4V, the maximum and minimum Vgs of the other MOS tubes when the switch is turned off are: 5.34V and 2.46V (such as Figure 5 The asynchronous driving phenomenon is very obvious.

[0038] When following the current new synchronization design ideas: For details, please refer to Figure 3 , is the case where there is a shared driving resistor, that is, Figure 3 The resistance of R15 is not equal to 0; the simulation parameters selected for this time are R15=4.5Ω, and the resistance of each branch is 13Ω; it should be noted that: 6 tubes in parallel R15=4.5Ω, the branch resistance is 13Ω, which is equivalent to the branch resistance of 40Ω when there is no shared drive resistance (the comparison is based on the consistent resistance value of the equivalent drive resistance).

[0039] For the new scheme of the present invention: the method of splitting the driving resistor is adopted. If the branch where R14 is located (due to the difference in device parasitic parameters) is opened first, the charging energy of the branch that is opened first is subject to the influence of the branch that is opened later, Vcc-VR_15-VR_14. At this time, although MOS1 is opened first, as other branches are opened, the VR_15 voltage increases, which slows down the charging rate of MOS1 (the equivalent MOS of the branch where R14 is located); for the branch that is opened later, the branch is opened first at this time, the driving current is small, and the coupling effect is very low. It is equivalent to opening a branch that is charged separately, and it can be opened at a faster speed throughout the whole process, making up for the lag under the line impedance and reducing the difference between the drive openings; similarly, when analyzing the shutdown, synchronous suppression can also be achieved to ensure that the parallel power tubes are shut down more synchronously.

[0040] For further information, see Figure 6 and Figure 7 , Figure 6 for Figure 3 The simulation waveform of multi-channel MOS tubes connected in parallel when the common resistance is equal to 4.5Ω. Figure 7 for Figure 3 The simulation waveform of multi-channel MOS tube parallel shutdown when the common resistance is equal to 4.5Ω.

[0041] Comparison Figure 4 ,like Figure 6As shown in the figure, the open-loop drive difference waveform of the current design still has differences due to differences in its own devices and wiring, and differences in the parasitic parameters of the power tube in parallel. However, compared with independent driving resistance, under relative tube parameters (the equivalent capacitance model remains consistent), when the tube Vgs=4V at the typical value (11nF), the difference between the maximum and minimum voltages of the other MOS tubes at this time is significantly reduced. It can be seen that the open-loop effect can suppress the open-loop differences of multiple tubes in parallel.

[0042] When the idea of ​​driving division provided by the new solution of the present invention is adopted (here only 6 tubes are shown in parallel, and it can be known by the same logic that more tubes are connected in parallel, the voltage drop of R15 is larger, the single branch is more coupled by the other branches, and the synchronization effect is better), due to the existence of the common resistor R15, when the power tube MOS1 is turned off first, coupling is caused. As other branches are gradually turned off, the VR_15 voltage increases, which slows down the discharge rate of the power tube 1. However, at this time, the influence on the branch tube turned off after the power tube is slightly smaller, which is in the just-turned-off stage and has a larger turn-off current. Figure 5 ,like Figure 7 As shown in the figure, the turn-off drive difference waveform under the open-loop action of the current design is significantly reduced compared to the independent drive resistance. Under the relative tube parameters (the equivalent capacitance model remains consistent), when the tube Vgs=4V at the typical value (11nF), the difference between the maximum and minimum voltages of the other MOS tubes at this time is significantly reduced. It can be seen that the open-loop effect can also suppress the turn-off difference of multiple tubes in parallel.

[0043] It should be noted that the design circuit itself relies on the open-loop method of resistor division to suppress the drive synchronization difference, so that the turn-on and turn-off differences of the parallel power tubes are reduced. It is combined with the closed-loop feedback synchronization composed of the aforementioned op amp sampling and triode combination, which makes it have a better advantage in the design end, and its drive synchronization performance is more obvious.

[0044] When designing the circuit, the present invention takes into account various factors such as the switching frequency, device specifications and consistency during the actual product operation process, and adjusts the circuit structure accordingly according to different application scenarios. By appropriately increasing the coupling relationship between the parallel drives of the power tubes, the asynchronous opening phenomenon caused by the consistency differences between the power tubes themselves and the layout devices is suppressed.

[0045] The advantages of the parallel drive synchronization circuit provided by the present invention are further described below from various perspectives: 1) Cost: Currently, most major power devices are products of foreign giants such as Infineon, Semiconductor, ST, and Cree. The price cost of the same type of devices is about 2-3 times or even more than that of domestic devices such as New Clean Energy, China Resources Microelectronics, and Core Control Source. If a product has a large number of parallel devices in an application, taking a domestic power tube with a single tube price of 15 yuan as an example, if the consistency of domestic devices is too different and the consistency of parallel drive cannot be guaranteed, and foreign devices are selected, the cost per tube will increase by at least 20 yuan. If the new circuit provided by the present invention is adopted, using differential sampling plus a closed-loop negative feedback loop, the increase in the cost of a single tube will be less than 20 yuan. Therefore, in certain power level occasions, the power parallel drive synchronous circuit of the present invention has obvious cost advantages, which is convenient for domestic substitution and cost reduction.

[0046] 2) Functional performance: It has been pointed out in the above principle analysis that the power tube parallel drive synchronization circuit provided by the present invention, in principle, adopts the form of bypassing the drive branch through differential sampling and forming a closed-loop negative feedback, so that the power tube is gradually charged, and then multiple power tubes in parallel are turned on synchronously, and the parallel power tubes are synchronously driven from the source. Compared with relying solely on the good consistency and high-quality parameters of the power tube itself to overcome the influence of driving differences, it has greater advantages. If this solution is adopted under the power tube with good consistency, the selection parameters can be further saved; For example, if the driving peak is large due to asynchronous oscillation (the 20V driving level specification and 30V cost and tube are very different), the switching peak is even larger (the switching peak is proportional to the power tube current. If they cannot be opened and closed at the same time, one of the devices will inevitably be subjected to a larger current on and off, and its voltage stress will inevitably be greater, resulting in a larger margin for device selection), which will inevitably increase the cost. Therefore, if this solution is adopted under devices with better consistency, it can also simultaneously improve performance and reduce selection pressure.

[0047] At the same time, the designed circuit also suppresses the difference in the opening of parallel power tubes in the open loop by driving the resistor division. Compared with the existing solution, the designed circuit has a better effect.

[0048] 3) Feasibility: The power tube parallel drive synchronization circuit provided by the present invention has great advantages in circuit principle. The design circuit can not only synchronize the switch of the drive in a closed-loop form by increasing the operational amplifier sampling, but also its own resistance division idea also optimizes the drive synchronization. It simply suppresses the opening difference in the open-loop level in the form of shared resistance and road resistance. Therefore, the solution provided by the present invention can be selected and adjusted according to the actual application scenario. The circuit has obvious advantages in the design end for solving the drive synchronization of multiple tubes in parallel and has strong feasibility.

[0049] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A multi-power tube parallel drive synchronous circuit, characterized in that: The circuit is arranged at the input end of a plurality of power tubes connected in parallel, and the plurality of power tubes connected in parallel drive synchronous circuit comprises: A plurality of driving branches are connected to the plurality of power tubes in a one-to-one correspondence; A common resistor connected in series with each of the driving branches; A first differential sampling circuit, used for collecting the terminal voltage of the common resistor; Wherein, any of the driving branches comprises: A discrete resistor is arranged in series between the corresponding power tube and the common resistor; A second differential sampling circuit, used for collecting the terminal voltage of the discrete resistor; A comparator circuit, used for comparing the terminal voltage of the common resistor with the terminal voltage of the discrete resistor, and outputting a positive level when a preset condition is met, otherwise outputting a negative level; the preset condition includes that the terminal voltage of the discrete resistor is greater than the terminal voltage of the common resistor; The balancing transistor is used to turn on when receiving the positive level to make the corresponding power tube discharge in reverse; and turn off when receiving the negative level to make the current flow through the discrete resistor to charge the corresponding power tube.

2. A multi-power tube parallel drive synchronous circuit according to claim 1, characterized in that: The preset condition also includes: a difference between a terminal voltage of the discrete resistor and a terminal voltage of the common resistor is greater than a preset margin.

3. The multi-power tube parallel drive synchronous circuit according to claim 1, characterized in that: The first differential sampling circuit includes a first resistor and a first operational amplifier; One end of the first resistor is connected to the negative input terminal of the first operational amplifier, and the other end is connected to the output terminal of the first operational amplifier; the negative input terminal of the first operational amplifier is connected to the voltage input terminal and one end of the common resistor, the positive input terminal is connected to the other end of the common resistor and one end of the discrete resistor, and the output terminal is connected to the negative input terminal of the comparator circuit.

4. A multi-power tube parallel drive synchronous circuit according to claim 3, characterized in that: The second differential sampling circuit includes a second resistor and a second operational amplifier; One end of the second resistor is connected to the negative input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier; the negative input terminal of the second operational amplifier is connected to the other end of the common resistor and one end of the discrete resistor, the positive input terminal is connected to the other end of the discrete resistor, and the output terminal is connected to the positive input terminal of the comparator circuit.

5. The multi-power tube parallel driving synchronous circuit according to claim 4, characterized in that: The gate of the power tube is connected to the other end of the corresponding discrete resistor, the source is connected to one end of the parallel capacitor, and the drain is connected to the other end of the parallel capacitor through a third resistor.

6. The multi-power tube parallel driving synchronous circuit according to claim 5, characterized in that: The base of the balancing transistor is connected to the output end of the comparator circuit, the collector is connected to one end of the discrete resistor, and the emitter is connected to one end of the parallel capacitor.

7. A multi-power tube parallel drive synchronous circuit, characterized in that: The circuit is arranged at the input end of a plurality of power tubes connected in parallel, and the plurality of power tubes connected in parallel drive synchronous circuit comprises: A plurality of branch resistors are connected to the plurality of power tubes in a one-to-one correspondence; The common-circuit resistor has one end connected to the voltage input terminal and the other end connected in series with each of the branch resistors.

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