Support shielding structure for trench semiconductor device

Abstract

A power semiconductor device includes a semiconductor layer structure including a drift region of a first conductivity type and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface between the sidewalls. And a bottom shielding structure of a second conduction type is arranged below the bottom surface of the gate trench. First and second support shielding structures of a second conductivity type extend into the drift region on opposite sides of the gate trench and are spaced apart from sidewalls of the gate trench. A material composition of the bottom shielding structure, a distance extending into the drift region relative to a surface of the semiconductor layer structure, and / or a dopant concentration may be different from those of the first and second support shielding structures. Related devices and methods of manufacture are also discussed.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. patent application No. 17 / 703,708, filed on March 24, 2022, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to semiconductor devices, in particular to power semiconductor devices. Background Art

[0004] A power semiconductor device refers to a device that includes one or more "power" semiconductor dies that are designed to carry large currents (e.g., tens or hundreds of amperes) and / or are capable of blocking high voltages (e.g., hundreds, thousands or tens of thousands of volts). A variety of power semiconductor devices are known in the art, including, for example, power metal insulator semiconductor field effect transistors ("MISFETs," including metal oxide semiconductor FETs ("MOSFETs")), bipolar junction transistors ("BJTs"), insulated gate bipolar transistors ("IGBTs"), junction barrier Schottky diodes, gate turn-off transistors ("GTOs"), MOS-controlled thyristors, and a variety of other devices. These power semiconductor devices are typically made of wide bandgap semiconductor materials (e.g., semiconductor materials based on silicon carbide ("SiC") or group III nitrides (e.g., gallium nitride ("GaN")). In this article, a wide bandgap semiconductor material refers to a semiconductor material having a bandgap greater than about 1.40 eV (e.g., greater than about 2 eV).

[0005] Conventional power semiconductor devices generally have a semiconductor substrate having a first conductivity type (e.g., an n-type substrate) on which an epitaxial layer structure having a first conductivity type (e.g., n-type) is formed. A portion of the epitaxial layer structure (which may include one or more separate layers) is used as a drift layer or drift region of a power semiconductor device. The device generally includes an "active region" comprising one or more "unit cell" structures having a junction (e.g., a pn junction). The active region may be formed on and / or in the drift region. The active region acts as a main junction for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction. The power semiconductor device may also have an edge terminal in a terminal region adjacent to the active region. One or more power semiconductor devices may be formed on the substrate, and each power semiconductor device will generally have its own edge terminal. After the substrate is fully processed, the resulting structure may be cut to separate individual edge-terminated power semiconductor devices.

[0006] A power semiconductor device may have a unit cell construction in which a large number of individual unit cell structures of an active area are electrically connected (e.g., in parallel) to function as a single power semiconductor device. In high power applications, such a power semiconductor device may include thousands or tens of thousands of unit cells implemented in a single chip or "die". A die or chip may include a small piece of semiconductor material or other substrate in which electronic circuit elements are fabricated. For example, a plurality of individual power semiconductor devices may be formed on a relatively large semiconductor substrate (e.g., by growing epitaxial layers thereon, doping selected regions with dopants, forming insulating layers and metal layers thereon, etc.), and the completed structure may then be cut (e.g., by sawing or cutting operations) into a plurality of individual dies, each of which is a power semiconductor device.

[0007] The power semiconductor device may have a lateral structure or a vertical structure. In a device having a lateral structure, the terminals of the device (e.g., the drain terminal, gate terminal, and source terminal of a power MOSFET device) are located on the same main surface (e.g., top or bottom) of the semiconductor layer structure. In contrast, in a device having a vertical structure, at least one terminal is provided on each main surface of the semiconductor layer structure (e.g., in a vertical MOSFET device, the source may be on the top surface of the semiconductor layer structure, and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include a lower substrate. In this article, the term "semiconductor layer structure" refers to a structure including one or more semiconductor layers, including a semiconductor substrate and / or a semiconductor epitaxial layer.

[0008] Vertical power semiconductor devices, such as MOSFET or IGBT devices, can have a standard gate electrode design, in which the gate electrode of the transistor is formed on top of the semiconductor layer structure, or alternatively, the gate electrode can be buried in a trench within the semiconductor layer structure. Devices with buried gate electrodes are generally referred to as gate trench devices. In the case of a standard gate electrode design, the channel region of each unit cell transistor is horizontally deployed below the gate electrode. In contrast, in a gate trench design, the channel is vertically deployed. Gate trench devices can provide enhanced performance, but generally require more complex manufacturing processes.

[0009] Power semiconductor devices are designed to block (in the forward or reverse blocking state) large voltages and / or currents, or to pass large voltages and / or currents (in the forward operating state). For example, in the blocking state, the power semiconductor device can be designed to withstand potentials of hundreds or thousands of volts. When the applied voltage approaches or exceeds the voltage level at which the device is designed to block, non-trivial levels of current (called leakage current) may begin to flow through the power semiconductor device. The blocking capability of the device can be a function of the doping density / concentration and thickness of the drift region, among other things. Leakage current may also be generated for other reasons, such as failure of the edge terminals and / or main junctions of the device. If the voltage applied to the device is increased beyond the breakdown voltage to a critical level, the increased electric field may result in uncontrollable and undesirable runaway generation of charge carriers within the semiconductor device, leading to a condition known as avalanche breakdown.

[0010] Furthermore, a relatively thin gate insulating layer (e.g., a gate oxide layer) separating the gate electrode from the semiconductor layer structure may degrade when the gate insulating layer is subjected to high electric field levels during on-state (conducting) or off-state (blocking) operation. Such degradation of the gate insulating layer may ultimately lead to breakdown of the gate insulating layer, whereupon the gate electrode may short-circuit to the semiconductor layer structure, which may damage the device. Summary of the invention

[0011] According to some embodiments, a power semiconductor device includes: a semiconductor layer structure, which includes a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including side walls and a bottom surface located between the side walls; a bottom shielding structure of a second conductivity type located below the bottom surface of the gate trench; and first and second supporting shielding structures of the second conductivity type extending into the drift region on opposite sides of the gate trench and spaced apart from the side walls of the gate trench.

[0012] In some embodiments, one or more of the first and second supporting shield structures extend into the drift region to a depth relative to the surface of the semiconductor layer structure that is different from a depth of the bottom shield structure.

[0013] In some embodiments, the first support shield structure and the second support shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micron.

[0014] In some embodiments, at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure includes a material different from a material of the drift region.

[0015] In some embodiments, the drift region includes a wide bandgap semiconductor material, and the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure includes polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0016] In some embodiments, the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure further comprises an implanted portion of the drift region.

[0017] In some embodiments, the bottom shield structure includes a first concentration of dopants of the second conductivity type, and the first and second supporting shield structures include a second concentration of dopants of the second conductivity type that is different than the first concentration.

[0018] In some embodiments, the second concentration is higher than the first concentration.

[0019] In some embodiments, the semiconductor layer structure further comprises a substrate, the substrate comprising a drift region thereon and a well region of a second conductivity type in or on the drift region opposite to the substrate. The first support shield structure and the second support shield structure extend through the well region and beyond the bottom shield structure and are spaced apart from the substrate.

[0020] In some embodiments, the first supporting shield structure and the second supporting shield structure have a different concentration of dopants of the second conductivity type than the well region.

[0021] In some embodiments, the first support shield structure and the second support shield structure are spaced apart from the substrate by about 1 to about 100 microns.

[0022] In some embodiments, the bottom shield structure extends along a portion of a bottom surface of the gate trench.

[0023] In some embodiments, the bottom shield structure extends along the entirety of the bottom surface of the gate trench.

[0024] According to some embodiments, a power semiconductor device includes: a semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface located between the sidewalls; a bottom shield structure of a second conductivity type located below the bottom surface of the gate trench; and a first support shield structure and a second support shield structure of the second conductivity type extending into the drift region on opposite sides of the gate trench and spaced apart from the sidewalls of the gate trench. The material composition, the distance extending into the drift region relative to the surface of the semiconductor layer structure, and / or the dopant concentration of the bottom shield structure are different from those of the first support shield structure and the second support shield structure.

[0025] In some embodiments, one or more of the first and second supporting shield structures extend a distance into the drift region greater than a distance that the bottom shield structure extends into the drift region relative to a surface of the semiconductor layer structure.

[0026] In some embodiments, the first support shield structure and the second support shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micron.

[0027] In some embodiments, a material composition of at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure is different from a material composition of the drift region.

[0028] In some embodiments, the drift region includes a wide bandgap semiconductor material, and the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure includes polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0029] In some embodiments, the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure further comprises an implant region of the drift region.

[0030] In some embodiments, the first support shield structure and the second support shield structure have a lower dopant concentration than the bottom shield structure.

[0031] In some embodiments, the dopant concentration of the first support shield structure and the second support shield structure is higher than the dopant concentration of the bottom shield structure.

[0032] In some embodiments, the semiconductor layer structure further includes a substrate including a drift region thereon, wherein the first support shield structure and the second support shield structure are spaced apart from the substrate by about 1 to about 100 microns.

[0033] According to some embodiments, a method for manufacturing a power semiconductor device includes providing a semiconductor layer structure including a drift region of a first conductivity type; forming a bottom shielding structure of a second conductivity type extending into the drift region and a first supporting shielding structure and a second supporting shielding structure; and forming a gate trench extending into the drift region and spaced apart from the first supporting shielding structure and the second supporting shielding structure, wherein the bottom shielding structure is located under the gate trench.

[0034] In some embodiments, forming the gate trench is performed after forming the bottom shield structure.

[0035] In some embodiments, forming a bottom shield structure and a first support shield structure and a second support shield structure includes forming one or more support shield structures of the first support shield structure and the second support shield structure, wherein the one or more support shield structures extend into the drift region to a depth relative to the surface of the semiconductor layer structure that is different from the depth of the bottom shield structure.

[0036] In some embodiments, the first support shield structure and the second support shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micron.

[0037] In some embodiments, forming at least one of the bottom shielding structure or the first supporting shielding structure and the second supporting shielding structure includes performing one or more etching operations to form a corresponding shielding trench in the drift region; and performing one or more deposition operations to form a material different from the material of the drift region in the corresponding shielding trench.

[0038] In some embodiments, the drift region includes a wide bandgap semiconductor material, and the at least one of the bottom shield structure or the first and second supporting shield structures includes polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0039] In some embodiments, forming the at least one of the bottom shield structure or the first and second supporting shield structures further comprises performing one or more ion implantation operations to implant dopants of the second conductivity type into portions of the drift region beneath the respective shield trenches.

[0040] In some embodiments, forming the bottom shield structure or at least one of the first and second supporting shield structures includes performing one or more ion implantation operations to implant dopants of the second conductivity type into the drift region.

[0041] In some embodiments, in response to the one or more ion implantation operations, the bottom shield structure includes a first concentration of dopants of the second conductivity type, and the first and second supporting shield structures include a second concentration of dopants of the second conductivity type that is different from the first concentration. The second concentration may be higher than the first concentration.

[0042] According to some embodiments, a method for manufacturing a power semiconductor device includes providing a semiconductor layer structure including a drift region of a first conductivity type; forming a first support shielding structure and a second support shielding structure of a second conductivity type extending into the drift region; forming a gate trench extending into the drift region and spaced apart from the first support shielding structure and the second support shielding structure, the gate trench including side walls and a bottom surface located between the side walls; and forming a bottom shielding structure of the second conductivity type under the bottom surface of the gate trench.

[0043] In some embodiments, forming the bottom shield structure includes performing one or more ion implantation and / or deposition operations after forming the gate trench to form the bottom shield structure extending into the drift region to a first depth relative to a surface of the semiconductor layer structure.

[0044] In some embodiments, the bottom shield structure has a different material composition, a distance extending into the drift region relative to the surface of the semiconductor layer structure, and / or a dopant concentration than the first and second supporting shield structures.

[0045] In some embodiments, forming a first support shield structure and a second support shield structure includes: before forming a gate trench, forming one or more support shield structures of the first support shield structure and the second support shield structure, wherein the one or more support shield structures extend into the drift region to reach a second depth relative to the surface of the semiconductor layer structure, wherein the second depth is different from the first depth.

[0046] In some embodiments, the second depth is about 0.1 to about 1 micron greater than the first depth.

[0047] In some embodiments, forming the first supporting shield structure and the second supporting shield structure includes, before forming the gate trench, performing one or more etching operations to form corresponding shielding trenches in the drift region, and performing one or more deposition operations to form a material different from the material of the drift region in the corresponding shielding trenches.

[0048] In some embodiments, the drift region includes a wide bandgap semiconductor material, and at least one of the bottom shield structure or the first and second supporting shield structures includes polysilicon, nickel oxide, gallium nitride, or gallium oxide.

[0049] In some embodiments, forming the first supporting shield structure and the second supporting shield structure further includes performing one or more ion implantation operations to implant dopants of the second conductivity type into portions of the drift region under the respective shield trenches before forming the gate trenches.

[0050] In some embodiments, forming the first supporting shield structure and the second supporting shield structure includes performing one or more ion implantation operations to implant dopants of the second conductivity type into the drift region before forming the gate trench.

[0051] In some embodiments, in response to the one or more ion implantation operations, the first and second supporting shield structures include a second concentration of the dopant of the second conductivity type that is different from the first concentration of the dopant of the second conductivity type of the bottom shield structure. The second concentration is higher than the first concentration.

[0052] Other devices, apparatuses and / or methods according to some embodiments will be apparent to those skilled in the art after reading the following drawings and detailed description. In addition to any and all combinations of the above embodiments, all of these additional embodiments are intended to be included in this specification, within the scope of the invention and protected by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1A is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device including a shielding region beneath a gate trench.

[0054] Figure 1B is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device including a shielding region below and along one sidewall of a gate trench.

[0055] Figure 2 is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device according to some embodiments of the present invention, the gate trench power semiconductor device including a bottom shield structure located below a gate trench and a supporting shield structure spaced apart from a sidewall of the gate trench.

[0056] Figure 3A , Figure 3B , Figure 3C and Figure 3D is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device according to some embodiments of the present invention, the gate trench power semiconductor device including a bottom shield structure and a supporting shield structure at various combinations of different dopant concentrations, depths and / or material compositions.

[0057] Figure 4A , Figure 4B , Figure 4C and Figure 4D is a schematic cross-sectional view illustrating an example unit cell of a gate trench power semiconductor device including a bottom shield structure and a supporting shield structure of different dopant concentrations and different material compositions according to some embodiments of the present invention.

[0058] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Fig. 5F is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device including a bottom shield structure below a gate trench and a supporting shield structure spaced apart from sidewalls of the gate trench according to some embodiments of the present invention.

[0059] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E , Fig. 6F , Figure 6G and Figure 6H is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device including a bottom shield structure below a gate trench and a supporting shield structure spaced apart from a sidewall of the gate trench according to further embodiments of the present invention.

[0060] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G and Figure 7H is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device including a bottom shield structure below a gate trench and a supporting shield structure spaced apart from sidewalls of the gate trench according to still other embodiments of the present invention.

[0061] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Figure 8F , Figure 8G and Figure 8H is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device including a bottom shield structure below a gate trench and a supporting shield structure spaced apart from sidewalls of the gate trench according to yet other embodiments of the present invention. DETAILED DESCRIPTION

[0062] Some embodiments of the present invention are directed to improvements in power semiconductor devices (e.g., MOSFETs, IGBTs, and other gate-controlled power devices). Many power semiconductor devices include a so-called deep or "buried" shielded semiconductor region, also referred to as a shielding structure, whose conductivity type is different from the (one or more) layers of semiconductor material underlying the well region and / or gate electrode of the device. For example, in a device having a gate electrode and a gate insulation layer formed within a trench in a semiconductor layer structure, high electric fields may degrade the gate insulation layer over time and may ultimately lead to failure of the device. Therefore, a deep shielding structure may be provided beneath the gate trench to reduce the electric field level in the gate insulation layer, particularly at the corners of the gate trench where the electric field level may be more concentrated. The shielding structure may have the same conductivity type as the well region, which is opposite to the conductivity type of the drift region.

[0063] The deep shield structure may typically include a highly doped semiconductor region having the same conductivity type as the channel region. Methods of doping semiconductor materials with n-type and / or p-type dopants include (1) doping the semiconductor material during growth of the semiconductor material, (2) diffusing the dopant into the semiconductor material, and (3) selectively implanting the dopant into the semiconductor material using ion implantation. When doping silicon carbide during epitaxial growth, the dopant tends to accumulate unevenly, so the dopant concentration may vary by, for example, + / - 15%, which may negatively affect device operation and / or reliability. In addition, doping by diffusion may not be an option for silicon carbide, gallium nitride, and various wide bandgap semiconductor devices because n-type and p-type dopants tend to diffuse poorly (or not diffuse at all) in these materials, even at high temperatures.

[0064] In view of the above, ion implantation is commonly used to dope wide bandgap semiconductor materials, such as silicon carbide. However, in a gate-trench vertical power device (also referred to herein as a trench vertical power device or a trench gate device), it may be desirable to form deep shielding structures under the well region and / or gate electrode of the device, and these deep shielding structures typically extend into the device to a depth of about 1-3 microns or more. The depth of ion implantation is directly related to the energy of the implantation, that is, ions implanted into a semiconductor layer with higher energy tend to penetrate deeper into the layer.

[0065] Therefore, forming a deep shielding structure via ion implantation may require high energy implantation. However, when the dopant ions are implanted into the semiconductor layer, the ions damage the lattice of the semiconductor layer. This lattice damage may usually only be partially repaired by a thermal annealing process. That is, the lattice damage caused by the ion implantation process may not be completely repaired. In addition, the amount of lattice damage may also be directly related to the implantation energy, with higher energy implants tending to cause more lattice damage than lower energy implants. The uniformity of dopant concentration also tends to decrease with increasing implantation depth.

[0066] A variety of approaches can be used to form trench vertical power semiconductor devices. Figure 1A and Figure 1B Two examples of these different approaches are schematically illustrated.

[0067] Figure 1A and Figure 1B 1 is a schematic cross-sectional view illustrating an example unit cell of a trench vertical power device (illustrated as power MOSFETs 100a and 100b, respectively) including deeply buried P-type shielding regions 140a, 140b. Figure 1A and Figure 1B As shown in FIG. 1 , each of the power MOSFETs 100 a and 100 b includes a heavily doped (eg, N + ) of a first conductivity type (eg, n-type) substrate 110. A lightly doped (eg, N - ) is disposed on the substrate 110, for example, by epitaxial growth. In some embodiments, the drift region 120 may be a wide bandgap semiconductor material such as silicon carbide (SiC). For example, the substrate 110 may be a 4H-SiC substrate, and the drift region 120 may be a 4H-SiC n-type epitaxial layer formed on the substrate 110. A portion of the drift region 120 may include a current spreading layer (“CSL”) 185 of the first conductivity type having a higher dopant concentration than a lower portion of the drift region 120. A moderately doped second conductivity type (e.g., p-type) layer is formed on or in the drift region 120 (e.g., by epitaxial growth or implantation), and the layer serves as a well region (e.g., “P-well”) 170 of the devices 100a, 100b. A heavily doped second conductivity type (e.g., P-type) layer is formed in the well region 170, for example, via ion implantation. + ) region 174. A transistor channel or conduction path 178 may be formed in the moderately doped region P-well 170. The substrate 110, the drift region 120 (including the current spreading layer 185), and the moderately doped layer defining the P-well 170 and the various regions / patterns formed therein are included in the semiconductor layer structure 106 of the MOSFETs 100a, 100b.

[0068] Still refer to Figure 1A and Figure 1B , trenches 180 are formed in the semiconductor layer structure 106, for example, having a "strip-like" gate trench layout in which the trenches 180 extend continuously parallel to each other in the longitudinal direction. The trenches 180 are spaced apart in a lateral direction that intersects (e.g., is perpendicular to) the longitudinal direction, and extend in the vertical direction toward the substrate 110 into the drift region 120. The trenches 180 (in which the gate electrodes 184 are formed) can be formed to extend through the moderately doped layer 170 to define a corresponding P well. The heavily doped (e.g., P + ) is formed in the drift region 120 by, for example, ion implantation. The shielding structures 140a, 140b may be electrically connected to the P-well 170. A gate insulating layer 182 (e.g., a gate oxide) is conformally formed on the bottom surface and sidewalls of each trench 180. The corners of the gate trench 180 and the gate insulating layer 182 thereon may be rounded, even though this is not shown.

[0069] A gate electrode 184 (or "gate") is formed on each gate insulating layer 182 to fill the corresponding gate trench 180. The portion of the drift region 120 under and / or adjacent to the gate electrode 184 may be referred to as a "JFET region" 175. A vertical transistor channel region (wherein a conduction 178 is indicated by a dashed arrow) is defined in the well region 170 adjacent to the gate insulating layer 182. A heavily doped first conductivity type (e.g., N + ) source region 160 is formed in the upper portion of P well 170, for example, by ion implantation. The heavily doped second conductivity type (eg, P + ) region 174 contacts the well region 170. A source contact 190 is formed on the source region 160, the heavily doped region 174 and ( Figure 1B 14. In some embodiments, the source contact 190 may be an ohmic metal. The drain contact 192 is formed on the lower surface of the substrate 110. A gate contact (not shown) may be electrically connected to each gate electrode 184, for example, by a conductive gate bus (not shown). An intermetallic dielectric layer 186 may be formed on the gate 184, and a metal (e.g., aluminum) layer 196 may be formed on the intermetallic dielectric layer 186 to contact the source contact 190. In some embodiments, the source contact 190 may extend onto the intermetallic dielectric layer 186 and may include, for example, a diffusion barrier layer and / or an adhesion layer.

[0070] As described above, some devices may be susceptible to premature oxide breakdown due to electric field crowding effects near the corners of the gate trench 180. Figure 1A and Figure 1BIn the example of FIG. 1 , the buried semiconductor region or the shield pattern 140a, 140b of the opposite conductivity type to the drift region 120 is configured to prevent the trench MOSFET 100a, 100b from degrading under a high electric field. In particular, in the example devices 100a and 100b, at the bottom of the gate trench 180 ( Figure 1A ) at the bottom of the gate trench 180 and along one sidewall of the gate trench 180 ( Figure 1B The shield patterns 140a, 140b of the deep shield patterns 140a, 140b are configured to provide electric field (e.g., voltage and / or current) blocking by connecting to respective source contacts 190 that are grounded. The shield connection pattern may be connected to the source contacts 190 at the top of the devices 100a, 100b (or may be otherwise connected to the deep shield patterns 140a, 140b) to allow the deep shield patterns 140a, 140b to be electrically grounded.

[0071] The shielding patterns 140a, 140b may extend to a lower corner region ( Figure 1B middle) or the two lower corner areas ( Figure 1A Since the gate insulating layer 182 may be particularly susceptible to breakdown at the corner regions, the shielding patterns 140a, 140b may help protect the gate insulating layer 182 at the lower corner region(s) of the gate trench 180 from the high electric field during the reverse blocking operation.

[0072] Figure 1A The bottom gate shield (BPS_TMOS) configuration of the shield pattern 140a is illustrated, which can allow a significant reduction in cell pitch and improve sidewall conductivity utilization. Figure 1A 1, conduction 178 (shown by dashed arrows) occurs along both sides of the channel in device 100a. However, since masks and / or other operations are required to block or protect the sidewalls of trench 180 during the implantation process used to form shielding pattern 140a, Figure 1A The structure of device 100a shown in FIG. 1 may be difficult to manufacture.

[0073] To achieve more reliable on and off state performance and / or improve durability, Figure 1B A contact scheme with an asymmetric shield (APS_TMOS) configuration is illustrated, in which the shield pattern 140b extends along only one sidewall of the trench 180, leaving the other sidewall of the trench 180 free of the shield pattern 140b. However, this configuration may limit the effective conductive area of ​​the device 100b by blocking conduction 178 at one side of the channel.

[0074] Embodiments of the present invention are directed to power semiconductor devices, including layout and design arrangements that further improve reliability by forming shielding regions 240a, 340a, 340a' (also referred to herein as bottom shielding structures 240a, 340a, 340a') at the bottom of gate trench 180, in combination with additional supporting shielding structures or regions 240b, 340b, 340b' on the opposite side of gate trench 180 and spaced from the sidewalls of gate trench 180. Shielding structures 240a / 240b, 340a / 340b, 340a' / 340b' have a second conductivity type or a conductivity type (e.g., p-type) opposite to the first conductivity type (e.g., n-type) of drift region 120. Although described and illustrated herein by way of example with reference to regions of specific first and second conductivity types (i.e., n-type and p-type), it should be understood that the conductivity types of the regions in any of the illustrated examples may be reversed (i.e., p-type and n-type) according to embodiments of the present invention. Likewise, although primarily described herein with reference to MOSFET implementations, it should be understood that the same techniques may be used with other vertical power semiconductor devices, such as insulated gate bipolar transistors (IGBTs) and / or other related power devices utilizing trench structures.

[0075] In some embodiments, a support shield structure or region is disposed adjacent to a JFET portion 175 of the drift region 120 that is located below and / or adjacent to the gate trench 180 . Figure 2 is a schematic cross-sectional view illustrating an example unit cell of a power semiconductor device 200 according to some embodiments of the present invention, which includes a bottom shield structure 240a located below a gate trench 180 and a support shield structure 240b spaced apart from a sidewall of the gate trench 180. Elements, layers or regions identical to those of the semiconductor layer structure 106 described herein are indicated by the same reference numerals.

[0076] like Figure 2As shown in , in the trench vertical power semiconductor device 200, the JFET region 175 may include an upper portion of the drift region 120 adjacent to the gate trench 180 and located below the well region. A main bottom shield structure 240a is provided below the bottom surface of the gate trench 180, and a first support shield structure and a second support shield structure 240b are provided spaced apart from the sidewalls of the gate trench 180 and on opposite sides of the gate trench 180, so that the JFET region 175 extends at least partially between each support shield structure 240b and the bottom shield structure 240a. The bottom shield structure 240a and the support shield structure 240b (collectively referred to as shield structures) extend beyond the gate trench 180 toward the substrate 110 (i.e., extend closer to the substrate 110 than the gate trench 180). The shield connection pattern may be connected to the shield structures 240a, 240b and the source contact 190 (eg, at the top of the device 200), or the source contact 190 may be otherwise connected to the shield structures 240a, 240b to allow the shield structures 240a, 240b to be electrically grounded.

[0077] The support shield structure 240b may differ from the bottom shield structure 240a (e.g., in material composition, distance or depth extending from the surface S of the semiconductor layer structure 106 to the substrate 110, and / or dopant concentration) to provide greater protection for the gate insulating layer 182 along the gate trench 180 (e.g., at the corners of the bottom surface of the gate trench 180), for example, by providing a lower resistance current path under avalanche breakdown conditions. In some embodiments, the support shield structure 240b may extend to a depth D2 toward the substrate 110 that is substantially equal to the depth D1 of the bottom shield structure 240a (i.e., where D2=D1). In some embodiments, the support shield structure 240b may extend to a depth D2 toward the substrate 110 that is greater than the depth D1 of the bottom shield structure 240a. For example, the support shield structure 240b may extend to the substrate 110 beyond the bottom shield structure 240a by a depth ΔD of about 0.1 micrometers to about 1 micrometer (e.g., about 0.3 micrometers to about 0.7 micrometers, for example, about 0.5 micrometers). That is, the difference ΔD between the depth D2 of the support shield structure 240b and the depth D1 of the bottom shield structure D1 may be less than about 0.1 micrometers to about 1 micrometer. As described herein, the depth or distance extending into the drift region 120 may be along the vertical direction in the drawings, and may be relative to the (top) surface S of the semiconductor layer structure 106. The depth D2 of the support shield structure 240b may be sufficient to reduce or prevent avalanche breakdown at the bottom of the gate trench 180. In some embodiments, the support shield structure 240b may extend from the surface S of the semiconductor layer structure 106 toward the substrate 110 to a depth D2 of about 1 micrometer to about 10 micrometers (e.g., about 3 micrometers to about 7 micrometers, for example, about 5 micrometers).

[0078] Additionally, in some embodiments, the support shield structure 240b can have a different shape than the bottom shield structure 240a and / or the trench 180. For example, the width of the support shield structure 240b (along a horizontal or lateral direction) can be different than the width of the trench 180 (and / or the bottom shield structure 240a extending under the trench 180). That is, while illustrated as being substantially similar in width, in some embodiments, the first and second support shield structures 240b can be wider or narrower than the gate trench 180.

[0079] The support shield structure 240b may define a pn junction (e.g., a body diode) with the drift region 120. A spacing T between the support shield structure 240b and the substrate 110 (e.g., defined by a portion of the drift region 120 therebetween) may correspond to a breakdown voltage of the device 200. For example, the support shield structure 240b and / or the bottom shield structure 240a may be separated from the substrate 110 by a spacing T of about 1 micron to about 100 microns (e.g., about 30 microns to about 70 microns, e.g., about 50 microns). The spacing T may vary, for example, based on the material and / or dopant concentration of the shield structures 240a, 240b.

[0080] In some embodiments, the support shield structure 240b can have a lower resistance than the bottom shield structure 240a. For example, the support shield structure 240b can contact the source contact 190 over a longer length (e.g., in a direction into the page) than the bottom shield structure 240a (which may only be intermittently connected to the source along its length), thereby reducing resistance. The support shield structure 240b can be formed of the same or different material as the bottom shield structure 240a and / or with a similar or different dopant concentration than the bottom shield structure 240a. In some embodiments, the shield structures 240a, 240b can be defined with a substantially uniform concentration or a stepwise or continuous grading by one or more implantation processes, and can extend to contact the source contact 190 for connection to an electrical ground within the unit cell. The support shield structure 240b can include approximately 1x10 17 About 1x10 20 cm -3 , for example, about 5x10 17 About 5x10 19 cm -3 , or about 1x10 18 About 1x10 19 cm -3The dopant concentration of the second conductivity type of the support shield structure 240b can be higher than the dopant concentration of the well region 170 (e.g., about more than 10 times higher; e.g., about 100 times higher) and can be similar to or higher than the dopant concentration of the bottom shield structure 240a. The dopant concentrations of the shield structures 240a, 240b can vary based on the implementation of the manufacturing process and / or device design, such as Figure 5A-5F and Figure 6A-6H The shielding structures 340a, 340b of the method embodiment are shown.

[0081] In some embodiments, the shielding structures 240a, 240b may be formed of a material different from the drift region 120, for example, a semiconductor material having a lower resistance than the semiconductor material of the drift region 120. For example, in an embodiment where the drift region 120 is an n-type material (e.g., SiC), the supporting shielding structure 240b and / or the bottom shielding structure 240a may be a p-type material(s) (e.g., nickel oxide (p-NiO), polycrystalline silicon (poly-Si), gallium nitride (p-GaN), gallium oxide (p-Ga2O3)). In an embodiment where the drift region 120 is a p-type material, the supporting shielding structure 240b and / or the bottom shielding structure 240a may be a n-type material(s) (e.g., n-SiC, n-Si, n-GaN). Therefore, the shielding structures 240a and / or 240b formed of a different material(s) of opposite conductivity type to the drift region 120 may define a corresponding pn heterojunction or body diode in the drift region 120.

[0082] Shielding structures formed of different materials (one or more) that define a heterojunction with the drift region 120 may also differ in their ability to withstand repeated breakdown events (compared to implanted shielding structures). For example, heterojunction-based shielding structures (also described herein with reference to shielding structures 340a' and 340b') can be formed to provide lower resistance and / or extend to greater depths than implanted-based shielding structures (e.g., shielding structures 340a and 340b herein) to improve effectiveness. That is, heterojunction-based shielding structures can provide advantages in resistance and / or depth control (i.e., can be formed to have lower resistance and / or greater depth than implanted shielding structures) relative to implanted-based shielding regions.

[0083] Additionally or alternatively, the support shield structure 240b may be formed of a different material than the bottom shield structure 240a. For example, the bottom shield structure 240a may be an implanted region of the drift region 120 (and thus may have the same material as the drift region 120), while the support shield structure 240b may be formed of a different material than the drift region 120, or vice versa, e.g. Figure 3C-Figure 3D and Figure 4A-4D 340a, 340b and 340a', 340b' of the device embodiment. Shielding structures 240a and / or 240b formed of different materials from each other can provide improved protection for the gate insulation layer 182. For example, a supporting shielding structure 240b formed of a different material of the second conductivity type (e.g., p-NiO, p-polycrystalline Si (poly-Si), p-GaN, p-Ga2O3) can provide a lower resistance (in some cases, several orders of magnitude lower) than some implanted bottom shielding structures 240a of the second conductivity type (e.g., P+ region), thereby providing a lower resistance current path under avalanche breakdown conditions. That is, the shielding structures 240a, 240b can be formed of a different material from the drift region 120, and / or can be formed of a different material from each other.

[0084] The shape and / or depth of the support shield structure 240b may also allow the shape and / or depth of the bottom shield structure 240a to vary while still providing desired avalanche breakdown characteristics. For example, in some embodiments, because the support shield structure 240b provides better protection for the gate oxide 182, the bottom shield structure 240a may extend along only a portion of the bottom surface of the gate trench 180 (i.e., may be narrower than the bottom surface), which may increase the available area for conduction 178 at the bottom corner of the gate trench 180 (so that the JFET region 175 may extend below the outer edge of the gate trench 180 in addition to along the trench sidewalls). In contrast, in some embodiments, the bottom shield structure 240a may extend along the entire bottom surface of the gate trench 180 (or may extend laterally beyond the bottom surface or be wider than the bottom surface), and the dopant concentration of the JFET region 175 may be increased to maintain the desired conduction 178. The width of the bottom shield structure 240a (ie, along the bottom of the gate trench 180) may vary based on the masking, implantation, deposition, and / or other manufacturing operations used to form the shield structures 240a and 240b.

[0085] More generally, the support shield structure 240b may be formed having a different depth, dopant concentration, and / or material than the bottom shield structure 240a, one or more of which may be configured to reduce or prevent avalanche breakdown at the bottom of the gate trench 180. Figure 3A-3D and Figure 4A-4D Example unit cells of power semiconductor devices 300a-300d and 400a-400d including various combinations of bottom shield structures 340a, 340a' and support shield structures 340b, 340b' are illustrated in FIG.

[0086] exist Figure 3A-3D and Figure 4A-4DIn the example, for ease of illustration, a simplified semiconductor layer structure 106 is shown (e.g., without the JFET region 175, the CSL 185, etc.), and although these and other well-known elements are not specifically shown, it can be understood that these and other well-known elements exist. Similarly, elements, layers and / or regions of devices 300a-300d and 400a-400d similar to those discussed above are indicated by the same figure numbers, and for the sake of brevity, the description of these elements, layers and / or regions may be omitted. Unless otherwise stated, the bottom shield structure 340a, 340a' and the support shield structure 340b, 340b' may include characteristics similar to those of the bottom shield structure 240a and the support shield structure 240b, respectively.

[0087] In particular, if Figure 3A As shown in , the power semiconductor device 300a includes a bottom shielding structure 340a and a supporting shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type) in a drift region 120 of a first conductivity type (e.g., n-type). Depending on the manufacturing process used, the supporting shielding structure 340b may be different from the bottom shielding structure 340a (e.g., in terms of the depth extending into the substrate 110 and / or the dopant concentration). For example, a first ion implantation process may be performed to define a bottom shielding structure 340a having a first depth D1 and a first concentration of a second conductivity type dopant, and a second ion implantation process may be performed to define a supporting shielding structure 340b having a second depth D2 (e.g., greater than or equal to the first depth D1) and a second concentration (e.g., less than or equal to the first concentration) of a second conductivity type dopant. In embodiments where the supporting shielding structure 340b is an implanted region (such as in Figure 3A , Figure 3C and Figure 4A In the embodiment of the present invention, the support shielding structure 340b can effectively provide a heavily doped region 174 of the second conductivity type, which can be omitted. Figure 3A In the embodiment, the bottom shield structure 340a is illustrated as being narrower than the bottom surface of the gate trench 180 (i.e., extending only partially along the bottom surface), but depending on the manufacturing process used, it may be equal to or wider than the bottom surface of the gate trench 180. Figure 5A-5F and Figure 6A-6H A method of fabricating the device 300a including the implanted bottom shield structure 340a and the supporting shield structure 340b is discussed.

[0088] like Figure 3BAs shown in , the power semiconductor device 300b includes a bottom shield structure 340a' and a support shield structure 340b' of one or more materials different from the drift region 120. In particular, the bottom shield structure 340a' and the support shield structure 340b' include a material of a second conductivity type (e.g., p-type), thereby forming a corresponding heterojunction with the drift region 120 of the first conductivity type (e.g., n-type). For example, the drift region 120 can be formed of an n-type material (e.g., SiC), and the bottom shield structure 340a' and the support shield structure 340b' can be formed of a p-type material (e.g., p-NiO, p-polycrystalline-Si, p-GaN, p-Ga2O3), for example, using one or more deposition operations. Depending on the manufacturing process used, the support shield structure 340b' can be different from the bottom shield structure 340a' (e.g., in terms of the depth extending to the substrate 110 and / or the material composition). For example, in some embodiments, the bottom shield structure 340a' can be formed of a first material at a first depth D1 using a first etching and deposition process, and the supporting shield structure 340b' can be formed of a second material (e.g., the same as or different from the first material) at a second depth D2 (e.g., greater than or equal to the first depth D1) using a second etching and deposition process, so that the shield structures 340a' and 340b can be formed of different materials and / or different depths from each other (e.g., the bottom shield structure 340a' can be p-poly-Si, and the supporting shield structure 340b' can be p-NiO). In embodiments where the supporting shield structure 340b' defines a heterojunction with the drift region 120 (such as in Figure 3B , Figure 3D ,as well as Figure 4B , Figure 4C and Figure 4D ), the support shield structure 340b', the heavily doped region 174, and the source region 160 may each be in contact with the source contact 190 (eg, an ohmic contact). Figure 7A-7F and Figure 8A-8H A method of manufacturing a device 300 b including a bottom shield structure 340 a ′ and a supporting shield structure 340 b ′ defining a heterojunction with the drift region 120 is discussed.

[0089] Figure 3CA power semiconductor device 300c is illustrated, which includes a support shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type), combined with a bottom shielding structure 340a' having (one or more) second conductivity type materials different from the drift region 120 of the first conductivity type (e.g., n-type) (and therefore, different (one or more) materials from the implanted support shielding structure 340b). The bottom shielding structure 340a' defines a heterojunction with the drift region 120 below the bottom surface of the gate trench 180'. The support shielding structure 340b and the bottom shielding structure 340a' can be formed using different manufacturing operations (e.g., ion implantation and deposition, respectively), and therefore, depending on the respective manufacturing processes used, the depth D2 of the support shielding structure 340b can be the same as or different from the depth D1 of the bottom shielding structure 340a'.

[0090] Figure 3D A power semiconductor device 300d is illustrated, which includes a bottom shielding structure 340a provided by an implanted region of a second conductivity type (e.g., p-type), combined with a supporting shielding structure 340b' of (one or more) second conductivity type material different from the first conductivity type drift region 120 (e.g., n-type). Spaced apart from the sidewalls of the gate trench 180 and on the opposite side thereof, the supporting shielding structure 340b' defines a heterojunction with the drift region 120. The supporting shielding structure 340b' and the bottom shielding structure 340a can be formed using different manufacturing operations (e.g., deposition and ion implantation, respectively), and therefore, depending on the corresponding manufacturing process used, the depth D2 of the supporting shielding structure 340b' can be the same as or different from the depth D1 of the bottom shielding structure 340a. Figure 3D , the bottom shield structure 340a is illustrated by way of example as being wider than (ie, extending laterally beyond) the bottom surface of the gate trench 180, but may be equal to or narrower than the bottom surface of the gate trench 180 depending on the manufacturing process used.

[0091] Figure 4AA power semiconductor device 400a is illustrated, which includes a support shielding structure 340b provided by an implanted region of a second conductivity type (e.g., p-type), a first bottom shielding structure portion 340a provided by an implanted region of the second conductivity type, and a second bottom shielding structure portion 340a' of (one or more) second conductivity type materials different from the drift region 120. The second bottom shielding structure portion 340a' defines a heterojunction with the drift region 120 below the bottom surface of the gate trench 180'. The support shielding structure 340b and the second bottom shielding structure portion 340a' can be formed using different manufacturing operations (e.g., ion implantation and deposition, respectively). The support shielding structure 340b and the first bottom shielding structure portion 340a can be formed using the same or different implantation operations. Thus, depending on the manufacturing process used, the depth D2 and / or dopant concentration of the support shielding structure 340b can be the same as or different from the depth D1 and / or dopant concentration of the first bottom shielding structure portion 340a. Similarly, in Figure 4A , the first bottom shield structure portion 340a is illustrated by way of example as being narrower than the bottom surface of the gate trench 180', but may be equal to or wider than the bottom surface of the gate trench 180' depending on the manufacturing process used.

[0092] Figure 4B A power semiconductor device 400b is illustrated, which includes a first support shielding structure portion 340b provided by an implanted region of a second conductivity type. The second support shielding structure portion 340b' and the bottom shielding structure 340a' include (one or more) second conductivity type materials different from the first conductivity type drift region 120. The bottom shielding structure 340a' and the second support shielding structure portion 340b' define a heterojunction with the drift region 120 (later spaced apart from the opposite sidewalls of the gate trench 180', respectively, below the bottom surface of the gate trench 180'). The bottom shielding structure 340a' and the second support shielding structure portion 340b' can be formed using the same or different manufacturing operations (e.g., the same or different deposition steps), and therefore, depending on the manufacturing process used, they can be the same or different from each other (e.g., in terms of the depth extending to the substrate 110 and / or the material composition). The first support shielding structure portion 340b can be formed using a different manufacturing operation (e.g., one or more ion implantation processes) than the shielding structures 340a', 340b'. Depending on the manufacturing process used, the depth D2 of the first support shield structure portion 340b may be the same as or different from the depth D1 of the bottom shield structure 340a'.

[0093] Figure 4CA power semiconductor device 400c is illustrated, which includes a bottom shield structure and a supporting shield structure, each of which includes an implantation region and a heterojunction region. In particular, the bottom shield structure and the supporting shield structure each include a first portion 340a and 340b provided by an implantation region of the second conductivity type and a second portion 340a' and 340b' of (one or more) second conductivity type material different from the drift region 120. The second portions 340a' and 340b' define a heterojunction with the drift region 120 (respectively below the bottom surface of the gate trench 180' and laterally spaced apart from the opposite sidewalls of the gate trench 180'). The first portions 340a and 340b extend from the second shield structure portions 340a' and 340b' to the substrate 110 to depths D1 and D2, respectively. The first portions 340a and 340b may be formed using the same or different manufacturing operations (e.g., the same or different ion implantation processes), and thus, depending on the manufacturing process used, the first portions 340a and 340b may be the same or different from each other (e.g., in terms of the depth of extension into the substrate 110 and / or dopant concentration). The second portions 340a' and 340b' may be formed using the same or different manufacturing operations (e.g., the same or different deposition steps), and thus, depending on the manufacturing process used, the second portions 340a' and 340b' may be the same or different from each other (e.g., in terms of the depth of extension into the substrate 110 and / or material composition). Thus, the depth D2 of the first and second portions 340b and 340b' in the support shield structure may be the same or different from the depth D1 of the first and second portions 340a and 340a' in the bottom shield structure. Figure 4C , the first portion 340a of the bottom shield structure is illustrated by way of example as being wider than (ie, extending laterally beyond) the bottom surface of the gate trench 180', but may be equal to or narrower than the bottom surface of the gate trench 180' depending on the manufacturing process used.

[0094] Figure 4DA power semiconductor device 400d is illustrated, which includes a bottom shield structure 340a provided by an implanted region of a second conductivity type (e.g., p-type). A first support shield structure portion 340b is provided by an implanted region of the second conductivity type, and a second support shield structure portion 340b' is formed of a second conductivity type material (one or more) different from the first conductivity type drift region 120. The second support shield structure portion 340b' defines heterojunctions with the drift region 120, which are laterally spaced apart from opposite sidewalls of the gate trench 180. The bottom shield structure 340a and the first support shield structure portion 340b can be formed using the same or different manufacturing operations (e.g., the same or different ion implantation processes), and therefore, depending on the manufacturing process used, they can be the same or different from each other (e.g., in terms of the depth of extension to the substrate 110 and / or the dopant concentration). The second support shield structure portion 340b' can be formed using a different manufacturing operation (e.g., one or more ion implantation processes) than the shield structures 340a, 340b. The depth D2 of the first and second support shield structure portions 340 b and 340 b ′ may be the same as or different from the depth D1 of the bottom shield structure 340 a .

[0095] Figure 5A-5F is a schematic cross-sectional view illustrating an example manufacturing operation for forming a power semiconductor device according to some embodiments of the present invention, the power semiconductor device including a bottom shield structure located below a gate trench and a support shield structure spaced apart from the sidewalls of the gate trench. In particular, Figure 5A-5F A method of forming shield structures 340a, 340b as implant regions is illustrated, wherein the bottom shield structure 340a is formed prior to forming the gate trench 180, which may be referred to herein as a pre-trench shield implant process.

[0096] like Figure 5A As shown in , a semiconductor layer structure 106 is provided. As described above, the semiconductor layer structure 106 includes a drift region 120 of a first conductivity type (e.g., n-type), a current spreading layer 185, a JFET region 175, a well region 170, and a source region 160. A heavily doped region 174 of a second conductivity type is illustrated, but in an embodiment where a support shielding structure 340b is to be formed as an injection region, the heavily doped region may be omitted. The semiconductor layer structure 106 may include a substrate 110 and / or other layers. A mask layer 501 is formed on a surface S of the semiconductor layer structure 106, and a patterned layer 502 is formed on the mask layer 501.

[0097] exist Figure 5BIn the embodiment, the mask layer 501 is patterned (eg, photolithographically) using the patterning layer 502 to form an implantation mask pattern 501', which includes an opening in which a portion of the surface S of the semiconductor layer structure 106 is exposed. Figure 5C , using the mask pattern 501' as an implantation mask, one or more ion implantation processes 500 are performed to implant a dopant of a second conductivity type (e.g., p-type) into the exposed portion of the surface S to form shielding structures 340a and 340b extending into the drift region 120 toward the substrate 100. The dose and / or implantation energy of the implantation process(es) 500 may be controlled to form shielding structures 340a and 340b having a desired dopant concentration and / or depth (e.g., D1 and D2) relative to the surface S (e.g., higher implantation energy results in a deeper depth). The dopant concentration of the shielding structures 340a and / or 340b may be substantially uniform or graded (e.g., stepwise or continuous).

[0098] FIG. 5A to FIG. 5C The example illustrates a single mask 501' and high energy ion implantation process 500 for forming a bottom shield structure 340a and a supporting shield structure 340b simultaneously or in the same process step, such that the shield structures 340a, 340b may have the same dopant concentration and / or the same depth relative to the surface S of the semiconductor layer structure 106 (i.e., D1=D2). However, it will be understood that the embodiments described herein are not limited to a single mask application and / or implantation process, and that multiple mask applications and implantation operations may be performed sequentially (e.g., may be repeated or iterated) using different mask shapes (for exposing different portions of the surface S), different implantation energies, and / or different doses. Figure 5A , Figure 5B or Figure 5C ), such that the bottom shield structure 340a and the supporting shield structure 340b may have different shapes, different depths (ie, D1≠D2), and / or different dopant concentrations from each other.

[0099] exist Figure 5D In the process, the mask 501' is removed, an etching mask layer 503 (eg, an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterned layer 504 is formed on the etching mask layer 503. Figure 5E In the embodiment, the etching mask layer 503 is patterned using the patterning layer 504 to form an etching mask pattern 503', which includes openings in which portions of the surface S of the semiconductor layer structure 106 between the support shield structures 340b are exposed. Fig. 5FIn the embodiment of the present invention, an etching process 550 is performed to selectively etch the portion of the surface S exposed by the etching mask pattern 503', thereby forming a gate trench 180 extending into the drift region 120 between and spaced apart from the supporting shield structures 340b. The bottom shield structure 340a extends below and at least partially along the bottom surface of the gate trench 180. After removing the mask pattern 503', a gate oxide layer 182, a gate electrode 184, a source contact 190, an intermetallic dielectric 186, and a metal layer 196 may be formed to provide a gate electrode 184. Figure 3A Device 300a.

[0100] exist Figure 5A-5F In an example operation of , the support shield structure 340b and the bottom shield structure 340a are formed using the same (one or more) implantation processes 500 before forming the gate trench 180. Therefore, the support shield structure 340b and the bottom shield structure 340a can have the same or substantially similar depth and dopant concentration. However, because the gate trench 180 is etched into the bottom shield structure 340a formed by the pre-trench implantation process, the dopant profile in the bottom shield structure 340a (from the bottom surface of the trench 180 toward the substrate 110) may be steeper than the dopant profile of the support shield structure 340b (from the surface S toward the substrate 110).

[0101] Figure 6A-6H 1 is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device according to other embodiments of the present invention, the power semiconductor device including a bottom shield structure located below a gate trench and a support shield structure spaced apart from the sidewalls of the gate trench. In particular, Figure 6A-6H A method of forming shield structures 340a, 340b as implant regions is illustrated, wherein the bottom shield structure 340a is formed after the gate trench 180, which may be referred to herein as a trench-later-shield implant process.

[0102] like Fig. 6A As shown in , a semiconductor layer structure 106 is provided. As described above, the semiconductor layer structure 106 includes a drift region 120 of a first conductivity type (e.g., n-type), a current spreading layer 185, a JFET region 175, a well region 170, and a source region 160. A heavily doped region 174 of a second conductivity type is illustrated, but in an embodiment where the support shielding structure 340b is to be formed as an injection region, the heavily doped region may be omitted. The semiconductor layer structure 106 may include a substrate 110 and / or other layers. A mask layer 601 is formed on a surface S of the semiconductor layer structure 106, and a patterned layer 602 is formed on the mask layer 601.

[0103] exist Figure 6BIn the embodiment, the mask layer 601 is patterned (eg, photolithographically) using the patterning layer 602 to form an implantation mask pattern 601', which includes openings in which portions of the surface S of the semiconductor layer structure 106 are exposed. Figure 6C , one or more ion implantation processes 600 are performed using the mask pattern 601' as an implantation mask to implant a dopant of a second conductivity type (e.g., p-type) into the exposed portion of the surface S to form a support shield structure 340b extending into the drift region 120 toward the substrate 100. The dose and / or implantation energy of the implantation process(es) 600 may be controlled to form a support shield structure 340b having a desired dopant concentration and / or a desired depth (e.g., D2) relative to the surface S. The dopant concentration of the support shield structure 340b may be substantially uniform or graded (e.g., stepwise or continuous).

[0104] exist Fig.6D In the process, the mask 601' is removed, an etching mask layer 603 (eg, an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterned layer 604 is formed on the etching mask layer 603. Fig. 6E In the embodiment, the etching mask layer 603 is patterned using the patterning layer 604 to form an etching mask pattern 603', which includes openings in which portions of the surface S of the semiconductor layer structure 106 between the support shield structures 340b are exposed. Fig. 6F In the embodiment, an etching process 650 is performed to selectively etch portions of the surface S exposed by the etching mask pattern 603', thereby forming gate trenches 180 extending into the drift region 120 between and spaced apart from the supporting shield structures 340b.

[0105] exist Figure 6G , a mask 655 (e.g., an oxide mask) is formed on the sidewalls and bottom surface of the gate trench 180. For example, the trench 180 may be oxidized and / or a coating may be deposited along the sidewalls and bottom surface of the gate trench 180 to form the mask 655. In some embodiments, the portion of the mask 655 on the sidewalls may be formed thicker than the portion of the mask 655 on the bottom surface of the gate trench 180, for example, to protect the conductive sidewalls of the trench 180 from the implantation process used to form the shield structure 340a.

[0106] exist Figure 6H, one or more ion implantation processes 600' are performed to implant a second conductivity type dopant into the bottom surface of the trench 180 using the mask 655 as an implantation mask to form a bottom shield structure 340a located below the bottom surface of the gate trench 180 and extending at least partially along the bottom surface of the gate trench 180. The dose and / or implantation energy of the (one or more) implantation processes 600' can be controlled to form a bottom shield structure 340a having a desired dopant concentration and / or a desired depth (e.g., D1) relative to the surface S, and / or having a substantially uniform or graded dopant concentration. The mask 655 is removed, and then the gate oxide layer 182, the gate electrode 184, the source contact 190, the intermetallic dielectric 186, and the metal layer 196 can be formed to provide Figure 3A Device 300a.

[0107] exist Figure 6A-6H In an example operation, before forming the gate trench 180, a first high energy implant 600 is used to form the support shield structure 340b, and a second high energy implant 600' is used to form the bottom shield structure 340a. The dose and / or implant energy of the second implant 600' may be the same or different from the first implant 600. Therefore, 6A to 6H The operations shown in can be advantageous in easily forming a supporting shield structure 340b having a different depth, concentration, and / or material than the bottom shield structure 340a. For example, using multiple implant processes 600 and 600' can allow different implant energies and / or dopant profiles to be selected for each of the first implant process and the second implant process, for example, to form a supporting shield structure 340b that extends to a deeper depth than the bottom shield structure 340a and / or has a different dopant concentration. For example, a bottom shield structure 340a can be formed separately to have a dopant concentration similar to or lower than that of the supporting shield structure 340b. Forming the bottom shield structure 340a after forming the gate trench 180 can also produce similar (e.g., Gaussian) distributions of dopants over the depths of the shield structures 340a and 340b (from the bottom surface of the trench 180 toward the substrate 110 and from the surface S toward the substrate 110, respectively).

[0108] Figure 7A-7H 1 is a schematic cross-sectional view illustrating an example manufacturing operation for forming a power semiconductor device according to some other embodiments of the present invention, the power semiconductor device including a bottom shield structure located below a gate trench and a support shield structure spaced apart from the sidewalls of the gate trench. In particular, Figure 7A-7H Illustrated is a method of forming shield structures 340a', 340b' of different material(s) than the drift region 120, wherein the bottom shield structure 340a' is formed prior to forming the gate trench 180', which may be referred to herein as a pre-trench heterojunction shielding process.

[0109] like Fig. 7A As shown in , a semiconductor layer structure 106 is provided as described with reference to any of the above embodiments. A mask layer 701 is formed on a surface S of the semiconductor layer structure 106, and a patterned layer 702 is formed on the mask layer 701. Figure 7B In the embodiment, the mask layer 701 is patterned (eg, photolithographically) using the patterning layer 702 to form a first etch mask pattern 701' including an opening in which a portion of the surface S of the semiconductor layer structure 106 is exposed.

[0110] exist Figure 7C In one embodiment, one or more etching processes 700 are performed using the first mask pattern 701' as an etching mask to form shielding trenches 780 into the exposed portion of the surface S. The etching process(es) 700 may be controlled to provide shielding trenches 780 having a desired depth (e.g., D1, D2). Fig.7D In the embodiment of the present invention, one or more deposition processes are performed to form a material of a second conductivity type (e.g., p-type) in the shielding trench 780, and the material of the second conductivity type can be removed from the surface S of the semiconductor layer structure 106 (e.g., by one or more planarization processes), thereby forming shielding structures 340a' and 340b' extending into the drift region 120 toward the substrate 100. For example, the drift region 120 can be formed of an n-type material (e.g., SiC), and the shielding structures 340a' and 340b' can be formed of one or more p-type materials (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0111] FIG. 7A to FIG. 7D The example illustrates a single mask 701', etching process 700, and deposition process for forming a bottom shield structure 340a' and a supporting shield structure 340b' simultaneously or in the same processing step, such that the shield structures 340a', 340b' may be formed of the same (one or more) materials and / or have the same depth relative to the surface S of the semiconductor layer structure 106 (i.e., D1=D2). However, it will be understood that the embodiments described herein are not limited to a single mask application and / or etching process, and that multiple mask application and etching operations may be performed sequentially (e.g., may be repeated or iterated) with different mask shapes (for exposing different portions of the surface S), with different etching processes (for forming shield trenches 780 of different depths), and / or with different deposition processes. Fig. 7A , Figure 7B , Figure 7C or Fig.7Done or more of), such that the bottom shield structure 340a' and the supporting shield structure 340b' may have different shapes, different depths (i.e., D1≠D2) and / or may be formed of different materials from each other (e.g., the bottom shield structure 340a' may be p-poly-Si, while the supporting shield structure 340b' may be p-NiO).

[0112] exist Fig. 7E In the process, a mask layer 703 (eg, an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterned layer 704 is formed on the mask layer 703. Figure 7F In the embodiment, the mask layer 703 is patterned using the patterned layer 704 to form a second etch mask pattern 703', which includes an opening between the supporting shield structures 340b' in which a portion of the surface S of the semiconductor layer structure 106 (including the surface of the bottom shield structure 340a') is exposed. Figure 7G In the embodiment, an etching process 750 is performed to selectively etch the portion of the surface S exposed by the etching mask pattern 03', thereby forming a gate trench 180 extending into the drift region 120 and located between and spaced apart from the supporting shield structures 340b'. The bottom shield structure 340a' remains below and at least partially along the bottom surface of the gate trench 180. Figure 7H The mask pattern 503' is removed. Subsequently, a gate oxide layer 182, a gate electrode 184, a source contact 190, an intermetallic dielectric 186, and a metal layer 196 may be formed to provide Figure 3B Device 300b.

[0113] Figure 8A-8H 1 is a schematic cross-sectional view illustrating example manufacturing operations for forming a power semiconductor device according to yet other embodiments of the present invention, the power semiconductor device including a bottom shield structure located below a gate trench and a support shield structure spaced apart from the sidewalls of the gate trench. In particular, Figure 8A-8H Illustrated is a method of forming shield structures 340a', 340b' of different material(s) than the drift region 120, wherein the bottom shield structure 340a' is formed after the gate trench 180', which may be referred to herein as a post-trench heterojunction shielding process.

[0114] like Fig. 8A As shown in , a semiconductor layer structure 106 is provided as described in any of the above embodiments. A mask layer 801 is formed on a surface S of the semiconductor layer structure 106, and a patterned layer 802 is formed on the mask layer 801. Figure 8BIn the embodiment, the mask layer 801 is patterned (eg, photolithographically) using the patterning layer 802 to form a first etch mask pattern 801' including an opening in which a portion of the surface S of the semiconductor layer structure 106 is exposed.

[0115] exist Figure 8C In one embodiment, one or more etching processes 800 are performed using the first mask pattern 801' as an etching mask to form a support shield trench 880 extending into the exposed portion of the surface S. The etching process(es) 800 may be controlled to form the support shield trench 880 having a desired depth (e.g., D2) relative to the surface S. Fig.8D In the embodiment of the present invention, one or more deposition processes are performed to form a material of a second conductivity type (e.g., p-type) in the support shield trench 880, and the material of the second conductivity type is removed from the surface S (e.g., by one or more planarization processes), thereby forming a support shield structure 340b' extending into the drift region 120 toward the substrate 100. For example, the drift region 120 may be formed of an n-type material (e.g., SiC), and the support shield structure 340b' may be formed of a p-type material (e.g., p-NiO, p-poly-Si, p-GaN, p-Ga2O3).

[0116] exist Fig. 8E In the embodiment, an etching mask layer 803 (eg, an oxide layer) is formed on the surface S of the semiconductor layer structure 106, and a patterned layer 804 is formed on the etching mask layer 803. Figure 8F In the embodiment, the etch mask layer 803 is patterned using the patterning layer 804 to form a second etch mask pattern 803' including openings between the support shield structures 340b' in which portions of the surface S of the semiconductor layer structure 106 are exposed.

[0117] exist Figure 8G In the embodiment, an etching process 850 is performed to selectively etch portions of the surface S exposed by the etching mask pattern 803', thereby forming a gate trench 180' extending into the drift region 120 between and spaced apart from the supporting shield structures 340b'. The etching process(es) 850 may be controlled to form the supporting gate trench 180' having a desired depth (e.g., D1) relative to the surface S, which may be the same as or different from the depth D2 of the supporting shield trench 880.

[0118] exist Figure 8HIn the process, one or more selective deposition processes are performed to form a material of a second conductivity type (e.g., p-type) in the gate trench 180', thereby forming a bottom shield structure 340a' extending into the drift region 120 toward the substrate 100. The bottom shield structure 340a' may partially fill the gate trench 180', such that the depth of the gate trench 180' may define a depth D1 of the bottom shield structure 340a'. Different deposition processes may be performed, such that the bottom shield structure 340a' and the supporting shield structure 340b' may have different shapes, different depths (i.e., D1≠D2), and / or may be formed of different materials from each other. The second mask pattern 803' is removed, and then a gate oxide layer 182, a gate electrode 184, a source contact 190, an intermetallic dielectric 186, and a metal layer 196 may be formed to provide Figure 3B Device 300b.

[0119] exist Figure 8A-8H In an example operation, before forming the gate trench 180', a first etching and deposition process is used to form the support shield structure 340b', and a second etching and deposition process is used to fill a portion of the gate trench 180' to form the bottom shield structure 340a'. FIG. 8A to FIG. 8H The operations shown in can be advantageous in easily forming a support shield structure 340b' having a different depth and / or material than the bottom shield structure 340a'. For example, using multiple etching processes 800, 850 and / or multiple deposition processes can allow different depths and / or materials to be selected, such that the support shield structure 340b' extends to a greater depth and / or is formed of a material with a lower resistance than the bottom shield structure 340a'.

[0120] It will be understood that Figures 5A-8H Any of the operations shown in can be combined in various embodiments herein. For example, Figure 5A-5F One or more of the trench front shield implant operations may be performed in Figure 7A-7H One or more operations are performed between the trench front heterojunction shielding operations and vice versa. Figure 6A-6H One or more of the trench post-shield implant operations may be performed in Figure 8A-8H One or more operations are performed between the trenching and post-heterojunction shielding operations, and vice versa. More generally, Figures 5A-8H The manufacturing operations shown in the reference form Figure 3A The implantation shielding regions 340a, 340b or Figure 3B The heterojunction shielding regions 340a', 340b are described by way of example, but it will be understood that any of the operations shown can be used in combination to provide any desired combination of injection shielding regions and heterojunction shielding regions, such as, for example Figures 3C to 4DAny structures shown in , which have similar or different shapes, similar (ie, D1=D2) or different (ie, D1≠D2) depths, and / or the same or different materials as each other.

[0121] Thus, the embodiments described herein illustrate various examples of different combinations of bottom shield structures (e.g., 240a, 340a, 340a') and support shield structures (e.g., 240b, 340b, 340b') according to the present invention that can be beneficial in protecting the gate oxide 182, particularly at the bottom surface and edges / corners of the gate trenches 180, 180'. However, it will be understood that embodiments of the present invention may include any and all combinations of the features described herein and are not limited to the examples shown. Embodiments of the present invention may be used for trench vertical semiconductor power transistors, including but not limited to MOSFETs, IGBTs, or other power devices that include transistor terminals in the trench region.

[0122] In the above description, each example embodiment is described with reference to regions of a particular conductivity type. It will be appreciated that by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments, devices of opposite conductivity types can be formed. Thus, it will be appreciated that the present invention encompasses both n-channel and p-channel devices of each of the different device structures (e.g., MOSFET, IGBT, etc.).

[0123] The present invention is discussed above primarily with respect to power semiconductor devices based on silicon carbide. However, it will be appreciated that silicon carbide is used herein as an example, and the devices discussed herein may be formed in any suitable wide bandgap semiconductor material system. As an example, in any of the above embodiments, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide. More generally, while discussed with reference to silicon carbide devices, embodiments of the present invention are less limited and may be applicable to devices formed using other wide bandgap semiconductor materials (e.g., gallium nitride, zinc selenide, or any other II-VI or III-V wide bandgap compound semiconductor material).

[0124] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are illustrated. However, it will be appreciated that the present invention may be implemented in many different forms and should not be construed as being limited to the above-described embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0125] It will be understood that, although the terms first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0126] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms unless the context clearly indicates otherwise. It will also be understood that the terms "comprise", "include" and / or "comprising" specify the presence of stated features, complete objects, steps, operations, elements and / or components when used herein, but do not exclude the presence or addition of one or more other features, complete objects, steps, operations, elements, components and / or groups thereof.

[0127] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending onto the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0128] Relative terms such as "below" or "above" or "up" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0129] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Embodiments of the invention are also described with reference to manufacturing operations. It will be appreciated that the steps shown in the manufacturing operations need not be performed in the order shown.

[0130] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions that are characterized as having conductivity types such as n-type or p-type, where the conductivity type relates to the majority carrier concentration in the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. A material may be designed to have a "+" or "-" (such as n+, n-, p+, p-, n++, n--, p++, p--, etc.) to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers than another layer or region. However, such a symbol does not mean that a particular concentration of majority or minority carriers is present in a layer or region.

[0131] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A power semiconductor device, comprising: A semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls; a bottom shield structure of a second conductivity type located below a bottom surface of the gate trench; as well as First and second supporting shield structures of a second conductivity type extend into the drift region on opposite sides of the gate trench and are spaced apart from sidewalls of the gate trench.

2. The power semiconductor device of claim 1 , wherein one or more of the first and second supporting shield structures extend into the drift region to a depth relative to the surface of the semiconductor layer structure that is different from a depth of the bottom shield structure. 3 . The power semiconductor device of claim 2 , wherein the first supporting shield structure and the second supporting shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micrometer. 4 . The power semiconductor device of claim 1 , wherein at least one of the bottom shield structure, the first supporting shield structure or the second supporting shield structure comprises a material different from a material of the drift region.

5. The power semiconductor device of claim 4, wherein the drift region comprises a wide bandgap semiconductor material, and the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide. 6 . The power semiconductor device of claim 4 , wherein the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure further comprises an implanted portion of the drift region.

7. A power semiconductor device as described in any one of claims 1 to 3, wherein the bottom shield structure includes a first concentration of dopants of the second conductivity type, and the first supporting shield structure and the second supporting shield structure include a second concentration of dopants of the second conductivity type different from the first concentration. The power semiconductor device of claim 7 , wherein the second concentration is higher than the first concentration.

9. A power semiconductor device as claimed in any preceding claim, wherein the semiconductor layer structure further comprises a substrate, the substrate comprising a drift region thereon and a well region of a second conductivity type opposite to the substrate in or on the drift region, The first support shielding structure and the second support shielding structure extend through the well region and beyond the bottom shielding structure and are spaced apart from the substrate. 10 . The power semiconductor device of claim 9 , wherein the first supporting shield structure and the second supporting shield structure have a different concentration of dopants of the second conductivity type than the well region. 11 . The power semiconductor device of claim 9 , wherein the first support shield structure and the second support shield structure are spaced apart from the substrate by about 1 to about 100 microns. 12 . The power semiconductor device of claim 1 , wherein the bottom shield structure extends along a portion of a bottom surface of the gate trench.

13. The power semiconductor device of any one of claims 1 to 11, wherein the bottom shield structure extends along the entirety of the bottom surface of the gate trench.

14. A power semiconductor device, comprising: A semiconductor layer structure including a drift region of a first conductivity type; a gate trench extending into the drift region, the gate trench including sidewalls and a bottom surface between the sidewalls; a bottom shield structure of a second conductivity type located below a bottom surface of the gate trench; as well as first and second supporting shield structures of a second conductivity type extending into the drift region on opposite sides of the gate trench and spaced apart from the sidewalls of the gate trench, The material composition, the distance extending into the drift region relative to the surface of the semiconductor layer structure and / or the dopant concentration of the bottom shield structure differ from the first supporting shield structure and the second supporting shield structure.

15. A power semiconductor device as claimed in claim 14, wherein relative to the surface of the semiconductor layer structure, a distance that one or more of the first supporting shielding structure and the second supporting shielding structure extend into the drift region is greater than a distance that the bottom shielding structure extends into the drift region. 16 . The power semiconductor device of claim 15 , wherein the first supporting shield structure and the second supporting shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micron. 17 . The power semiconductor device of claim 14 , wherein a material composition of at least one of the bottom shield structure, the first supporting shield structure or the second supporting shield structure is different from a material composition of the drift region.

18. The power semiconductor device of claim 17, wherein the drift region comprises a wide bandgap semiconductor material, and the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

19. The power semiconductor device of claim 18, wherein the at least one of the bottom shield structure, the first supporting shield structure, or the second supporting shield structure further comprises an implanted region of the drift region.

20. The power semiconductor device of any one of claims 14 to 16, wherein the dopant concentration of the first supporting shield structure and the second supporting shield structure is lower than the dopant concentration of the bottom shield structure.

21. The power semiconductor device of claim 20, wherein the dopant concentration of the first supporting shield structure and the second supporting shield structure is higher than the dopant concentration of the bottom shield structure.

22. The power semiconductor device of any one of claims 14 to 21, wherein the semiconductor layer structure further comprises a substrate including a drift region thereon, and wherein the first support shield structure and the second support shield structure are spaced apart from the substrate by about 1 to about 100 microns.

23. A method for manufacturing a power semiconductor device, the method comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming a bottom shield structure of the second conductivity type extending into the drift region and a first supporting shield structure and a second supporting shield structure; as well as forming a gate trench extending into the drift region and spaced apart from the first support shield structure and the second support shield structure, The bottom shielding structure is located under the gate trench.

24. The method of claim 23, wherein forming the gate trench is performed after forming the bottom shield structure.

25. The method of claim 23, wherein forming a bottom shield structure and a first supporting shield structure and a second supporting shield structure comprises: One or more of the first and second supporting shield structures are formed extending into the drift region to a depth relative to a surface of the semiconductor layer structure that is different from a depth of the bottom shield structure.

26. The method of claim 25, wherein the first support shield structure and the second support shield structure extend into the drift region beyond the bottom shield structure by about 0.1 to about 1 micron.

27. The method of claim 23, wherein forming at least one of a bottom shield structure or first and second supporting shield structures comprises: performing one or more etching operations to form corresponding shielding trenches in the drift region; as well as One or more deposition operations are performed to form a material in the corresponding shield trenches that is different from the material of the drift region.

28. The method of claim 27, wherein the drift region comprises a wide bandgap semiconductor material, and the at least one of the bottom shield structure or the first and second supporting shield structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

29. The method of claim 27, wherein forming the at least one of a bottom shield structure or first and second supporting shield structures further comprises: One or more ion implantation operations are performed to implant dopants of the second conductivity type into portions of the drift region underlying corresponding shield trenches.

30. The method of claim 23, wherein forming at least one of a bottom shield structure or first and second supporting shield structures comprises: One or more ion implantation operations are performed to implant dopants of the second conductivity type into the drift region.

31. The method of claim 30, wherein: In response to the one or more ion implantation operations, the bottom shield structure includes a first concentration of dopants of the second conductivity type, and the first and second supporting shield structures include a second concentration of dopants of the second conductivity type different from the first concentration.

32. The method of claim 30, wherein the second concentration is higher than the first concentration.

33. A method for manufacturing a power semiconductor device, the method comprising: providing a semiconductor layer structure including a drift region of a first conductivity type; forming a first support shield structure and a second support shield structure of a second conductivity type extending into the drift region; forming a gate trench extending into the drift region and spaced apart from the first support shield structure and the second support shield structure, the gate trench including sidewalls and a bottom surface between the sidewalls; as well as A bottom shield structure of the second conductivity type is formed below a bottom surface of the gate trench.

34. The method of claim 33, wherein forming a bottom shield structure comprises: After forming the gate trench, one or more ion implantation and / or deposition operations are performed to form a bottom shield structure extending into the drift region to a first depth relative to a surface of the semiconductor layer structure.

35. The method of claim 34, wherein the bottom shield structure has a different material composition, a distance extending to the drift region relative to the surface of the semiconductor layer structure and / or a dopant concentration than the first and second supporting shield structures.

36. The method of claim 34, wherein forming the first support shield structure and the second support shield structure comprises: Before forming the gate trench, one or more of the first and second supporting shield structures are formed, the one or more supporting shield structures extending into the drift region to a second depth relative to the surface of the semiconductor layer structure, wherein the second depth is different from the first depth.

37. The method of claim 36, wherein the second depth is about 0.1 to about 1 micron greater than the first depth.

38. The method of claim 34, wherein forming a first support shield structure and a second support shield structure comprises: Prior to forming the gate trenches, one or more etching operations are performed to form corresponding shield trenches in the drift region, and one or more deposition operations are performed to form a material different from a material of the drift region in the corresponding shield trenches.

39. The method of claim 38, wherein the drift region comprises a wide bandgap semiconductor material and at least one of the bottom shield structure or the first and second supporting shield structures comprises polysilicon, nickel oxide, gallium nitride, or gallium oxide.

40. The method of claim 38, wherein forming the first support shield structure and the second support shield structure further comprises: Prior to forming the gate trenches, one or more ion implantation operations are performed to implant dopants of the second conductivity type into portions of the drift region underlying the respective shield trenches.

41. The method of claim 34, wherein forming a first support shield structure and a second support shield structure comprises: Prior to forming the gate trench, one or more ion implantation operations are performed to implant dopants of the second conductivity type into the drift region.

42. The method of claim 41, wherein: In response to the one or more ion implantation operations, the first and second supporting shield structures include a second concentration of dopants of the second conductivity type that is different from the first concentration of dopants of the second conductivity type of the bottom shield structure.

43. The method of claim 42, wherein the second concentration is higher than the first concentration.

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