Three-dimensional memory device with source line isolation and method of manufacturing same

Abstract

A memory device includes a horizontal source layer laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench filling structure or a source isolation dielectric structure.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Patent Application No. 17 / 934,676 filed on September 23, 2022 and U.S. Non-Provisional Patent Application No. 17 / 934,685 filed on September 23, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional memory device including source lines laterally electrically isolated by a source line isolation structure and a method of manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High-Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory device includes: a source layer, the source layer including at least one doped semiconductor material; an alternating stack of insulating layers and conductive layers located above the source layer, the alternating stack extending along a first horizontal direction and laterally spaced apart from each other by backside trenches along a second horizontal direction, wherein the backside trenches include at least one first backside trench and at least one second backside trench, the at least one first backside trench containing a corresponding backside contact via structure, the backside contact via structure including conductive material contacting the source layer, the at least one second backside trench containing a corresponding dielectric trench filling structure, the dielectric trench filling structure extending from above the topmost surface of the alternating stack to at least the bottom surface of the source layer; memory openings, wherein each of the memory openings extends vertically through a corresponding one of the alternating stacks; and a memory opening filling structure, the memory opening filling structure being located in the memory opening and including a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel.

[0006] According to another aspect of the present disclosure, a method for forming a memory device is provided, the method comprising: forming a vertical alternating sequence of continuous insulating layers and continuous sacrificial material layers above a substrate; forming a memory opening through the vertical alternating sequence; forming a memory opening in the memory opening, wherein each of the memory opening filling structures includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; dividing the vertical alternating sequence into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches that extend laterally along a first horizontal direction and are laterally spaced apart along a second horizontal direction; replacing the sacrificial material layer with a conductive layer to form alternating stacks of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the backside trenches; extending a second subset of the backside trenches vertically without extending the first subset of the backside trenches vertically; forming a dielectric trench filling structure in the second subset of the backside trenches; and forming a backside trench filling structure in the first subset of the backside trenches, wherein each of the backside trench filling structures includes a corresponding backside insulating spacer and a corresponding backside contact through-hole structure.

[0007] According to another aspect of the present disclosure, a memory device includes: a source layer, the source layer including at least one doped semiconductor material; a source isolation dielectric structure, the source isolation dielectric structure extending laterally along a first horizontal direction and laterally separating the source layer into a first source layer portion and a second source layer portion electrically isolated from the first source layer portion; an alternating stack of insulating layers and conductive layers located above the source layer, the alternating stack extending along the first horizontal direction and laterally spaced apart from each other along a second horizontal direction by at least one first backside trench and at least one second backside trench, the at least one first backside trench being filled with a dielectric structure including a first source layer portion contacting the source layer; a corresponding first back side trench filling structure of a corresponding first back side contact through-hole structure, the at least one second back side trench being filled with a corresponding second back side trench filling structure including a corresponding second dummy back side contact through-hole structure contacting the source isolation dielectric structure; a memory opening, wherein each of the memory openings vertically extends through a corresponding one of the alternating stacks; and a memory opening filling structure, the memory opening filling structure being located in the memory opening and comprising a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel, wherein a sidewall of the corresponding vertical semiconductor channel is in contact with the source layer.

[0008] According to another aspect of the present disclosure, a method for forming a memory device includes: forming a lateral alternating sequence of source level material layers and source isolation dielectric structures in a process above a substrate; forming a vertical alternating sequence of continuous insulating layers and continuous sacrificial material layers above the lateral alternating sequence; forming a memory opening through the vertical alternating sequence; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming a back side trench through the vertical alternating sequence to divide the vertical alternating sequence into an alternating stack of insulating layers and sacrificial material layers; replacing the sacrificial source layer within each source level material layer in the process with a corresponding source contact layer to convert the source level material layer in the process into a source level material layer; replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the back side trench; and forming a back side trench filling structure in the back side trench.

[0009] According to yet another aspect of the present disclosure, a method for forming a memory device includes: forming a source level material layer in a process above a substrate; forming a vertical alternating sequence of continuous insulating layers and continuous sacrificial material layers above the source level material layer in the process; forming a memory opening through the vertical alternating sequence; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming a backside trench through the vertical alternating sequence to divide the vertical alternating sequence into The invention relates to an alternating stack of insulating layers and sacrificial material layers; replacing a sacrificial source layer within a source level material layer in the process with a source contact layer to convert the source level material layer in the process into a continuous source level material layer; replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stack being laterally spaced apart from each other by the back side trench; forming a back side trench filling structure in the back side trench; removing at least a back side portion of the substrate; and dividing the continuous source level material layer into a plurality of source level material layers by forming a source isolation trench passing through the continuous source level material layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a vertical cross-sectional view of the first exemplary structure after forming a semiconductor device, a lower level dielectric layer, a lower level metal interconnect structure, and a source level material layer in process according to the first embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Figure 1AA plane of a vertical section.

[0012] Figure 1C It is along Figure 1B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0013] Figure 2 is a vertical cross-sectional view of the first exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the first embodiment of the present disclosure.

[0014] Figure 3 is a vertical cross-sectional view of the first exemplary structure after patterning the first stepped surface, the first backward stepped dielectric material portion, and the interlayer dielectric layer according to the first embodiment of the present disclosure.

[0015] Figure 4A is a vertical cross-sectional view of the first exemplary structure after forming a first layer memory opening and a first layer support opening according to the first embodiment of the present disclosure.

[0016] Figure 4B yes Figure 4A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Figure 4A A plane of a vertical section.

[0017] Figure 5 is a vertical cross-sectional view of the first exemplary structure after forming a sacrificial memory opening filling portion and a first layer support opening filling portion according to the first embodiment of the present disclosure.

[0018] Figure 6 is a vertical cross-sectional view of the first exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to the first embodiment of the present disclosure.

[0019] Fig. 7A is a vertical cross-sectional view of the first exemplary structure after forming a second layer memory opening and a second layer support opening according to the first embodiment of the present disclosure.

[0020] Figure 7B It is along Fig. 7A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 7A A plane of a vertical section.

[0021] Fig. 8A is a vertical cross-sectional view of the first exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to the first embodiment of the present disclosure.

[0022] Figure 8B yes Fig. 8A A vertical cross-sectional view of a region of a first exemplary structure.

[0023] 9A to 9D are sequential vertical cross-sectional views of a pair of inter-layer memory openings during formation of a pair of memory opening filling structures according to a first embodiment of the present disclosure.

[0024] Fig. 10A is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0025] Fig. 10B It is along Fig. 10A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig. 10A A plane of a vertical section.

[0026] Fig.11A is a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0027] Fig. 11B It is along Fig.11A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.11A A plane of a vertical section.

[0028] Fig. 11C It is along Fig. 11B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0029] Fig.12 is a vertical cross-sectional view of the first exemplary structure after forming backside trench spacers in the backside trenches according to the first embodiment of the present disclosure.

[0030] FIG. 13A to FIG. 13E Sequential vertical cross-sectional views showing regions of a first exemplary structure during formation of a source level material layer according to a first embodiment of the present disclosure.

[0031] Fig.14 is a vertical cross-sectional view of the first exemplary structure after forming a source level material layer according to the first embodiment of the present disclosure.

[0032] Fig.15 is a vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0033] Fig.16A is a vertical cross-sectional view of a first exemplary structure after forming a conductive layer in a backside recess according to the first embodiment of the present disclosure.

[0034] Fig. 16B It is along Fig.16A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0035] Fig.17A is a vertical cross-sectional view of the first exemplary structure after forming a patterned etch mask layer covering the second subset of backside trenches but not covering the first subset of backside trenches according to the first embodiment of the present disclosure.

[0036] Fig. 17B yes Fig.17A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.17A A plane of a vertical section.

[0037] Fig. 17C It is along Fig. 17B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0038] Fig.18A is a vertical cross-sectional view of the first exemplary structure after forming a dielectric trench fill structure in the second subset of backside trenches and removing the patterned etch mask layer according to the first embodiment of the present disclosure.

[0039] Fig.18B yes Fig.18A A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.18A A plane of a vertical section.

[0040] Fig.18C It is along Fig.18B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0041] Fig.18D yes 18A to 18C An enlarged vertical cross-sectional view of a region of a first exemplary structure.

[0042] Fig.19A is a vertical cross-sectional view of the first exemplary structure after forming a backside trench fill structure in a first subset of backside trenches according to the first embodiment of the present disclosure.

[0043] Fig.19B It is along Fig.19AThe horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.19A A plane of a vertical section.

[0044] Fig.19C It is along Fig.19B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0045] Fig.19D It is along Fig.19B A vertical cross-sectional view of the first exemplary structure taken along a serrated vertical plane DD'.

[0046] Fig.19E yes 19A to 19D A top view of the first exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.19A The zigzag vertical plane D-D' corresponds to Fig.19D A plane of a vertical section.

[0047] Fig.19F yes FIG. 19A to FIG. 19E An enlarged vertical cross-sectional view of a region of a first exemplary structure.

[0048] Fig. 20A is a vertical cross-sectional view of a first alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0049] Fig. 20B is a vertical cross-sectional view of a second alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0050] Fig.21A is a vertical cross-sectional view of the first exemplary structure after forming a drain contact via structure and a layer contact via structure according to the first embodiment of the present disclosure.

[0051] Fig. 21B It is along Fig.21A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.21A A plane of a vertical section.

[0052] Fig. 22 is a vertical cross-sectional view of the first exemplary structure after forming a through-memory level connection via structure and a higher level metal interconnect structure according to the first embodiment of the present disclosure.

[0053] Fig.23A is a vertical cross-sectional view of a second exemplary structure after forming a source level material layer and a source isolation dielectric structure according to a second embodiment of the present disclosure.

[0054] Fig. 23B yes Fig.23A A top view of the second exemplary structure of FIG. The vertical plane AA' is Fig.23A A plane of a vertical section.

[0055] Fig.23C It is along Fig. 23B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0056] Fig.24 is a vertical cross-sectional view of a second exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the second embodiment of the present disclosure.

[0057] Fig.25 is a vertical cross-sectional view of a second exemplary structure after patterning a first stepped surface, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a second embodiment of the present disclosure.

[0058] Fig.26A is a vertical cross-sectional view of a second exemplary structure after forming a first-layer memory opening and a first-layer support opening according to the second embodiment of the present disclosure.

[0059] Fig.26B It is along Fig.26A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.26A A plane of a vertical section.

[0060] Fig. 27 is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial memory opening-filling portion and a first-layer support opening-filling portion according to the second embodiment of the present disclosure.

[0061] Fig.28 is a vertical cross-sectional view of a second exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to a second embodiment of the present disclosure.

[0062] Fig.29 is a vertical cross-sectional view of a second exemplary structure after forming a second layer memory opening and a second layer support opening according to the second embodiment of the present disclosure.

[0063] Fig.30 is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to the second embodiment of the present disclosure.

[0064] Fig.31A is a vertical cross-sectional view of a second exemplary structure after forming backside trenches according to the second embodiment of the present disclosure.

[0065] Fig.31B It is along Fig.31A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.31A A plane of a vertical section.

[0066] Fig.31C It is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0067] Fig.31D It is along Fig.31B A vertical cross-sectional view of the second exemplary structure taken along a serrated vertical plane DD'.

[0068] Fig.32A is a vertical cross-sectional view of a second exemplary structure after a source level material layer is replaced with a source level material layer according to the second embodiment of the present disclosure.

[0069] Fig.32B It is along Fig.32A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.32A A plane of a vertical section.

[0070] Fig.32C It is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0071] Fig.32D It is along Fig.32B A vertical cross-sectional view of the second exemplary structure taken along a serrated vertical plane DD'.

[0072] Fig.33 is a vertical cross-sectional view of a second exemplary structure after forming a backside recess according to the second embodiment of the present disclosure.

[0073] Fig.34A is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer in a backside recess according to a second embodiment of the present disclosure.

[0074] Fig.34B It is along Fig.34A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.34A A plane of a vertical section.

[0075] Fig.34C It is along Fig.34B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0076] Fig.34D It is along Fig.34B A vertical cross-sectional view of the second exemplary structure taken along a serrated vertical plane DD'.

[0077] Fig.35A is a vertical cross-sectional view of the second exemplary structure after forming a backside trench fill structure in the backside trench according to the second embodiment of the present disclosure.

[0078] Fig.35B yes Fig.35A A top view of a second exemplary structure of FIG. The sawtooth vertical plane AA' corresponds to Fig.35A A plane of a vertical section.

[0079] Fig.35C It is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a vertical plane CC'.

[0080] Fig.35D It is along Fig.35B A vertical cross-sectional view of the second exemplary structure taken along a serrated vertical plane DD'.

[0081] Fig.35E yes FIG. 35A to FIG. 35D An enlarged vertical cross-sectional view of a region of a second exemplary structure.

[0082] Fig.36 is a vertical cross-sectional view of a first alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0083] Fig.37 is a vertical cross-sectional view of a second alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure.

[0084] Fig.38A is a vertical cross-sectional view of a second exemplary structure after forming a drain contact via structure and a layer contact via structure according to the second embodiment of the present disclosure.

[0085] Fig.38B yes Fig.38A The zigzag vertical plane AA' corresponds to Fig.38A A plane of a vertical section.

[0086] Fig.39is a vertical cross-sectional view of a second exemplary structure after forming a through-memory level connection via structure and a higher level metal interconnect structure according to the second embodiment of the present disclosure.

[0087] Fig.40A is a vertical cross-sectional view of a third exemplary structure after forming a source level material layer and a source isolation dielectric structure on a substrate according to the third embodiment of the present disclosure.

[0088] Fig.40B yes Fig.40A An enlarged vertical cross-sectional view of a source level material layer in the process of the third exemplary structure.

[0089] Fig.41 is a vertical cross-sectional view of a third exemplary structure after forming a first vertical alternating sequence of first insulating layers and first spacer material layers according to the third embodiment of the present disclosure.

[0090] Fig.42 is a vertical cross-sectional view of a third exemplary structure after patterning a first stepped surface, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to a third embodiment of the present disclosure.

[0091] Fig.43A is a vertical cross-sectional view of a third exemplary structure after forming a first-layer memory opening and a first-layer support opening according to the third embodiment of the present disclosure.

[0092] Fig.43B It is along Fig.43A The horizontal cross-sectional view of the first exemplary structure is taken along the horizontal plane BB'. The sawtooth vertical plane AA' corresponds to Fig.43A A plane of a vertical section.

[0093] Fig.44 is a vertical cross-sectional view of a third exemplary structure after forming a sacrificial memory opening-filling portion and a first-layer support opening-filling portion according to the third embodiment of the present disclosure.

[0094] Fig.45 is a vertical cross-sectional view of a third exemplary structure after forming a second vertical alternating sequence of second insulating layers and second spacer material layers, a second stepped surface, a second backward stepped dielectric material portion, and a drain select level isolation structure according to a third embodiment of the present disclosure.

[0095] Fig.46A is a vertical cross-sectional view of a third exemplary structure after forming a second layer memory opening and a second layer support opening according to the third embodiment of the present disclosure.

[0096] Fig.46B yes Fig.46A A top view of a third exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.46A A plane of a vertical section.

[0097] Fig.47 is a vertical cross-sectional view of a third exemplary structure after forming an inter-layer memory opening according to the third embodiment of the present disclosure.

[0098] Fig.48A is a vertical cross-sectional view of a third exemplary structure after forming a memory opening filling structure and a support pillar structure according to the third embodiment of the present disclosure.

[0099] Fig.48B yes Fig.48A A top view of a third exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.48A A plane of a vertical section.

[0100] Fig.49A is a vertical cross-sectional view of a third exemplary structure after forming backside trenches according to a third embodiment of the present disclosure.

[0101] Fig.49B yes Fig.49A A top view of a third exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.49A A plane of a vertical section.

[0102] Fig.49C It is along Fig.49B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0103] Fig.50 is a vertical cross-sectional view of a third exemplary structure after forming sacrificial backside insulating spacers according to the third embodiment of the present disclosure.

[0104] Fig.51A is a vertical cross-sectional view of a third exemplary structure after a source level material layer is replaced with a source level material layer according to the third embodiment of the present disclosure.

[0105] Fig.51B yes Fig.51A An enlarged vertical cross-sectional view of a region of a third exemplary structure.

[0106] Fig.52 is a vertical cross-sectional view of a third exemplary structure after forming a backside recess according to a third embodiment of the present disclosure.

[0107] Fig.53A is a vertical cross-sectional view of a third exemplary structure after forming a conductive layer in a backside recess according to a third embodiment of the present disclosure.

[0108] Fig.53B yes Fig.53A A top view of a third exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.53A A plane of a vertical section.

[0109] Fig.54A is a vertical cross-sectional view of the third exemplary structure after forming a backside trench fill structure in the backside trench according to the third embodiment of the present disclosure.

[0110] Fig.54B yes Fig.54A A top view of a third exemplary structure. The sawtooth vertical plane AA' corresponds to Fig.54A A plane of a vertical section.

[0111] Fig.54C It is along Fig.54B A vertical cross-sectional view of the third exemplary structure taken along a vertical plane CC'.

[0112] Fig.54D yes FIG. 54A to FIG. 54C An enlarged vertical cross-sectional view of a region of a third exemplary structure.

[0113] Fig.55A is a vertical cross-sectional view of a third exemplary structure after forming a drain contact via structure and a layer contact via structure according to the third embodiment of the present disclosure.

[0114] Fig.55B yes Fig.55A A horizontal cross-sectional view of a third exemplary structure of FIG. The sawtooth vertical plane AA' corresponds to Fig.55A A plane of a vertical section.

[0115] Fig.56 is a vertical cross-sectional view of a third exemplary structure after forming a metal interconnection structure according to the third embodiment of the present disclosure.

[0116] Fig.57 is a vertical cross-sectional view of a third exemplary structure after forming a memory die according to the third embodiment of the present disclosure.

[0117] Fig.58 is a vertical cross-sectional view of a third exemplary structure after bonding a logic die to a memory die according to the third embodiment of the present disclosure.

[0118] Fig.59 is a vertical cross-sectional view of a third exemplary structure after thinning the memory side substrate of the memory die according to the third embodiment of the present disclosure.

[0119] Fig.60is a vertical cross-sectional view of a third exemplary structure after patterning a memory-side substrate and a source level material layer according to the third embodiment of the present disclosure.

[0120] Fig.61A is a vertical cross-sectional view of the third exemplary structure after forming a source isolation dielectric structure according to the third embodiment of the present disclosure.

[0121] Fig.61B yes Fig.61A A vertical cross-sectional view of a first alternative embodiment of a third exemplary structure at a processing step of .

[0122] Fig.61C yes Fig.61A A vertical cross-sectional view of a second alternative embodiment of the third exemplary structure at a processing step of .

[0123] Fig.62 is a vertical cross-sectional view of a third alternative embodiment of the third exemplary structure after attaching a carrier substrate to a memory die according to the third embodiment of the present disclosure.

[0124] Fig.63 is a vertical cross-sectional view of a third alternative embodiment of the third exemplary structure after thinning the memory side substrate and patterning the memory side substrate and source level material layers according to the third embodiment of the present disclosure.

[0125] Fig.64 is a vertical cross-sectional view of a third alternative embodiment of the third exemplary structure after forming a source isolation dielectric structure according to the third embodiment of the present disclosure.

[0126] Fig.65 is a vertical cross-sectional view of a third alternative embodiment of the third exemplary structure after separating the carrier substrate and bonding the logic die and forming the backside insulating layer and the backside contact via structure according to the third embodiment of the present disclosure. DETAILED DESCRIPTION

[0127] Embodiments of the present disclosure relate to a three-dimensional memory device including source lines laterally electrically isolated by a source line isolation structure and a method for manufacturing the same, various aspects of which are described in detail below.

[0128] The drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0129] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0130] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0131] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stacked" element refers to an element that extends vertically through a memory level.

[0132] As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10-5S / m to 1.0×105S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10-5S / m to 1.0S / m in the absence of an electrical dopant, and is capable of producing a doped material having an electrical conductivity in the range of 1.0S / m to 1.0×107S / m when appropriately doped with an electrical dopant. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×105S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity less than 1.0×10-5S / m. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0×105S / m) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). "Doped semiconductor material" may be a heavily doped semiconductor material, or may be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration providing a conductivity in the range of 1.0×10-5S / m to 1.0×107S / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material including at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0133] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0134] refer to Figures 1A to 1C , shows a first exemplary structure according to the first embodiment of the present disclosure. The first exemplary structure includes a semiconductor substrate 8 and a peripheral circuit 710 formed thereon. The first exemplary structure includes a memory array region 100 in which a three-dimensional memory array is to be formed subsequently, a staircase region 200 of a stepped surface in which a conductive layer and a contact via structure are to be formed subsequently, and a connection region 400 in which a peripheral contact via structure is to be formed subsequently.

[0135] The semiconductor substrate 8 includes a substrate semiconductor layer 9 at least at its upper portion. Various doped wells can be formed in the upper portion of the substrate semiconductor layer 9. A shallow trench isolation structure 720 can be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation between semiconductor devices. The peripheral circuit 710 includes field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channel regions 746, and gate structures 750. The field effect transistors can be arranged in a CMOS configuration. Each gate structure 750 can include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758.

[0136] The peripheral circuit 710 may include additional semiconductor devices other than the p-type field effect transistor and the n-type field effect transistor, which may be used to support the operation of the memory structure to be formed subsequently. The peripheral circuit 710 includes a driver circuit, which is also referred to as a peripheral circuit. As used herein, a peripheral circuit refers to any one, each or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer and / or a latch, or may be any other semiconductor circuit that can be implemented outside the memory array structure of the memory device. For example, the semiconductor device may include a word line switching device for electrically biasing the word lines of the three-dimensional memory structure to be formed subsequently.

[0137] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a lower-level dielectric material layer 760. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0138] The dielectric layer stack (which includes the lower level dielectric material layer 760) serves as a matrix of lower level metal interconnect structures 780 that provide electrical routing between various nodes of the semiconductor device and the landing pads of the through memory level contact via structures to be subsequently formed. The lower level metal interconnect structures 780 are embedded within the dielectric layer stack of the lower level dielectric material layer 760 and include lower level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0139] For example, the lower level metal interconnect structure 780 may be embedded in the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower level metal interconnect structure 780 are sequentially embedded. Each dielectric material layer selected among the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organic silicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxide (such as aluminum oxide). In one embodiment, the first dielectric material layer 764 may include or be substantially composed of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide). The lower level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting the corresponding source and drain nodes of the device or gate electrode contacts), intermediate lower level metal line structures 784, and lower level metal via structures 786. A subset of the lower level metal line structures 784 and / or lower level metal via structures 786 may be configured to serve as landing pads for subsequently formed through-memory level contact via structures.

[0140] At least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from among the at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organic silicate glass. In one embodiment, at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding 3.9 of the dielectric constant of undoped silicate glass (silicon oxide).

[0141] The peripheral circuit 710 may include peripheral devices for memory level components to be formed later. The lower level metal interconnect structure 780 is embedded in the lower level dielectric layer 760. The combination of the lower level dielectric layer 760 and the lower level metal interconnect structure 780 covers the peripheral circuit 710.

[0142] The lower level metal interconnect structure 780 may be electrically connected to an active node (e.g., transistor active region 742 or gate electrode 754) of the peripheral circuit 710 (e.g., a CMOS device) and is positioned at the level of the lower level dielectric layer 760. A through memory level contact via structure may then be formed directly on the lower level metal interconnect structure 780 to provide electrical connection to a memory device to be subsequently formed.

[0143] A process source level material layer 110' including a layer stack of material layers may be formed above the lower level dielectric layer 760. The process source level material layer 110' may include various layers that are subsequently modified to form the source level material layer. The source level material layer includes a source contact layer when formed, which serves as a common source region of a vertical field effect transistor of a three-dimensional memory device. In one embodiment, the process source level material layer 110' may include, from bottom to top, a lower source level material layer 112, a lower sacrificial liner 103, a source level sacrificial layer 104, a higher sacrificial liner 105, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118.

[0144] The lower source level material layer 112 and the higher source level material layer 116 may include doped semiconductor materials, such as doped polysilicon or doped amorphous silicon. The doped semiconductor material of the lower source level material layer 112 is referred to herein as a first doped semiconductor material, and the doped semiconductor material of the higher source level material layer 116 is referred to herein as a second doped semiconductor material, which may be the same as or different from the first doped semiconductor material. The conductivity type of the lower source level material layer 112 and the higher source level material layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a doping of a first conductivity type, the lower source level material layer 112 and the higher source level material layer 116 have a doping of a second conductivity type opposite to the first conductivity type. The thickness of each of the lower source level material layer 112 and the higher source level material layer 116 may be in the range of 10nm to 300nm, such as 20nm to 150nm, but smaller and larger thicknesses may also be used.

[0145] The source level sacrificial layer 104 includes sacrificial material that can be selectively removed for the lower sacrificial pad 103 and the upper sacrificial pad 105. In one embodiment, the source level sacrificial layer 104 can include a dielectric material such as silicon nitride or a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source level sacrificial layer 104 can be in the range of 30nm to 400nm, such as 60nm to 200nm, but smaller and larger thicknesses can also be used.

[0146] The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that can be used as etch stop materials during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can include silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can include a silicon oxide layer having a thickness in the range of 2nm to 30nm, although lesser and greater thicknesses can also be used.

[0147] The source level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source level insulating layer 117 may be in the range of 20 nm to 400 nm, such as 40 nm to 200 nm, although smaller and larger thicknesses may also be used. The optional source select level conductive layer 118 may include a conductive material that may be used as a source select level gate electrode. For example, the optional source select level conductive layer 118 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon, which may subsequently be converted into doped polysilicon by an annealing process. The thickness of the optional source level conductive layer 118 may be in the range of 30 nm to 200 nm, such as 60 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0148] The source level material layer 110' may be formed directly above a subset of semiconductor devices on a semiconductor substrate 8 (e.g., a silicon wafer) during the process. As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and an area of ​​the first element and the area of ​​the second element has an area overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8).

[0149] The in-process source level material layer 110' may be patterned to provide openings in areas where through memory level contact via structures and through dielectric contact via structures are subsequently formed. Patterned portions of the in-process source level material layer 110' are present in each memory array region 100 where a three-dimensional memory stacked structure is subsequently formed. At least one second dielectric material layer 768 may include: a blanket layer portion that is below the in-process source level material layer 110'; and a patterned portion that fills gaps between patterned portions of the in-process source level material layer 1110'.

[0150] The source level material layer 110' may be patterned in the process so that the opening extends over the staircase region 200 where the contact via structure for contacting the word line conductive layer is to be formed laterally. In one embodiment, the staircase region 200 may be laterally spaced apart from the memory array region 100 along a first horizontal direction hd1. A horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as a second horizontal direction hd2.

[0151] refer to Figure 2 , subsequently forming an alternating stack of first material layers and second material layers. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first vertical alternating sequence. The levels of the first vertical alternating sequence are referred to herein as first level levels, and the levels of the alternating stack to be subsequently formed immediately above the first level levels are referred to herein as second level levels, and so on.

[0152] The first vertical alternating sequence may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are clearly contemplated herein.

[0153] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed above the source level material layer during the process. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0154] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0155] The first vertical alternating sequence (132, 142) may include a first insulating layer 132 composed of a first material and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0156] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0157] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0158] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0159] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each first sacrificial material layer 142 in the first vertical alternating sequence (132, 142) may have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0160] A first insulating capping layer 170 may then be formed over the alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the insulating capping layer 170 may be in the range of 20 nm to 300 nm, although lesser and greater thicknesses may also be employed.

[0161] refer to Figure 3 , the first insulating cap layer 170 and the first vertical alternating sequence (132, 142) may be patterned to form a first stepped surface in the staircase region 200. The staircase region 200 may include a corresponding first stepped region and a second stepped region, in which a first stepped surface is formed, and in which an additional stepped surface is subsequently formed in a second layer structure (which is subsequently formed above the first layer structure) and / or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively extending the etching region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped cavity.

[0162] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the region overlying the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first vertical alternating sequence (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0163] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 includes a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may include doped silicate glass, which has a greater etching rate than the material of the first insulating layer 132 (which may include undoped silicate glass). For example, the interlayer dielectric layer 180 may include phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30nm to 300nm, but smaller and larger thicknesses may also be used.

[0164] refer to Figure 4A and Figure 4B , the first layer openings (149, 129) can be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110'. For example, a photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and partially through the in-process source level material layer 110' by a first anisotropic etching process to form the first layer openings (149, 129) simultaneously (i.e., during the first anisotropic etching process).

[0165] The first layer openings (149, 129) may include first layer memory openings 149 and first layer support openings 129. The first layer memory openings 149 are openings formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. In one embodiment, the bottom surface of the first layer openings (149, 129) may be a recessed surface of the source level sacrificial layer 104. Thus, each first layer opening (149, 129) may have a bottom surface between a horizontal plane including the bottom surface of the source level sacrificial layer 104 and a horizontal plane including the top surface of the source level sacrificial layer 104. In another embodiment, the bottom surface of the first layer openings (149, 129) may be formed within the lower source level material layer 112.

[0166] The first layer support openings 129 are openings formed in the staircase region 200 and subsequently used to form support structures that are subsequently used to provide structural support to the first exemplary structure during replacement of the sacrificial material layer with the conductive layer. In the case where the first spacer material is formed as the first conductive layer, the first layer support openings 129 may be omitted. A subset of the first layer support openings 129 may be formed through the horizontal surface of the first stepped surface of the first alternating stack (132, 142).

[0167] In one embodiment, the first layer memory openings 149 can be formed into clusters that are laterally spaced apart from each other along a second horizontal direction hd2. Each cluster of the first layer memory openings 149 can include a respective two-dimensional array of first layer memory openings 149 having a first pitch along one horizontal direction and a second pitch along another horizontal direction. In one embodiment, the direction of the first memory structure pitch can be a first horizontal direction (e.g., a word line direction) hd1, and the direction of the second memory structure pitch can be a second horizontal direction (e.g., a bit line direction) hd2, or vice versa.

[0168] The interlayer dielectric layer 180 may include a dielectric material (such as borosilicate glass) having a greater etching rate than the first insulating layer 132 (which may include undoped silicate glass). In one embodiment, the bottom surface of each first-level memory opening 149 may be formed between the top surface and the bottom surface of the source-level sacrificial layer 104. In this case, the surface of the source-level sacrificial layer 104 may be exposed at the bottom portion of each first-level memory opening 149. Figure 4B The positions of the steps S in the first vertical alternating sequence (132, 142) are shown in dashed lines.

[0169] refer to Figure 5, a sacrificial first layer opening filling portion (148, 128) may be formed in the first layer opening (149, 129). For example, a sacrificial filling material may be simultaneously deposited in each of the first layer openings (149, 129). The sacrificial filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142.

[0170] In one embodiment, the sacrificial fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop layer (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be employed prior to depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0171] In another embodiment, the sacrificial fill material may include a silicon oxide material having a higher etching rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer insulating layer 180. For example, the sacrificial fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etching rate at least 100 times higher than the etching rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and then densifying in an annealing process) in 100:1 dilute hydrofluoric acid. In this case, a thin etch stop layer (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer of fill material. The sacrificial fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0172] In yet another embodiment, the sacrificial fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed with respect to the material of the first alternating stack (132, 142).

[0173] Portions of the deposited sacrificial fill material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0174] The remaining portions of the sacrificial filling material include sacrificial first layer opening filling portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening filling portion 128. The top surface of the sacrificial first layer opening filling portion (148, 128) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening filling portions (148, 128) may or may not include a cavity therein.

[0175] refer to Figure 6 , a second layer structure may be formed above the first layer structure (132, 142, 170, 165, 148, 128). The second layer structure may include an additional vertical alternating sequence of additional insulating layers and additional spacer material layers, which may be sacrificial material layers. The second vertical alternating sequence is also referred to as a second alternating stack. For example, a second alternating stack (232, 242) of material layers may be subsequently formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0176] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0177] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0178] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0179] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) may have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0180] The same set of processing steps as those used to form the first stepped surface in the first stepped region may be used, while appropriately adjusting the pattern of at least one mask layer, to form a second stepped surface in the second stepped region of each stair region 200. A second backward stepped dielectric material portion 265 may be formed over the second stepped surface in the stair region 200.

[0181] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265. The second insulating capping layer 270 includes a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may include silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride.

[0182] Optionally, a drain selection level isolation structure 72 may be formed through the second insulating cap layer 270 and through a subset of the layers in the upper portion of the second vertical alternating sequence (232, 242). The second sacrificial material layer 242 cut by the drain selection level shallow trench isolation structure 72 corresponds to a level at which a drain selection level conductive layer is subsequently formed. The drain selection level isolation structure 72 includes a dielectric material such as silicon oxide. The drain selection level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0183] In general, at least one vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source level material layer 10' during the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the staircase area on at least one alternating stack (132, 142, 232, 242). Each of the insulating layers (132, 232) and the spacer material layers (such as sacrificial material layers (142, 242)) can be formed as a respective single continuous material layer. In this case, the insulating layers (132, 232) can be referred to as continuous insulating layers, and the spacer material layers can be referred to as continuous spacer material layers (e.g., continuous sacrificial material layers).

[0184] refer to Fig. 7A and Figure 7B , second layer openings (249, 229) may be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first layer openings (149, 129), which are the same as the sacrificial first layer opening filling portions (148, 128). Thus, the photoresist layer may be patterned using a photolithographic mask used to pattern the first layer openings (149, 129).

[0185] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form second layer openings (249, 229). The second layer openings (249, 229) can include second layer memory openings 249 and second layer support openings.

[0186] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support opening 229 is formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. Figure 7B The positions of the steps S in the first vertical alternating sequence (132, 142) and the second vertical alternating sequence (232, 242) are shown in dashed lines.

[0187] refer to Fig. 8A and Figure 8B The sacrificial fill material can be removed from below the second layer memory opening 249 and the second layer support opening 229 using an etching process that selectively etches the sacrificial fill material with respect to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49, also referred to as an interlayer memory opening 49, is formed in each volume from which a sacrificial first layer memory opening fill portion 148 is removed. A support opening 19, also referred to as an interlayer support opening 19, is formed in each volume from which a sacrificial first layer support opening fill portion 128 is removed.

[0188] 9A to 9D Sequential cross-sectional views of the memory openings 49 are provided during the formation of the memory opening filling structure 58 or the support pillar structure 20. The same structural changes occur in each memory opening 49.

[0189] refer to Fig. 9A , showing Fig. 8A and Figure 8B The memory opening 49 in the first exemplary device structure. The memory opening 49 extends through the first layer structure and the second layer structure.

[0190] refer to Fig. 9B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide.Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0191] Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. As used herein, a first surface and a second surface "vertically coincide" if there is a second surface above or below the first surface and if there is a vertical plane that intersects both the first surface and the second surface. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2nm to 20nm, but smaller and larger thicknesses can also be used.

[0192] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be employed. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0193] The semiconductor channel material layer 60L includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L includes amorphous silicon or polycrystalline silicon. The semiconductor channel material layer 60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0194] refer to Fig. 9C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or deposited by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0195] refer to Fig.9D , a doped semiconductor material may be deposited in a cavity covering the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has a doping of a second conductivity type. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 covering the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0196] Each remaining portion of the doped semiconductor material having the doping of the second conductivity type constitutes a drain region 63. The drain region 63 may have a doping of the second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 may be in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0197] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0198] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. In the process, the source level material layer 10', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 58 together constitute a memory level component.

[0199] refer to Fig. 10A and Fig. 10B , shows a first exemplary structure after forming a memory opening filling structure 58 in the memory opening 49 and forming a support pillar structure 20 in the support opening 19. While forming the memory opening filling structure 58, each of the support openings 19 is filled with a corresponding support pillar structure 20. Each support pillar structure 20 may have the same structural elements as the memory opening filling structure 58. Each support pillar structure 20 is a dummy structure (i.e., an electrically inert structure) and therefore does not subsequently contact any contact via structure.

[0200] refer to FIG. 11A to FIG. 11C A first contact-level dielectric layer 280 may be formed over the second layer structure (232, 242, 270, 265, 72). The contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be employed.

[0201] A photoresist layer (not shown) may be applied over the contact level dielectric layer 280 and may be photolithographically patterned to form openings in regions extending across the memory array region 100 and the staircase region 200. The openings in the photoresist layer may extend laterally along the first horizontal direction hd1 between each adjacent cluster of memory opening fill structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the contact level dielectric layer 280, the second alternating stack (232, 242, 270, 265, 72), the first alternating stack (132, 142, 170, 165), and the source level material layer 110' during the process. Portions of the contact level dielectric layer 280, the second alternating stacks (232, 242, 270, 265, 72), the first alternating stacks (132, 142, 170, 165), and the source level material layer 110' in the process below the openings in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of memory opening fill structures 58. The clusters of memory opening fill structures 58 may be laterally spaced apart by backside trenches 79 along a second horizontal direction hd2.

[0202] In general, at least one vertical alternating sequence of continuous insulating layers (132, 232) and continuous spacer material layers (such as continuous sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 142), (232, 242)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) by forming backside trenches 79 extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The contact-level dielectric layer 280 is divided into a plurality of contact-level dielectric layers 280 by the backside trenches 280. Each of the plurality of contact-level dielectric layers 280 overlies a corresponding alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) and overlies a corresponding array of memory opening filling structures 58.

[0203] refer to Fig.12 and Fig.13A , a backside trench spacer 77 may be formed on the sidewall of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the contact-level dielectric layer 280, and may be anisotropically etched to form the backside trench spacer 77. The backside trench spacer 77 includes a material different from that of the source-level sacrificial layer 104. For example, the backside trench spacer 77 may include silicon oxide, a dielectric metal oxide, or silicon nitride.

[0204] refer to Fig. 13BIn an isotropic etching process, an etchant that selectively etches the material of the source level sacrificial layer 104 with respect to the material of the first alternating stack (132, 142), the second alternating stack (232, 242), the first and second insulating capping layers (170, 270), the upper dielectric liner layer 105, and the lower dielectric liner layer 103 can be introduced into the backside trench 79. For example, if the source level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon germanium alloy, the backside trench spacers 77 comprise silicon nitride, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process that employs thermal trimethyl-2-hydroxyethylammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH) can be employed to selectively remove the source level sacrificial layer 104 with respect to the backside trench spacers 77 and the upper and lower dielectric liner layers (105, 103). Alternatively, if the source level sacrificial material layer 104 comprises silicon nitride, the backside trench spacers 77 comprise silicon oxide or dielectric metal oxide, and the upper and lower dielectric liner layers (105, 103) comprise silicon oxide, a wet etching process (which employs hot phosphoric acid) may be employed to selectively remove the source level sacrificial layer 104 with respect to the backside trench spacers 77 and the upper and lower dielectric liner layers (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0205] refer to Fig. 13C , a sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 through the backside trenches 79 and the source cavity 109 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the bottom surface and cylindrical side surfaces of the vertical semiconductor channel 60 at the level of the source cavity 109. The upper and lower dielectric liner layers (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower dielectric liner layers (105, 103). The top surface of the lower source level material layer 112 and the bottom surface of the higher source level material layer 116 can be physically exposed to the source cavity 109. After removing the physically exposed portion of the memory film 50, the outer sidewall of each vertical semiconductor channel 60 is physically exposed to the source cavity 109. A dielectric material stack 150 is formed under each physically exposed cylindrical surface of the vertical semiconductor channel 60. Each dielectric material stack 150 is a remaining portion of the memory film 50 and includes the same dielectric material stack as the memory film 50.

[0206] Therefore, the higher source level material layer 116 can act as an etch stop layer during the selective etching of the memory film 50 through the source cavity 109 and can prevent lateral expansion of the source cavity 109. This prevents a short circuit between the source select level conductive layer 118 and a source contact layer that is subsequently formed in the source cavity 109 during a subsequent step.

[0207] refer to Fig.13D , the source contact layer 114 can be formed by a selective deposition process of depositing a doped semiconductor material having a second conductivity type, which is referred to herein as a third doped semiconductor material. The doped semiconductor material may include amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy. The third doped semiconductor material of the source contact layer 114 can be grown from a physically exposed semiconductor surface surrounding the source cavity 109. The average atomic concentration of the second conductivity type dopant in the source contact layer 114 can be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations can also be used.

[0208] In-process source level material layer 110' is replaced with source level material layer 10. Source level material layer 110 includes a layer stack, which includes, from bottom to top, a lower source level material layer 112, a source contact layer 114, a higher source level material layer 116, a source level insulating layer 117, and an optional source selection level conductive layer 118. The combination of lower source level material layer 112, source contact layer 114, and higher source level material layer 116 constitutes a source layer (112, 114, 116). When source level sacrificial layer 104 is replaced with source contact layer 114, in-process source level material layer 110' is converted into a source level material layer 110 including source layer (112, 114, 116).

[0209] refer to Fig.13E and Fig.14 , the backside trench spacers 77 can be removed selectively to the semiconductor material of the source contact layer 114. For example, if the backside trench spacers 77 include silicon nitride, a wet etching process (which uses hot phosphoric acid) can be used to remove the backside trench spacers 77. If the backside trench spacers 77 include silicon oxide, a wet etching process (which uses dilute hydrofluoric acid) can be used to remove the backside trench spacers 77. The sidewalls of the first and second alternating stacks (132, 142, 232, 242), the higher source level material layer 116, the source level insulating layer 117, and the optional source select level conductive layer 118 can be physically exposed after removing the backside trench spacers 77.

[0210] A thermal oxidation process may be performed to convert physically exposed surface portions of various semiconductor materials into semiconductor oxide portions. Specifically, physically exposed surface portions of source contact layer 114, higher source level material layer 116, and source select level conductive layer 118 (if present) are converted into thermal semiconductor oxide material portions. As used herein, "thermal semiconductor oxide" refers to a material formed by thermal oxidation of a semiconductor material. Unlike semiconductor oxide materials formed by chemical vapor deposition, thermal semiconductor oxide materials do not contain carbon or hydrogen above trace levels unless the semiconductor material from which the semiconductor oxide material is derived contains carbon prior to the thermal oxidation process.

[0211] The thermal oxidation process forms a semiconductor oxide plate 122 at the bottom of each backside trench 79 and a semiconductor oxide rail 124 on the sidewalls of the source select level conductive layer 118. Fig.14 The semiconductor oxide rail 124 is not shown in FIG. The semiconductor oxide plate 122 includes various thermal semiconductor oxide material portions formed by thermal conversion of surface portions of the source contact layer 114 and the upper source level material layer 116.

[0212] The layer stack including the lower source level material layer 112, the source contact layer 114 and the upper source level material layer 116 constitutes a source layer (112, 114, 116), which is a buried source layer used as a common source region that connects each of the vertical semiconductor channels 60 and has a second conductivity type of doping. The average dopant concentration of the buried source layer (112, 114, 116) can be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, but smaller and larger dopant concentrations can also be used.

[0213] refer to Fig.15 , an etchant that selectively etches the material of the first and second sacrificial material layers (142, 242) relative to the material of the first and second insulating layers (132, 232), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the first and second sacrificial material layers (142, 242) can include silicon nitride, and the first and second insulating layers (132, 232), the first and second insulating cap layers (170, 270), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can include silicon oxide material. The first backside recess 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess 243 is formed in the volume from which the second sacrificial material layer 242 is removed.

[0214] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced in the vapor phase into the backside trench 79. For example, if the first and second sacrificial material layers (142, 242) include silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0215] Each of the first backside recess and the second backside recess (143, 243) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second backside recesses (143, 243) can be greater than the height of the corresponding backside recess (143, 243). A plurality of first backside recesses 143 can be formed in a volume from which the material of the first sacrificial material layer 142 is removed. A plurality of second backside recesses 243 can be formed in a volume from which the material of the second sacrificial material layer 242 is removed. Each of the first and second backside recesses (143, 243) can extend substantially parallel to the top surface of the substrate 8. The backside recess (143, 243) can be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the insulating layer (132 or 232) covering it. In one embodiment, each of the first and second backside recesses (243, 243) may have a uniform height throughout.

[0216] refer to Fig.16A and Fig. 16B , a backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses and the backside trenches 79 and over the contact-level dielectric layer 280. At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trenches 79, and over the contact-level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element.

[0217] A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 280. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0218] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. In one embodiment, the metal material may include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0219] The deposited metal material of the continuous metal material layer may be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 280. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure.

[0220] A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode can be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55. The source select level conductive layer 118 is used as a source select gate electrode.

[0221] Each memory opening filling structure in the memory opening filling structure 58 (which includes a corresponding memory stack structure 55) includes a vertical stack of memory elements at each level of the conductive layer (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The semiconductor devices in the peripheral device area 700 below may include word line switch devices that are configured to control bias voltages to corresponding word lines. The memory level component includes all structures located above the topmost surface of the lower level metal interconnect structure 780 and is located above the substrate semiconductor layer 9 and vertically spaced apart from the substrate semiconductor layer. The memory level component includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 that vertically extends through at least one alternating stack (132, 146, 232, 246). Each of the at least one alternating stack (132, 146, 232, 246) includes alternating layers of a respective insulating layer (132 or 232) and a respective conductive layer (146 or 246). The at least one alternating stack (132, 146, 232, 246) includes a staircase region including steps in which each underlying conductive layer (146, 246) extends further along a first horizontal direction hd1 than any overlying conductive layer (146, 246) within the memory level assembly.

[0222] Alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are formed, which are laterally spaced apart from each other along the second horizontal direction hd1 by the backside trenches 79. The source layer (112, 114, 116) includes: a lower source level material layer 112, which includes a first doped semiconductor material; a higher source level material layer 116, which includes a second doped semiconductor material; and a source contact layer 114, which includes a third doped semiconductor material and is located between the higher source level material layer 116 and the lower source level material layer 112. In one embodiment, each of the vertical semiconductor channels 60 is in contact with the source contact layer 114. In one embodiment, each of the memory opening filling structures 58 includes a corresponding memory film 50 that laterally surrounds a corresponding vertical semiconductor channel 60, has a corresponding annular concave bottom surface that contacts the source contact layer 114, and has a corresponding cylindrical outer surface that contacts the higher source level material layer 116 and each insulating layer within a corresponding one of the alternating stacks {(132, 146), (232, 246)}.

[0223] refer to 17A to 17C, a patterned etch mask layer (e.g., a hard mask layer) 287 may be formed over the first exemplary structure. For example, a carbon-based etch mask material may be non-conformally deposited over the first exemplary structure, and a photoresist layer may be formed on the carbon-based etch mask material. The carbon-based etch mask material may include amorphous carbon, diamond-like carbon, or any other carbon-based material including an atomic percentage greater than 50%, and / or greater than 70%, and / or greater than 90% carbon. In one embodiment, the carbon-based etch mask material may include a commercially available carbon-based patterned film. The thickness of the carbon-based etch mask material over the top surface of the contact-level dielectric layer 280 may be in the range of 150nm to 1 micron, but smaller and larger thicknesses may also be used. Alternatively, other hard mask materials may be used. A photoresist layer (not shown) may be applied over the carbon-based etch mask material layer, and the photoresist layer may be photolithographically patterned to cover a first subset of the backside trenches 79 without covering a second subset of the backside trenches 79. An etching process may be performed to pattern the carbon-based etch mask material layer into a patterned carbon-based etch mask material layer, which is the patterned etch mask layer 287. The photoresist layer may then be removed, for example, by ashing.

[0224] According to one aspect of the present disclosure, the photolithographic pattern used to pattern the photoresist layer and the etching mask layer may have periodicity along the second horizontal direction hd2. In one embodiment, the backside groove 79 may be formed into a periodic structure having periodicity along the second horizontal direction hd2. The periodicity of the backside groove 79 along the second horizontal direction hd2 is referred to as the backside groove periodicity in this article. The periodicity of the photolithographic pattern along the second horizontal direction hd2 may be a non-unit integer multiple of the backside groove periodicity, that is, an integer multiple of the backside groove periodicity greater than 1. In other words, the ratio of the periodicity of the photolithographic pattern along the second horizontal direction hd2 to the backside groove periodicity may be a positive integer greater than 1, that is, 2, 3, 4, 5, 6, 7, etc.

[0225] In one embodiment, the patterned etch mask layer 287 may have only one slit-shaped opening that covers one of the backside trenches 79 within each distance that surrounds the periodicity of the lithographic pattern along the second horizontal direction hd2. In one embodiment, the ratio of the periodicity of the lithographic pattern along the second horizontal direction hd2 to the periodicity of the backside trenches may be a positive integer N (which is greater than 1), and every Nth backside trench 79 may belong to the second subset of the backside trenches 79, and all other backside trenches 79 may belong to the first subset of the backside trenches 79 (the first subset being a complementary subset of the second subset of the backside trenches 79). In one embodiment, each of the backside trenches 79 may be numbered in positive integer sequence starting from 1, and all backside trenches having a positive residue after a modulo-N division may be in the first subset of the backside trenches 79, and all backside trenches having a zero residue after a modulo-N division may be in the second subset of the backside trenches 79. Modulo-N division refers to a mathematical operation that divides a positive integer by another positive integer N (which is greater than 1) to produce an integer quotient and a non-negative integer remainder, and the output of the operation is equal to the non-negative integer remainder. According to an embodiment of the present disclosure, a patterned etch mask layer 287 may be formed over and may cover the alternating stacks {(132, 146), (232, 246)} and the first subset of backside trenches 79, while not covering the second subset of backside trenches 79. Therefore, every Nth backside trench 79 is not covered by the patterned etch mask layer 287, and all other backside trenches 79 may be covered by the patterned etch mask layer 287. Each backside trench 79 in the first subset of backside trenches 79 is referred to herein as a first backside trench 79, and each backside trench 79 in the second subset of backside trenches 79 is referred to herein as a second backside trench 79.

[0226] An anisotropic etching process may be performed to extend a second subset of the backside trenches 79 vertically through the in-process source level material layer 110' and into the at least one second dielectric layer 768. The bottom surface of the second subset of the backside trenches 79 is formed below a horizontal plane including the bottom surface of the in-process source level material layer 110'. Fig. 17C As shown, the first exemplary structure may include a periodic repetition of a unit structure US that repeats along a second horizontal direction (e.g., a bit line direction) hd2 within the periodicity of the pattern of the patterned etch mask layer 287. Each unit structure US may include a memory block of a memory plane. Each unit structure US includes a backside trench 79 within a second subset of backside trenches 79 and one or more backside trenches 79 within a first subset of backside trenches 79.

[0227] refer to 18A to 18D, a dielectric fill material may be conformally deposited in the second subset of the backside trenches 79 and over the second patterned etch mask layer 287. The dielectric fill material may be deposited by a conformal deposition process such as low pressure chemical vapor deposition (LPCVD). The duration of the deposition process used to deposit the dielectric fill material may be selected such that the dielectric fill material fills the second subset of the backside trenches 79.

[0228] The patterned etch mask layer 287 and the portion of the dielectric filling material deposited on the patterned etch mask layer 287 are then removed from above the first exemplary structure. For example, the removal process may include a reactive ion etch (RIE) and / or CMP process. Each remaining portion of the second subset of the dielectric filling material filling the backside trenches 79 constitutes a dielectric trench filling structure 176.

[0229] The dielectric trench fill structure 176 may include any suitable insulating material. For example, the dielectric trench fill structure 176 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or a dielectric metal oxide such as aluminum oxide, hafnium oxide, tantalum oxide, or the like.

[0230] refer to FIG. 19A to FIG. 19F , a layer of insulating spacer material such as a silicon oxide layer may be formally deposited in a first subset of the backside trenches 79 and over the contact level dielectric layer 280 and the dielectric trench filling structures 176 filling the second subset of the backside trenches. An anisotropic etching process may be performed to remove horizontally extending portions of the insulating spacer material layer from above the contact level dielectric layer 280 and the bottom of the first subset of the backside trenches 79. For example, if the insulating spacer material comprises silicon oxide, the dielectric trench filling structures 176 may comprise silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or a dielectric metal oxide that is resistant to an anisotropic etching process for etching the silicon oxide insulating spacer material layer. In one embodiment, a central portion of the semiconductor oxide plate 122 may be incidentally etched to physically expose a top surface segment of a portion of the underlying source contact layer 114. Each remaining vertically extending tubular portion of the insulating spacer material layer constitutes a backside insulating spacer 74.

[0231] At least one conductive material (such as at least one metallic material) may then be deposited in the cavities in the first subset of backside trenches 79. The at least one conductive material may include at least one metal barrier material (e.g., a metal nitride material such as TiN, TaN, MoN, and / or WN) and at least one metal filling material (e.g., W, Cu, Co, Ru, Mo, etc.). Excess portions of the at least one metallic material may be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 280 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one metallic material constitutes a backside contact via structure 76. Each continuous combination of a backside insulating spacer 74 and a backside contact via structure 76 constitutes a backside trench filling structure (74, 76). Each backside trench 79 within the first subset of backside trenches 79 may be filled with a corresponding backside trench filling structure (74, 76).

[0232] In general, the backside trench filling structures (74, 76) can be formed in a first subset of the backside trenches 79. Each of the backside trench filling structures (74, 76) includes a corresponding backside insulating spacer 74 and a corresponding backside contact via structure 76. In one embodiment, each of the backside contact via structures 76 is formed directly on a corresponding surface of the source contact layer 114. Thus, the backside contact via structure 76 includes a source line or a source electrode. In one embodiment, each recessed surface segment of the source layer (112, 114, 116) contacted by the corresponding backside contact via structure 76 is a surface of the source contact layer 114. In one embodiment, each backside contact via structure 76 is laterally surrounded by a corresponding backside insulating spacer 74 and laterally spaced apart from the corresponding adjacent pair of alternating stacks {(132, 146), (232, 246)} by the corresponding backside insulating spacer. Each backside insulating spacer 74 laterally surrounds a corresponding backside contact via structure 76 therein.

[0233] like Fig.19CAs shown, the first exemplary structure includes multiple instances of the unit structure US extending laterally along a first horizontal direction (eg, word line direction) hd1 and repeated along a second horizontal direction (eg, bit line direction) hd2 perpendicular to the first horizontal direction hd1. Each instance of the unit structure US includes: a source layer (112, 114, 116), the source layer including at least one doped semiconductor material; alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246), the alternating stacks being located above the source layer (112, 114, 116) and laterally spaced apart from each other along a second horizontal direction hd2 by at least one first backside trench 79, the at least one first backside trench including a respective backside contact through-hole structure 76 contacting a respective recessed surface segment of the source layer (112, 114, 116); a memory opening 49 extending vertically through a respective one of the alternating stacks {(132, 146), (232, 246)}; a memory opening filling structure 58, The memory opening filling structure is located in the memory opening 49 and includes a corresponding vertical stack of memory elements (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60; and a dielectric trench filling structure 176, which extends vertically from above the topmost surface of the alternating stack {(132, 146), (232, 246)} to at least the bottom surface of the source layer (112, 114, 116) (and preferably below the bottom surface), and includes a first sidewall contacting the outermost alternating stack in the alternating stack {(132, 146), (232, 246)}, and includes a second sidewall contacting another alternating stack in the alternating stack {(132, 146), (232, 246)} within an adjacent instance of the unit structure US. In one embodiment, the contact area between the source layer (112, 114, 116) and the dielectric trench filling structure 176 extends vertically continuously from the top surface of the source layer (112, 114, 116) to the bottom surface of the source layer (112, 114, 116).

[0234] In one embodiment, each instance of the unit structure US includes a plurality of contact-level dielectric layers 280 overlying a respective one of the alternating stacks {(132, 146), (232, 246)} and a respective subset of the memory opening filling structures 58 and having respective top surfaces located within a horizontal plane including top surfaces of the backside contact via structures 76 and the dielectric trench filling structures 176. In one embodiment, each of the plurality of contact-level dielectric layers 280 contacts sidewalls of a pair of backside insulating spacers 74, or sidewalls of the respective backside insulating spacers 74 and sidewalls of the dielectric trench filling structures 176 of the respective instance of the unit structure US, or sidewalls of the additional dielectric trench filling structures 176 of the adjacent unit structure US. In one embodiment, each of the memory opening filling structures 58 includes a corresponding drain region 63 containing a corresponding doped semiconductor material, and each of the plurality of contact level dielectric layers 280 overlies a horizontal plane including a top surface of the drain region 63 .

[0235] exist Fig.19C In one embodiment shown, the dielectric trench fill structure 176 separates the source layer (112, 114, 116) into first and second source layer portions (110A, 110B) that contact sidewalls of vertical semiconductor channels 60 located in different concentrations of memory opening fill structures 58. In other words, the first source layer portion 110A contacts the sidewalls of the vertical semiconductor channels 60 of the memory opening fill structures 58 located in a first alternating stack in the alternating stacks, while the second source layer portion 110B contacts the sidewalls of the vertical semiconductor channels 60 of the memory opening fill structures 58 located in a second alternating stack in the alternating stacks.

[0236] Generally speaking, each unit structure US may include two alternating stacks {(132, 146), (232, 246)} or three or more alternating stacks {(132, 146), (232, 246)}. Fig.19C In one configuration of the first exemplary structure, the number N is 4, and there are two alternating stacks within the unit structure US, namely, one backside trench filling structure ( 74 , 76 ) and one dielectric trench filling structure 176 .

[0237] refer to Fig. 20A , shows a first alternative configuration of the first exemplary structure, which is a configuration in which the number N is 4, and there are four alternating stacks within the unit structure US, namely three backside trench filling structures ( 74 , 76 ) and one dielectric trench filling structure 176 .

[0238] refer to Fig. 20B, shows a second alternative configuration of the first exemplary structure, which is a configuration in which the number N is 8, and there are eight alternating stacks in the unit structure US, including eight alternating stacks, namely seven backside trench filling structures (74, 76) and one dielectric trench filling structure 176.

[0239] Thus, in the first and second alternative configurations, at least two of the first back side trenches 79 (e.g., three and seven, respectively) containing corresponding back side contact via structures 76 are located between the nearest adjacent pair of second back side trenches 79 containing corresponding dielectric trench filling structures 176.

[0240] refer to Fig.21A and Fig. 21B , a via-level dielectric layer 282 may be formed over the contact-level dielectric layer 280. A photoresist layer (not shown) may be applied over the via-level dielectric layer 282 and may be photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure may be formed through the via-level dielectric layer 282 and the contact-level dielectric layer in the memory array region 100, and an opening for forming a layer contact via structure may be formed through the via-level dielectric layer 282, the contact-level dielectric layer 280, and the backward stepped dielectric material portion (165, 265) in the staircase region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the via-level dielectric layer 282, the contact-level dielectric layer 280, and the underlying dielectric material portion. The drain region 63 and the conductive layer (146, 246) may be used as an etch stop structure. A drain contact via cavity may be formed over each drain region 63, and a layer contact via cavity may be formed over each conductive layer (146, 246) at the stepped surface below the first and second backward stepped dielectric material portions (165, 265). The photoresist layer may then be removed, for example, by ashing.

[0241] At least one conductive material may be deposited in the layer contact via cavity and the drain contact via cavity. The at least one conductive material may include at least one metallic material. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the via level dielectric layer 282 by a planarization process. The planarization process may employ a recess etching process and / or a chemical mechanical planarization process. The remaining portion of the at least one conductive material in the drain contact via cavity constitutes the drain contact via structure 88. The remaining portion of the at least one conductive material in the layer contact via cavity constitutes the layer contact via structure 86.

[0242] refer to Fig. 22, a connecting via structure (referred to herein as a through-memory level connecting via structure 488) may be formed through the backward stepped dielectric material portion (165, 265) on a corresponding one of the lower level metal interconnect structures 780. A higher level metal interconnect structure (96, 98) and a higher level dielectric material layer may be formed above the via level dielectric layer 282. For example, the higher level dielectric material layer may include a bit line level dielectric layer 290 and an additional dielectric material layer (not shown). The higher level metal interconnect structure (96, 98) may include a bit line 98, a bit line level metal line 96, and additional metal lines and via structures (not shown) formed above the bit line 98 and the bit line level metal line 96.

[0243] In one embodiment, each of the alternating stacks {(132, 146), (232, 246)} has a respective stepped surface having a lateral extent along a first horizontal direction hd1 that decreases with vertical distance from the semiconductor substrate 8. The backward stepped dielectric material portion (165, 265) overlies the stepped surface of the alternating stack {(132, 146), (232, 246)}. The through-memory level connection via structure 488 extends vertically through a respective one of the backward stepped dielectric material portions (165, 265). The peripheral circuit is electrically connected to the conductive layer (146, 246) and the memory element vertical stack (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) through the lower level metal interconnect structure 780 and through the higher level metal interconnect structure.

[0244] Common Reference Figures 1A to 22And according to various embodiments of the present disclosure, the memory device includes: a source layer (112, 114, 116), which includes at least one doped semiconductor material; an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) located above the source layer (112, 114, 116), which extend along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by backside trenches 79. The backside trenches 79 include at least one first backside trench including a corresponding backside contact via structure 76 including a conductive material contacting the source layer (112, 114, 116), and at least one second backside trench including a corresponding dielectric trench fill structure 176 extending from above the topmost surface of the alternating stack {(132, 146), (232, 246)} to at least the bottom surface of the source layer (112, 114, 116) (e.g., extending to at least the bottom of layer 112). The memory device also includes memory openings 49. Each of the memory openings 49 extends vertically through a corresponding one of the alternating stacks {(132, 146), (232, 246)}. The memory opening filling structure 58 is located in the memory opening 49 and includes a corresponding vertical stack of memory elements (eg, portions of the memory film 50 ) and a corresponding vertical semiconductor channel 60 .

[0245] In one embodiment, the source layer (112, 114, 116) includes: a lower source level material layer 112, which includes a first doped semiconductor material; a higher source level material layer 116, which includes a second doped semiconductor material; and a source contact layer 114, which includes a third doped semiconductor material and is located between the higher source level material layer 116 and the lower source level material layer 112.

[0246] In one embodiment, each of the respective backside contact via structures 76 contacts a surface of the source contact layer 114. In one embodiment, the source contact layer 114 contacts a sidewall of the vertical semiconductor channel 60. In one embodiment, each respective memory element vertical stack includes a portion of the respective memory film 50 laterally surrounding the respective vertical semiconductor channel 60, having a respective annular concave bottom surface contacting the source contact layer 114, and having a respective cylindrical outer surface contacting the higher source level material layer 116 and each insulating layer within a respective one of the alternating stacks {(132, 146), (232, 246)}.

[0247] In one embodiment, each of the backside contact via structures 76 is laterally surrounded by a corresponding backside insulating spacer 74 and laterally spaced apart from a corresponding adjacent pair of alternating stacks {(132, 146), (232, 246)} by the corresponding backside insulating spacer.

[0248] In one embodiment, the memory device further includes a plurality of contact-level dielectric layers 280 overlying a respective one of the alternating stacks {(132, 146), (232, 246)} and a respective subset of the memory opening filling structures 58 and having respective top surfaces located within a horizontal plane including top surfaces of the backside contact via structures 76 and the dielectric trench filling structures 176. In one embodiment, at least one first backside trench 79 includes a respective backside insulating spacer 74 laterally surrounding the respective backside contact via structure 76. In one embodiment, each of the plurality of contact-level dielectric layers 280 contacts either sidewalls of a pair of backside insulating spacers 74 or sidewalls of the respective backside insulating spacer 74 and sidewalls of the dielectric trench filling structures 176.

[0249] In one embodiment, each of the memory opening filling structures 58 also includes a corresponding drain region 63 containing a corresponding doped semiconductor material, and each of the multiple contact level dielectric layers 280 covers a horizontal plane including a top surface of the drain region 63.

[0250] In one embodiment, the contact area between the source layer (112, 114, 116) and the dielectric trench filling structure 176 extends vertically continuously from the top surface of the source layer (112, 114, 116) to the bottom surface of the source layer (112, 114, 116).

[0251] In one embodiment, the memory device further includes a semiconductor substrate 8 below the source layer (112, 114, 116), and a peripheral circuit 710 located on the semiconductor substrate 8 and electrically connected to the conductive layer (146, 246).

[0252] In one embodiment, each of the alternating stacks {(132, 146), (232, 246)} has a corresponding stepped surface having a lateral extent that decreases with the vertical distance from the semiconductor substrate 8 along the first horizontal direction hd1, a backward stepped dielectric material portion (165, 265) covers the stepped surface of the alternating stack {(132, 146), (232, 246)}, and a through-memory level connection via structure 488 extends vertically through a corresponding one of the backward stepped dielectric material portions (165, 265).

[0253] refer to FIG. 23A to FIG. 23C The second exemplary structure according to the second embodiment of the present disclosure can be obtained by forming a source isolation dielectric structure 12 passing through the source level material layer 110' in the process. Figures 1A to 1C The first exemplary structure shown is obtained. A photoresist layer (not shown) may be applied on Figures 1A to 1C The photoresist layer may be formed over the top surface of the first exemplary structure shown, and may be photolithographically patterned to form a slit-shaped opening extending laterally along a first horizontal direction hd1. The area of ​​the slit-shaped opening may include and may be greater than the area of ​​a subset of the backside trenches to be formed subsequently. In one embodiment, the slit-shaped openings in the photoresist layer may have the same periodicity as the periodicity of each instance of the unit structure to be formed subsequently along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0254] An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer through the in-process source level material layer 110' and into the upper portion of at least one second dielectric layer 768. A shallow trench may be formed through the in-process source level material layer 110' and in the upper portion of at least one semiconductor dielectric layer 768. The in-process source level material layer 110' may be divided into a plurality of discrete portions spaced laterally apart along the second horizontal direction hd2. The top surface of at least one second dielectric layer 768 may be physically exposed at the bottom of each shallow trench. The shallow trench may have tapered sidewalls so that the width of each shallow trench along the second horizontal direction hd2 increases with the vertical distance from the semiconductor substrate 8. The photoresist layer may then be removed, for example, by ashing.

[0255] At least one dielectric filling material may be deposited in the shallow trench, and excess portions of the at least one dielectric filling material may be removed from above a horizontal plane including a top surface of the source level material layer 110' during the process by CMP and / or etch back. The remaining portions of the at least one dielectric filling material include source isolation dielectric structures 12. In one embodiment, each of the source isolation dielectric structures 12 may include a corresponding pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1.

[0256] The source isolation dielectric structure 12 may include a material that resists etching of the insulating layer and the sacrificial material layer to be formed in subsequent steps. For example, the source isolation dielectric structure 12 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or a dielectric metal oxide such as aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0257] Typically, a laterally alternating sequence (110', 12) of strips of source level material layer 110' and source isolation dielectric structures 12 may be formed on the substrate. In one embodiment, each of the source isolation dielectric structures 12 has a variable width along the second horizontal direction hd2 that increases with the vertical distance from the substrate.

[0258] refer to Fig.24 , executable reference Figure 2 The processing steps are described to form a first vertical alternating sequence of first insulating layers 132 and first spacer material layers 142 .

[0259] refer to Fig.25 , executable reference Figure 3 The processing steps are described to pattern the first stepped surface and form the first back stepped dielectric material portion 165 and the interlayer dielectric layer 180 .

[0260] refer to Fig.26A and Fig.26B , executable Figure 4A and Figure 4B The processing steps are as follows to form the first layer memory opening 149 and the first layer support opening 129. In one embodiment, each of the first layer memory opening 149 and the first layer support opening 129 can be formed directly into a corresponding layer stack of the source level material layer 110' in the process (as divided by the source isolation dielectric structure 12), and can be laterally offset from the source isolation dielectric structure 12.

[0261] refer to Fig. 27 , executable reference Figure 5 The processing steps are described to form sacrificial first layer memory opening filling portion 148 and sacrificial first layer support opening filling portion 128 .

[0262] refer to Fig.28 , executable reference Figure 6 The processing steps are described to form a second vertical alternating sequence of second insulating layers 232 and second spacer material layers 242 , a second stepped surface, a second backward stepped dielectric material portion 265 , and a drain select level isolation structure 72 .

[0263] refer to Fig.29 , executable reference Fig. 7A and Figure 7B The processing steps are described to form the second layer memory opening 249 and the second layer support opening 229 .

[0264] refer to Fig.30 , executable reference Fig. 8A and Figure 8B , 9A to 9D 10 to form memory opening filling structures 58 and support pillar structures 20. Each of memory opening filling structures 58 includes a corresponding vertical stack of memory elements (which may include a portion of memory film 50 at the level of conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60.

[0265] refer to FIG. 31A to FIG. 31D , executable reference FIG. 11A to FIG. 11C The processing steps are described to form a contact level dielectric layer 280 over the memory opening fill structure 58, and to form the backside trenches 79. A first subset of the backside trenches 79A may be formed between respective adjacent pairs of the source isolation dielectric structures 12, and a second subset of the backside trenches 79B may be formed on a respective one of the source isolation dielectric structures 12.

[0266] In general, the vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 142), (232, 242)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) by forming backside trenches 79. The backside trenches 79 include a first backside trench 79A vertically extending into a corresponding one of the process source level material layers 110' and a second backside trench 79B vertically extending into a corresponding one of the source isolation dielectric structures 12.

[0267] The second exemplary structure may include a periodic repetition of a unit structure US that is repeated along the second horizontal direction hd2 in a periodicity. Each unit structure US includes a backside groove 79B (i.e., a second backside groove) in the second subset of backside grooves 79 and one or more backside grooves 79A (i.e., one or more first backside grooves) in the first subset of backside grooves 79.

[0268] The surface of the source level material layer 110' during the process may be physically exposed around the bottom portion of each first backside trench 79A. Each bottom portion of the second backside trench 79B may be laterally surrounded by a corresponding one of the source dielectric isolation structures 12. Therefore, the surface of the stack of source level material layers 110' during the process is not physically exposed to the second backside trenches 79B.

[0269] refer to FIG. 32A to FIG. 32D , executable reference FIG. 13A to FIG. 13E The processing steps are described to replace each layer stack of in-process source level material layers 110' with a layer stack of source level material layers 110. After replacing the sacrificial source layer 104 within each of the in-process source level material layers 110' with a corresponding source contact layer 114, the in-process source level material layers 110' are converted into source level material layers 110. Each layer stack of source level material layers 110 may include a corresponding source layer (112, 114, 116) including a lower source level material layer 112, an upper source level material layer 116, and a source contact layer 114. In one embodiment, the lower source level material layer 112 includes a first doped semiconductor material, the upper source level material layer 116 includes a second doped semiconductor material, and the source contact layer 114 includes a third doped semiconductor material and is located between the upper source level material layer 116 and the lower source level material layer 112.

[0270] refer to Fig.33 , execute reference Fig.15 The processing steps are described to form the backside recess (143, 243) by removing the sacrificial material layer (142, 242).

[0271] refer to FIG. 34A to FIG. 34D , executable reference Fig.16A and Fig. 16B The processing steps described are used to form conductive layers (146, 246) in the backside recesses (143, 243). Alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are formed, and these alternating stacks are laterally spaced apart from each other by backside trenches 79.

[0272] refer to FIG. 35A to FIG. 35E , executable reference FIG. 19A to FIG. 19F The processing steps are described to form backside trench filling structures (74, 76) in each backside trench 79. Each of the backside trench filling structures (74, 76) includes a corresponding backside insulating spacer 74 and a corresponding backside contact via structure 76. The backside trench filling structures (74, 76) include first backside trench filling structures (74, 76) formed in the first backside trench 79A and contacting the source contact layer 114 of the corresponding layer stack of the source level material layer 110. In addition, the backside trench filling structures (74, 76) include second backside trench filling structures (74D, 76D) formed in the second backside trench 79 and contacting the corresponding source isolation dielectric structure 12. The second backside trench fill structure ( 74D, 76D) does not contact the source contact layer 114 and thus comprises a dummy backside trench fill structure because no electrical connection exists between the dummy backside contact via structure 76 and the source contact layer 114 .

[0273] Each of the backside contact via structures 76 in the first backside trench filling structures (74, 76) is electrically connected to the corresponding underlying source contact layer 114. Each of the backside contact via structures 76D in the second backside trench filling structures (74, 76) is electrically isolated from the source contact layer 114 by the corresponding source isolation dielectric structure 12. In one embodiment, each recessed surface segment of the source layer (112, 114, 116) contacted by the corresponding backside contact via structure 76 (located in the corresponding first backside trench 79A) is a surface of the source contact layer 114.

[0274] The second exemplary structure includes a plurality of instances of the unit structure US extending laterally along the first horizontal direction hd1 and repeated along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each instance of the unit structure US includes: a source layer (112, 114, 116), the source layer including at least one doped semiconductor material; a source isolation dielectric structure 12, the source isolation dielectric structure contacting a first sidewall of the source layer (112, 114, 116) and extending laterally along a first horizontal direction hd1; alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246), the alternating stacks being located above the source layer (112, 114, 116) and laterally spaced apart from each other along a second horizontal direction hd2 by at least one first backside trench 79A, the at least one first backside trench being filled with a respective first backside trench including a respective backside contact via structure 76 contacting a respective recessed surface segment of the source layer (112, 114, 116); A trench filling structure (74, 76); a memory opening 49 extending vertically through a corresponding one of the alternating stacks {(132, 146), (232, 246)}; a memory opening filling structure 58 located in the memory opening 49 and including a corresponding vertical stack of memory elements (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60; and a second backside trench filling structure (74D, 76D) contacting the top surface of the source isolation dielectric structure 12 and located in a second backside trench 79B located between the outermost alternating stack among the alternating stacks {(132, 146), (232, 246)} and an adjacent instance of the unit structure US.

[0275] exist Fig.35CIn one embodiment shown, a portion 110A of the source layer (112, 114, 116) within each instance of the cell structure US is electrically isolated from another portion 110B of the source layer (112, 114, 116) in an adjacent instance of the cell structure US by a source isolation dielectric structure 12. In one embodiment, the source layer (112, 114, 116) within each instance of the cell structure US includes a second sidewall that contacts another source isolation dielectric structure 12 within another adjacent instance of the cell structure US. In one embodiment, each instance of the cell structure US includes a plurality of contact level dielectric layers 280 that overlie a respective one of the alternating stacks {(132, 146), (232, 246)} and a respective subset of the memory opening fill structures 58 and have respective top surfaces that are located within a horizontal plane that includes each top surface of at least one backside contact via structure 76.

[0276] refer to Fig.36 By forming a plurality of first backside trenches 79A in each instance of the unit structure US (ie, between each pair of adjacent second backside trenches 79B), FIG. 35A to FIG. 35E The second exemplary structure shown results in a first alternative configuration of the second exemplary structure. Generally speaking, at least one first backside trench 79A (and at least one first backside trench filling structure (74, 76) therein) may be formed between adjacent pairs of second backside trenches 79B (and a pair of second backside trench filling structures (74D, 76D) therein) within each instance of the unit structure US. At least one first backside trench 79A may include a plurality of first backside trenches 79A including a plurality of backside contact via structures 76 therein, and the source layer (112, 114, 116) may contact each of the plurality of backside contact via structures 76 within the instance of the unit structure US. Fig.36 In the example shown, each instance of unit structure US includes four alternating stacks of insulating layers (132, 232) and conductive layers (146, 246), which are laterally spaced apart from each other by three first backside trench fill structures (74, 76).

[0277] refer to Fig.37 , showing a second alternative configuration of the second exemplary structure, wherein each instance of the unit structure US includes eight alternating stacks of insulating layers (132, 232) and conductive layers (146, 246), the eight alternating stacks being laterally spaced apart from each other by seven first backside trench filling structures (74, 76).

[0278] refer to Fig.38A and Fig.38B , executable reference Fig.21A and Fig. 21BThe processing steps are described to form the via level dielectric layer 282 , the drain contact via structure 88 , and the layer contact via structure 86 .

[0279] refer to Fig.39 , executable reference Fig. 22 The processing steps are described to form through-memory level connection via structures 488 and higher level metal interconnect structures (96, 98).

[0280] In one embodiment, each of the alternating stacks {(132, 146), (232, 246)} has a respective stepped surface having a lateral extent along a first horizontal direction hd1 that decreases with vertical distance from the semiconductor substrate 8. The backward stepped dielectric material portion (165, 265) overlies the stepped surface of the alternating stack {(132, 146), (232, 246)}. The through-memory level connection via structure 488 extends vertically through a respective one of the backward stepped dielectric material portions (165, 265). The peripheral circuit is electrically connected to the conductive layer (146, 246) and the memory element vertical stack (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) through the lower level metal interconnect structure 780 and through the higher level metal interconnect structure.

[0281] refer to Fig.40A and Fig.40B , a third exemplary structure according to a third embodiment of the present disclosure includes a substrate 908 including a substrate material layer 909. The substrate 8 may include a semiconductor substrate, an insulating substrate, and / or a conductive substrate. Generally speaking, the substrate 908 may be any substrate that can be used as a carrier substrate, such as a silicon wafer. In one embodiment, the substrate material layer 909 may include a single crystal semiconductor material layer (such as a single crystal silicon epitaxial layer or a doped silicon well in a silicon wafer). Optionally, the substrate 908 may include a silicon-on-insulator substrate including an insulating layer (such as a silicon oxide layer) in its upper portion.

[0282] The in-process source level material layer 110' may be formed on the top surface of the substrate 908. The in-process source level material layer 110' may be the same as the in-process source level material layer 110' described above.

[0283] refer to Fig.41 , executable reference Figure 2 The processing steps are described to form a first vertical alternating sequence of first insulating layers 132 and first spacer material layers 142 .

[0284] refer to Fig.42 , executable reference Figure 3The processing steps are described to pattern the first stepped surface and form the first back stepped dielectric material portion 165 and the interlayer dielectric layer 180 .

[0285] refer to Fig.43A and Fig.43B , executable Figure 4A and Figure 4B The processing steps are as follows to form the first layer memory opening 149 and the first layer support opening 129. In one embodiment, each of the first layer memory opening 149 and the first layer support opening 129 may be formed directly into a respective layer stack of the source level material layer 110' in the process.

[0286] refer to Fig.44 , executable reference Figure 5 The processing steps are described to form sacrificial first layer memory opening filling portion 148 and sacrificial first layer support opening filling portion 128 .

[0287] refer to Fig.45 , executable reference Figure 6 The processing steps are described to form a second vertical alternating sequence of second insulating layers 232 and second spacer material layers 242 , a second stepped surface, a second backward stepped dielectric material portion 265 , and a drain select level isolation structure 72 .

[0288] refer to Fig.46A and Fig.46B , executable reference Fig. 7A and Figure 7B The processing steps are described to form the second layer memory opening 249 and the second layer support opening 229 .

[0289] refer to Fig.47 , executable reference Fig. 8A and Figure 8B The processing steps are described to form the inter-layer memory opening 49 and the inter-layer support opening 19 .

[0290] refer to Fig.48A and Fig.48B , executable 9A to 9D 10 to form memory opening filling structures 58 and support pillar structures 20. Each of memory opening filling structures 58 includes a corresponding vertical stack of memory elements (which may include a portion of memory film 50 located at the level of conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60.

[0291] refer to FIG. 49A to FIG. 49C , executable reference FIG. 11A to FIG. 11CThe processing steps are described to form a contact level dielectric layer 280 over the memory opening filling structure 58 and to form backside trenches 79. By forming the backside trenches 79, the vertical alternating sequence of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be divided into alternating stacks {(132, 142), (232, 242)} of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)). During the process, the surface of the source level material layer 110' can be physically exposed around the bottom portion of each backside trench 79.

[0292] refer to Fig.50 , executable reference Fig.12 The processing steps described.

[0293] refer to Fig.51A and Fig.51B , executable reference FIG. 13A to FIG. 13E The processing steps are described to replace each layer stack of the in-process source level material layer 110' with a layer stack of the source level material layer 110. After replacing the sacrificial source layer 104 with the source contact layer 114, the in-process source level material layer 110' is converted into the source level material layer 110. The source level material layer 110 includes source layers (112, 114, 116) including a lower source level material layer 112, an upper source level material layer 116, and a source contact layer 114. In one embodiment, the lower source level material layer 112 includes a first doped semiconductor material, the upper source level material layer 116 includes a second doped semiconductor material, and the source contact layer 114 includes a third doped semiconductor material and is located between the upper source level material layer 116 and the lower source level material layer 112.

[0294] In the third exemplary structure, various component layers within the source level material layer 110 may be formed as a continuous layer. Therefore, the source level material layer 110 is also referred to as a continuous source level material layer 110. The third exemplary structure may be provided in a memory die that is subsequently bonded to a logic die.

[0295] refer to Fig.52 , execute reference Fig.15 The processing steps are described to form the backside recess (143, 243) by removing the sacrificial material layer (142, 242).

[0296] refer to Fig.53A and Fig.53B , executable reference Fig.16A and Fig. 16BThe described processing steps are used to form a conductive layer (146, 246) in the backside recess (143, 243). Alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are formed, and these alternating stacks are laterally spaced apart from each other by backside trenches 79. The alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) are laterally spaced apart from each other along the second horizontal direction hd1 by backside trenches 79, which extend laterally along the first horizontal direction hd1.

[0297] refer to FIG. 54A to FIG. 54D , executable reference FIG. 19A to FIG. 19F The processing steps are described to form backside trench fill structures (74, 76) in each backside trench 79. Each of the backside trench fill structures (74, 76) includes a corresponding backside insulating spacer 74 and a corresponding backside contact via structure 76. The backside trench fill structures (74, 76) contact the source contact layer 114. Each of the backside contact via structures 76 in the backside trench fill structures (74, 76) is electrically connected to the source contact layer 114. In one embodiment, each corresponding backside contact via structure 76 contacts a surface of the source contact layer 114. Each backside contact via structure 76 is laterally surrounded by a corresponding backside insulating spacer 74 and is laterally spaced apart from a corresponding adjacent pair of alternating stacks {(132, 146), (232, 246)} by the corresponding backside insulating spacer.

[0298] refer to Fig.55A and Fig.55B , executable reference Fig.21A and Fig. 21B The processing steps are described to form the via level dielectric layer 282 , the drain contact via structure 88 , and the layer contact via structure 86 .

[0299] refer to Fig.56 , executable reference Fig. 22 Processing steps are described to form metal interconnect structures (96, 98).

[0300] refer to Fig.57, an additional dielectric material layer 960 and an additional metal interconnect structure (986, 988) may be subsequently formed. The additional dielectric material layer 960 may include an interconnect level dielectric material layer 964, a passivation dielectric layer 966, and a pad level dielectric material layer 968. The additional dielectric material layer 960 is also referred to as a memory side dielectric material layer 960. The additional metal interconnect structure (986, 988) may include a memory side metal line 988 and a memory side metal via structure 986. A memory side bonding pad 998 may be formed in the pad level dielectric material layer 968. In one embodiment, the memory side bonding pad 998 may include a metal bonding pad configured for metal to metal bonding (such as copper to copper bonding). This completes the memory die 900.

[0301] refer to Fig.58 , a logic die 700 is provided, the logic die including a logic side substrate 708, the logic side substrate including a logic side substrate semiconductor layer 709 and a peripheral circuit 710 formed on the top surface of the logic side substrate semiconductor layer 709. The peripheral circuit 710 may be configured to control the operation of the conductive layer (146, 246) and the bit line 98, and may have the same set of components as the peripheral circuit 710 described above and may provide the same functionality. In the third exemplary structure, the dielectric material layer corresponding to the lower level dielectric material layer 760 in the first and second exemplary structures is referred to as the logic side dielectric material layer 760, and the metal interconnect structure corresponding to the lower level metal interconnect structure 780 in the first and second exemplary structures is referred to as the logic side metal interconnect structure 780. The logic side dielectric material layer 760 may include a pad-level dielectric material layer 769 embedded with a logic side bonding pad 798. In one embodiment, the logic side bonding pad 798 may include a metal bonding pad configured for metal-to-metal bonding (such as copper-to-copper bonding). The pattern of logic side bond pads 798 as seen in a top view may be a mirror image pattern of the pattern of memory side bond pads 998 as seen in a top view.

[0302] Logic die 700 may be bonded to memory die 900 by aligning logic side bond pads 798 with memory side bond pads 998 and by causing metal-to-metal bonds between mating pairs of logic side bond pads 798 and memory side bond pads 998 .

[0303] refer to Fig.59, at least a backside portion of the substrate 909 of the memory die 900 may be removed. In one embodiment, the substrate material layer 909 of the substrate 909 of the memory die 900 may be thinned from the backside, for example, by grinding, polishing, cleaving, at least one anisotropic etching process, and / or at least one isotropic etching process. In one embodiment, the substrate material layer 909 may include a single crystalline semiconductor layer such as a single crystalline silicon layer, and a single crystalline semiconductor layer 9' including a remaining portion of the substrate material layer 909 may be present on the backside of the source level material layer 110. In this case, the single crystalline semiconductor layer 9' may be in direct contact with the lower source level semiconductor layer 112. In one embodiment, the lower source level semiconductor layer 112 may be formed as a single crystalline doped semiconductor (e.g., silicon) material layer having epitaxial alignment with the single crystalline semiconductor layer 9'. In one embodiment, the thickness of the single crystalline semiconductor layer 9' may be in the range of 100 nm to 5 microns, but smaller and larger thicknesses may also be employed. In one embodiment, the single crystalline semiconductor layer 9' may have a doping of a second conductivity type.

[0304] Alternatively, the substrate material layer 909 may be completely removed by grinding, polishing, cleaving, at least one anisotropic etching process, and / or at least one isotropic etching process. In this case, the backside surface (ie, bottom surface) of the lower source level semiconductor layer 112 may be physically exposed.

[0305] refer to Fig.60 , a photoresist layer 217 may be formed over the back side of the source level material layer 110. In one embodiment, the photoresist layer 217 may be formed over the back side of the single crystalline semiconductor layer 9'. The photoresist layer 217 may be photolithographically patterned along the second horizontal direction hd2 with a periodicity that is equal to an integer multiple of the periodicity of the backside trench filling structure (74, 76) along the second horizontal direction hd2. The ratio of the periodicity of the pattern in the photoresist layer 217 along the second horizontal direction hd2 to the periodicity of the backside trench filling structure (74, 76) along the second horizontal direction hd2 may be an integer greater than 1, i.e., 2, 3, 4, etc. Therefore, the pattern of the photoresist layer 217 is a repetition of a unit photoresist pattern repeated along the second horizontal direction hd2.

[0306] Each unit pattern in the patterned photoresist layer 217 includes a single slit-shaped opening covering a corresponding one of the backside trench filling structures (74, 76). The patterned photoresist layer 217 may cover all areas except the area of ​​the slit-shaped opening. Each slit-shaped opening in the patterned photoresist layer 217 may extend laterally along a first horizontal direction hd1 and have a uniform width along a second horizontal direction hd2. Each slit-shaped opening in the photoresist layer 217 covers a corresponding underlying backside trench filling structure (74, 76) and may be wider than the backside trench filling structure.

[0307] An anisotropic etching process may be performed to transfer the pattern of the openings in the patterned photoresist layer 217 through the optional single crystalline semiconductor layer 9' and through the continuous source level material layer 110. A source isolation trench 211 may be formed in each volume, from which the material of the optional single crystalline semiconductor layer 9' is etched and through the continuous source level material layer 110. In one embodiment, the horizontal surface of the nearest insulating layer 32 of the alternating stack {(132, 146), (23, 2 246)} may be physically exposed at the bottom of each source isolation trench 211. In one embodiment, the entire end surface of the backside trench fill structure (74, 76) may be physically exposed and / or vertically recessed below each source isolation trench 211. If present, the single crystalline semiconductor layer 9' may be divided into a plurality of single crystalline semiconductor strips 9S.

[0308] In general, the continuous source-level material layer 110 is divided into a plurality of source-level material layer portions (110A, 110B, 110C) by forming source isolation trenches 211 passing through the continuous source-level material layer 110. The backside trenches 79 include first backside trenches 79 covered by the corresponding layer stack of the source-level material layer 110 (which are filled with the first backside trench filling structure (74, 76)) and second backside trenches 79 located below a corresponding one of the source isolation trenches 211 (which are filled with the second (e.g., dummy) backside trench filling structure (74D, 76D)). In other words, the first backside trenches 79 are covered by the corresponding source-level material layer 110, and each of the second backside trenches 79 is exposed below a corresponding one of the source isolation trenches 211 after the source isolation trenches 211 are formed.

[0309] In one embodiment, the source isolation trench 211 may be formed with tapered sidewalls. In this case, each of the source isolation trenches 211 may have a variable width along the second horizontal direction hd2 that increases with the vertical distance from the alternating stack {(132, 146), (232, 246)}. The patterned photoresist layer 217 may then be removed, for example, by ashing.

[0310] refer to Fig.61A , at least one dielectric filling material may be deposited in the source isolation trench 211. A planarization process may be performed to remove a portion of the at least one dielectric filling material from above a horizontal plane including the top surface (backside surface) of the source level dielectric material layer 110. The planarization process may include, for example, a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one dielectric filling material filling the corresponding source isolation trench 211 constitutes a source isolation dielectric structure 212. In one embodiment, the source isolation dielectric structure 212 may have a variable width along the second horizontal direction hd2 that increases with the vertical distance from the alternating stack {(132, 146), (232, 246)}. The source isolation dielectric structure 212 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or a dielectric metal oxide such as aluminum oxide, hafnium oxide, tantalum oxide, etc.

[0311] The third exemplary structure includes a plurality of instances of the unit structure US extending laterally along the first horizontal direction hd1 and repeated along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Each instance of the unit structure US includes: a source layer (112, 114, 116), the source layer including at least one doped semiconductor material; a source isolation dielectric structure 212, the source isolation dielectric structure contacting a first sidewall of the source layer (112, 114, 116) and extending laterally along a first horizontal direction hd1; alternating stacks {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246), the alternating stacks being located above the source layer (112, 114, 116) and laterally spaced apart from each other along a second horizontal direction hd2 by at least one first backside trench 79, the at least one first backside trench being filled with a corresponding first backside trench including a corresponding backside contact via structure 76 contacting a corresponding recessed surface segment of the source layer (112, 114, 116); A trench filling structure (74, 76); a memory opening 49 extending vertically through a corresponding one of the alternating stacks {(132, 146), (232, 246)}; a memory opening filling structure 58 located in the memory opening 49 and including a corresponding vertical stack of memory elements (which may include a portion of the memory film 50 located at the level of the conductive layer (146, 246)) and a corresponding vertical semiconductor channel 60; and a second backside trench filling structure (74D, 76D) contacting the top surface of the source isolation dielectric structure 212 and located in a second backside trench 79 located between the outermost alternating stack among the alternating stacks {(132, 146), (232, 246)} and an adjacent instance of the unit structure US.

[0312] In each instance of unit structure US, source layer portion 110A is electrically isolated from another source layer portion 110B in an adjacent instance of unit structure US by source isolation dielectric structure 212. Source layer (112, 114, 116) includes a second sidewall contacting another source isolation dielectric structure 212 in an adjacent instance of unit structure US.

[0313] In one embodiment, the backside trench 79 includes multiple repetitions of a unit pattern including at least one first backside trench 79 and a second backside trench 79 repeated along a second horizontal direction hd2. In one embodiment, each instance of the unit structure US includes a plurality of contact-level dielectric layers 280 overlying a respective one of the alternating stacks {(132, 146), (232, 246)} and a respective subset of the memory opening fill structures 58 and having respective top surfaces located within a horizontal plane including each top surface of at least one backside contact via structure 76.

[0314] The third exemplary structure includes a memory device. In one embodiment, multiple instances of a unit structure US are located in a memory die 900, and the memory device also includes a logic die 700 bonded to the memory die 900. The logic die 700 includes a peripheral circuit 710, which is electrically connected to the conductive layer (146, 246) and the bit line 98 in each instance of the unit structure US through a logic side metal interconnect structure located in the logic die 700 and a logic side bonding pad 798 located in the logic die 700. The memory device includes a memory side bonding pad 998 located in the memory die 900, and a memory side metal interconnect structure 980 covering multiple instances of the unit structure US and located in the memory die 900.

[0315] refer to Fig.61B , a first alternative embodiment of the third exemplary structure can be derived from the third exemplary structure described above by changing the pattern of the source isolation dielectric structure 212. Generally speaking, each instance of the unit structure US includes at least one first backside trench 79 and a second backside trench 79. In one embodiment, the at least one first backside trench 79 includes a plurality of first backside trenches 79 containing a plurality of backside contact via structures 76; and the source layer (112, 114, 116) in each instance of the unit structure US contacts each of the plurality of backside contact via structures 76. Fig.61B In the example shown, each instance of the unit structure US includes three alternating stacks of insulating layers (132, 232) and conductive layers (146, 246), namely, two first back side trench filling structures (74, 76) including two back side contact via structures 76 directly contacting the source contact layer 114 within the source layer (112, 114, 116), and one dummy back side trench filling structure (74D, 76D) including a dummy back side contact via structure 76D electrically isolated from the source layer (112, 114, 116).

[0316] refer to Fig.61C, showing a second alternative embodiment of the third exemplary structure. Each instance of the unit structure US includes six alternating stacks of insulating layers (132, 232) and conductive layers (146, 246), namely, five first backside trench filling structures (74, 76) including five backside contact via structures 76 directly contacting the source contact layer 114 in the source layer (112, 114, 116), and one dummy backside trench filling structure (74D, 76D) including a dummy backside contact via structure 76D electrically isolated from the source layer (112, 114, 116).

[0317] Generally speaking, the number of first backside trench filling structures ( 74 , 76 ) within each unit structure may be 1 or any integer greater than 1.

[0318] refer to Fig.62 , by attaching the carrier substrate 600 to the memory die 900 and by performing reference Fig.59 The described processing steps remove at least a backside portion of the substrate 909 of the memory die 900, which may be removed from the memory die 900. Fig.57 The third exemplary structure shown in yields a third alternative embodiment of the third exemplary structure.

[0319] refer to Fig.63 , executable reference Fig.60 The processing steps are described to form the source isolation trench 211 .

[0320] refer to Fig.64 , executable reference Figures 61A to 61C The processing steps are described to form a source isolation dielectric structure 212 in the source isolation trench 211 .

[0321] refer to Fig.65 , the carrier substrate 600 can be separated from the memory die 900, and the logic die 700 described above can be bonded to the memory die 900, for example by causing metal-to-metal bonding between mating pairs of logic side bonding pads 798 and memory side bonding pads 998.

[0322] Generally, the source isolation trench 211 and the source isolation dielectric structure 212 may be formed on the backside of the memory die 900 before or after the memory die 900 is attached to the logic die 700 .

[0323] refer to Figures 23A to 65and related figures and according to various embodiments of the present disclosure, a memory device includes: a source layer (112, 114, 116), the source layer including at least one doped semiconductor material; a source isolation dielectric structure (12, 212), the source isolation dielectric structure extending laterally along a first horizontal direction hd1 and laterally separating the source layer into a first source layer portion 110A and a second source layer portion 110B electrically isolated from the first source layer portion 110A; an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) located above the source layer (112, 114, 116), the alternating stacks extending along the first horizontal direction hd1 and extending along a second horizontal direction hd2 through at least one first backside trench 79A and at least one second backside trench The trenches 79B are laterally spaced apart from each other, the at least one first backside trench being filled with a corresponding first backside trench filling structure (74, 76) including a corresponding first backside contact via structure 76 that contacts the source layer (112, 114, 116), and the at least one second backside trench being filled with a corresponding second backside trench filling structure (74D, 76D) including a corresponding second dummy backside contact via structure 76D that contacts the source isolation dielectric structure (12, 112); a memory opening 49, wherein each of these memory openings extends vertically through a corresponding one of the alternating stacks; and a memory opening filling structure 58, which is located in the memory opening and includes a corresponding vertical stack of memory elements (e.g., a portion of the memory film 50) and a corresponding vertical semiconductor channel 60.

[0324] In one embodiment, the at least one first backside trench 79A includes a plurality of first backside trenches 79A including a plurality of first backside contact via structures 76 therein, and the first source layer portion 110A contacts each of the plurality of first backside contact via structures 79A.

[0325] In one embodiment, the source isolation dielectric structure 12 has a variable width along the second horizontal direction that increases with vertical distance from the alternating stack. In another embodiment, the source isolation dielectric structure 212 has a variable width along the second horizontal direction that decreases with vertical distance from the alternating stack.

[0326] In one embodiment, the source layer includes: a lower source level material layer 112, the lower source level material layer includes a first doped semiconductor material; a higher source level material layer 116, the higher source level material layer includes a second doped semiconductor material; and a source contact layer 114, the source contact layer includes a third doped semiconductor material and is located between the higher source level material layer and the lower source level material layer. Each of the respective first backside contact via structures 76 contacts a surface of the source contact layer 114 located in the first source layer portion 110A or in the second source layer portion 110B. In one embodiment, the source contact layer 114 contacts the sidewalls of the vertical semiconductor channel 60. In one embodiment, the respective memory element vertical stack includes a portion of the respective memory film 50 laterally surrounding the respective vertical semiconductor channel 60, having a respective annular concave bottom surface contacting the source contact layer, and having a respective cylindrical outer surface contacting the higher source level material layer and each insulating layer within a respective one of the alternating stacks.

[0327] In one embodiment, the first backside trench filling structure further includes a first backside insulating spacer 74 laterally surrounding the first backside contact via structure 76.

[0328] The second back trench fill structure further includes a second back insulating spacer 74D laterally surrounding a second dummy back contact via structure 76D, and the second dummy back contact via structure 76D is electrically isolated from the source layer by the source isolation dielectric structure (12, 212). In one embodiment, the contact region between the source layer (112, 114, 116) and the source isolation dielectric structure (12, 212) vertically extends continuously from the top surface of the source layer to the bottom surface of the source layer.

[0329] In one embodiment, a memory device includes: a semiconductor substrate 8 below a source layer (112, 114, 116), and a peripheral circuit located on the semiconductor substrate 8 and electrically connected to the conductive layer (146, 246).

[0330] In one embodiment, the source layer and the alternating stack are located in a memory die 900. The memory device also includes a logic die 700 bonded to the memory die 900, wherein the logic die 700 includes peripheral circuits electrically connected to the conductive layer (146, 246) via a logic-side metal interconnect structure located in the logic die 700, a logic-side bonding pad located in the logic die 700, a memory-side bonding pad located in the memory die 900, and a memory-side metal interconnect structure overlying multiple instances of the cell structure US and located in the memory die 900.

[0331] Various embodiments of the present disclosure provide configurations in which the source layer (112, 114, 116) is separated into electrically isolated portions (110A, 100B, etc.) in different memory blocks. Portions (110A, 110B) in adjacent blocks are electrically isolated from each other by dielectric trench fill structures 176 or by source isolation dielectric structures (12, 212). This reduces the probability of read interference between adjacent memory blocks because the word lines in unselected blocks are electrically floating. In addition, since the resistive load is reduced due to the electrical isolation of adjacent memory blocks from each other, a lower operating current can be used. Finally, a crack in one block does not invalidate an entire memory plane containing multiple blocks because the blocks in the same plane are electrically isolated from each other.

[0332] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprise" or "include" contemplate all embodiments in which the words "consist essentially of..." or the words "consist of..." replace the words "comprise" or "include". A third embodiment using a specific structure and / or configuration is shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such replacement is not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, comprising: a source layer, the source layer comprising at least one doped semiconductor material; an alternating stack of insulating and conductive layers overlying the source layer, the alternating stack extending along a first horizontal direction and laterally spaced apart from one another along a second horizontal direction by backside trenches, wherein the backside trenches include at least one first backside trench and at least one second backside trench, the at least one first backside trench including a corresponding backside contact via structure including a conductive material contacting the source layer, the at least one second backside trench including a corresponding dielectric trench fill structure extending from above a topmost surface of the alternating stack to at least a bottom surface of the source layer; a memory opening, wherein each of the memory openings extends vertically through a corresponding one of the alternating stacks; and A memory opening filling structure is located in the memory opening and includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel.

2. The memory device according to claim 1, wherein the source layer comprises: a lower source level material layer, the lower source level material layer comprising a first doped semiconductor material; an upper source level material layer, the upper source level material layer comprising a second doped semiconductor material; and A source contact layer includes a third doped semiconductor material and is located between the higher source level material layer and the lower source level material layer. 3 . The memory device of claim 2 , wherein each of the respective backside contact via structures contacts a surface of the source contact layer. The memory device of claim 2 , wherein the source contact layer contacts a sidewall of the vertical semiconductor channel.

5. A memory device according to claim 4, wherein the corresponding vertical stack of memory elements includes a portion of the corresponding memory film that laterally surrounds the corresponding vertical semiconductor channel, has a corresponding annular concave bottom surface that contacts the source contact layer, and has a corresponding cylindrical outer surface that contacts the higher source level material layer and each insulating layer within a corresponding one of the alternating stacks.

6. The memory device of claim 1, wherein each of the backside contact via structures is laterally surrounded by a corresponding backside insulating spacer and is laterally spaced apart from a corresponding adjacent pair of alternating stacks by the corresponding backside insulating spacers.

7. The memory device of claim 1 , further comprising a plurality of contact-level dielectric layers, each contact-level dielectric layer covering a corresponding one of the alternating stacks and a corresponding subset of the memory opening filling structures, and having a corresponding top surface located within a horizontal plane including top surfaces of the backside contact through-hole structure and the dielectric trench filling structure.

8. The memory device according to claim 7, wherein: The at least one first backside trench comprises a respective backside insulating spacer laterally surrounding the respective backside contact via structure; and Each of the plurality of contact-level dielectric layers contacts: a pair of sidewalls of a back insulating spacer; or The sidewalls of the corresponding backside insulating spacers and the sidewalls of the dielectric trench filling structure.

9. The memory device according to claim 7, wherein: Each of the memory opening filling structures further includes a corresponding drain region, the corresponding drain region including a corresponding doped semiconductor material; and Each of the plurality of contact-level dielectric layers covers a horizontal plane including a top surface of the drain region.

10. The memory device of claim 1, wherein the dielectric trench fill structure comprises silicon oxycarbide or silicon carbonitride. 11 . The memory device of claim 1 , wherein a contact region between the source layer and the dielectric trench filling structure vertically extends continuously from a top surface of the source layer to a bottom surface of the source layer.

12. The memory device of claim 1, wherein: the dielectric trench-fill structure extending vertically from above the topmost surface of the alternating stack to below the bottom surface of the source layer; The dielectric trench filling structure divides the source layer into a first source layer portion and a second source layer portion; The first source layer partially contacts a sidewall of the vertical semiconductor channel of a memory opening filling structure in a first alternating stack of the alternating stacks; The second source layer partially contacts a sidewall of the vertical semiconductor channel of a memory opening filling structure in a second alternating stack in the alternating stacks; and The at least one second backside trench is completely filled with the corresponding dielectric trench filling structure.

13. The memory device according to claim 1, further comprising: A semiconductor substrate, wherein the semiconductor substrate is located below the source layer; and A peripheral circuit is located on the semiconductor substrate and is electrically connected to the conductive layer.

14. The memory device of claim 1, wherein at least two of the first backside trenches containing the respective backside contact via structures are located between a nearest adjacent pair of second backside trenches of the second backside trenches containing the respective dielectric trench fill structures.

15. A method of forming a memory device, the method comprising: forming a vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers over the substrate; forming a reservoir opening through the vertical alternating sequence; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures comprises a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; dividing the vertical alternating sequence into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction; replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the backside trenches; extending the second subset of the backside grooves vertically without extending the first subset of the backside grooves vertically; forming a dielectric trench fill structure in said second subset of said backside trenches; as well as Backside trench fill structures are formed in a first subset of the backside trenches, wherein each of the backside trench fill structures includes a corresponding backside insulating spacer and a corresponding backside contact via structure.

16. The method according to claim 15, further comprising: forming a source level material layer including a source level sacrificial layer over the substrate in a process wherein the vertical alternating sequence is formed over the source level material layer in the process; as well as The source level sacrificial layer is replaced with a source contact layer after forming the backside trench and before replacing the sacrificial material layer with the conductive layer, thereby converting the in-process source level material layer into a source level material layer including a source layer.

17. The method according to claim 16, further comprising: forming a patterned etch mask layer over the alternating stacks and the first subset of the backside trenches without covering the second subset of the backside trenches; as well as An anisotropic etching process is performed, wherein the anisotropic etching process vertically extends the second subset of the backside trenches such that a bottom surface of the second subset of the backside trenches is formed below a horizontal plane including a bottom surface of a source level material layer in the process.

18. The method of claim 17, wherein the dielectric trench filling structure is formed by depositing a dielectric filling material in the second subset of the backside trenches and above the patterned etch mask layer and by removing a portion of the dielectric filling material from above the patterned etch mask layer, wherein the remaining portion of the dielectric filling material filling the second subset of the backside trenches constitutes the dielectric trench filling structure. 19 . The method of claim 16 , wherein each of the backside contact via structures is formed directly on a corresponding surface of the source contact layer.

20. The method according to claim 15, further comprising: forming peripheral circuits including field effect transistors on a top surface of the substrate; forming a lower level metal interconnect structure over the peripheral circuitry, wherein the vertical alternating sequence is formed over the lower level metal interconnect structure; and A higher level metal interconnect structure is formed over the alternating stack, wherein the peripheral circuitry is electrically connected to the conductive layer and the vertical stack of memory elements via a lower level metal interconnect structure and via the higher level metal interconnect structure.

21. A memory device, comprising: a source layer, the source layer comprising at least one doped semiconductor material; a source isolation dielectric structure extending laterally along a first horizontal direction and laterally separating the source layer into a first source layer portion and a second source layer portion electrically isolated from the first source layer portion; an alternating stack of insulating layers and conductive layers over the source layer, the alternating stack extending along the first horizontal direction and laterally spaced apart from each other along a second horizontal direction by at least one first backside trench and at least one second backside trench, the at least one first backside trench being filled with a respective first backside trench filling structure including a respective first backside contact via structure contacting the source layer, and the at least one second backside trench being filled with a respective second backside trench filling structure including a respective second dummy backside contact via structure contacting the source isolation dielectric structure; a memory opening, wherein each of the memory openings extends vertically through a corresponding one of the alternating stacks; and A memory opening filling structure is located in the memory opening and includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel, wherein a sidewall of the corresponding vertical semiconductor channel contacts the source layer.

22. The memory device of claim 21, wherein: The at least one first backside trench comprises a plurality of first backside trenches containing a plurality of first backside contact via structures therein; and The first source layer portion contacts each of the plurality of first back-contact via structures.

23. The memory device of claim 21, wherein the source isolation dielectric structure has a variable width along the second horizontal direction that increases with a vertical distance from the alternating stacks.

24. The memory device of claim 21, wherein the source isolation dielectric structure has a variable width along the second horizontal direction that decreases with vertical distance from the alternating stacks.

25. The memory device of claim 21, wherein the source layer comprises: a lower source level material layer, the lower source level material layer comprising a first doped semiconductor material; an upper source level material layer, the upper source level material layer comprising a second doped semiconductor material; and A source contact layer includes a third doped semiconductor material and is located between the higher source level material layer and the lower source level material layer. 26 . The memory device of claim 25 , wherein each of the corresponding first backside contact via structures contacts a surface of the source contact layer located in the first source layer portion or in the second source layer portion.

27. The memory device of claim 25, wherein: The source contact layer contacts a sidewall of the vertical semiconductor channel; and The respective memory element vertical stack includes a portion of a respective memory film laterally surrounding the respective vertical semiconductor channel, having a respective annular concave bottom surface contacting the source contact layer, and having a respective cylindrical outer surface contacting the higher source level material layer and each insulating layer within a respective one of the alternating stacks.

28. The memory device of claim 21, wherein the source isolation dielectric structure comprises silicon oxycarbide or silicon carbon nitride.

29. The memory device of claim 21, wherein: The first backside trench filling structure further includes a first backside insulating spacer laterally surrounding the first backside contact via structure; The second backside trench filling structure further includes a second backside insulating spacer laterally surrounding the second dummy backside contact via structure; and The second dummy back contact via structure is electrically isolated from the source layer by the source isolation dielectric structure.

30. The memory device of claim 21, wherein a contact region between the source layer and the source isolation dielectric structure vertically extends continuously from a top surface of the source layer to a bottom surface of the source layer.

31. The memory device of claim 21 , further comprising a plurality of contact level dielectric layers, each contact level dielectric layer covering a corresponding one of the alternating stacks and a corresponding subset of the memory opening filling structures, and having a corresponding top surface located within a horizontal plane including each top surface of at least one backside contact through-hole structure.

32. The memory device of claim 21, further comprising: A semiconductor substrate, wherein the semiconductor substrate is located below the source layer; A peripheral circuit is located on the semiconductor substrate and is electrically connected to the conductive layer.

33. The memory device of claim 21, wherein the source layer and the alternating stacks are located in a memory die.

34. A memory device according to claim 33, wherein the memory device also includes a logic die bonded to the memory die, wherein the logic die includes a peripheral circuit, and the peripheral circuit is electrically connected to the conductive layer in the memory die through a logic side metal interconnect structure located in the logic die, a logic side bonding pad located in the logic die, a memory side bonding pad located in the memory die, and a memory side metal interconnect structure located in the memory die.

35. A method of forming a memory device, the method comprising: a laterally alternating sequence of source level material layers and source isolation dielectric structures during formation over the substrate; forming a vertical alternating sequence of continuous insulating layers and continuous sacrificial material layers above the lateral alternating sequence; forming a reservoir opening through the vertical alternating sequence; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures comprises a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming backside trenches through the vertical alternating sequence to divide the vertical alternating sequence into alternating stacks of insulating layers and sacrificial material layers; replacing a sacrificial source layer within each of the in-process source level material layers with a corresponding source contact layer to convert the in-process source level material layers into source level material layers; replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the backside trenches; as well as A backside trench filling structure is formed in the backside trench.

36. A method according to claim 35, wherein the backside trench includes a first backside trench and a second backside trench, the first backside trench vertically extending into a corresponding one of the source level material layers in the process, and the second backside trench vertically extending into a corresponding one of the source isolation dielectric structures. 37 . The method of claim 35 , wherein each of the backside trench filling structures comprises a corresponding backside insulating spacer and a corresponding backside contact via structure.

38. A method of forming a memory device, the method comprising: forming a source level material layer in process over the substrate; forming a vertical alternating sequence of continuous insulating layers and continuous sacrificial material layers over the source level material layer in the process; forming a reservoir opening through the vertical alternating sequence; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures comprises a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel; forming backside trenches through the vertical alternating sequence to divide the vertical alternating sequence into alternating stacks of insulating layers and sacrificial material layers; replacing a sacrificial source layer within a source level material layer in the process with a source contact layer to convert the source level material layer in the process into a continuous source level material layer; replacing the sacrificial material layer with a conductive layer to form an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other by the backside trenches; forming a backside trench filling structure in the backside trench; removing at least a backside portion of the substrate; as well as The continuous source level material layer is divided into a plurality of source level material layers by forming a source isolation trench passing through the continuous source level material layer.

39. The method of claim 38, wherein: The back side groove extends laterally along a first horizontal direction; The backside grooves include multiple repetitions of a unit pattern, the unit pattern including at least one first backside groove and a second backside groove repeated along a second horizontal direction; and The first backside trenches are covered by corresponding source level material layers, and each of the second backside trenches is exposed below a corresponding one of the source isolation trenches after the source isolation trenches are formed.

40. The method of claim 38, wherein: forming the continuous source level material layer and the alternating stack in a memory die; The method also includes providing a logic die including peripheral circuitry configured to control operation of the conductive layer and the vertical stack of memory elements, and bonding the logic die to the memory die before or after forming the source isolation trenches.

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