Integrated circuit (IC) structure and method of forming same

Abstract

The embodiment of the invention relates to an integrated circuit (IC) structure. The IC structure includes a semiconductor device having a front side and a back side opposite the front side. A first interconnect structure is disposed on a front side of the semiconductor device. The first interconnect structure includes a first dielectric structure having a plurality of inter-layer dielectric (ILD) layers. A second dielectric structure is disposed on the back side of the semiconductor device. The second dielectric structure includes a first high thermal conductivity layer having a thermal conductivity greater than a thermal conductivity of the ILD layer. The embodiment of the invention also relates to an integrated circuit (IC) structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit (IC) structures and methods of forming the same. Background Art

[0002] Modern integrated circuits (ICs) contain millions of semiconductor devices. The semiconductor devices are electrically interconnected by conductive interconnects formed above and / or below the semiconductor devices on the IC. The conductive interconnects are disposed within a dielectric structure and are configured to selectively provide power to the semiconductor devices. Summary of the invention

[0003] Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor device having a front side and a back side opposite to the front side; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a first dielectric structure having a plurality of interlayer dielectric (ILD) layers; and a second dielectric structure located on the back side of the semiconductor device, wherein the second dielectric structure includes a first high thermal conductivity layer having a thermal conductivity greater than that of the interlayer dielectric layer.

[0004] Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor device having a front side and a back side opposite to the front side, wherein the semiconductor device includes a gate structure located between a pair of source / drain regions; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a plurality of first conductive interconnects electrically coupled to the semiconductor device and disposed in a first dielectric structure; and a second interconnect structure located on the back side of the semiconductor device, wherein the second interconnect structure includes a plurality of second conductive interconnects disposed in a second dielectric structure, wherein the plurality of second conductive interconnects include a plurality of conductive contacts disposed on the source / drain regions and electrically coupled to the source / drain regions, wherein the plurality of conductive contacts are disposed in a first high thermal conductivity layer of the second dielectric structure.

[0005] Still other embodiments of the present application provide a method for forming an integrated circuit (IC) structure, comprising: forming a layer stack above a base substrate, wherein the layer stack includes an etch stop layer located above the base substrate and a lower semiconductor layer located on the etch stop layer; forming a plurality of semiconductor devices on the lower semiconductor layer; forming a first interconnect structure on the front side of the plurality of semiconductor devices, wherein the first interconnect structure includes a plurality of first conductive interconnects arranged in a first dielectric structure; bonding the first interconnect structure to a carrier substrate; removing the base substrate, the etch stop layer and the lower semiconductor layer from above the back side of the plurality of semiconductor devices, wherein the back side is opposite to the front side; and forming a first high thermal conductivity layer on the back side of the plurality of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of integrated circuit (IC) structures including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are shown.

[0008] FIG. 2A to FIG. 2B Various cross-sectional views of some additional embodiments of IC structures including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are shown.

[0009] Figure 3 Shows FIG. 2A to FIG. 2B An isometric view of some embodiments of an IC structure of a first semiconductor device.

[0010] FIG. 4A to FIG. 4B to FIG. 9A to FIG. 9B Various cross-sectional views of some other embodiments of IC structures including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are shown.

[0011] Fig.10 Cross-sectional views of some other embodiments of IC structures including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are shown.

[0012] Figures 11 to 24A to Fig. 24B Various cross-sectional views of some embodiments of methods for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are illustrated.

[0013] FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B Various cross-sectional views of some embodiments of methods for forming an interconnect structure having one or more high thermal conductivity layers on a plurality of semiconductor devices are shown.

[0014] Figures 28 to 37A to Fig.37B Various cross-sectional views of some other embodiments of methods for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices are shown.

[0015] FIG. 38A to FIG. 38B to FIG. 39A to FIG. 39B Various cross-sectional views of some other embodiments of methods for forming at least a portion of an interconnect structure having one or more high thermal conductivity layers on a plurality of semiconductor devices are shown.

[0016] Fig.40 A flow chart illustrating some embodiments of a method for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] An integrated circuit (IC) structure may include a plurality of semiconductor devices (e.g., transistors) located on the front side of a device layer (e.g., a silicon substrate). A first interconnect structure is disposed on the front side of the device layer. The first interconnect structure is bonded to a carrier substrate, and a second interconnect structure is disposed on the back side of the device layer. The first interconnect structure and the second interconnect structure facilitate electrically coupling the semiconductor devices together and / or electrically coupling to other devices. The second interconnect structure includes a dielectric structure on the device layer and a plurality of conductive interconnects in the dielectric structure. During operation, the semiconductor devices and / or the plurality of conductive interconnects may generate heat (e.g., due to Joule heating). The dissipation of the heat generated during operation of the IC structure becomes increasingly important as the devices are reduced and / or more densely packed together. The dielectric structure typically includes a low dielectric constant material (e.g., silicon dioxide, etc.) that increases the electrical isolation between the conductive interconnects. However, the low dielectric constant material of the dielectric structure has a low thermal conductivity (i.e., has a low heat dissipation capability).

[0020] During the formation of the IC structure, a semiconductor device is formed on the device layer, and a first interconnect structure is formed on the semiconductor device. After the first interconnect structure is bonded to the carrier substrate, a thinning process is performed on the device layer. This removes all or most of the device layer from above the semiconductor device, wherein the device layer has a relatively high thermal conductivity (e.g., greater than 10 watts per meter-Kelvin (W / mK)). Subsequently, a second interconnect structure is formed on the back side of the device layer. The challenge faced by the IC structure is the high local heat accumulation across the IC structure. For example, the dielectric structure of the second interconnect structure contacts a portion of the semiconductor device and / or can be relatively close to the semiconductor device. The low dielectric constant material of the dielectric structure has a relatively low thermal conductivity (e.g., about 0.9 watts per meter-Kelvin (W / mK), etc.). Low thermal conductivity may cause high local heat accumulation at or around the semiconductor device. High local heat accumulation across the IC structure may cause breakdown of the semiconductor device and / or delamination of the layers in the IC structure. Therefore, the IC structure has low heat dissipation performance (e.g., with low heat dissipation generated by the semiconductor device) that may reduce the reliability and overall performance of the IC structure.

[0021] Various embodiments of the present application are directed to an IC structure including a high thermal conductivity layer disposed on a plurality of semiconductor devices and configured to increase the diffusion of heat from the semiconductor devices. In some embodiments, the IC structure includes a plurality of semiconductor devices disposed on the device layer and a first interconnect structure located on the front side of the device layer. The first interconnect structure is bonded to a carrier substrate, and a second interconnect structure is disposed on the back side of the device layer. The second interconnect structure includes a dielectric structure and a plurality of conductive interconnects disposed in the dielectric structure. The dielectric structure includes one or more high thermal conductivity layers disposed on a plurality of semiconductor devices. One or more high thermal conductivity layers each have a relatively high thermal conductivity (e.g., greater than about 10W / mK) and are configured to dissipate heat from the semiconductor devices and / or the plurality of conductive interconnect structures. Therefore, heat can be effectively transferred from an area of ​​the IC structure that is prone to high local heat accumulation (e.g., heat can be effectively transferred from the semiconductor device). Therefore, one or more high thermal conductivity layers increase the heat dissipation performance of the IC structure and reduce or eliminate high local heat accumulation across the IC structure. This increases the reliability and overall performance of the IC structure.

[0022] Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) structure 100 including an interconnect structure having one or more high thermal conductivity layers disposed on a plurality of semiconductor devices is shown.

[0023] The IC structure 100 includes a first interconnect structure 106 disposed on a front side 108f of a device layer 108. An insulating layer 104 is disposed on the first interconnect structure 106, and a carrier substrate 102 is located above the insulating layer 104. A plurality of semiconductor devices 118 are disposed in and / or on the device layer 108. The first interconnect structure 106 includes a first dielectric structure 112 and a plurality of first conductive interconnects 113, 114, 116 disposed in the first dielectric structure 112. The plurality of first conductive interconnects 113, 114, 116 include a plurality of first conductive contacts 113, a plurality of first conductive lines 116, and a plurality of first conductive vias 114. The plurality of first conductive interconnects 113, 114, 116 are electrically coupled to the semiconductor device 118.

[0024] In some embodiments, the semiconductor device 118 is configured as a transistor and includes a gate dielectric 121 disposed above the device layer 108, a gate electrode 120 above the gate dielectric 121, one or more semiconductor channels 123, and a source / drain structure 122 pair disposed on opposite sides of the one or more semiconductor channels 123. The source / drain region may refer to a source or a drain, individually or collectively depending on the context. In various embodiments, the one or more semiconductor channels 123 are part of the device layer 108 and / or include the same material as the device layer 108 (e.g., silicon). In some embodiments, the source / drain structure 122 pair may be a doped region of the device layer 108, or may be or include doped epitaxial silicon. The gate electrode 120 is located above the one or more semiconductor channels 123. In some embodiments, the gate electrode 120 is located above the top surface of the one or more semiconductor channels 123 and extends along the sidewalls of the one or more semiconductor channels 123. In various embodiments, during use of the semiconductor devices 118, the gate electrode 120 of each semiconductor device 118 may be selectively biased to change the conductivity of one or more semiconductor channels 123 between the pair of source / drain structures 122. The semiconductor devices 118 may be, for example, planar metal oxide semiconductor (MOS) field effect transistors (FETs), gate-all-around (GAA) FETs, fin FETs (FinFETs), nanowire FETs, nanoring FETs, nanosheet (NS) FETs (NSFETs), some other type of semiconductor device and / or transistor, or any combination of the above.

[0025] The IC structure 100 also includes a second interconnect structure 110 disposed on the back side 108b of the device layer 108. The second interconnect structure 110 includes a second dielectric structure 115 and a plurality of second conductive interconnects 124, 126, 128 disposed in the second dielectric structure 115. The plurality of second conductive interconnects 124, 126, 128 include a plurality of second conductive contacts 124, a plurality of second conductive lines 126, and a plurality of second conductive vias 128. The plurality of second conductive interconnects 124, 126, 128 are electrically coupled to the semiconductor device 118 and / or the first interconnect structure 106. In various embodiments, one or more of the second conductive contacts 124 directly contacts one or more structures of the semiconductor device 118. For example, an independent second conductive contact 124a directly contacts a source / drain region 122 of an independent semiconductor device 118a of the plurality of semiconductor devices 118.

[0026] The second dielectric structure 115 includes a plurality of high thermal conductivity layers 111 stacked with a plurality of dielectric layers 117. The plurality of high thermal conductivity layers 111 include a first high thermal conductivity layer 111a disposed along the back side 108b of the device layer 108. The plurality of dielectric layers 117 include a low dielectric constant material having a relatively low thermal conductivity (e.g., less than about 1 W / mK). The high thermal conductivity layer 111 includes a dielectric material having a relatively high thermal conductivity (e.g., greater than about 10 W / mK) and is configured to effectively transfer heat away from the plurality of semiconductor devices 118 and / or the plurality of second conductive interconnects 124, 126, 128. In various embodiments, the thermal conductivity of the high thermal conductivity layer 111 is greater than the thermal conductivity of the first dielectric structure 112, the device layer 108, the insulating layer 104, and / or the plurality of dielectric layers 117.

[0027] During operation of the IC structure 100, current flowing through the conductive structures of the first interconnect structure 106 and / or the second interconnect structure 110 and / or through the semiconductor device 118 causes the generation of heat. In various embodiments, this may cause heat to accumulate at or around the semiconductor device 118. Because the second dielectric structure 115 includes the high thermal conductivity layer 111, heat can be effectively dissipated away from areas of the IC structure 100 that are prone to high local heat accumulation (e.g., heat is effectively transferred away from the semiconductor device 118). The effective dissipation of heat increases the heat dissipation performance of the IC structure 100 and reduces or eliminates high local heat accumulation across the IC structure 100. Therefore, the performance of the semiconductor device 118 is increased, and damage to the semiconductor device 118 and / or the conductive structures of the first interconnect structure 106 and / or the second interconnect structure 110 is reduced. Therefore, the reliability and overall performance of the IC structure 100 are increased.

[0028] FIG. 2A to FIG. 2B Various cross-sectional views of some embodiments of an IC structure 200 including an interconnect structure having one or more high thermal conductivity layers are shown. Figure 2A A cross-sectional view of some embodiments of the IC structure 200 is shown taken along a first plane (eg, the zx plane). Figure 2B A cross-sectional view of some embodiments of the IC structure 200 is shown taken along a second plane (eg, a zy plane) perpendicular to the first plane.

[0029] like Figure 2AAs shown in , the IC structure 200 includes a first interconnect structure 106 on a front side FS of a plurality of semiconductor devices 118 and a second interconnect structure 110 on a back side BS of the plurality of semiconductor devices 118. The front side FS of the semiconductor device 118 corresponds to an upper surface of the semiconductor device 118 and faces the first interconnect structure 106. The back side BS of the semiconductor device 118 corresponds to a lower surface of the semiconductor device 118 and faces the second interconnect structure 110. The front side FS is opposite to the back side BS. In various embodiments, the semiconductor device 118 is disposed in and / or on a device layer 108, wherein the front side FS corresponds to a first surface of the device layer 108, and the back side BS corresponds to a second surface of the device layer 108 opposite to the first surface.

[0030] The insulating layer 104 is disposed on the first interconnect structure 106, and the carrier substrate 102 is located on the insulating layer 104. The insulating layer 104 can be, for example, or include an oxide, such as silicon dioxide or some other suitable material. The carrier substrate 102 is a semiconductor substrate or some other suitable substrate. In some embodiments, the carrier substrate 102 is or includes silicon, germanium, some other suitable material, or any combination of the above materials. In various embodiments, the insulating layer 104 is configured to facilitate bonding between the carrier substrate 102 and the first interconnect structure 106.

[0031] The semiconductor device 118 is a gate-all-around (GAA) field effect transistor (FET). In other embodiments, the semiconductor device 118 may alternatively be a planar metal oxide semiconductor (MOS) FET (MOSFET), a fin FET (FinFET), a nanowire FET, a nanoring FET, a nanosheet (NS) FET (NSFET), some other type of semiconductor device and / or transistor, or any combination of the above devices. The semiconductor devices 118 each include a plurality of semiconductor channels 206, a gate dielectric structure 210, a gate electrode 120, a spacer layer 208, and corresponding source / drain regions 122. The semiconductor channels 206 for each of the semiconductor devices 118 are stacked vertically on each other. The gate electrode 120 is located above the semiconductor channels 206 and is vertically spaced apart between adjacent semiconductor channels 206. The gate dielectric structure 210 is spaced apart between the gate electrode 120 and the semiconductor channels 206. In various embodiments, the gate dielectric structure 210 and the gate electrode 120 both extend continuously around the bottom and top surfaces of at least two or more of the semiconductor channels 206. The gate structure of the semiconductor device 118 includes a gate electrode 120 and a gate dielectric structure 210 .

[0032] In various embodiments, the semiconductor channel 206 is part of and / or formed by the device layer 108 and includes the semiconductor material (e.g., silicon) of the device layer 108. In some embodiments, the semiconductor channel 206 is a nanostructure, a nanosheet, some other suitable structure, etc. The semiconductor channel 206 extends continuously between two of the source / drain regions 122. In various embodiments, the source / drain regions 122 directly contact the corresponding semiconductor channel 206. The spacer layer 208 is disposed between the source / drain regions 122 and the gate dielectric structure 210. In various embodiments, two of the semiconductor devices 118 in the plurality of semiconductor devices 118 share one of the source / drain regions 122. In alternative embodiments, the semiconductor devices 118 do not share the source / drain regions 122, but rather each have a discrete pair of source / drain regions and are laterally separated from each other by a non-zero distance (not shown). By applying appropriate bias conditions to the gate electrode 120 and the source / drain regions 122 , the conductivity of the semiconductor channel 206 may be controlled (eg, may be switched between one or more conductive and non-conductive states).

[0033] In some embodiments, the gate electrode 120 may be, for example, or include polysilicon, titanium, aluminum, tungsten, titanium, tantalum, gallium, carbon, some other suitable material, or any combination of the above materials. In various embodiments, the gate dielectric structure 210 may be, for example, or include silicon dioxide, aluminum oxide, hafnium oxide, silicon oxynitride, a high-k dielectric material, some other suitable dielectric, or any combination of the above materials. In further embodiments, the source / drain region 122 may be, for example, or include silicon, germanium, silicon germanium, an epitaxial semiconductor material (e.g., epitaxial silicon, epitaxial germanium, epitaxial silicon germanium, etc.), some other suitable material, or any combination of the above materials. In addition, the source / drain region 122 is doped. In some embodiments, the source / drain region 122 includes silicon or epitaxial silicon doped with phosphorus, wherein the doping concentration of phosphorus in the source / drain region 122 is approximately 1*10 21 Atom / cm 3 In a further embodiment, the source / drain region 122 comprises epitaxial silicon germanium doped with boron, wherein the boron doping concentration in the source / drain region 122 is about 5*10 20 Atom / cm 3 or greater. In further embodiments, the spacer layer 208 may be, for example, or include silicon oxynitride, silicon oxycarbide, silicon carbon oxynitride, some other dielectric material, or any combination thereof. In various embodiments, the spacer layer 208 includes silicon carbon oxynitride, wherein the atomic percentage of carbon in the spacer layer 208 is about 6% or less.

[0034] The first interconnect structure 106 is electrically coupled to the plurality of semiconductor devices 118 on the front side FS of the semiconductor devices 118. The first interconnect structure 106 includes a first dielectric structure 112 and a plurality of first conductive interconnects 113, 114, 116, the first conductive interconnects 113, 114, 116 including a plurality of first conductive contacts 113, a plurality of first conductive lines 116, and a plurality of first conductive vias 114. A topmost layer of the plurality of first conductive lines 116 is separated from the insulating layer 104 by at least a portion of the first dielectric structure 112. In a further embodiment, a topmost layer of the plurality of first conductive lines 116 directly contacts at least a portion of a bottom surface of the insulating layer 104. In various embodiments, the first dielectric structure 112 includes a plurality of interlayer dielectric (ILD) layers 202 and one or more etch stop layers 204 disposed between the corresponding ILD layers 202. The plurality of ILD layers 202 may be, for example, or include an oxide (e.g., silicon dioxide), borosilicate glass, silicon oxycarbide, silicon oxycarbonitride, a low-k dielectric material, or the like. The one or more etch stop layers 204 may be, for example, or include silicon nitride, silicon carbonitride, some other dielectric material, etc. In some embodiments, the thermal conductivity of the one or more ILD layers 202 is relatively low (eg, less than about 1 W / mK).

[0035] The second interconnect structure 110 is electrically coupled to the plurality of semiconductor devices 118 on the back side BS of the semiconductor devices 118. The second interconnect structure 110 includes a second dielectric structure 115 and a plurality of second conductive interconnects 124, 126, 128 disposed in the second dielectric structure 115. The plurality of second conductive interconnects 124, 126, 128 include a plurality of second conductive contacts 124, a plurality of second conductive lines 126, and a plurality of second conductive vias 128. In various embodiments, the second conductive contacts 124 directly contact the source / drain regions 122 of the corresponding semiconductor devices 118. The plurality of second conductive interconnects 124, 126, 128 may be, for example, or include titanium nitride, aluminum, tungsten, copper, ruthenium, molybdenum, titanium aluminum, tantalum nitride, some other conductive material, or any combination thereof.

[0036] The second dielectric structure 115 includes a plurality of high thermal conductivity layers 111a-111c and a plurality of dielectric layers 117a-117b. The plurality of dielectric layers 117a-117b include a first dielectric layer 117a and a second dielectric layer 117b. The plurality of high thermal conductivity layers 111a-111c are configured to increase heat transfer in the horizontal direction within the second dielectric structure 115. The plurality of high thermal conductivity layers 111a-111c include a first high thermal conductivity layer 111a disposed along the back side BS of the plurality of semiconductor devices 118 and a second high thermal conductivity layer 111b disposed on the first high thermal conductivity layer 111a. In some embodiments, the plurality of second conductive contacts 124 include vertical segments 212 and body segments 214, respectively. In various embodiments, the vertical segments 212 may be configured as contacts or vias, and the body segments 214 may be configured as wires. In some embodiments, the vertical segment 212 is disposed in the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b, and the main body segment 214 is disposed in the first dielectric layer 117a. In further embodiments, the third high thermal conductivity layer 111c of the plurality of high thermal conductivity layers 111a-111c extends continuously along the bottom surface of the second conductive contact 124. The first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b directly contact the opposite sidewalls of the vertical segment 212 and / or directly contact the top surface of the main body segment 214. In addition, the third high thermal conductivity layer 111c directly contacts the opposite sidewalls of the second conductive via 128. In various embodiments, the second conductive contact 124 may be configured as a conductive plug. In further embodiments, the second conductive contact 124 is configured as a power rail or is directly electrically coupled to the power rail, wherein the second conductive contact 124 may deliver high power to the semiconductor device 118.

[0037] In some embodiments, the plurality of high thermal conductivity layers 111a-111c include a material having a thermal conductivity greater than about 10 W / mK, in a range of about 10 to 2500 W / mK, or some other suitable value. In some embodiments, the plurality of high thermal conductivity layers 111a-111c may be, for example, or include aluminum nitride (AlN), boron nitride (BN), yttrium oxide (Y2O3), yttrium aluminum garnet (Y3Al5O 12), aluminum oxide (Al2O3), beryllium oxide (BeO), silicon carbide (SiC), graphene, diamond-like carbon (DLC), diamond (e.g., nearly isotropic diamond particles), another suitable material, or any combination of the foregoing materials. In some embodiments, the plurality of high thermal conductivity layers 111a-111c may be polycrystalline, single crystal, amorphous, etc. For example, the high thermal conductivity layers 111a-111c may be or include polycrystalline silicon carbide, single crystal silicon carbide, or amorphous silicon carbide. In further embodiments, the high thermal conductivity layers 111a-111c have a cubic crystal structure, a hexagonal crystal structure, a tetragonal crystal structure, an orthorhombic crystal structure, a monoclinic crystal structure, a triclinic crystal structure, etc. In various embodiments, the high thermal conductivity layers 111a-111c have a cubic crystal structure that may be different from the crystal structure of the dielectric layers 117a-117b, the ILD layer 202, and / or the one or more etch stop layers 204. For example, the dielectric layers 117a-117b and / or the ILD layer 202 may include silicon dioxide having a hexagonal crystal structure, and the one or more etch stop layers 204 may include silicon nitride having a hexagonal crystal structure, wherein the high thermal conductivity layers 111a-111c have a cubic crystal structure. The high thermal conductivity layers 111a-111c having a cubic crystal structure increase the ability for the high thermal conductivity layers 111a-111c to dissipate heat. In further embodiments, the high thermal conductivity layers 111a-111c have a thermal conductivity higher than the thermal conductivity of the plurality of semiconductor channels 206, the source / drain regions 122, and / or the gate dielectric structure 210.

[0038] In a further embodiment, the high thermal conductivity layers 111a-111c are also configured to serve as an etch stop layer for the second interconnect structure 110, wherein the high thermal conductivity layers 111a-111c include a material that is more resistant to etching than the plurality of dielectric layers 117a-117b. For example, when exposed to an etchant (e.g., such as a dry etchant including fluorine), the high thermal conductivity layers 111a-111c are etched at a first rate that is less than a second rate at which the plurality of dielectric layers 117a-117b are etched. In some embodiments, the top surface of the first high thermal conductivity layer 111a is aligned with the top surfaces of the plurality of second conductive contacts 124. In various embodiments, the thickness of the first high thermal conductivity layer 111a is less than the thickness of the second high thermal conductivity layer 111b. In addition, the thickness of the second high thermal conductivity layer 111b is greater than the thickness of the first dielectric layer 117a. In some embodiments, the thickness of each of the high thermal conductivity layers 111a-111c is greater than the thickness of one or more etch stop layers 204. The high thermal conductivity layers 111a-111c include a material different from that of the one or more etch stop layers 204. In various embodiments, the high thermal conductivity layers 111a-111c may be or include materials different from each other. In further embodiments, the high thermal conductivity layers 111a-111c may each be or include the same material.

[0039] Since high thermal conductivity layers 111a-111c are disposed in second interconnect structure 110 and along backside BS of semiconductor device 118, heat can be effectively dissipated away from semiconductor device 118 and / or conductive interconnects of second interconnect structure 110. Thus, performance and reliability of IC structure 200 are increased.

[0040] It should be understood that the high thermal conductivity layers 111 a - 111 c may be disposed at different locations within the IC structure 200 , and that the IC structure 200 may have different numbers of high thermal conductivity layers disposed in the second interconnect structure 110 . FIG. 4A to FIG. 4B to Fig.10 Various cross-sectional views are shown in which the high thermal conductivity layer is disposed at different locations within the second interconnect structure 110 and / or the second interconnect structure 110 has different numbers of high thermal conductivity layers.

[0041] like Figure 2B As shown in , a plurality of semiconductor devices 118 are arranged in an array including at least two rows and at least two columns. For example, Figure 2A The cross-sectional view is taken along a first column of the plurality of semiconductor devices 118, and Figure 2B The cross-sectional view is taken along the source / drain region 122 of the first row of the plurality of semiconductor devices 118. In some embodiments, the first dielectric structure 112 extends along the top surface of the source / drain region 122 to the second dielectric structure 115. In various embodiments, the bottom surface of the first dielectric structure 112 directly contacts the top surface of the second dielectric structure 115.

[0042] Figure 3 Shows FIG. 2A to FIG. 2B An isometric view of some embodiments of an individual semiconductor device 118 of an IC structure 200 .

[0043] like Figure 3 As shown in FIG. 1 , the semiconductor device 118 includes a gate structure 302 disposed above and around a plurality of semiconductor channels 206. In various embodiments, the gate structure 302 includes a gate electrode ( FIG. 2A to FIG. 2B 120) and gate dielectric structure ( FIG. 2A to FIG. 2B 210). A plurality of semiconductor channels 206 extend continuously and laterally between the source / drain regions 122. In various embodiments, vertical segments of the independent second conductive contact 124 are disposed in the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b. In some embodiments, the first high thermal conductivity layer 111a extends continuously along the bottom surface of the source / drain region 122.

[0044] FIG. 4A to FIG. 4B to FIG. 9A to FIG. 9B Shows FIG. 2A to FIG. 2B1 and 2. The cross-sectional views of some other embodiments of the IC structure 200 are shown in FIG. 1. The views with an "A" suffix show cross-sectional views taken along the zx plane, and the views with a "B" suffix show cross-sectional views taken along the zy plane.

[0045] FIG. 4A to FIG. 4B Various cross-sectional views of some embodiments of an IC structure 400 are shown, wherein the second conductive contact 124 extends a non-zero distance d1 above the bottom surface of the source / drain region 122. In various embodiments, a liner layer 402 is disposed along opposite sidewalls of each of the second conductive contacts 124. The liner layer 402 may be, for example, or include silicon nitride, silicon carbide, some other suitable material, or any combination of the foregoing materials. In further embodiments, the liner layer 402 is omitted (not shown), and the source / drain region 122 directly contacts the opposite sidewalls of the corresponding second conductive contact 124.

[0046] FIG. 5A to FIG. 5B Various cross-sectional views of some embodiments of the IC structure 500 are shown, wherein the width of each second conductive contact 124 is greater than the width of the corresponding source / drain region 122. In various embodiments, each second conductive contact 124 extends continuously along the entire bottom surface of the corresponding source / drain region 122.

[0047] FIG. 6A to FIG. 6B Various cross-sectional views of some embodiments of the IC structure 600 are shown, wherein a plurality of second conductive contacts 124 are disposed in the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b. In addition, the second high thermal conductivity layer 111b extends continuously along the top surface of the third high thermal conductivity layer 111c. Thus, the ability for the IC structure 600 to dissipate heat from the second conductive contacts 124 and / or the semiconductor device 118 is increased, thereby increasing the overall performance of the IC structure 600.

[0048] FIG. 7A to FIG. 7B Shows the corresponding FIG. 5A to FIG. 5B 1 and 10. Various cross-sectional views of some other embodiments of the IC structure 500 and some embodiments of the IC structure 700, wherein the source / drain regions 122 extend below the top surface of the first high thermal conductivity layer 111a.

[0049] In addition, in Figure 7BIn some embodiments shown in , the lower etch stop layer 702 is disposed along the bottom surface of the first dielectric structure 112, and the isolation structure 704 is disposed along the lower portion of the source / drain region 122 and the upper portion of the second conductive contact 124. The lower etch stop layer 702 may be, for example, or include silicon nitride, silicon oxynitride, some other suitable dielectric, or any combination of the above materials. In various embodiments, the lower etch stop layer 702 has a thermal conductivity less than the thermal conductivity of the high thermal conductivity layers 111a-111b. In various embodiments, the first dielectric layer 117a extends from the bottom surface of the first high thermal conductivity layer 111a to the opposite sidewalls of the first high thermal conductivity layer 111a. In some embodiments, the isolation structure 704 may be configured as a shallow trench isolation (STI) structure. The isolation structure 704 may be, for example, or include silicon dioxide, silicon nitride, some other dielectric material, or any combination of the above materials. In still further embodiments, the isolation structure 704 has a thermal conductivity that is less than the thermal conductivity of the high thermal conductivity layers 111 a - 111 b .

[0050] FIG. 8A to FIG. 8B Shows the corresponding FIG. 7A to FIG. 7B 800 of some other embodiments of the IC structure 700, wherein the first high thermal conductivity layer 111a extends continuously from the source / drain region 122 to a point aligned with the bottom surface of the second conductive contact 124. Figure 8B As shown in FIG. 7 , in some embodiments, the isolation structure 704 extends from the sidewalls of the source / drain region 122 to the sidewalls of the second conductive contact 124 .

[0051] FIG. 9A to FIG. 9B Shows the corresponding FIG. 5A to FIG. 5B 900 of some other embodiments of the IC structure 500 of the present invention, wherein the conductive interconnects of the first interconnect structure 106 and the second interconnect structure 110 respectively include a conductive core structure 904 surrounded by a conductive liner layer 902. In some embodiments, the conductive core structure 904 can be, for example, or include tungsten, aluminum, copper, ruthenium, tantalum, titanium, some other conductive material, or any combination of the foregoing materials. In various embodiments, the conductive liner layer 902 can be, for example, or include titanium nitride, tantalum nitride, some other suitable material, or any combination of the foregoing materials. In some embodiments, the conductive liner layer 902 is configured as a barrier layer and is disposed between the conductive core structure 904 and the corresponding dielectric layer of the first dielectric structure 112 or the second dielectric structure 115.

[0052] In various embodiments, the upper surface of the conductive pad layer 902 of each of the second conductive contacts 124 is disposed along the bottom surface of the first high thermal conductivity layer 111 a. In further embodiments, the top surface of the conductive pad layer 902 of each of the second conductive contacts 124 is disposed along the corresponding source / drain region 122 and aligned with the top surface of the first high thermal conductivity layer 111 a.

[0053] It should be understood that although IC structure 900 shows FIG. 5A to FIG. 5B Another embodiment of the IC structure 500, but Figure 1 , FIG. 2A to FIG. 2B , Figure 3 , FIG. 4A to FIG. 4B and FIG. 6A to FIG. 6B to FIG. 8A to FIG. 8B Any one of the IC structures may include FIG. 9A to FIG. 9B The conductive liner layer 902 and the conductive core structure 904 shown and / or described in FIG. FIG. 4A to FIG. 4B to FIG. 9A to FIG. 9B A single via level and a single line level are shown in the second interconnect structure 110 of FIG. 1 , but more via levels and / or line levels are possible.

[0054] Fig.10 Cross-sectional views of some other embodiments of IC structures 1000 including interconnect structures having one or more high thermal conductivity layers are shown.

[0055] The IC structure 1000 includes a first interconnect structure 106 disposed on an upper surface of a plurality of semiconductor devices 118 and a second interconnect structure 110 disposed on a lower surface of the plurality of semiconductor devices 118. The bottom layer 126b of the plurality of second conductive lines 126 of the second interconnect structure 110 may be configured, for example, as a redistribution line, a bonding pad, etc. A plurality of solder bumps 1002 are disposed on the bottom layer 126b of the plurality of second conductive lines 126 and are configured to couple and / or bond the IC structure 1000 to another semiconductor structure (e.g., a package substrate, a semiconductor die, etc.).

[0056] Figures 11 to 24A to Fig. 24B Various cross-sectional views of some embodiments of methods for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers are shown. Figures 11 to 24A to Fig. 24B Although described with respect to methods, it should be understood that the structures disclosed in the methods are not limited to the methods, but can exist independently as structures independent of the methods. Figures 11 to 24A to Fig. 24BDescribed as a series of steps, it should be understood that these steps are not limited, because in other embodiments, the order of the steps can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the steps shown and / or described can be omitted in whole or in part. In addition, the figures with an "A" suffix show a cross-sectional view taken along the zx plane, and the figures with a "B" suffix show a cross-sectional view taken along the zy plane.

[0057] like Fig.11 As shown in the cross-sectional view 1100 of FIG. 1 , a base substrate 1102 is provided, and a layer stack 1103 is formed over the base substrate 1102. The base substrate 1102 may be, for example, or include silicon, germanium, silicon germanium, some other semiconductor body, etc. In some embodiments, the layer stack 1103 includes an etch stop layer 1104 on the base substrate 1102, a lower semiconductor layer 1106 on the etch stop layer 1104, a first high thermal conductivity layer 111a, a plurality of first semiconductor layers 1110, and a plurality of second semiconductor layers 1112. The plurality of first semiconductor layers 1110 and the plurality of second semiconductor layers 1112 are alternately stacked with each other. In various embodiments, the plurality of second semiconductor layers 1112 are part of the device layer 108 or define the device layer 108.

[0058] In some embodiments, the process for forming the etch stop layer 1104 includes depositing or growing the etch stop layer 1104 over the base substrate 1102 by, for example, a chemical vapor deposition (CVD) process, an epitaxial process, or some other suitable deposition or growth process. The lower semiconductor layer 1106 may be formed over the etch stop layer 1104 by, for example, a CVD process, an epitaxial process, or some other suitable deposition or growth process. The first high thermal conductivity layer 111a may be formed over the lower semiconductor layer 1106 by, for example, a CVD process, a thermal CVD process, a hybrid physical CVD (HPCVD) process, a plasma enhanced CVD (PECVD) process, a microwave plasma CVD (MWCVD) process, a physical vapor deposition (PVD) process, a thermal atomic layer deposition (ALD) process, a plasma enhanced ALD (PEALD) process, or some other suitable deposition or growth process. In addition, the first semiconductor layer 1110 and the second semiconductor layer 1112 are each formed over the first high thermal conductivity layer 111a by an epitaxial process or some other suitable deposition or growth process. In various embodiments, the independent epitaxial process for forming any one of the etch stop layer 1104, the lower semiconductor layer 1106, the first semiconductor layer 1110 and the second semiconductor layer 1112 may, for example, be or include molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), some other suitable epitaxial process, or any combination of the above processes.

[0059] In various embodiments, the first high thermal conductivity layer 111a is deposited at a low processing temperature, such as less than about 400 degrees Celsius, in the range of about 100 to 400 degrees Celsius, or some other suitable temperature. The first high thermal conductivity layer 111a may be, for example, or include aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, diamond, another suitable material, or any combination of the above materials. The etch stop layer 1104 and / or the first semiconductor layer 1110 may be, for example, or include silicon germanium (e.g., having a germanium atomic percentage in the range of about 10% to 35%), silicon, doped silicon (e.g., silicon doped with boron), etc. The second semiconductor layer 1112 and / or the lower semiconductor layer 1106 may be, for example, or include silicon, epitaxial silicon, or some other suitable semiconductor material.

[0060] like Fig.12 As shown in the cross-sectional view 1200, in the plurality of second semiconductor layers ( Fig.11 A masking layer 1202 is formed on the top of the plurality of first semiconductor layers 1110 and the plurality of second semiconductor layers ( Fig.11 The masking layer 1202 is patterned by performing a patterning process on the first semiconductor layer 1112 to form a plurality of semiconductor channels 206 vertically stacked with the first semiconductor layer 1110. In some embodiments, the patterning process includes performing a dry etching process, a wet etching process, another suitable etching process, or any combination of the above processes. In addition, the masking layer 1202 (not shown) can be removed during or after the patterning process.

[0061] like Fig.13 As shown in the cross-sectional view 1300 of , a plurality of semiconductor devices 118 are formed above the base substrate 1102. In various embodiments, the semiconductor devices 118 are GAA FETs. The semiconductor devices 118 include a plurality of semiconductor channels 206, a gate dielectric structure 210, a gate electrode 120, a spacer layer 208, and a source / drain region 122, respectively. The semiconductor channels 206 for each of the semiconductor devices 118 are stacked vertically on each other. The gate electrode 120 is located above the semiconductor channels 206 and is vertically spaced apart between adjacent semiconductor channels 206. The gate dielectric structure 210 is spaced apart between the gate electrode 120 and the semiconductor channels 206. The gate electrode 120 and the gate dielectric structure 210 of each semiconductor device 118 define the gate structure of the corresponding semiconductor device.

[0062] In some embodiments, a process for forming the semiconductor device 118 includes: forming a semiconductor layer ( Fig.12 A dummy gate structure (not shown) is formed (eg, by CVD, PVD, etc.) above the first semiconductor layer ( Fig.121110) and a dummy gate structure (e.g., by CVD, PVD, ALD, etc.) to form a spacer layer 208; forming (e.g., by an epitaxial process) a source / drain region 122 adjacent to the semiconductor channel; selectively removing the dummy gate structure and the first semiconductor layer ( Fig.12 1110); forming a gate dielectric structure 210 on the semiconductor channel 206 (eg, by CVD, PVD, etc.); and forming a gate electrode 120 on the gate dielectric structure 210 (eg, by CVD, PVD, electroplating, chemical plating, etc.).

[0063] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 14 , a first interconnect structure 106 is formed over the front side FS of the semiconductor device 118. The first interconnect structure 106 includes a plurality of first conductive contacts 113, a plurality of first conductive lines 116, and a plurality of first conductive vias 114 disposed within the first dielectric structure 112. In some embodiments, the conductive structures of the first interconnect structure 106 may each be formed by a damascene process (e.g., a single damascene process or a dual damascene process) or some other suitable process. In further embodiments, the first dielectric structure 112 includes one or more interlayer dielectric (ILD) layers and one or more etch stop layers (e.g., such as etch stop layers) that may each be formed by, for example, CVD, PVD, ALD, or some other suitable growth or deposition process. FIG. 2A to FIG. 2B ).

[0064] like Fig.15 As shown in the cross-sectional view 1500 of , a carrier substrate 102 is provided which is subsequently bonded to the first interconnect structure 106. The carrier substrate 102 may, for example, be or include silicon, germanium, or some other suitable semiconductor substrate material. In various embodiments, bonding the carrier substrate 102 to the first interconnect structure 106 includes: forming (e.g., by CVD, PVD, ALD, etc.) an insulating layer 104 on the carrier substrate 102; and bonding (e.g., by fusion bonding, vacuum bonding, direct bonding, etc.) the insulating layer 104 to the first interconnect structure 106. The insulating layer 104 may, for example, be or include an oxide such as silicon dioxide, or some other suitable material.

[0065] like FIG. 16A to FIG. 16B As shown in the cross-sectional views 1600a and 1600b, the flip Fig.15 and performing a thinning process to remove the base substrate ( Fig.15 1102). In various embodiments, the thinning process includes thinning the base substrate ( Fig.15 1102 ) performs a mechanical grinding process, a chemical mechanical polishing (CMP) process, an etching process or some other suitable process until the etching stop layer 1104 is reached.

[0066] In addition, if Fig. 16B As shown in FIG. 1 , in some embodiments, the isolation structure 704 is disposed along the sidewalls of the first high thermal conductivity layer 111a, the sidewalls of the lower semiconductor layer 1106, and the sidewalls of the etch stop layer 1104. In various embodiments, the isolation structure 704 is disposed along the sidewalls of the first high thermal conductivity layer 111a, the lower semiconductor layer 1106, and the etch stop layer 1104. Fig.12 The lower etch stop layer 702 is formed after the patterning process of the semiconductor device 118 and before the first interconnect structure 106 is formed (e.g., by CVD, PVD, etc.). In various embodiments, the isolation structure 704 is configured as an STI structure or some other suitable isolation structure. In addition, the lower etch stop layer 702 is disposed along the first dielectric structure 112. In some embodiments, the lower etch stop layer 702 is formed after the semiconductor device 118 is formed and before the first interconnect structure 106 is formed (e.g., by CVD, PVD, etc.).

[0067] like FIG. 17A to FIG. 17B As shown in cross-sectional views 1700a and 1700b, a removal process is performed to remove the etch stop layer ( FIG. 16A to FIG. 16B 1104) and the lower semiconductor layer ( FIG. 16A to FIG. 16B 1106). In some embodiments, the removal process includes: removing the etching stop layer ( FIG. 16A to FIG. 16B 1104) deposits (e.g., by CVD, PVD, etc.) a sacrificial oxide (e.g., silicon dioxide) (not shown); and deposits (e.g., by CVD, PVD, etc.) a sacrificial oxide, an etch stop layer ( FIG. 16A to FIG. 16B 1104) and the lower semiconductor layer ( FIG. 16A to FIG. 16B 1106) performs a planarization process (e.g., a CMP process). In further embodiments, the removal process includes performing an etching process (e.g., dry etching), a mechanical grinding process, or some other suitable removal process. In addition, the removal process removes at least a portion of the isolation structure 704.

[0068] like FIG. 18A to FIG. 18B As shown in the cross-sectional views 1800a and 1800b, the isolation structure ( Fig. 17B 704), and a second high thermal conductivity layer 111b is formed on the back side BS of the semiconductor device 118. In some embodiments, the isolation structure ( Fig. 17B 704) is removed by a wet etching process, a dry etching process, some other suitable removal process, etc. In some embodiments, the second high thermal conductivity layer 111b may be, for example, or include aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, diamond, another suitable material, or any combination of the foregoing materials. In various embodiments, the second high thermal conductivity layer 111b has a thermal conductivity greater than about 10 W / mK, in a range of about 10 to 2500 W / mK, or some other suitable value. The thermal conductivity of the second high thermal conductivity layer 111b is greater than the thermal conductivity of one or more ILD layers of the first dielectric structure 112.

[0069] In some embodiments, the second high thermal conductivity layer 111b is formed on the semiconductor device 118 by, for example, a CVD process, a thermal CVD process, an HPCVD process, a PECVD process, a MWCVD process, a PVD process, a thermal ALD process, a PEALD process, or some other suitable deposition or growth process. In addition, the second high thermal conductivity layer 111b is formed or deposited at a low processing temperature, such as less than about 400 degrees Celsius, in a range of about 100 to 400 degrees Celsius, or some other suitable temperature. Depositing (e.g., by CVD, PVD, ALD, etc.) the second high thermal conductivity layer 111b at a low processing temperature (e.g., less than about 400 degrees Celsius) promotes the second high thermal conductivity layer 111b to have a relatively high thermal conductivity (e.g., greater than about 10 W / mK) while preventing damage (e.g., delamination, device damage, etc.) to the plurality of semiconductor devices 118 and / or layers within the first interconnect structure 106. In addition, the second high thermal conductivity layer 111b is formed to have a crystalline structure (e.g., a single crystal structure, a polycrystalline structure, an amorphous structure, etc.) that promotes heat dissipation across the second high thermal conductivity layer 111b. In a further embodiment, after the second high thermal conductivity layer 111b is deposited over the semiconductor device 118, a planarization process (e.g., a CMP process) is performed on the second high thermal conductivity layer 111b so that the top surface of the second high thermal conductivity layer 111b is substantially flat. In some embodiments, the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b include the same material. In a further embodiment, the material of the first high thermal conductivity layer 111a is different from the material of the second high thermal conductivity layer 111b. In a further embodiment, the second high thermal conductivity layer 111b can be deposited at a processing temperature in the range of about 100 to 1400 degrees Celsius.

[0070] like FIG. 19A to FIG. 19B As shown in cross-sectional views 1900a and 1900b of the drawings, a first dielectric layer 117a is formed on the second high thermal conductivity layer 111b. The first dielectric layer 117a is formed on the second high thermal conductivity layer 111b by, for example, a CVD process, a PVD process, an ALD process, or some other suitable deposition or growth process. The first dielectric layer 117a may, for example, be or include an oxide such as silicon dioxide or some other suitable material. In some embodiments, the thermal conductivity of the first dielectric layer 117a is less than about 1 W / mK, and is less than the thermal conductivity of the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b.

[0071] like FIG. 20A to FIG. 20BAs shown in cross-sectional views 2000a and 2000b of , a patterning process is performed on the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b and the first dielectric layer 117a to form a plurality of openings 2002 above the source / drain region 122. In some embodiments, the patterning process includes: forming a masking layer (not shown) above the first dielectric layer 117a; performing an etching process (e.g., dry etching, wet etching, etc.) on the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b and the first dielectric layer 117a to define a plurality of openings 2002; and performing a removal process to remove the masking layer.

[0072] like FIG. 21A to FIG. 21B As shown in the cross-sectional views 2100a and 2100b, in the plurality of openings ( FIG. 20A to FIG. 20B In some embodiments, forming the second conductive contact 124 includes: forming a plurality of second conductive contacts 124 in the opening ( FIG. 20A to FIG. 20B 2002) deposits (e.g., by CVD, PVD, sputtering, electroplating, etc.) one or more conductive materials (e.g., titanium nitride, titanium, aluminum, titanium aluminum, molybdenum, ruthenium, titanium nitride, tantalum nitride, etc.) in a substrate; and performs a planarization process (e.g., a CMP process) on the one or more conductive materials. In various embodiments, the second conductive contact 124 includes a conductive liner layer (e.g., such as FIG. 9A to FIG. 9B In such an embodiment, forming the second conductive contact 124 includes depositing (eg, by CVD, PVD, etc.) a liner of the opening ( FIG. 20A to FIG. 20B 2002) of the conductive liner layer; depositing (for example, by CVD, PVD, sputtering, electroplating, etc.) a conductive core structure over the conductive liner layer; and performing a planarization process on the conductive liner layer and the conductive core structure.

[0073] like FIG. 22A to FIG. 22BAs shown in the cross-sectional views 2200a and 2200b of FIG. 1 , a third high thermal conductivity layer 111c and a second dielectric layer 117b are formed on the plurality of second conductive contacts 124, thereby defining a second dielectric structure 115. In some embodiments, the third high thermal conductivity layer 111c is formed on the second conductive contacts 124 by, for example, a CVD process, a thermal CVD process, an HPCVD process, a PECVD process, a MWCVD process, a PVD process, a thermal ALD process, a PEALD process, or some other suitable deposition or growth process. In addition, the third high thermal conductivity layer 111c is formed or deposited at a low processing temperature, such as less than about 400 degrees Celsius, in a range of about 100 to 400 degrees Celsius, or some other suitable temperature. Depositing (e.g., by CVD, PVD, ALD, etc.) the third high thermal conductivity layer 111c at a low processing temperature (e.g., less than about 400 degrees Celsius) promotes the third high thermal conductivity layer 111c to have a relatively high thermal conductivity (e.g., greater than about 10 W / mK) while preventing damage to the plurality of semiconductor devices 118 (e.g., delamination, device damage, etc.).

[0074] The second dielectric layer 117b is formed on the third high thermal conductivity layer 111c by, for example, a CVD process, a PVD process, an ALD process, or some other suitable deposition or growth process. The second dielectric layer 117b may be, for example, or include an oxide such as silicon dioxide or some other suitable material. In some embodiments, the thermal conductivity of the second dielectric layer 117b is less than about 1 W / mK, and is less than the thermal conductivity of the first high thermal conductivity layer 111a, the second high thermal conductivity layer 111b, and the third high thermal conductivity layer 111c.

[0075] like FIG. 23A to FIG. 23B As shown in the cross-sectional views 2300a and 2300b of , a patterning process is performed on the third high thermal conductivity layer 111c and the second dielectric layer 117b to form a plurality of openings 2302. In some embodiments, the patterning process includes: forming a masking layer (not shown) over the second dielectric layer 117b; performing an etching process (e.g., dry etching, wet etching, etc.) on the third high thermal conductivity layer 111c and the second dielectric layer 117b to define a plurality of openings 2302; and performing a removal process to remove the masking layer.

[0076] like FIG. 24A to FIG. 24B As shown in the cross-sectional views 2400a and 2400b, in the plurality of openings ( FIG. 23A to FIG. 23B 2302) to form a plurality of second conductive vias 128 and a plurality of second conductive wires 126, thereby forming a second interconnect structure 110. In some embodiments, forming the second conductive vias 128 and the conductive wires 126 includes: FIG. 23A to FIG. 23B2302) is deposited (e.g., by CVD, PVD, sputtering, electroplating, etc.) with one or more conductive materials (e.g., titanium nitride, titanium, aluminum, titanium aluminum, molybdenum, ruthenium, etc.); and a planarization process (e.g., CMP process) is performed on the one or more conductive materials. In various embodiments, the second conductive via 128 and the conductive line 126 include a conductive liner layer (e.g., such as FIG. 9A to FIG. 9B In further embodiments, although a single via level and a single line level are shown, the FIG. 23A to FIG. 24B Processing steps are performed to form additional via and / or line levels.

[0077] FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B Shows that it can replace FIG. 19A to FIG. 19B to FIG. 24A to FIG. 24B Various cross-sectional views of some embodiments of the steps of implementing the steps in Figures 11 to 24A to Fig. 24B The method can optionally be changed from Figures 11 to 18A to Fig.18B Enter FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B (i.e., skip FIG. 19A to FIG. 19B to FIG. 24A to FIG. 24B ). In various embodiments, FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B Various cross-sectional views of some other embodiments of forming the second interconnect structure 110 are shown. FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B The cross-sectional views shown in the figure are described with reference to the method, but it should be understood that FIG. 25A to FIG. 25B to FIG. 27A to FIG. 27B The structure shown in is not limited to the method, but can exist independently of the method. In addition, the figures with an "A" suffix show a cross-sectional view taken along the zx plane, and the figures with a "B" suffix show a cross-sectional view taken along the zy plane.

[0078] like FIG. 25A to FIG. 25B As shown in the cross-sectional views 2500a and 2500b of FIG. 1 , a third high thermal conductivity layer 111c is formed on the second high thermal conductivity layer 111b. In various embodiments, the third high thermal conductivity layer 111c is formed by FIG. 18A to FIG. 18BThe third high thermal conductivity layer 111c is formed by the process described in the second high thermal conductivity layer 111b in . For example, the third high thermal conductivity layer 111c is formed by a CVD process, a thermal CVD process, an HPCVD process, a PECVD process, a MWCVD process, a PVD process, a thermal ALD process, a PEALD process, or some other suitable deposition or growth process at a low processing temperature (e.g., less than about 400 degrees Celsius). In some embodiments, the third high thermal conductivity layer 111c may be, for example, or include aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, diamond, another suitable material, or any combination of the above materials. In various embodiments, the third high thermal conductivity layer 111c has a thermal conductivity greater than about 10 W / mK, in a range of about 10 to 2500 W / mK, or some other suitable value. In further embodiments, the third high thermal conductivity layer 111c includes the same material as the first high thermal conductivity layer 111a and / or the second high thermal conductivity layer 111b.

[0079] like FIG. 26A to FIG. 26B As shown in the cross-sectional views 2600a and 2600b of FIG. 1 , a plurality of second conductive contacts 124 are formed above the source / drain regions 122. In addition, a fourth high thermal conductivity layer 111d and a first dielectric layer 117a are formed above the plurality of second conductive contacts 124, thereby forming or defining a second dielectric structure 115. In some embodiments, the plurality of second conductive contacts 124 are formed by FIG. 20A to FIG. 20B to FIG. 21A to FIG. 21B For example, the process for forming the second conductive contact 124 includes: patterning the first high thermal conductivity layer 111a, the second high thermal conductivity layer 111b, and the third high thermal conductivity layer 111c to form an opening above the source / drain region 122; depositing one or more conductive materials in the opening; and performing a planarization process on the one or more conductive materials.

[0080] In some embodiments, the fourth high thermal conductivity layer 111d is formed by FIG. 18A to FIG. 18B The fourth high thermal conductivity layer 111d is formed by the process described for the second high thermal conductivity layer 111b in . In some embodiments, the fourth high thermal conductivity layer 111d may be, for example, or include aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, diamond, another suitable material, or any combination of the foregoing materials. In various embodiments, the fourth high thermal conductivity layer 111d has a thermal conductivity greater than about 10 W / mK, in a range of about 10 to 2500 W / mK, or some other suitable value. In some embodiments, the first dielectric layer 117a is deposited by CVD, PVD, ALD, etc., and includes a dielectric material (e.g., silicon dioxide) having a thermal conductivity less than the thermal conductivity of the fourth high thermal conductivity layer 111d.

[0081] like FIG. 27A to FIG. 27B As shown in the cross-sectional views 2700a and 2700b of FIG. 1 , a plurality of second conductive vias 128 and a plurality of second conductive wires 126 are formed in the fourth high thermal conductivity layer 111d and the first dielectric layer 117a. In some embodiments, the plurality of second conductive vias 128 and the plurality of second conductive wires 126 are formed by passing through the fourth high thermal conductivity layer 111d and the first dielectric layer 117a. FIG. 23A to FIG. 23B to FIG. 24A to FIG. 24B is formed by the process described in .

[0082] Figures 28 to 37A to Fig.37B Various cross-sectional views of some embodiments of methods for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers are shown. Figures 28 to 37A to Fig.37B Although described with respect to methods, it should be understood that the structures disclosed in the methods are not limited to the methods, but can exist independently as structures independent of the methods. Figures 28 to 37A to Fig.37B Described as a series of steps, it should be understood that these steps are not limited, because in other embodiments, the order of the steps can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some of the steps shown and / or described can be omitted in whole or in part. In addition, the figures with an "A" suffix show a cross-sectional view taken along the zx plane, and the figures with a "B" suffix show a cross-sectional view taken along the zy plane.

[0083] like Fig.28 As shown in the cross-sectional view 2800 of FIG. 28 , a base substrate 1102 is provided, and a layer stack 2802 is formed over the base substrate 1102. In some embodiments, the layer stack 2802 includes an etch stop layer 1104 on the base substrate 1102, a lower semiconductor layer 1106 on the etch stop layer 1104, a plurality of first semiconductor layers 1110, and a plurality of second semiconductor layers 1112. The plurality of first semiconductor layers 1110 and the plurality of second semiconductor layers 1112 are alternately stacked with each other. In various embodiments, the plurality of second semiconductor layers 1112 and the lower semiconductor layer 1106 are part of the device layer 108 or define the device layer 108. In various embodiments, the individual layers of the layer stack 2802 can each be formed by one or more growth or deposition processes, such as, for example, a CVD process, a PVD process, an ALD process, an epitaxial process (e.g., MBE, VPE, LPE, etc.), or some other suitable growth or deposition process.

[0084] like Fig.29As shown in the cross-sectional view 2900 of FIG. 1 , a plurality of semiconductor devices 118 are formed over the base substrate 1102, and a first interconnect structure 106 is formed on the front side FS of the semiconductor device 118. In various embodiments, the semiconductor device 118 is a GAA FET, and includes a plurality of semiconductor channels 206, a gate dielectric structure 210, a gate electrode 120, a spacer layer 208, and a source / drain region 122, respectively. In various embodiments, the plurality of semiconductor devices 118 are formed by substantially similar to the above in Fig.12 and Fig.13 The semiconductor channel 206 is formed by the process described in (wherein the patterning process for forming the semiconductor channel 206 is over-etched into the lower semiconductor layer 1106).

[0085] The first interconnect structure 106 includes a plurality of first conductive contacts 113, a plurality of first conductive lines 116, and a plurality of first conductive vias 114 disposed within the first dielectric structure 112. In some embodiments, the conductive structures of the first interconnect structure 106 may each be formed by a damascene process (e.g., a single damascene process or a dual damascene process) or some other suitable process. In further embodiments, the first dielectric structure 112 includes one or more interlayer dielectric (ILD) layers that may each be formed by, for example, CVD, PVD, ALD, or some other suitable growth or deposition process.

[0086] like FIG. 30A to FIG. 30B As shown in the cross-sectional views 3000a and 3000b, the Fig.29 The structure of the carrier substrate 102 is bonded to the first interconnect structure 106, and a thinning process is performed to remove the base substrate ( Fig.29 1102). In some embodiments, bonding the carrier substrate 102 to the first interconnect structure includes: forming an insulating layer 104 on the carrier substrate 102; and bonding the insulating layer 104 to the first interconnect structure 106. In various embodiments, the thinning process includes: Fig.29 1102) performs a mechanical grinding process, a CMP process, an etching process or some other suitable process until the etching stop layer 1104 is reached.

[0087] In addition, if Fig. 30BAs shown in , in some embodiments, the isolation structure 704 is disposed along the sidewalls of the lower semiconductor layer 1106 and the sidewalls of the etch stop layer 1104. In various embodiments, the isolation structure 704 is formed after the patterning process for forming the semiconductor channel 206 (e.g., by CVD, PVD, etc.). In addition, the lower etch stop layer 702 is disposed along the first dielectric structure 112. In some embodiments, the lower etch stop layer 702 is formed after the semiconductor device 118 is formed and before the first interconnect structure 106 is formed (e.g., by CVD, PVD, etc.).

[0088] like FIG. 31A to FIG. 31B As shown in the cross-sectional views 3100a and 3100b of FIG. 1 , a removal process is performed to remove the etch stop layer ( FIG. 30A to FIG. 30B 1104) and at least a portion of the lower semiconductor layer 1106. In some embodiments, the removal process includes: removing the etch stop layer ( FIG. 30A to FIG. 30B 1104) deposits (e.g., by CVD, PVD, etc.) a sacrificial oxide (e.g., silicon dioxide) (not shown); and deposits (e.g., by CVD, PVD, etc.) a sacrificial oxide, an etch stop layer ( FIG. 30A to FIG. 30B A planarization process (eg, a CMP process) is performed on the semiconductor layer 1104 and the lower semiconductor layer 1106. In a further embodiment, the removal process includes performing an etching process (eg, dry etching), a mechanical grinding process, or some other suitable removal process.

[0089] like FIG. 32A to FIG. 32B As shown in cross-sectional views 3200a and 3200b of FIG. 1 , an etching process is performed to remove the lower semiconductor layer ( FIG. 31A to FIG. 31B 1106). In various embodiments, the etching process includes etching the lower semiconductor layer ( FIG. 31A to FIG. 31B 1106) is exposed to a wet etchant, such as, for example, hydrogen peroxide (e.g., H2O2), ammonium hydroxide (e.g., NH4OH), nitric acid (e.g., HNO3), some other suitable etchant, or any combination of the foregoing etchants.

[0090] like FIG. 33A to FIG. 33BAs shown in the cross-sectional views 3300a and 3300b of FIG. 1 , a first high thermal conductivity layer 111a is formed on the back side BS of the semiconductor device 118. In some embodiments, the first high thermal conductivity layer 111a is formed on the semiconductor device 118 by, for example, a CVD process, a thermal CVD process, a HPCVD process, a PECVD process, a MWCVD process, a PVD process, a thermal ALD process, a PEALD process, or some other suitable deposition or growth process. In addition, the first high thermal conductivity layer 111a is formed or deposited at a low processing temperature, such as less than about 400 degrees Celsius, in a range of about 100 to 400 degrees Celsius, or some other suitable temperature. Depositing (e.g., by CVD, PVD, ALD, etc.) the first high thermal conductivity layer 111a at a low processing temperature (e.g., less than about 400 degrees Celsius) promotes the third high thermal conductivity layer 111c to have a relatively high thermal conductivity (e.g., greater than about 10 W / mK) while preventing damage to the plurality of semiconductor devices 118 (e.g., delamination, device damage, etc.).

[0091] In some embodiments, the first high thermal conductivity layer 111a may be, for example, or include aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, diamond, another suitable material, or any combination of the above materials. In various embodiments, the first high thermal conductivity layer 111a has a thermal conductivity greater than about 10 W / mK, in a range of about 10 to 2500 W / mK, or some other suitable value.

[0092] like FIG. 34A to FIG. 34B As shown in the cross-sectional views 3400a and 3400b of , a planarization process (e.g., a CMP process) is performed on the first high thermal conductivity layer 111a, and a first dielectric layer 117a is formed on the first high thermal conductivity layer 111a. In various embodiments, after the planarization process, the top surface of the first high thermal conductivity layer 111a is coplanar with the top surface of the source / drain region 122. In addition, the first dielectric layer 117a is formed on the first high thermal conductivity layer 111a by, for example, a CVD process, a PVD process, an ALD process, or some other suitable deposition or growth process. The first dielectric layer 117a may, for example, be or include an oxide such as silicon dioxide or some other suitable material. In some embodiments, the thermal conductivity of the first dielectric layer 117a is less than about 1 W / mK, and is less than the thermal conductivity of the first high thermal conductivity layer 111a.

[0093] like FIG. 35A to FIG. 35BAs shown in the cross-sectional views 3500a and 3500b of , a patterning process is performed on the first dielectric layer 117a and the first high thermal conductivity layer 111a to form a plurality of openings 3502 above the source / drain regions 122. In some embodiments, the patterning process includes: forming a masking layer (not shown) above the first dielectric layer 117a; performing an etching process (e.g., dry etching, wet etching, etc.) on the first dielectric layer 117a and the first high thermal conductivity layer 111a to define the plurality of openings 3502; and performing a removal process to remove the masking layer.

[0094] like FIG. 36A to FIG. 36B As shown in the cross-sectional views 3600a and 3600b, in the plurality of openings ( FIG. 35A to FIG. 35B In some embodiments, forming the second conductive contact 124 includes: forming a plurality of second conductive contacts 124 in the opening ( FIG. 35A to FIG. 35B 3502) is deposited (e.g., by CVD, PVD, sputtering, electroplating, etc.) with one or more conductive materials (e.g., titanium nitride, titanium, aluminum, titanium aluminum, molybdenum, ruthenium, etc.); and a planarization process (e.g., CMP process) is performed on the one or more conductive materials. In various embodiments, the second conductive contact 124 includes a conductive liner layer (e.g., such as FIG. 9A to FIG. 9B ).

[0095] like FIG. 37A to FIG. 37B As shown in cross-sectional views 3700a and 3700b, a second high thermal conductivity layer 111b and a second dielectric layer 117b are formed over the plurality of second conductive contacts 124, thereby defining a second dielectric structure 115. In addition, a plurality of second conductive vias 128 and a plurality of second conductive lines 126 are formed in the second dielectric structure 115, thereby defining a second interconnect structure 110.

[0096] FIG. 38A to FIG. 38B to FIG. 39A to FIG. 39B Shows that it can replace FIG. 34A to FIG. 34B to FIG. 36A to FIG. 36B Various cross-sectional views of some embodiments of the steps of implementing the steps in Figures 28 to 37A to Fig.37B The method can optionally be changed from Figures 28 to 33A to Fig.33B Enter FIG. 38A to FIG. 38B to FIG. 39A to FIG. 39B , and then from FIG. 39A to FIG. 39B Enter FIG. 37A to FIG. 37B (jump over FIG. 34A to FIG. 34B to FIG. 36A to FIG. 36B ).

[0097] like FIG. 38A to FIG. 38BAs shown in the cross-sectional views 3800a and 3800b of FIG. 1 , a planarization process (e.g., a CMP process) is performed on the first high thermal conductivity layer 111a, and a second high thermal conductivity layer 111b is formed on the first high thermal conductivity layer 111a. In various embodiments, the second high thermal conductivity layer 111b is formed by the above-mentioned FIG. 33A to FIG. 33B In some embodiments, the second high thermal conductivity layer 111b includes the same high thermal conductivity material as the first high thermal conductivity layer 111a. In other embodiments, the second high thermal conductivity layer 111b includes a high thermal conductivity material different from the high thermal conductivity material of the first high thermal conductivity layer 111a.

[0098] like FIG. 39A to FIG. 39B As shown in the cross-sectional views 3900a and 3900b of FIG. 1 , a plurality of second conductive contacts 124 are formed in the first high thermal conductivity layer 111a and the second high thermal conductivity layer 111b. In various embodiments, the plurality of second conductive contacts 124 are formed by FIG. 35A to FIG. 35B to FIG. 36A to FIG. 36B is formed by the process described in .

[0099] Fig.40 A flow chart of some embodiments of a method 4000 for forming an IC structure including an interconnect structure having one or more high thermal conductivity layers is shown. Although the method 4000 is shown and described below as a series of steps or events, it should be understood that the order in which such steps or events are shown should not be interpreted in a limiting sense. For example, some steps may occur in a different order and / or occur simultaneously with other steps or events other than those shown and / or described herein. In addition, not all of the steps shown are necessary to implement one or more aspects or embodiments described herein. In addition, one or more of the steps depicted herein may be performed in one or more separate steps and / or stages.

[0100] In step 4002, a layer stack is formed over a base substrate, the layer stack comprising an etch stop layer over the base substrate, a lower semiconductor layer over the etch stop layer, and a plurality of first semiconductor layers alternately stacked with a plurality of second semiconductor layers over the etch stop layer. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of step 4002 is shown. Fig.28 A cross-sectional view 2800 corresponding to some other embodiments of step 4002 is shown.

[0101] In step 4004, a plurality of semiconductor devices are formed on a base substrate. The semiconductor devices include source / drain regions located on opposite sides of corresponding channel structures and gate structures located above the corresponding channel structures. In some embodiments, the channel structures are formed by patterning a first semiconductor layer and a second semiconductor layer and selectively removing the first semiconductor layer. Fig.12 and Fig.13 Cross-sectional views 1200 and 1300 corresponding to some embodiments of step 4004 are shown. Fig.29 A cross-sectional view 2900 corresponding to some other embodiments of step 4004 is shown.

[0102] In step 4006 , a first interconnect structure is formed on the front side of the plurality of semiconductor devices, wherein the first interconnect structure includes a plurality of first conductive interconnects disposed in a first dielectric structure. Fig.14 A cross-sectional view 1400 corresponding to some embodiments of step 4006 is shown. Fig.29 A cross-sectional view 2900 corresponding to some other embodiments of step 4006 is shown.

[0103] In step 4008, a first interconnect structure is bonded to a carrier substrate. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of step 4008 is shown. FIG. 30A to FIG. 30B Cross-sectional views 3000a - 3000b corresponding to some other embodiments of step 4008 are shown.

[0104] In step 4010, at least portions of a base substrate, an etch stop layer, and a lower semiconductor layer are removed from over backsides of a plurality of semiconductor devices. FIG. 16A to FIG. 16B and FIG. 17A to FIG. 17B Cross-sectional views 1600a-1600b and 1700a-1700b corresponding to some embodiments of step 4010 are shown. FIG. 30A to FIG. 30B and FIG. 31A to FIG. 31B Cross-sectional views 3000a-3000b and 3100a-3100b corresponding to some other embodiments of step 4010 are shown.

[0105] In step 4012, one or more first high thermal conductivity layers are formed on the backside of the plurality of semiconductor devices. In some embodiments, a first dielectric layer is formed on the one or more first high thermal conductivity layers. FIG. 18A to FIG. 18B and FIG. 19A to FIG. 19B Cross-sectional views 1800a-1800b and 1900a-1900b corresponding to some embodiments of step 4012 are shown. FIG. 33A to FIG. 33B and FIG. 34A to FIG. 34B Cross-sectional views 3300a-3300b and 3400a-3400b corresponding to some other embodiments of step 4012 are shown.

[0106] In step 4014, a plurality of electrically conductive contacts are formed in the one or more first high thermal conductivity layers and on the plurality of semiconductor devices. FIG. 20A to FIG. 20B and FIG. 21A to FIG. 21B Cross-sectional views 2000a-2000b and 2100a-2100b corresponding to some embodiments of step 4014 are shown. FIG. 35A to FIG. 35B and FIG. 36A to FIG. 36B Cross-sectional views 3500a-3500b and 3600a-3600b corresponding to some other embodiments of step 4014 are shown.

[0107] In step 4016, a second high thermal conductivity layer is formed over the plurality of electrically conductive contacts, and a second dielectric layer is formed on the second high thermal conductivity layer. FIG. 22A to FIG. 22B Cross-sectional views 2200a - 2200b corresponding to some embodiments of step 4016 are shown. FIG. 37A to FIG. 37B Cross-sectional views 3700a-3700b corresponding to some other embodiments of step 4016 are shown.

[0108] In step 4018, a plurality of conductive vias and a plurality of conductive lines are formed in the second high thermal conductivity layer and the second dielectric layer. FIG. 23A to FIG. 23B and FIG. 24A to FIG. 24B Cross-sectional views 2300a-2300b and 2400a-2400b corresponding to some embodiments of step 4018 are shown. FIG. 37A to FIG. 37B Cross-sectional views 3700a-3700b corresponding to some other embodiments of step 4018 are shown.

[0109] Therefore, an embodiment of the present disclosure relates to an IC structure including a first interconnect structure located on the front side of multiple semiconductor devices and a second interconnect structure located on the back side of the semiconductor devices, wherein the second interconnect structure includes one or more high thermal conductivity layers arranged on the semiconductor devices and configured to increase the heat dissipation performance of the IC structure.

[0110] In some embodiments, embodiments of the present disclosure relate to an integrated circuit (IC) structure. The IC structure includes: a semiconductor device having a front side and a back side opposite to the front side; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a first dielectric structure having a plurality of interlayer dielectric (ILD) layers; and a second dielectric structure located on the back side of the semiconductor device, wherein the second dielectric structure includes a first high thermal conductivity layer having a thermal conductivity greater than that of the ILD layer. In some embodiments, the semiconductor device includes a gate structure disposed between a source / drain region pair, wherein the first high thermal conductivity layer directly contacts the gate structure. In some embodiments, the first high thermal conductivity layer directly contacts opposite sidewalls of independent source / drain regions in the source / drain region pair. In some embodiments, the IC structure further includes: a plurality of conductive contacts disposed in the first high thermal conductivity layer, wherein the conductive contacts are disposed on the source / drain regions. In some embodiments, the first high thermal conductivity layer directly contacts opposite sidewalls of the plurality of conductive contacts. In some embodiments, the second dielectric structure further comprises a first dielectric layer on the first high thermal conductivity layer and a second high thermal conductivity layer on the first dielectric layer, wherein the thermal conductivity of the first dielectric layer is less than the thermal conductivity of the first high thermal conductivity layer and the second high thermal conductivity layer. In some embodiments, the thickness of the first dielectric layer is less than the thickness of the first high thermal conductivity layer. In some embodiments, the thermal conductivity of the first high thermal conductivity layer is greater than or equal to about 10 W / mK. In some embodiments, the first high thermal conductivity layer comprises one or more of aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, and diamond.

[0111] In some embodiments, embodiments of the present disclosure relate to an integrated circuit (IC) structure. The IC structure includes: a semiconductor device having a front side and a back side opposite to the front side, wherein the semiconductor device includes a gate structure located between a source / drain region pair; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a plurality of first conductive interconnects electrically coupled to the semiconductor device and disposed in a first dielectric structure; and a second interconnect structure located on the back side of the semiconductor device, wherein the second interconnect structure includes a plurality of second conductive interconnects disposed in a second dielectric structure, wherein the plurality of second conductive interconnects include a plurality of conductive contacts disposed on and electrically coupled to the source / drain region, wherein the plurality of conductive contacts are disposed in a first high thermal conductivity layer of the second dielectric structure. In some embodiments, the semiconductor device includes a channel structure adjacent to the gate structure and located between the source / drain region pair, wherein the first high thermal conductivity layer directly contacts the gate structure or the channel structure. In some embodiments, the second dielectric structure further includes a dielectric layer located on the first high thermal conductivity layer, wherein the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the dielectric layer. In some embodiments, the first high thermal conductivity layer has a crystal structure different from the crystal structure of the dielectric layer. In some embodiments, the crystal structure of the first high thermal conductivity layer is cubic. In some embodiments, the second dielectric structure further comprises a second high thermal conductivity layer disposed along a bottom surface of the plurality of conductive contacts. In some embodiments, the first dielectric structure comprises an etch stop layer disposed between interlayer dielectric (ILD) layers, wherein the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the etch stop layer.

[0112] In yet other embodiments, embodiments of the present disclosure relate to a method for forming an integrated circuit (IC) structure. The method includes: forming a layer stack above a base substrate, wherein the layer stack includes an etch stop layer located above the base substrate and a lower semiconductor layer located on the etch stop layer; forming a plurality of semiconductor devices on the lower semiconductor layer; forming a first interconnect structure on the front side of the plurality of semiconductor devices, wherein the first interconnect structure includes a plurality of first conductive interconnects disposed in a first dielectric structure; bonding the first interconnect structure to a carrier substrate; removing the base substrate, the etch stop layer, and the lower semiconductor layer from the back side of the plurality of semiconductor devices, wherein the back side is opposite to the front side; and forming a first high thermal conductivity layer on the back side of the plurality of semiconductor devices. In some embodiments, the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the etch stop layer. In some embodiments, the method further includes: forming a plurality of conductive contacts in the first high thermal conductivity layer, wherein the conductive contacts contact the semiconductor devices. In some embodiments, the first high thermal conductivity layer is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD) at a temperature in a range of about 100 to 400 degrees Celsius.

[0113] Some embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor device having a front side and a back side opposite to the front side; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a first dielectric structure having a plurality of interlayer dielectric (ILD) layers; and a second dielectric structure located on the back side of the semiconductor device, wherein the second dielectric structure includes a first high thermal conductivity layer having a thermal conductivity greater than that of the interlayer dielectric layer.

[0114] In some embodiments, the semiconductor device includes a gate structure disposed between a source / drain region pair, wherein the first high thermal conductivity layer directly contacts the gate structure. In some embodiments, the first high thermal conductivity layer directly contacts opposite sidewalls of independent source / drain regions in the source / drain region pair. In some embodiments, the integrated circuit structure further includes: a plurality of conductive contacts disposed in the first high thermal conductivity layer, wherein the conductive contacts are disposed on the source / drain region. In some embodiments, the first high thermal conductivity layer directly contacts opposite sidewalls of the plurality of conductive contacts. In some embodiments, the second dielectric structure further includes a first dielectric layer disposed on the first high thermal conductivity layer and a second high thermal conductivity layer disposed on the first dielectric layer, wherein the thermal conductivity of the first dielectric layer is less than the thermal conductivity of the first high thermal conductivity layer and the second high thermal conductivity layer. In some embodiments, the thickness of the first dielectric layer is less than the thickness of the first high thermal conductivity layer. In some embodiments, the thermal conductivity of the first high thermal conductivity layer is greater than or equal to about 10 W / mK. In some embodiments, the first high thermal conductivity layer includes one or more of aluminum nitride, boron nitride, yttrium oxide, yttrium aluminum garnet, aluminum oxide, beryllium oxide, silicon carbide, graphene, diamond-like carbon, and diamond.

[0115] Some other embodiments of the present application provide an integrated circuit (IC) structure, comprising: a semiconductor device having a front side and a back side opposite to the front side, wherein the semiconductor device includes a gate structure located between a pair of source / drain regions; a first interconnect structure located on the front side of the semiconductor device, wherein the first interconnect structure includes a plurality of first conductive interconnects electrically coupled to the semiconductor device and disposed in a first dielectric structure; and a second interconnect structure located on the back side of the semiconductor device, wherein the second interconnect structure includes a plurality of second conductive interconnects disposed in a second dielectric structure, wherein the plurality of second conductive interconnects include a plurality of conductive contacts disposed on the source / drain regions and electrically coupled to the source / drain regions, wherein the plurality of conductive contacts are disposed in a first high thermal conductivity layer of the second dielectric structure.

[0116] In some embodiments, the semiconductor device includes a channel structure adjacent to the gate structure and located between the source / drain region pair, wherein the first high thermal conductivity layer directly contacts the gate structure or the channel structure. In some embodiments, the second dielectric structure also includes a dielectric layer located on the first high thermal conductivity layer, wherein the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the dielectric layer. In some embodiments, the first high thermal conductivity layer has a crystal structure different from the crystal structure of the dielectric layer. In some embodiments, the crystal structure of the first high thermal conductivity layer is cubic. In some embodiments, the second dielectric structure also includes a second high thermal conductivity layer disposed along the bottom surface of the plurality of conductive contacts. In some embodiments, the first dielectric structure includes an etch stop layer disposed between interlayer dielectric (ILD) layers, wherein the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the etch stop layer.

[0117] Still other embodiments of the present application provide a method for forming an integrated circuit (IC) structure, comprising: forming a layer stack above a base substrate, wherein the layer stack includes an etch stop layer located above the base substrate and a lower semiconductor layer located on the etch stop layer; forming a plurality of semiconductor devices on the lower semiconductor layer; forming a first interconnect structure on the front side of the plurality of semiconductor devices, wherein the first interconnect structure includes a plurality of first conductive interconnects arranged in a first dielectric structure; bonding the first interconnect structure to a carrier substrate; removing the base substrate, the etch stop layer and the lower semiconductor layer from above the back side of the plurality of semiconductor devices, wherein the back side is opposite to the front side; and forming a first high thermal conductivity layer on the back side of the plurality of semiconductor devices.

[0118] In some embodiments, the thermal conductivity of the first high thermal conductivity layer is greater than the thermal conductivity of the etch stop layer. In some embodiments, the method further comprises: forming a plurality of conductive contacts in the first high thermal conductivity layer, wherein the conductive contacts contact the semiconductor device. In some embodiments, the first high thermal conductivity layer is formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD) at a temperature in the range of about 100 to 400 degrees Celsius.

[0119] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. An integrated circuit (IC) structure, comprising: A semiconductor device having a front side and a back side opposite to the front side; a first interconnect structure on the front side of the semiconductor device, wherein the first interconnect structure comprises a first dielectric structure having a plurality of inter-layer dielectric (ILD) layers; and A second dielectric structure is located on the back side of the semiconductor device, wherein the second dielectric structure includes a first high thermal conductivity layer having a thermal conductivity greater than that of the interlayer dielectric layer.

2. The integrated circuit structure according to claim 1, wherein: The semiconductor device includes a gate structure disposed between a pair of source / drain regions, wherein the first high thermal conductivity layer directly contacts the gate structure.

3. The integrated circuit structure according to claim 2, wherein: The first high thermal conductivity layer directly contacts opposite sidewalls of an independent source / drain region in the pair of source / drain regions.

4. The integrated circuit structure according to claim 2, further comprising: A plurality of conductive contacts are disposed in the first high thermal conductivity layer, wherein the conductive contacts are disposed on the source / drain regions.

5. The integrated circuit structure according to claim 4, wherein: The first high thermal conductivity layer directly contacts opposite side walls of the plurality of conductive contacts.

6. The integrated circuit structure according to claim 1, wherein: The second dielectric structure further includes a first dielectric layer on the first high thermal conductivity layer and a second high thermal conductivity layer on the first dielectric layer, wherein thermal conductivity of the first dielectric layer is smaller than thermal conductivity of the first high thermal conductivity layer and the second high thermal conductivity layer.

7. The integrated circuit structure according to claim 6, wherein: The thickness of the first dielectric layer is smaller than the thickness of the first high thermal conductivity layer.

8. The integrated circuit structure according to claim 1, wherein: The thermal conductivity of the first high thermal conductivity layer is greater than or equal to about 10 W / mK.

9. An integrated circuit (IC) structure comprising: A semiconductor device having a front side and a back side opposite the front side, wherein the semiconductor device includes a gate structure located between a source / drain region pair; a first interconnect structure on the front side of the semiconductor device, wherein the first interconnect structure includes a plurality of first conductive interconnects electrically coupled to the semiconductor device and disposed in a first dielectric structure; and a second interconnect structure located on the back side of the semiconductor device, wherein the second interconnect structure comprises a plurality of second conductive interconnects disposed in a second dielectric structure, wherein the plurality of second conductive interconnects comprises a plurality of conductive contacts disposed on and electrically coupled to the source / drain regions, wherein the plurality of conductive contacts are disposed in a first high thermal conductivity layer of the second dielectric structure.

10. A method for forming an integrated circuit (IC) structure, comprising: forming a layer stack over a base substrate, wherein the layer stack comprises an etch stop layer over the base substrate and a lower semiconductor layer over the etch stop layer; forming a plurality of semiconductor devices on the lower semiconductor layer; forming a first interconnect structure on the front sides of the plurality of semiconductor devices, wherein the first interconnect structure comprises a plurality of first conductive interconnects disposed in a first dielectric structure; bonding the first interconnect structure to a carrier substrate; removing the base substrate, the etch stop layer, and the lower semiconductor layer from over a back side of the plurality of semiconductor devices, wherein the back side is opposite to the front side; and A first high thermal conductivity layer is formed on the backside of the plurality of semiconductor devices.

Images