Metal oxide semiconductor transistor and manufacturing method thereof

Abstract

The embodiment of the invention discloses a metal oxide semiconductor transistor and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a source region and a drain region in the substrate; forming a first dielectric structure exposing the drain region and the source region on the substrate, wherein the first dielectric structure comprises a gate dielectric layer located on the substrate and a first dielectric layer located on the gate dielectric layer; forming a gate conductor at a preset position of the gate dielectric layer, wherein the first dielectric layer at least exposes part of the upper surface of the gate conductor; forming a first field plate on the first dielectric layer; and after the first dielectric structure and the first field plate are formed, gate silicide, source silicide and drain silicide are respectively formed on the exposed gate conductor, the source region and the drain region. The first field plate is used as a partial etching barrier layer of the etching process for forming the opening for exposing the source region and the gate conductor, so that the process difficulty of forming the etching barrier layer is reduced.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor devices. More specifically, embodiments of the present invention relate to metal oxide semiconductor transistors and methods for manufacturing metal oxide semiconductors. Background Art

[0002] Power amplifier devices are core devices for power electronic systems to convert electrical energy and control circuits. Laterally diffused metal oxide semiconductor (LDMOS) transistors are widely used as radio frequency power devices because they are more compatible with silicon-based processes and have good frequency characteristics (e.g., high gain, high linearity, high withstand voltage, and high output power). Radio frequency (RF) LDMOS transistors are widely used in high-frequency, very high-frequency, and ultra-high-frequency communications, pulse radars, industrial, scientific and medical applications, avionics, and communication systems. In view of this, a metal oxide semiconductor transistor and a method for manufacturing the same are provided. Summary of the invention

[0003] An embodiment of the present invention provides a method for manufacturing a metal oxide semiconductor transistor. The manufacturing method comprises:

[0004] providing a substrate;

[0005] forming a source region and a drain region in the substrate;

[0006] forming a first dielectric structure on the substrate, wherein the first dielectric structure exposes the drain region and the source region, and the first dielectric structure comprises a gate dielectric layer on the substrate and a first dielectric layer on the gate dielectric layer;

[0007] forming a gate conductor at a predetermined position of the gate dielectric layer, wherein the first dielectric layer at least partially exposes an upper surface of the gate conductor;

[0008] forming a first field plate, wherein the first field plate is located on the first dielectric layer on a side of the gate conductor close to the drain region; and

[0009] After forming the first dielectric structure and the first field plate, a gate silicide, a source silicide and a drain silicide are respectively formed on the exposed gate conductor, the source region and the drain region.

[0010] In some embodiments, the first dielectric layer covers the side surface of the gate conductor and the upper surface of the gate dielectric layer between the gate conductor and the drain region.

[0011] In some embodiments, the method for forming the first dielectric structure includes: forming a gate dielectric material covering the upper surface of the substrate; forming a first dielectric material covering the upper surface of the gate dielectric material, the upper surface of the gate conductor, and the side surface of the gate conductor; after forming the first field plate at a predetermined position on the first dielectric material, forming a first etch barrier layer, the first etch barrier layer extending from above the first field plate to above one side of the first dielectric layer adjacent to the drain region; and etching the first dielectric material and the gate dielectric material using the first etch barrier layer and the first field plate as etch barriers to form the first dielectric structure.

[0012] In some embodiments, the method also includes: forming a drift region and a body region in the substrate, wherein the body region has a first doping type, the drift region has a second doping type, the source region is formed in the body region, and the drain region is formed in the drift region; and forming a body contact region having the first doping type in the body region by ion implantation.

[0013] In some embodiments, providing a base includes: forming an epitaxial layer on a substrate, the substrate and the epitaxial layer have a first doping type, and the resistivity of the silicon epitaxial layer is greater than the resistivity of the silicon substrate.

[0014] In some embodiments, the method further includes: forming a drift region and a body region in the epitaxial layer, wherein the body region has the first doping type, the drift region has the second doping type, the source region is formed in the body region, and the drain region is formed in the drift region; forming a body contact region having the first doping type in the body region by ion implantation; forming a substrate contact region having the first doping type by ion implantation, wherein the substrate contact region extends from at least the upper surface of the epitaxial layer to the upper surface of the substrate, and the body contact region is located between the substrate contact region and the source region.

[0015] In some embodiments, the gate silicide, the source silicide, and the drain silicide have a thickness of 10 nanometers to 100 nanometers.

[0016] In some embodiments, the first dielectric layer includes a silicon oxide layer and a silicon nitride layer.

[0017] In some embodiments, an overlapping length of the first field plate and the gate conductor is less than or equal to 1 / 2 of a length of the gate conductor.

[0018] In some embodiments, the method further includes: forming a second dielectric layer, wherein the second dielectric layer covers the gate silicide, the source silicide, the drain silicide and the gate dielectric layer; forming a second field plate on the second dielectric layer; and forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the second dielectric layer and the second field plate.

[0019] In some embodiments, a first edge of the first etch stop layer is used to define a formation position of the drain silicide, and a second edge is located on the first field plate.

[0020] An embodiment of the present invention further provides a metal oxide semiconductor transistor. The metal oxide semiconductor transistor is manufactured using the above manufacturing method, and the metal oxide semiconductor transistor includes:

[0021] substrate;

[0022] a source region and a drain region located in the substrate;

[0023] a first dielectric structure located on the substrate, the first dielectric structure exposing the drain region and the source region, the first dielectric structure comprising a gate dielectric layer located on the substrate and a first dielectric layer located on a portion of the gate dielectric layer;

[0024] A gate conductor located at a predetermined position of the gate dielectric layer, wherein the first dielectric layer covers a side surface of the gate conductor and exposes at least a portion of an upper surface of the gate conductor;

[0025] a first field plate located on the first dielectric layer; and

[0026] A gate silicide, a source silicide and a drain silicide are respectively located on the gate conductor, the source region and the drain region.

[0027] According to the manufacturing method of the metal oxide semiconductor transistor of the embodiment of the present invention, the first etch barrier layer and the first field plate are used as the etch barrier layer, and the gate dielectric material and the first dielectric material are etched to form the first dielectric structure to expose the gate conductor, the source region and the drain region, and then the gate silicide, the source silicide and the drain silicide are simultaneously formed by depositing metal and silicide reaction. The difficulty of overlaying the first etch barrier layer is reduced. The preparation of the silicide is effectively combined with the preparation of the field plate, which simplifies the process steps and reduces the process cost. The first dielectric layer forms side walls on both sides of the gate conductor, and the metal and the side walls do not undergo silicide reaction. After the silicide reaction, the unreacted metal on the first dielectric layer and the first field plate is removed, and the gate silicide and the source silicide are automatically disconnected, further reducing the source contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0029] Figure 1 is a flow chart of a method for manufacturing a metal oxide semiconductor transistor according to an embodiment of the present invention;

[0030] Figure 2 is a structural diagram of an LDMOS transistor according to an embodiment of the present invention;

[0031] Figure 3 is a structural diagram of an LDMOS transistor according to another embodiment of the present invention;

[0032] Figure 4 is a structural diagram of an LDMOS transistor according to yet another embodiment of the present invention;

[0033] Figures 5 to 20 is a cross-sectional view or a top view at various stages of a method for manufacturing an LDMOS transistor according to an embodiment of the present invention; and

[0034] Figure 21-24 are cross-sectional views of various stages of a method for manufacturing an LDMOS transistor in a comparative example.

[0035] Description of reference numerals:

[0036] 100, silicon substrate; 101, epitaxial layer; 102, field oxide layer; 103, substrate contact region;

[0037] 104, body region; 105, drift region; 106, body contact region; 107, source region;

[0038] 108, drain region; 109, gate conductor; 110, source metal silicide;

[0039] 111, drain metal silicide; 112, gate metal silicide;

[0040] 113, a first dielectric layer; 114, a gate dielectric layer; 115, a first field plate;

[0041] 116, a first interlayer dielectric layer; 117, a second interlayer dielectric layer; 118, a passivation layer;

[0042] 119, a second dielectric layer; 120, a second field plate; DETAILED DESCRIPTION

[0043] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0044] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0045] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0046] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0047] The present application relates to a metal oxide transistor and a manufacturing method thereof. The metal oxide transistor is, for example, an LDMOS transistor, and specifically may be a radio frequency LDMOS transistor.

[0048] The metal oxide transistor comprises: a substrate; a source region and a drain region located in the substrate; a first dielectric structure located on the substrate, the first dielectric structure exposing the drain region and the source region, the first dielectric structure comprising a gate dielectric layer located on the substrate and a first dielectric layer located on part of the gate dielectric layer; a gate conductor located at a predetermined position of the gate dielectric layer, the first dielectric layer covering the side surface of the gate conductor and exposing at least part of the upper surface of the gate conductor; a first field plate located on the first dielectric layer; and a gate silicide, a source silicide and a drain silicide respectively located on the gate conductor, the source region and the drain region.

[0049] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a metal oxide semiconductor transistor according to an embodiment of the present invention. Figure 1 As shown, the manufacturing method includes the following steps.

[0050] Step S101, providing a substrate. The substrate includes, for example, a substrate and an epitaxial layer located on the substrate. The substrate and the epitaxial layer have a first doping type, and the resistivity of the epitaxial layer is greater than the resistivity of the substrate. In this embodiment, the substrate is made of silicon material, the substrate is a silicon substrate, and the epitaxial layer is a silicon epitaxial layer. In other embodiments, silicon carbide, gallium nitride, etc. may also be selected, which is not limited here.

[0051] Step S103, forming a source region and a drain region in the substrate.

[0052] In some embodiments, the manufacturing method further includes: forming a drift region and a body region on the substrate, wherein the body region has a first doping type, the drift region has a second doping type, the source region is formed in the body region, and the drain region is formed in the drift region. The source region and the drain region are specifically of the second doping type. The first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping. In some embodiments, the drift region and the body region are formed in an epitaxial layer.

[0053] In some embodiments, the manufacturing method also includes: forming a substrate contact region having the first doping type by ion implantation, wherein the substrate contact region extends at least from the upper edge of the epitaxial layer to the upper surface of the substrate, and further, the bottom surface of the substrate contact region is located in the substrate.

[0054] In some embodiments, the method further includes: forming a body contact region having the first doping type in the body region by ion implantation, wherein the body contact region is located between the substrate contact region and the source region.

[0055] Step S105, forming a first dielectric structure on the substrate. The first dielectric structure exposes the drain region and the source region, and the first dielectric structure includes a gate dielectric layer located on the substrate and a first dielectric layer located on the gate dielectric layer. The first dielectric layer includes, for example, a stacked structure of a silicon oxide layer and a silicon nitride layer, or a single-layer structure of silicon nitride. The gate dielectric layer includes, for example, a silicon oxide layer.

[0056] Step S107, forming a gate conductor at a predetermined position of the gate dielectric layer, wherein the first dielectric layer at least exposes a portion of the upper surface of the gate conductor. Specifically, the upper surface of the entire gate conductor is not covered by the first dielectric layer, and the gate conductor and the first dielectric layer are in contact but do not overlap; or, the first dielectric layer covers a portion of the upper surface of the gate conductor, and the first dielectric layer and the gate conductor overlap.

[0057] In some embodiments, the first dielectric layer covers the side surface of the gate conductor and the upper surface of the gate dielectric layer between the gate conductor and the drain region. The gate conductor may be, for example, polysilicon.

[0058] Step S109, forming a first field plate. The first field plate is located on the first dielectric layer on the side of the gate conductor close to the drain region. From a top view, the first field plate may not overlap with the gate conductor, or the first field plate may overlap with the gate conductor, but the overlapping length is less than or equal to 1 / 2 of the length of the gate conductor.

[0059] In some embodiments, the first dielectric structure is formed by the following method: forming a gate dielectric material covering the upper surface of the substrate; forming a first dielectric material covering the upper surface of the gate dielectric material, the upper surface of the gate conductor, and the side surface of the gate conductor; after forming the first field plate at a predetermined position on the first dielectric material, forming a first etch barrier layer, the first etch barrier layer extending from above the first field plate to above one side of the first dielectric layer adjacent to the drain region; and etching the first dielectric material and the gate dielectric material with the first etch barrier layer and the first field plate as etch barriers to form the first dielectric structure. The first edge of the first etch barrier layer is used to define the formation position of the drain silicide, and the second edge is located on the first field plate. The gate dielectric material is, for example, silicon oxide, which is formed by a dry oxygen oxidation process.

[0060] Step S111 : after forming the first dielectric structure and the first field plate, forming a gate silicide, a source silicide and a drain silicide on the exposed gate conductor, the source region and the drain region respectively.

[0061] In some embodiments, the gate silicide, the source silicide, and the drain silicide have a thickness of 10 nanometers to 100 nanometers.

[0062] In some embodiments, the method of forming gate silicide, source silicide and drain silicide includes: depositing metal, annealing, and removing unreacted metal, wherein the metal includes: one or more of titanium, nickel, cobalt and platinum.

[0063] In some embodiments, the manufacturing method also includes: forming a second dielectric layer, wherein the second dielectric layer covers the gate silicide, the source silicide, the drain silicide and the gate dielectric layer; forming a second field plate on the second dielectric layer; and forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the second dielectric layer and the second field plate.

[0064] Figure 2 is a structural diagram of an LDMOS transistor according to an embodiment of the present invention. Figure 2As shown, the LDMOS transistor includes: a silicon substrate 100, an epitaxial layer 101 located on the silicon substrate 100, and a field oxide layer 102 formed on the epitaxial layer 101 by a wet oxygen process, wherein the field oxide layer 102 is used to define the active region of the LDMOS transistor, and is formed in the body region 104 and the drift region 105 of the epitaxial layer 101. The LDMOS transistor also includes a source region 107 located in the body region 104 and a drain region 108 located in the drift region 105. The LDMOS transistor also includes a gate conductor 109 located on the gate dielectric layer 114 and a gate metal silicide 112 located on the gate conductor 109. The LDMOS transistor also includes a source metal silicide 110 covering the upper surfaces of the source region 107, the body contact region 106 and the substrate contact region 103, and also includes a drain metal silicide 111 covering the upper surface of the drain region 108. The LDMOS transistor further includes a first dielectric structure, wherein the first dielectric structure includes a gate dielectric layer 114 and a first dielectric layer 113 located on the gate dielectric layer 114. The LDMOS transistor further includes a first field plate 115 located on the upper surface of the first dielectric layer 113 between the gate conductor 109 and the drain region 108. The first dielectric layer covers the side surface of the gate conductor 109 and exposes at least a portion of the upper surface of the gate conductor 109.

[0065] Specifically, the silicon substrate 100, the epitaxial layer 101 and the body region 104 have a first doping type, and the drift region 105, the source region 107 and the drain region 108 have a second doping type. The first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping. The embodiment of the present invention is described by taking the first doping type as P-type doping and the second doping type as N-type doping as an example. The silicon substrate 100 is, for example, a P-type silicon substrate, the epitaxial layer 101 is, for example, a P-type doped silicon epitaxial layer, the body region 104 is P-type doped, and the drift region 105, the source region 107 and the drain region 108 are N-type doped. The resistivity of the silicon substrate 100 is lower than the resistivity of the epitaxial layer 101. The thickness of the silicon substrate 100 is, for example, 100 microns, and the thickness of the epitaxial layer 101 is, for example, 5 microns. In an alternative embodiment, the silicon substrate 100 may be a silicon on insulator (SOI) substrate. The doping concentrations of the source region 107 and the drain region 108 are greater than the doping concentration of the drift region 105 .

[0066] The gate conductor 109 has a second doping type and a thickness of, for example, 300 nanometers. The gate conductor 109 is, for example, polysilicon. A portion of the first dielectric layer 113 serves as a sidewall of the gate conductor 109. The body region 104 and the drift region 105 may or may not be in contact. The gate dielectric layer 114 is, for example, silicon oxide, silicon nitride, etc.

[0067] The source metal silicide 110 , the drain metal silicide 111 , and the gate metal silicide 112 are, for example, nickel silicon, cobalt silicon, titanium silicon, platinum silicon, tungsten silicon, nickel platinum silicon, etc.

[0068] Field plate (FP), also known as Faraday shielding, is an existing technology in the field of power devices. Its principle is as follows: in the area near the PN junction (body region 104 and drift region 105), electric field lines enter the field plate through the surface of the device, which is similar to adding additional charges on the surface of the device. The electric field generated by the additional charges can weaken the electric field strength near the PN junction, thereby increasing the withstand voltage of the device. The material of the first field plate 115 is, for example, tungsten, and the first dielectric layer 113 includes, for example, a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer is, for example, 20 nanometers, and the thickness of the silicon nitride layer is, for example, 150 nanometers. The first field plate 115 can also be doped polysilicon. The first field plate 115 overlaps with the drift region 105.

[0069] The field oxide layer 102 is used to define the active region of the LDMOS transistor. The active region of the LDMOS transistor includes a body region 104, a drift region 105, a source region 107 and a drain region 108. In an alternative embodiment, a shallow trench isolation (STI) method is used to define the active region.

[0070] The LDMOS transistor further includes a substrate contact (Sinker) region 103. The substrate contact region 103 has a first doping type, and the bottom surface of the substrate contact region 103 extends at least to the upper surface of the substrate, and further, is located in the silicon substrate 100. The substrate contact region 103 connects the source region 107 to the silicon substrate 100, thereby reducing the parasitic inductance of the source end. The LDMOS transistor further includes a body contact region 106. The body contact region 106 is formed in the body region 104. The body contact region 106 is electrically connected to the source region 107. The body contact region 106 may be in contact with the source region 107, or may not be in contact with the source region 107. In some embodiments, the body contact region 106 is located between the substrate contact region 103 and the source region 107.

[0071] Figure 3 FIG. 1 is a structural diagram of an LDMOS transistor according to another embodiment of the present invention. Figure 3As shown, the LDMOS transistor also includes a second dielectric layer 119 and a second field plate 120. The present application does not limit the number of field plates. The material of the second field plate 120 is, for example, the same as that of the first field plate 115. The material of the second dielectric layer 119 is, for example, silicon nitride, or silicon oxide, or a stack of silicon oxide and silicon nitride. The second dielectric layer 119 covers the gate silicide 112, the source silicide 110, the drain silicide 111 and the gate dielectric layer 114. The second field plate 120 is located above the second dielectric layer 119. From a top-down perspective, the second field plate 120 is located between the first field plate 115 and the drain region 108. In the vertical direction, the second field plate 120 overlaps with the first field plate 115.

[0072] Figure 4 FIG. 1 is a structural diagram of an LDMOS transistor according to another embodiment of the present invention. Figure 4 As shown, the LDMOS transistor further includes: a first interlayer dielectric layer 116, a second interlayer dielectric layer 117, a passivation layer 118, a first metal layer M1, and a second metal layer M2. The first interlayer dielectric layer 116 covers the source metal silicide 110, the drain metal silicide 111, the gate metal silicide 112, the first field plate 115, and the field oxide layer 102. The first metal layer M1 is formed on the first interlayer dielectric layer 116. The second interlayer dielectric layer 117 covers the first metal layer M1. The second metal layer M2 is formed on the second interlayer dielectric layer 117, and the passivation layer 118 covers the second metal layer M2. The source metal silicide 110 is connected to the corresponding signal line in the first metal layer M1 through a conductive via located in the first interlayer dielectric layer 116, and the drain metal silicide 111 is connected to the corresponding signal line in the first metal layer M1 through a conductive via located in the first interlayer dielectric layer 116. The first metal layer M1 is connected to the second metal layer M2 through a conductive via located in the second interlayer dielectric layer 117. The gate metal silicide 112 is connected to the corresponding signal line in the first metal layer M1 through a conductive via located in the first interlayer dielectric layer 116. Generally, a chip contains multiple LDMOS transistors and other components. The first metal layer M1 and the second metal layer M2 are used for interconnection between these transistors and other components, and can also reduce the resistance of the signal line.

[0073] It should be noted that the interlayer dielectric layer may also include an interlayer dielectric layer and a corresponding metal layer, or a structure of more than two interlayer dielectric layers and a corresponding metal layer.

[0074] The present application provides a method for manufacturing an LDMOS transistor. Figure 5-Figure 17 1 is a cross-sectional view of various stages of a method for manufacturing an LDMOS transistor according to an embodiment of the present invention. The method for manufacturing an LDMOS transistor includes the following steps.

[0075] Step S1, providing a substrate. The substrate has a first doping type. The substrate, for example, includes a silicon substrate 100 and a silicon epitaxial layer 101 formed on the silicon substrate 100. Figure 5 As shown, a P-type silicon epitaxial layer 101 is formed on a P-type silicon substrate 100. The thickness of the silicon substrate 100 is, for example, 100 microns, and the thickness of the silicon epitaxial layer 101 is 5 microns. The resistivity of the silicon epitaxial layer 101 is greater than the resistivity of the silicon substrate 100. The method for forming the silicon epitaxial layer 101 includes, for example: forming a single crystal silicon layer on a silicon substrate by an epitaxial process, performing ion implantation on the single crystal silicon layer, and annealing activation. In an alternative embodiment, in-situ doping is performed during the epitaxial process to form the silicon epitaxial layer 101.

[0076] In some embodiments, the silicon substrate 100 or the silicon substrate 100 and the silicon epitaxial layer 101 may be replaced by an SOI substrate.

[0077] Step S2, forming a substrate contact region 103. Figure 6 As shown, the bottom surface of the substrate contact region 103 is located in the silicon substrate 100. The substrate contact region 103 has a first doping type. The substrate contact region 103 introduces the source of the LDMOS transistor to the back of the substrate 100 to reduce the source terminal parasitic inductance. The substrate contact region 103 is formed by ion implantation, and the implanted ions are, for example, boron (B) ions, and then interconnected with the silicon substrate 100 by high temperature junction activation.

[0078] Step S3, forming a field oxide layer 102 for defining the active region of the LDMOS transistor. The cross-sectional view of the device after forming the field oxide layer 102 is as follows: Figure 7 As shown. The field oxide layer 102 is also called Local Oxidation of Silicon. The field oxide layer 102 is implemented by, for example, a wet oxidation process and has a thickness of 450 nanometers. In some embodiments, the field oxide layer 102 can be replaced by STI.

[0079] Step S4, forming a gate dielectric material 1140 on the substrate. The device cross-sectional view after forming the gate dielectric material 1140 is as follows: Figure 8 As shown. The quality of the gate dielectric material 1140 plays a vital role in the characteristics of the LDMOS. The gate dielectric material 1140 is, for example, silicon oxide, silicon nitride, or a high dielectric constant material. In an exemplary embodiment, the gate dielectric material 1140 is silicon oxide, formed by a dry oxidation process, and has a thickness of, for example, 30 nanometers.

[0080] Step S5, forming a gate conductor 109 on the gate dielectric material 1140. The gate conductor 109 is formed at a predetermined position on the gate dielectric material 1140. The gate conductor 109 is, for example, polysilicon having a second doping type, such as N-doped polysilicon. The thickness of the gate conductor 109 is, for example, 300 nanometers. The gate conductor 109 is formed by a deposition process. The deposition process includes, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), epitaxy, atomic layer deposition (ALD), etc. The cross-sectional view of the device after the gate conductor 109 is formed is shown in FIG. Fig. 9 shown.

[0081] Step S6, forming a drift region 105 and a body region 104 on the substrate. The body region 104 has a first doping type, and the drift region 105 has a second doping type. For example, the body region 104 is P-type doped, and the drift region 105 is N-type doped. The drift region 105 and the body region 104 are formed by ion implantation and annealing activation. The implanted ions of the drift region 105 are, for example, phosphorus (P) ions. After the ion implantation, the drift region 105 is formed by annealing activation. The implanted ions of the body region 104 are, for example, boron (B) ions. After the ion implantation, the body region 104 is formed by annealing activation. The drift region 105 can be formed first, and then the body region 104, or the body region 104 can be formed first, and then the drift region 105 can be formed. After the ion implantation process of the drift region 105 and the body region 104 is completed, annealing can be performed simultaneously. The cross-sectional view of the device after the drift region 105 and the body region 104 are formed is shown as follows. Fig.10 shown.

[0082] The threshold voltage of the LDMOS transistor can be adjusted by the doping concentration of the body region 104, so that the threshold voltage of the LDMOS transistor is a target value. The body region 104 and the drift region 105 jointly limit the electric field strength of the gate close to the drain, thereby controlling the hot carrier effect and improving the device reliability.

[0083] In some embodiments, the drift region 105 and the body region 104 are ion implanted by a gate self-aligned process.

[0084] Step S7, forming a source region 107 in the body region 104, and forming a drain region 108 in the drift region 105. The cross-sectional view of the device after forming the source region 107 and the drain region 108 is as follows: Fig.11As shown. The source region 107 and the drain region 108 have a second doping type and can be formed simultaneously by ion implantation and annealing activation. The source region 107 and the drain region 108 are, for example, N-type doping. The implanted ions of the source region 107 and the drain region 108 are, for example, arsenic (As) ions, which are formed by high temperature activation after ion implantation.

[0085] In some embodiments, the LDMOS transistor further includes a body contact region, and step S7 further includes forming a body contact region 106. The body contact region 106 has the same doping type as the body region 104, and has a higher doping concentration than the body region 104. The implanted ions of the body contact region 106 are, for example, boron ions, which are implanted and activated at high temperature to form the body contact region 106. The body contact region 106 may or may not be in contact with the source region 107. In some embodiments, the body contact region 106 is located between the substrate contact region 103 and the source region 107.

[0086] Step S8, forming a first dielectric material 1130 on the gate dielectric material 1140 and the gate conductor 109. The first dielectric material 1130 covers the upper surface of the gate dielectric material 1140, the upper surface of the gate conductor 109, and the side surface of the gate conductor 109. The first dielectric material 1130 is formed, for example, by a deposition process, such as CVD or PVD. In some embodiments, the gate dielectric material 1140 is a silicon oxide layer, and the first dielectric material 1130 includes a silicon oxide layer and a silicon nitride layer. The thickness of the silicon oxide layer of the first dielectric material 1130 is, for example, 20 nanometers, and the thickness of the silicon nitride layer is, for example, 150 nanometers. The silicon oxide layer is used to relieve the stress on the silicon nitride layer.

[0087] Step S9, forming a first field plate 115 on the first dielectric material 1130. The first field plate 115 is formed on the first dielectric material 1130 on the side of the gate conductor 109 close to the drain region 108. The material of the first field plate 115 is, for example, tungsten, aluminum, titanium, titanium nitride, etc. In some embodiments, the first field plate material is first deposited on the first dielectric material 1130, and then the first field plate 115 is formed by etching. The cross-sectional view of the device after the first dielectric material 1130 and the first field plate 115 are formed is shown in FIG. Fig.12 shown.

[0088] Step S10, forming a first etching stop layer 131 by using a mask. The first etching stop layer 131 is, for example, a photoresist. Fig.13As shown in FIG. 1 , a photoresist 1310 is coated on the entire surface of the device, and the photoresist 1310 is exposed through a mask (the area blocked by the mask is an unexposed area, i.e., the target setting area of ​​the first etch stop layer 131), and then the photoresist at other positions is removed by development, and the photoresist in the target area is retained as the first etch stop layer 131. The cross-sectional view of the device after the first etch stop layer 131 is formed is shown in FIG. Fig.14 The first etch stop layer 131 extends from above the first field plate 151 to above the first dielectric material 1130 near the drain region 108 .

[0089] The range of the first etching stop layer 131 is defined by a mask. Fig.13 and Fig.14 As shown, the first edge L1 of the mask defines the first edge L1 of the first etch stop layer 131, and the second edge L2 of the mask defines the second edge L2 of the first etch stop layer 131. The first etch stop layer 131 defines the formation position of the drain silicide. The first edge L1 of the etch stop layer 131 is used to define the formation position of the drain silicide, and the second edge L2 is located on the first field plate. The above description is based on the example of positive photoresist.

[0090] The first etch stop layer 131 may also be other materials. The etching process in step S11 can etch the first dielectric material 1130 and the gate dielectric material 1140, but will not etch the first etch stop layer 131. The first etch stop layer 131 of non-photoresist material can be formed by the following method. Form an etch stop layer material on the entire surface; form a photoresist on the etch stop layer material; expose the photoresist through a mask, develop the exposed photoresist, and retain the photoresist at a predetermined position; use the photoresist as a barrier layer, etch the etch stop layer material, and form the first etch stop layer 131.

[0091] In some embodiments, the material of the first etch stop layer 131 and the material of the first field plate 115 are different.

[0092] Fig.13 and Fig.15 It shows the setting position of the mask during the exposure process. Fig.13 is a cross-sectional view, Fig.15 FIG. 1 is a top view of the gate conductor 109, the first field plate 115, the drain region 108 and the mask. Fig.15In the figure, the dotted line is the first field plate 115. During the exposure process, the photoresist in the target area is shielded by the mask. The first edge L1 of the mask is used to define the boundary of the drain silicide. The first field plate 115 and the first etch stop layer 131 together serve as etch stops for the first dielectric material 1130 and the gate dielectric material 1140. Therefore, the second edge L2 of the mask does not need to be aligned with the boundary of the gate conductor 109, and the second edge L2 of the mask can overlap with the first field plate 115. That is, the projection of the mask overlaps with the projection of the first field plate 115. A portion of the first field plate 115 is covered by the etch stop layer 131. As shown in FIG. Fig.13 and 15 As shown, the area of ​​the first field plate 115 not covered by the etching stop layer 131 is 1151 (that is, the area of ​​the first field plate 115 not covered by the mask is 1151), the area where the first field plate 115 and the gate conductor 109 overlap is 1152, and the length of the overlapping area is L. The overlapping length L of the first field plate 115 and the gate conductor 109 is less than or equal to 1 / 2 of the length L109 of the gate conductor 109. In the area of ​​the gate conductor 109 blocked by the first field plate 115, metal cannot be deposited in step S12, and silicide cannot be formed. This area cannot be too large.

[0093] In the present application, the boundary of the gate silicide 112 is defined by the first field plate 115, and the second edge L2 of the mask overlaps with the first field plate 115 and does not need to be aligned with the gate conductor 109. This reduces the alignment accuracy requirement of the second edge L2 of the mask and reduces the difficulty of overlay.

[0094] Step S11, using the first field plate 115 and the first etch stop layer 131 as an etch stop layer, etching the first dielectric material 1130 and the gate dielectric material 1140 to form a first dielectric layer 113 and a gate dielectric layer 114, that is, forming a first dielectric structure. The first dielectric structure exposes the source region 107 and the drain region 108, as well as the upper surface of the gate conductor 109.

[0095] The first field plate 115 is reused as an etching stopper for the first dielectric material 1130 and the gate dielectric material 1140. The etching process of the first dielectric material 1130 and the gate dielectric material 1140 is, for example, reactive ion etching (RIE). After the first dielectric structure is formed, the etching stopper 131 is removed, and the device cross-sectional view obtained is as shown in FIG. Fig.16 As shown. Fig.16 As shown, on the side of the gate conductor 109 close to the source region 107 , the first dielectric material 1130 is not completely etched away, and the remaining first dielectric material 1130 forms a sidewall spacer 1131 .

[0096] Step S12, depositing metal 121. Metal 121 includes, for example, one or more of titanium, nickel, cobalt, and platinum. The cross-sectional view of the device after depositing metal 121 is as follows: Fig.17 The deposition process includes, for example, PVD, CVD, etc.

[0097] Step S13, forming gate silicide 112, source silicide 110 and drain silicide 111. At high temperature (e.g., 300°C-500°C), metal 121 undergoes silicide reaction with silicon in gate conductor 109, source region 107 and drain region 108 to generate metal silicide. High temperature processes are, for example, rapid thermal processing (RTP), laser annealing, etc. The metal located on the first field plate 115 and the first dielectric layer 113 does not undergo silicide reaction in the high temperature process. That is, unreacted metal remains on the first field plate 115 and the first dielectric layer 113 (including the sidewall 1131), and these metals will electrically connect the gate silicide 112, the source silicide 110 and the drain silicide 111. After the gate silicide 112, the source silicide 110 and the drain silicide 111 are formed, the unreacted metal can be removed by wet etching. In this way, the connection between the gate silicide 112, the source silicide 110 and the drain silicide 111 is disconnected. Fig.18 The LDMOS transistor, that is Figure 2 LDMOS transistor shown.

[0098] In some embodiments, the first dielectric layer 113 and the gate dielectric layer 114 further expose the body contact region 106 and the substrate contact region 103 (eg, Fig.16 ), metal 121 is also deposited on the body contact region 106 and the substrate contact region 103 (as shown in Fig.17 As shown), the metal 121 and the body contact region 106 react to form silicide in a high temperature process, and the metal 121 and the substrate contact region 103 react to form silicide in a high temperature process.

[0099] Reference Figures 13 to 15, for the metal located on the region 1152 where the first field plate 115 and the gate conductor 109 overlap, these metals and the gate conductor 109 are separated by the first field plate 115, do not contact the gate conductor 109, and do not undergo silicidation reaction, so the area of ​​the gate silicide 112 is smaller than the area of ​​the gate conductor 109. The larger the overlapping region 1152, the smaller the area of ​​the gate silicide 112, and the larger the gate resistance. In the present application, the overlapping length L of the first field plate 115 and the gate conductor 109 is less than or equal to 1 / 2 of the length L109 of the gate conductor 109. That is, the manufacturing method of the LDMOS transistor of the present application does not require the boundary of the first field plate 115 and the gate conductor 109 to be aligned (overlap length L=0), which reduces the difficulty of overlaying of the photolithography process in the process of forming the first field plate 115.

[0100] In the present application, the first field plate 115 is formed first, and then the gate silicide 112, the source silicide 110, and the drain silicide 111 are formed. The boundary of the gate silicide 112 is defined by the first field plate 115, which reduces the difficulty of aligning the first etch stop layer 131.

[0101] In some embodiments, the manufacturing method of the LDMOS transistor also includes: forming a second dielectric layer, the second dielectric layer covers the gate silicide 112, the source silicide 110, the drain silicide 111 and the gate dielectric layer; forming a second field plate on the second dielectric layer; and forming an interlayer dielectric layer, the interlayer dielectric layer covers the second dielectric layer and the second field plate.

[0102] Figure 21-24 1 is a cross-sectional view of each stage of a comparative manufacturing method of an LDMOS transistor. In the comparative method, after forming the source region 107 and the drain region 108 in step S7, a gate conductor 109 is formed. Thereafter, a gate silicide 112 is formed by metal deposition and silicide reaction, and the unreacted metal is removed. An etching stop layer 141 is formed on the entire surface of the device, and the cross-section of the device is as follows: Fig.21 The etch barrier layer 141 and the gate dielectric layer 114 on the source region and the drain region are removed by mask, photolithography and etching to expose the source region 107 and the drain region 108. The cross section of the device is shown in FIG. Fig. 22 Metal is deposited, and a high temperature is provided to cause the silicon and metal in the source region 107 and the drain region 108 to undergo a silicidation reaction to generate source silicide 110 and drain silicide 111, and the unreacted metal is removed. The cross section of the device is as shown in FIG. Fig.23 The etching stop layer 141 is removed. The first dielectric layer 113 is deposited, and the first field plate 151 is formed. The cross section of the device is shown in FIG. Fig.24 shown.

[0103] In the comparative method, the gate silicide is first formed, then the source silicide 110 and the drain silicide 111 are formed, and then the first field plate 151 is formed. That is, the gate silicide, the source silicide 110 and the drain silicide 111 are formed in two steps, and the silicide is formed first, and then the first field plate 151 is formed. In the comparative method, the formation of the gate silicide requires a mask and a photolithography, and requires a high overlay accuracy; the formation of the source silicide 110 and the drain silicide 111 requires a mask and a photolithography; the formation of the first field plate 115 also requires a mask and a photolithography. In the present application provided Figure 5-Figure 20 In the method shown, forming the first field plate 115 requires a mask ( Fig.12 ); forming the source silicide 110, the drain silicide 111 and the gate silicide 112 requires a mask ( Fig.13 ).and Figure 21-24 Compared with the manufacturing method, Figure 5-Figure 20 The method shown reduces the number of photolithography times and masks, saves steps, and reduces process difficulty.

[0104] In some embodiments, the method for manufacturing the LDMOS transistor further includes the following steps.

[0105] Step S14, depositing a first interlayer dielectric layer 116, and planarizing the upper surface of the first interlayer dielectric layer 116. The material of the first interlayer dielectric layer 116 is, for example, silicon oxide, and the upper surface of the first interlayer dielectric layer 116 is planarized by chemical mechanical polishing (CMP). The thickness of the planarized first interlayer dielectric layer 116 is, for example, 3 microns.

[0106] Step S15, a through hole is formed by etching to penetrate the first interlayer dielectric layer 116, and filled with metal. The metal is, for example, tungsten. Conductive through holes are formed above the gate silicide 112, the source silicide 110, the drain silicide 111, and the first field plate 115, respectively, for the external connection of the gate silicide 112, the source silicide 110, the drain silicide 111, and the first field plate 115. When the metal in the conductive through hole is in direct contact with silicon, there is a large contact resistance between the two. The metal-metal silicide-silicon structure can reduce the contact resistance. Step S16, deposit a first metal layer M1, and pattern the first metal layer M1. The material of the first metal layer M1 is, for example, aluminum copper (AlCu), and the deposition thickness is, for example, 3 microns. The patterned first metal layer M1 is used for the interconnection of the gate silicide 112, the source silicide 110, the drain silicide 111, and the first field plate 115 with the corresponding structure. The cross section of the device obtained after step S16 is as follows: Fig.19As shown. The source region 107 and the body contact region 106 of the LDMOS transistor are electrically connected to the first metal layer M1 through a conductive via. Metal silicide is also formed on the body contact region 106, the substrate contact region 103, and a part of the body region 104, and the source region 107 and the substrate contact region 103 are electrically connected through the metal silicide. In this way, the source of the LDMOS transistor is introduced to the back side of the substrate 100.

[0107] Step S17, depositing a second interlayer dielectric layer 117, and planarizing the upper surface of the second interlayer dielectric layer 117. The material of the second interlayer dielectric layer 117 is, for example, silicon oxide, and the upper surface of the second interlayer dielectric layer 117 is planarized by CMP. The thickness of the planarized second interlayer dielectric layer 117 is, for example, 3 microns.

[0108] Step S18, forming a through hole penetrating the second interlayer dielectric layer 117 by etching, and filling it with metal. The metal is, for example, tungsten. The conductive through hole is connected to the gate silicide 112, the source silicide 110, the drain silicide 111, and the first field plate 115 respectively through the first metal layer M1.

[0109] Step S19, depositing a second metal layer M2 and patterning the second metal layer M2. The material of the second metal layer M2 is, for example, aluminum copper (AlCu), and the deposition thickness is 3 microns. The patterned second metal layer M2 is used for metal thickening of the source and drain terminals, and for interconnecting the gate pad and the gate conductor 109.

[0110] Step S20, depositing a passivation layer 118. The passivation layer 118, for example, includes a silicon oxide layer and a silicon nitride layer, the thickness of the silicon oxide layer is, for example, 300 nanometers, and the thickness of the silicon nitride layer is, for example, 800 nanometers. In addition, the passivation layer 118 in the PAD region is etched to form a source pad, a drain pad, and a gate pad. The cross-section of the device obtained after step S20 is as follows: Fig. 20 shown.

[0111] Step S21, thinning the silicon substrate 100, and depositing metal as back metal on the back side of the silicon substrate 100. The body contact region 106 is electrically connected to the back metal through the silicon substrate 100. The back metal, for example, includes a titanium layer, a nickel layer and a silver layer, i.e., Ti / Ni / Ag. The silicon substrate 100 is thinned, for example, by a back grinding process. The thickness of the thinned silicon substrate 100 is, for example, 100 microns.

[0112] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, it should be understood by those skilled in the art that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0113] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for manufacturing a metal oxide semiconductor transistor, characterized in that: include: providing a substrate; forming a source region and a drain region in the substrate; forming a first dielectric structure on the substrate, wherein the first dielectric structure exposes the drain region and the source region, and the first dielectric structure comprises a gate dielectric layer on the substrate and a first dielectric layer on the gate dielectric layer; forming a gate conductor at a predetermined position of the gate dielectric layer, wherein the first dielectric layer at least partially exposes an upper surface of the gate conductor; forming a first field plate, wherein the first field plate is located on the first dielectric layer on a side of the gate conductor close to the drain region; as well as After forming the first dielectric structure and the first field plate, a gate silicide, a source silicide and a drain silicide are respectively formed on the exposed gate conductor, the source region and the drain region.

2. The method according to claim 1, characterized in that The first dielectric layer covers the side surface of the gate conductor and the upper surface of the gate dielectric layer between the gate conductor and the drain region.

3. The method according to claim 1, characterized in that The method of forming the first dielectric structure includes: forming a gate dielectric material covering the upper surface of the substrate; forming a first dielectric material covering an upper surface of the gate dielectric material, an upper surface of the gate conductor, and a side surface of the gate conductor; After forming the first field plate at a predetermined position on the first dielectric material, forming a first etch stop layer, wherein the first etch stop layer extends from above the first field plate to above one side of the first dielectric layer adjacent to the drain region; and The first etch barrier layer and the first field plate are used as etch barrier layers, and the gate dielectric material and the first dielectric material are etched to form the first dielectric structure.

4. The method according to claim 1, characterized in that: The method further comprises: forming a drift region and a body region in the substrate, wherein the body region has a first doping type, the drift region has a second doping type, the source region is formed in the body region, and the drain region is formed in the drift region; and A body contact region having the first doping type is formed in the body region by ion implantation.

5. The method according to claim 1, characterized in that The providing of the base comprises: forming an epitaxial layer on a substrate, wherein the substrate and the epitaxial layer have a first doping type, and the resistivity of the silicon epitaxial layer is greater than the resistivity of the silicon substrate.

6. The method according to claim 5, characterized in that The method further comprises: forming a drift region and a body region in the epitaxial layer, wherein the body region has the first doping type, the drift region has the second doping type, the source region is formed in the body region, and the drain region is formed in the drift region; forming a body contact region having the first doping type in the body region by ion implantation; A substrate contact region having the first doping type is formed by ion implantation, wherein the substrate contact region at least extends from an upper surface of the epitaxial layer to an upper surface of the substrate, and the body contact region is located between the substrate contact region and the source region.

7. The method according to claim 1, characterized in that The thickness of the gate silicide, the source silicide and the drain silicide is 10 nanometers to 100 nanometers.

8. The method according to claim 1, characterized in that The first dielectric layer includes a silicon oxide layer and a silicon nitride layer.

9. The method according to claim 1, characterized in that: An overlapping length between the first field plate and the gate conductor is less than or equal to 1 / 2 of a length of the gate conductor.

10. The method according to claim 1, characterized in that The method further comprises: forming a second dielectric layer, wherein the second dielectric layer covers the gate silicide, the source silicide, the drain silicide and the gate dielectric layer; forming a second field plate on the second dielectric layer; and An interlayer dielectric layer is formed, wherein the interlayer dielectric layer covers the second dielectric layer and the second field plate.

11. The method according to claim 3, characterized in that The first edge of the first etch stop layer is used to define the formation position of the drain silicide, and the second edge is located on the first field plate.

12. A metal oxide semiconductor transistor, characterized in that: The metal oxide semiconductor transistor is manufactured by the method according to claim 1, wherein the metal oxide semiconductor transistor comprises: substrate; a source region and a drain region located in the substrate; a first dielectric structure located on the substrate, the first dielectric structure exposing the drain region and the source region, the first dielectric structure comprising a gate dielectric layer located on the substrate and a first dielectric layer located on a portion of the gate dielectric layer; A gate conductor located at a predetermined position of the gate dielectric layer, wherein the first dielectric layer covers a side surface of the gate conductor and exposes at least a portion of an upper surface of the gate conductor; a first field plate located on the first dielectric layer; and A gate silicide, a source silicide and a drain silicide are respectively located on the gate conductor, the source region and the drain region.

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