On-chip tandem edge-emitting semiconductor laser array and process method

Abstract

The invention relates to the technical field of laser, in particular to an on-chip series edge-emitting semiconductor laser array and a process method. The on-chip series edge-emitting semiconductor laser array sequentially comprises a semi-insulating substrate, a non-doped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding and a P-type cover layer from bottom to top. Table surfaces on the two sides of each light-emitting unit are deeply etched to the P-type heavily doped layer, and a lateral current diffusion suppression groove is formed between the bottoms of any two adjacent light-emitting units. An on-chip series edge-emitting semiconductor laser array structure is adopted, the parasitic effect is reduced through coplanar electrode design, upper and lower electrodes can be prepared through a single process to reduce the cost, lateral current diffusion suppression grooves are formed between light-emitting units to reduce crosstalk, the light-emitting units are connected in series to work under the same injection current, and the light-emitting efficiency is improved. The requirements of a driving circuit can be effectively reduced, and light-emitting uniformity is improved.

Description

Technical Field

[0001] The present application relates to the field of laser technology, and in particular to an on-chip tandem edge-emitting semiconductor laser array and a process method. Background Art

[0002] LiDAR has great application prospects in many fields. Semiconductor lasers are currently the most effective coherent light sources, and have the advantages of small size, low cost, long life, and electric pumping, making them the preferred light source for LiDAR systems. LiDAR systems usually require short pulses of laser sources, which have low requirements for heat dissipation, but require high peak power to increase the detection distance.

[0003] In order to achieve high output power and scanning speed, a multi-channel high-power laser array is required. To achieve high output power, each light-emitting point is required to work at a high current. The traditional semiconductor laser array is a parallel structure with extremely large working current, which has high requirements for the driving circuit. In the related technology, the series semiconductor laser array structure requires the deposition of P-type electrodes and N-type electrodes separately, and lift-off is performed separately, which is complex and costly. Summary of the invention

[0004] The present application provides an on-chip tandem edge-emitting semiconductor laser array and a process method, which are used to solve the problems of complex process and high cost of semiconductor laser array in the prior art.

[0005] The present application provides an on-chip tandem edge-emitting semiconductor laser array, which includes, from bottom to top, a semi-insulating substrate, a non-doped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding layer, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding layer, and a P-type cap layer. The laser array has multiple light-emitting units, and the two side mesas of each light-emitting unit are deeply etched to the P-type heavily doped layer. The upper electrode and the lower electrode of each light-emitting unit are prepared by a single process, and a lateral current diffusion inhibition groove is provided between the bottoms of any two adjacent light-emitting units.

[0006] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the upper electrode of each light-emitting unit is electrically connected to the lower electrode of the light-emitting unit adjacent to one side.

[0007] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, an electrical insulating layer is deposited on the top and bottom surfaces of each light-emitting unit except for the current injection region.

[0008] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the lateral current diffusion suppression grooves between adjacent light-emitting units are prepared by proton implantation or etching process, and the bottom of the lateral current diffusion suppression is located in a non-doped buffer layer or a semi-insulating substrate.

[0009] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the upper metal electrode and the lower metal electrode of each light-emitting unit have the same components, and the upper electrode and the lower electrode of the same light-emitting unit are disconnected.

[0010] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the active region is a single-layer or multi-layer quantum well, quantum dot or quantum wire.

[0011] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the thicknesses of the N-type waveguide layer and the P-type waveguide layer are different.

[0012] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the thicknesses of the N-type cladding layer and the P-type cladding layer are different.

[0013] According to an on-chip tandem edge-emitting semiconductor laser array provided by the present application, the semi-insulating substrate is any one of GaAs, InP, GaSb and GaN.

[0014] The present application also provides a process method for an on-chip tandem edge-emitting semiconductor laser array, wherein the on-chip tandem edge-emitting semiconductor laser array is the on-chip tandem edge-emitting semiconductor laser array as described above, and the process method comprises: S1: growing an epitaxial layer on the upper surface of a semi-insulating substrate; S2: preparing a light-emitting gain mesa, on the upper surface of the epitaxial layer, by cleaning, coating, exposure, development, and mesa etching processes, preparing the gain region of each light-emitting unit, and etching the grooves on both sides of the mesa to the P-type heavily doped layer, wherein the angle between the side wall of the mesa and the surface of the epitaxial layer is less than 90°; S3: preparing lateral current diffusion suppression groove; S4: depositing an electrical insulating layer to prepare a current injection region; S5: Deposit metal electrodes and prepare ohmic contacts and electrical connection layers through negative resist stripping process; S6: Thinning of semi-insulating substrate.

[0015] The on-chip tandem edge-emitting semiconductor laser array and process method provided by the present application adopt an on-chip tandem edge-emitting semiconductor laser array structure, reduce parasitic effects through coplanar electrode design, and the upper and lower electrodes can be prepared through a single process to reduce costs. Lateral current diffusion suppression grooves are provided between the light-emitting units to reduce crosstalk. Each light-emitting unit works in series under the same injection current, which can effectively reduce the driving circuit requirements and improve the uniformity of light emission. In addition, the structure realizes single-step electrode deposition through a tunnel junction, which can effectively reduce process costs and save process time, and is conducive to achieving low-cost, high-power pulsed laser output. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a schematic structural diagram of an on-chip tandem edge-emitting semiconductor laser array provided by the present application; Figure 2 Schematic diagram of the semiconductor laser wafer epitaxial structure provided in this application.

[0018] Figure 3 This is a schematic diagram of the etching structure of multiple light-emitting unit mesas of the semiconductor laser array provided in this application.

[0019] Figure 4 A schematic diagram of preparing lateral current diffusion suppression grooves between adjacent light-emitting units in the semiconductor laser array provided in the present application.

[0020] Figure 5 This is a schematic diagram of the electrical insulation layer deposition and current injection window opening structure in the preparation of the semiconductor laser array provided in this application.

[0021] Figure 6 This is a schematic diagram of the structure after the metal electrode layer is deposited and peeled off in the preparation of the semiconductor laser array provided in this application.

[0022] Reference numerals: 100. On-chip tandem edge-emitting semiconductor laser array; 1. Semi-insulating substrate; 2. Undoped buffer layer; 3. P-type heavily doped layer; 4. P-type tunnel junction layer; 5. N-type tunnel junction layer; 6. N-type cladding layer; 7. N-type waveguide layer; 8. Active region; 9. P-type waveguide layer; 10. P-type cladding layer; 11. P-type cap layer; E, light-emitting unit; E1, light-emitting unit; E2, light-emitting unit; E3, light-emitting unit; E4, light-emitting unit; B, lateral current spreading inhibition groove; M1, upper electrode window; M2, lower electrode window; C, electrical connection layer; 12. Electrical insulation layer; 13. Metal electrode. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] Combine the following Figure 1-Figure 6 The on-chip tandem edge-emitting semiconductor laser array 100 of the present application is described. It is worth noting that the following description is only an exemplary description, and is not a specific limitation of the present application.

[0025] According to the on-chip tandem edge-emitting semiconductor laser array 100 of the embodiment of the present application, it includes, from bottom to top, a semi-insulating substrate 1, an undoped buffer layer 2, a P-type heavily doped layer 3, a P-type tunnel junction layer 4, an N-type tunnel junction layer 5, an N-type cladding layer 6, an N-type waveguide layer 7, an active region 8, a P-type waveguide layer 9, a P-type cladding layer 10 and a P-type cap layer 11.

[0026] It should be noted that the substrate 1 can be a semi-insulating non-doped III-V compound, such as GaAs, InP, GaN, GaSb, etc. The non-doped buffer layer 2 is grown on the substrate 1. The non-doped buffer layer 2 is usually made of the same material as the substrate 1 and is used to bury the defects of the substrate 1 itself. The P-type heavily doped layer 3 is on the non-doped buffer layer 2. The lattice constant of the P-type heavily doped layer 3 is the same as that of the substrate 1 material and is used as the ohmic contact layer of the lower electrode of the laser.

[0027] The P-type tunnel junction layer 4 is on the P-type heavily doped layer 3 . The P-type tunnel junction layer 4 can be extremely highly doped with P-type. The lattice constant of the P-type tunnel junction layer 4 is the same as that of the substrate 1 material. The thickness is relatively thin, usually between 10nm and 200nm.

[0028] The N-type tunnel junction layer 5 is on the P-type heavily doped layer 3 . The N-type tunnel junction layer 5 can be extremely highly N-type doped. The lattice constant of the N-type tunnel junction layer 5 is the same as that of the substrate 1 material. The thickness is relatively thin, usually between 10nm and 200nm.

[0029] The N-type cladding layer 6 is grown on the N-type tunnel junction layer 5 , and the N-type cladding layer 6 is N-type doped.

[0030] The N-type waveguide layer 7 is grown on the N-type cladding layer 6 . The N-type waveguide layer 7 is N-type low-doped or undoped. The refractive index of the N-type waveguide layer 7 is higher than that of the N-type cladding layer 6 , but the band gap is lower than that of the N-type cladding layer 6 , so as to limit the light field from expanding toward the substrate 1 .

[0031] The active layer is located on the N-type waveguide layer 7 and is the gain region of the semiconductor laser. It is usually not doped and can be made of materials such as quantum wells and quantum dots.

[0032] The P-type waveguide layer 9 is located on the active layer, and is usually partially undoped and partially P-type low-doped.

[0033] The P-type cladding layer 10 is located on the P-type waveguide layer 9 , has a band gap higher than the band gap of the P-type waveguide layer 9 , but has a refractive index lower than that of the P-type waveguide layer 9 , and is usually P-type doped.

[0034] The P-type cap layer 11 is located on the P-type cladding layer 10 and is highly P-type doped to facilitate ohmic contact with the upper electrode.

[0035] The laser array has a plurality of light emitting units E, for example, see Figure 1 As shown, there are four light-emitting units E, namely light-emitting unit E1, light-emitting unit E2, light-emitting unit E3 and light-emitting unit E4, wherein light-emitting unit E1, light-emitting unit E2, light-emitting unit E3 and light-emitting unit E4 are different light-emitting points in the array.

[0036] The two side mesas of each light-emitting unit E are deeply etched to the P-type heavily doped layer 3. In other words, grooves are deeply etched on both sides of each light-emitting unit E, and the grooves are etched to the P-type heavily doped layer 3. The upper electrode and the lower electrode of each light-emitting unit are prepared by a single process. There is a lateral current diffusion inhibition groove B between the bottoms of any two adjacent light-emitting units E to inhibit the lateral diffusion of current, which can be achieved by proton bombardment, etching away the doping layer, etc.

[0037] According to the on-chip tandem edge-emitting semiconductor laser array 100 of the embodiment of the present application, the two side mesas of each of the light-emitting units E are deeply etched to the P-type heavily doped layer 3, and a lateral current diffusion inhibition groove B is provided between the bottoms of any two adjacent light-emitting units E to inhibit lateral current diffusion. This can simplify the process of the semiconductor laser array and reduce manufacturing costs.

[0038] According to some embodiments of the present application, an electrical insulating layer 12 is deposited on the top and bottom surfaces of each light-emitting unit E except for the current injection area. Figure 1As shown, an electrical insulating layer 12 is deposited on the upper surface of the mesa and the etched groove, and an electrode window is opened on the electrical insulating layer 12. Further, the electrical insulating layer 12 is etched away at the upper electrode window M1 position on the top of the mesa to expose a portion of the P-type cap layer 11, and the electrical insulating layer 12 is etched away at the lower electrode window M2 position on the bottom of the mesa to expose a portion of the P-type heavily doped layer 3, so as to limit the current injection area.

[0039] A metal electrode 13 is deposited on the upper electrode window M1, the lower electrode window M2 and the electrical connection layer C. The metal electrode 13 is realized by a single-step deposition and lift-off process, wherein the metal electrode 13 forms an ohmic contact with the P-type cap layer 11 on the top of each light-emitting unit E mesas that is not covered with the electrical insulating layer 12, and the metal electrode 13 forms an ohmic contact with the P-type heavily doped layer 3 on the bottom of each light-emitting unit E mesas that is not covered with the electrical insulating layer 12, so as to realize current injection, and there is no metal electrode 13 between the upper electrode and the lower electrode of the same light-emitting unit E.

[0040] According to the on-chip tandem edge-emitting semiconductor laser array 100 of the embodiment of the present application, the on-chip tandem edge-emitting semiconductor laser array 100 structure is adopted, and the parasitic effect is reduced by coplanar electrode design. A lateral current diffusion suppression groove B is provided between the light-emitting units E to reduce crosstalk. Each light-emitting unit E works in series under the same injection current, which can effectively reduce the driving circuit requirements and improve the uniformity of light emission. In addition, this structure realizes single-step electrode deposition through a tunnel junction, which can effectively reduce the process cost and save process time, and is conducive to achieving low-cost, high-power pulsed laser output.

[0041] According to some embodiments of the present application, the upper electrode of each light-emitting unit E is electrically connected to the lower electrode of the adjacent light-emitting unit E. In some embodiments, an electrical connection layer C is provided between different light-emitting units E to sequentially connect the lower electrode of the device and the upper electrode of the adjacent device to form a series current injection.

[0042] According to some embodiments of the present application, the lateral current diffusion suppression groove B between adjacent light-emitting units E is prepared by proton implantation or etching process, and the bottom of the lateral current diffusion suppression groove is located in the non-doped buffer layer 2 or the semi-insulating substrate 1.

[0043] According to some embodiments of the present application, the upper metal electrode 13 and the lower metal electrode 13 of each light-emitting unit E have the same components, and the upper electrode and the lower electrode of the same light-emitting unit E are disconnected. In some embodiments, the components of the upper metal electrode 13 and the lower metal electrode 13 can be the same.

[0044] According to some embodiments of the present application, the active region 8 is a single-layer or multi-layer quantum well, quantum dot or quantum wire.

[0045] According to some embodiments of the present application, the thickness of the N-type waveguide layer 7 is different from that of the P-type waveguide layer 9. In some embodiments, the composition of the N-type waveguide layer 7 and the composition of the P-type waveguide layer 9 may be the same. In some embodiments, the substrate 1 is any one of GaAs, InP, GaSb and GaN. In some embodiments, the thickness of the N-type cladding layer 6 and the P-type cladding layer 10 are different. In some embodiments, the composition of the N-type cladding layer 6 and the composition of the P-type cladding layer 10 may be the same.

[0046] The laser transmitter circuit provided according to the present application includes the on-chip tandem edge-emitting semiconductor laser array 100 as described above.

[0047] According to the laser emitter circuit of the embodiment of the present application, the two side mesas of each of the light-emitting units E are deeply etched to the P-type heavily doped layer 3, and a lateral current diffusion inhibition groove B is provided between the bottoms of any two adjacent light-emitting units E to inhibit lateral current diffusion. This can simplify the process of the semiconductor laser array and reduce manufacturing costs.

[0048] The embodiment of the present application provides a process method for an on-chip tandem edge-emitting semiconductor laser array 100. The on-chip tandem edge-emitting semiconductor laser array 100 is the on-chip tandem edge-emitting semiconductor laser array 100 as described above.

[0049] Specifically, the process comprises: S1: growing an epitaxial layer on the upper surface of the substrate 1; for example, in this step, a non-doped buffer layer 2, a P-type heavily doped layer 3, a P-type tunnel junction layer 4, an N-type tunnel junction layer 5, an N-type cladding layer 6, an N-type waveguide layer 7, an active region 8, a P-type waveguide layer 9, a P-type cladding layer 10, and a P-type cap layer 11 can be grown in sequence on the upper surface of a semi-insulating GaAs, InP, GaN, GaSb or other substrate 1 using a MOCVD (Metal-organic Chemical Vapor Deposition) device or an MBE (Molecular beam epitaxy) device to obtain an epitaxial layer of a semiconductor laser, such as Figure 2 shown.

[0050] S2: Prepare a light-emitting gain table. On the upper surface of the epitaxial layer, prepare the gain region of each light-emitting unit E through cleaning, coating, exposure, development, and table etching processes. The grooves on both sides of the table are etched to the P-type heavily doped layer 3, wherein the angle between the side wall of the table and the surface of the epitaxial layer is less than 90°; in this way, the thickness of the insulating layer deposition and the deposition of the electrical connection layer can be guaranteed. Figure 3 shown.

[0051] S3: preparing lateral current diffusion suppression groove B. In this step, a lateral current diffusion suppression groove B mask is prepared by cleaning, coating, exposure, and development, and then the lateral current diffusion suppression groove B is prepared by ion implantation or etching technology to suppress lateral carrier diffusion between different light-emitting units E. Figure 4 shown.

[0052] S4: Deposit an electrical insulating layer 12 to prepare a current injection area. In this step, the wafer is cleaned and an electrical insulating layer 12 is deposited on the surface of the wafer. Then, a window is opened by means of coating, photolithography, development, etching and other technical means, and the electrical insulating layer 12 in the current injection area is removed to prepare a current injection area M1 (i.e., an upper electrode window M1) and a lower current injection area M2 (i.e., a lower electrode window M2) on the surface. Figure 5 shown.

[0053] S5: Deposit metal electrode 13, and realize ohmic contact and electrical connection layer preparation by negative photoresist stripping process. In this step, electrode deposition pattern is prepared by negative photoresist, photolithography, and development, and then upper metal electrode 13 and lower metal electrode 13 are deposited, and then the unnecessary metal layer is removed by stripping process to complete the preparation of injection electrode and electrical connection layer. Figure 6 shown.

[0054] S6: Thinning the substrate 1. In this step, the thickness of the semi-insulating substrate 1 is thinned by grinding and then polished to facilitate subsequent cleavage and other processes. After the lower surface of the substrate 1 is thinned and polished, a layer of metal electrode 13 may also be deposited for subsequent packaging.

[0055] According to the process method of the on-chip tandem edge-emitting semiconductor laser array 100 of the embodiment of the present application, by deeply etching the two side mesas of each of the light-emitting units E to the P-type heavily doped layer 3 and providing a lateral current diffusion suppression groove B between the bottoms of any two adjacent light-emitting units E, the current lateral diffusion can be suppressed, which can simplify the process of the semiconductor laser array and reduce the manufacturing cost. Further, by adopting the on-chip tandem edge-emitting semiconductor laser array 100 structure, the parasitic effect is reduced by the coplanar electrode design, and the upper and lower electrodes can be prepared by a single process to reduce the cost, the current lateral diffusion suppression groove is provided between the light-emitting units E to reduce the crosstalk, and each light-emitting unit E works in series under the same injection current, which can effectively reduce the driving circuit requirements and improve the uniformity of light emission; in addition, the structure realizes single-step electrode deposition through the tunnel junction, which can effectively reduce the process cost and save the process time, and is conducive to the realization of low-cost, high-power pulsed laser output.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An on-chip tandem edge-emitting semiconductor laser array, characterized in that: From bottom to top, it includes a semi-insulating substrate, an undoped buffer layer, a P-type heavily doped layer, a P-type tunnel junction layer, an N-type tunnel junction layer, an N-type cladding layer, an N-type waveguide layer, an active region, a P-type waveguide layer, a P-type cladding layer, and a P-type cap layer. The laser array has multiple light-emitting units, and the two side mesas of each light-emitting unit are deeply etched to the P-type heavily doped layer. The upper electrode and the lower electrode of each light-emitting unit are prepared by a single process, and a lateral current diffusion inhibition groove is provided between the bottoms of any two adjacent light-emitting units.

2. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The upper electrode of each light-emitting unit is electrically connected to the lower electrode of the light-emitting unit adjacent to one side.

3. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: On each of the light-emitting units, an electrical insulating layer is deposited on the top and bottom surfaces of the mesa except the current injection area.

4. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The lateral current diffusion suppression grooves between adjacent light-emitting units are prepared by proton implantation or etching process, and the bottom of the lateral current diffusion suppression grooves is located in a non-doped buffer layer or a semi-insulating substrate.

5. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The upper metal electrode and the lower metal electrode of each light-emitting unit have the same components, and the upper electrode and the lower electrode of the same light-emitting unit are disconnected.

6. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The active region is a single-layer or multi-layer quantum well, quantum dot or quantum wire.

7. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The N-type waveguide layer and the P-type waveguide layer have different thicknesses.

8. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The N-type cladding layer and the P-type cladding layer have different thicknesses.

9. The on-chip tandem edge-emitting semiconductor laser array according to claim 1, characterized in that: The semi-insulating substrate is any one of GaAs, InP, GaSb and GaN.

10. A process method for an on-chip tandem edge-emitting semiconductor laser array, characterized in that: The on-chip tandem edge-emitting semiconductor laser array is an on-chip tandem edge-emitting semiconductor laser array according to any one of claims 1 to 9, and the process method comprises: S1: growing an epitaxial layer on the upper surface of a semi-insulating substrate; S2: preparing a light-emitting gain mesa, on the upper surface of the epitaxial layer, by cleaning, coating, exposure, development, and mesa etching processes, preparing the gain region of each light-emitting unit, and etching the grooves on both sides of the mesa to the P-type heavily doped layer, wherein the angle between the side wall of the mesa and the surface of the epitaxial layer is less than 90°; S3: preparing lateral current diffusion suppression groove; S4: depositing an electrical insulating layer to prepare a current injection region; S5: Deposit metal electrodes and prepare ohmic contacts and electrical connection layers through negative resist stripping process; S6: Thinning of semi-insulating substrate.

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