A method and system for dynamic current sharing of silicon carbide power modules

Abstract

The application discloses a silicon carbide power module dynamic current sharing method and system, sets a basic layout of a multi-chip parallel silicon carbide power module, and extracts circuit parasitic parameters; sets silicon carbide power module working conditions, sets bus voltage, load current, and power chip switching speed; sets the highest allowable voltage overshoot, limits the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot; according to the equivalent impedance of the parallel branch after the distributed decoupling capacitor group is added under the set switching speed, the capacitance value of the distributed decoupling capacitor is adjusted, so that the equivalent impedances of the branches are the same. The application solves the problem of uneven current distribution in the traditional parallel technology by integrating the distributed decoupling capacitor, and has important theoretical and practical significance for improving the performance of a power electronic system.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a dynamic current sharing method and system for a silicon carbide power module. BACKGROUND

[0002] A power module is a module formed by packaging and integrating a series of power semiconductor chips in a certain topology for the purpose of realizing a certain function. Compared with a topology composed of discrete power chips, the power module has high integration, and has great advantages in electrical performance, thermal performance, safety, chip life, cost, etc.

[0003] With the continuous development of semiconductor power chips, the application environment requirements of important military and civilian fields such as new energy grid connection, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, and pulse power are continuously improving, and the influence of the energy-saving and "double carbon" slogan. The power module is continuously developing towards miniaturization, low loss, high power density, high reliability, and high integration. In particular, the emergence of a new generation of wide-bandgap semiconductor chips represented by silicon carbide and gallium nitride materials gradually replaces silicon-based chips in various industries, accelerating the development of power modules, enabling power modules using wide-bandgap power semiconductor chips to have smaller size, work at higher temperature, and work at higher switching frequency, thereby further reducing the size of passive chips and improving the efficiency of the converter. Among them, the power chip represented by silicon carbide MOSFET is expected to replace traditional silicon IGBT in medium and high power conditions.

[0004] However, the area of the silicon carbide chip is small, and the current capacity is small, so multiple silicon carbide chips need to be used in parallel to enable the power module to pass a larger current. During parallel use, inconsistencies in circuit parameters can cause serious uneven current flow between parallel chips, leading to inconsistent chip losses and reducing the expected life of the power module. In a silicon carbide power module, due to the high operating frequency, the switching loss accounts for a large proportion, and the fast switching speed also makes the inconsistency of the loop parameters bring greater dynamic uneven current flow phenomenon, aggravating the uneven loss of parallel chips. In addition, the fast switching speed also brings higher voltage overshoot, increasing the switching loss of the chip and also bringing the risk of overvoltage breakdown to the system, so that the system must be voltage-reduced to use. In order to solve the problem of current sharing, the current solution is to expand the branch with small parasitic inductance to match the branch with the largest inductance, thereby achieving current sharing. However, this will increase the overall parasitic inductance of the module, reduce the switching speed, increase the switching loss, and aggravate the voltage overshoot.

[0005] In summary, the use of multi-chip silicon carbide power modules is limited by current sharing and voltage overshoot when multiple chips are connected in parallel, which requires silicon carbide modules to reduce voltage and current ratings. Therefore, a method is needed to overcome the problem of dynamic current sharing and voltage overshoot in multi-chip silicon carbide power modules, and to efficiently use silicon carbide chips. SUMMARY

[0006] The technical problem to be solved by the present application is to provide a silicon carbide power module dynamic current sharing method and system to overcome the shortcomings of the prior art. The method of inserting a distributed decoupling capacitor group inside the power module reduces the voltage overshoot during shutdown and weakens the impedance of the parallel high-impedance loop at high frequency, so that the impedance of the high-impedance loop in the on state matches the impedance of the lowest impedance loop, thereby achieving efficient dynamic current sharing. The technical problem of the prior art that the multi-chip silicon carbide power module cannot simultaneously achieve efficient dynamic current sharing and reduce voltage overshoot is solved.

[0007] The present application adopts the following technical solutions:

[0008] A silicon carbide power module dynamic current sharing method, characterized in that it comprises the following steps:

[0009] Set the basic layout of the multi-chip parallel silicon carbide power module, and extract the circuit parasitic parameters;

[0010] Set the working conditions of the silicon carbide power module, set the bus voltage, load current, and power chip switching speed;

[0011] Set the maximum allowable voltage overshoot, and limit the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot;

[0012] According to the equivalent impedance of the parallel branch after adding the distributed decoupling capacitor group at the set switching speed, adjust the capacitance value of the distributed decoupling capacitor so that the equivalent impedances of each branch are the same.

[0013] Preferably, the extracted parasitic parameters of the circuit include the parasitic inductance of the circuit at the frequency corresponding to the set switching speed, the parasitic inductance of the external busbar circuit and the busbar capacitor.

[0014] Preferably, the frequency equivalent to the power chip switching speed is as follows:

[0015]

[0016] Wherein, f is the equivalent frequency corresponding to the silicon carbide chip switching process, t r is the current rise time.

[0017] Preferably, the voltage overshoot is obtained by circuit simulation, and the peak value of the voltage overshoot after adding the decoupling capacitorV p1 is the voltage of the bus, V p2 is the voltage of the bus,

[0018]

[0019] wherein, V DC is the peak value of the bus voltage, v F_max is the maximum voltage drop of the anti-parallel diode or body diode, L in is the internal power loop inductance of the power module, L out is the external loop inductance of the power module, i ds is the current through the silicon carbide chip, C 0 is the total capacitance of the decoupling capacitor, I L is the current of the load inductance, Q 1 (0) is the voltage of the bus, Q 2 (0) is the charge of the capacitor during the turn-off process.

[0020] Preferably, the charge of the capacitor during the turn-off process Q 1 (0) is the voltage of the bus, Q 2 (0) is the voltage of the bus,

[0021]

[0022] wherein, t 2 is the time when the voltage reaches the bus voltage, t p1 is the time when the bus voltage reaches the first overshoot peak, t 3 is the time when the current reaches 0.

[0023] Preferably, the maximum allowed voltage overshoot is the minimum value of the total capacitance of the distributed decoupling capacitor.

[0024] Preferably, the maximum value of the total capacitance of the distributed decoupling capacitor is the point at which the first overshoot peak is equal to the second overshoot peak.

[0025] Preferably, the equivalent impedance is specifically:

[0026]

[0027] wherein, z s1 , z s2 ... zsn are the equivalent source impedances of the 1st-nth silicon carbide chips with distributed decoupling capacitors in parallel, z s1 , z s2 ... z sn are the equivalent source impedances of the 1st-nth silicon carbide chips without distributed decoupling capacitors in parallel, σ 1 σ n-1 are the impedance adjustment terms after adding the distributed decoupling capacitors, and the specific values need to be determined according to the circuit layout.

[0028] Preferably, by adjusting the capacitance value of the distributed decoupling capacitors, the impedance imbalance δ is minimized, and the impedance imbalance δ is calculated as follows:

[0029]

[0030] where max{Z} is the maximum value of the equivalent source impedance, min{Z} is the minimum value of the equivalent source impedance, and Z is the average value of the equivalent source impedance. z n z n

[0031] In a second aspect, an embodiment of the present application provides a silicon carbide power module dynamic current sharing system, comprising:

[0032] an extraction module configured to extract the basic layout of a multi-chip parallel silicon carbide power module and extract circuit parasitic parameters;

[0033] a condition module configured to set the working conditions of the silicon carbide power module, set the bus voltage, load current, and power chip switching speed;

[0034] a limiting module configured to set the maximum allowable voltage overshoot and limit the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot;

[0035] a current sharing module configured to adjust the capacitance value of the distributed decoupling capacitor according to the equivalent impedance of the parallel branch after adding the distributed decoupling capacitor group at a set switching speed, so that the equivalent impedances of the branches are the same.

[0036] In a third aspect, a computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above-mentioned silicon carbide power module dynamic current sharing method when executing the computer program.

[0037] ​​​In a fourth aspect, an embodiment of the present application provides a computer readable storage medium comprising a computer program which, when executed by a processor, implements the steps of the silicon carbide power module dynamic current sharing method described above.

[0038] In a fifth aspect, a chip comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the silicon carbide power module dynamic current sharing method described above when executing the computer program.

[0039] In a sixth aspect, an embodiment of the present application provides an electronic device comprising a computer program which, when executed by the electronic device, implements the steps of the silicon carbide power module dynamic current sharing method described above.

[0040] Compared with the prior art, the present application has at least the following beneficial effects:

[0041] A silicon carbide power module dynamic current sharing method introduces distributed decoupling capacitors in parallel silicon carbide power modules, quickly selects appropriate distributed decoupling capacitor values through modeling calculation, reduces voltage overshoot, and realizes dynamic current sharing of parallel silicon carbide chips; by accurately controlling the total capacitance value of the decoupling capacitor and the distribution ratio of each branch, the voltage can be quickly stabilized when the system is disturbed, and the voltage overshoot phenomenon can be significantly reduced. The silicon carbide power module is protected from overvoltage damage, and the overall stability of the system is improved; by optimizing the equivalent impedance of each parallel branch, the parallel silicon carbide chips can obtain balanced switching current, not only improving the power output capability of the system, but also helping to reduce the thermal stress of the device and prolong the service life of the device; the performance and reliability of the power electronic system are significantly improved, and by effectively managing and controlling the dynamic behavior of the silicon carbide power module, the system can run more smoothly in a high-power output state, while reducing the potential failure risk caused by uneven current.

[0042] Further, the parasitic parameters of the circuit, including the parasitic inductance of the circuit and the parasitic inductance of the bus capacitor, are extracted at the frequency corresponding to the switching speed, so that the entire circuit is modeled completely and accurately, thereby accurately describing the switching behavior of the circuit under normal working conditions and setting the basis conditions for subsequent optimization. Further, the minimum value of the total capacitance value of the distributed decoupling capacitor is set according to the maximum allowable voltage overshoot. Within the range where the decoupling capacitor has a significant impact on the turn-off voltage waveform, a larger total capacitance value of the distributed decoupling capacitor can more effectively suppress the voltage overshoot during the turn-off process, and the rated voltage of the components in the circuit will limit the maximum turn-off voltage overshoot amplitude, so a distributed decoupling capacitor total capacitance value that exceeds the minimum value needs to be set to ensure safe operation of the circuit.

[0043] Further, the maximum of the total capacitance value of the distributed decoupling capacitor is set according to the point at which the first overshoot peak value is equal to the second overshoot peak value. After the minimum capacitance value is added to the distributed decoupling capacitor, the two-stage peak value presented in the circuit turn-off process is generally embodied as the second overshoot peak value being much greater than the first overshoot peak value. In the range exceeding the minimum value, the peak value of the distributed decoupling capacitor continues to increase, which has a greater inhibitory effect on the second overshoot peak value and a smaller effect on the first overshoot peak value. When the total capacitance value is increased to the point at which the first overshoot peak value is equal to the second overshoot peak value, the first overshoot peak value becomes the voltage peak value in the turn-off process and is less affected by the total capacitance value, and the benefit of continuing to increase the capacitance value is not high at this time. Therefore, the maximum of the total capacitance value of the distributed decoupling capacitor is selected as the point at which the first overshoot peak value is equal to the second overshoot peak value.

[0044] It can be understood that the beneficial effects of the second aspect to the sixth aspect described above can be referred to the related description in the first aspect described above, and will not be repeated here.

[0045] In summary, the present application solves the problem of uneven current distribution in the traditional parallel technology by integrating the distributed decoupling capacitor, which has important theoretical and practical significance for improving the performance of power electronic systems.

[0046] The technical solutions of the present application will be further described in detail below through the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 Layout diagram of a multi-chip silicon carbide power module without installing a distributed decoupling capacitor according to an embodiment of the present application;

[0048] Figure 2 Layout diagram of a multi-chip silicon carbide power module with installing a distributed decoupling capacitor according to an embodiment of the present application;

[0049] Figure 3 Installation diagram of an external busbar circuit and busbar capacitor according to an embodiment of the present application;

[0050] Figure 4 Method step diagram according to the present application;

[0051] Figure 5 Schematic diagram of a computer device provided by an embodiment of the present application;

[0052] Figure 6 Block diagram of a chip according to an embodiment of the present application.

[0053] Wherein: 101. DC power terminal positive; 102. DC power terminal negative; 103. AC power terminal; 111. DC power positive area; 112. DC power negative area; 113. AC power area; 121. First chip upper surface; 122. Second chip upper surface; 123. Third chip upper surface; 124. Fourth chip upper surface; 125. Fifth chip upper surface; 126. Sixth chip upper surface; 201. First upper bridge arm; 202. Second upper bridge arm; 203. Third upper bridge arm; 204. First lower bridge arm; 205. Second lower bridge arm; 206. Third lower bridge arm; 301. First distributed decoupling capacitor; 302. Second distributed decoupling capacitor; 303. Third distributed decoupling capacitor; 400. Busbar circuit board; 411. First electrolytic capacitor; 412. Second electrolytic capacitor; 413. Third electrolytic capacitor; 414. Fourth electrolytic capacitor; 415. Fifth electrolytic capacitor; 416. Sixth electrolytic capacitor; 417. Seventh electrolytic capacitor; 418. Eighth electrolytic capacitor; 420. Film capacitor; 430. Connection circuit board. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0055] In the description of the present application, it should be understood that the terms "include" and "contain" indicate the existence of described features, whole, steps, operations, elements and / or components, but do not exclude the existence or addition of one or more other features, whole, steps, operations, elements, components and / or sets thereof.

[0056] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and the appended claims of the present application, unless otherwise clear from the context, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0057] It should be further understood that the term "and / or" used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations, for example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the character " / " in the present application generally represents an "or" relationship between the front and rear associated objects.

[0058] It should be understood that, although the terms first, second, third, etc. can be employed in describing the preset ranges, etc. in the embodiments of the present application, the preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, the first preset range can also be referred to as the second preset range, and similarly, the second preset range can also be referred to as the first preset range, without departing from the scope of the embodiments of the present application.

[0059] Depending on the context, the word "if" as used herein can be interpreted to mean "when" or "while" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]."

[0060] Various structural diagrams according to the disclosed embodiments of the present application are shown in the accompanying drawings. These diagrams are not drawn to scale, in which certain details are exaggerated for clarity and others omitted. The shapes and relative sizes of the various regions, layers, and their relative positions shown in the diagrams are merely exemplary, and in actuality can deviate due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.

[0061] In modern power electronic systems, silicon carbide (SiC) power modules are widely used due to their high efficiency, high reliability, and high voltage resistance. In particular, in high-power output application scenarios, multi-chip parallel technology has become an effective means to improve the power capacity of the system. However, in the actual operation of parallel silicon carbide power modules, due to factors such as device characteristic differences and inconsistent line impedance, uneven current distribution often occurs, which in turn leads to problems such as device overheating, system efficiency decline, and even equipment damage. Therefore, it is crucial to study how to achieve dynamic current sharing among parallel silicon carbide power modules to improve the overall performance of the system.

[0062] The application provides a silicon carbide power module dynamic current sharing method, and integrates distributed decoupling capacitors in a multi-chip parallel silicon carbide power module.

[0063] Please refer to Figure 1 and Figure 2 The power module used in the application is a half-bridge structure and is parallel to three silicon carbide chips.

[0064] The first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are arranged at intervals in the DC power positive region 111, and the first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are connected to the AC power region 113 through the first chip upper surface 121, the second chip upper surface 122 and the third chip upper surface 123 respectively.

[0065] The main power conductive region of the power module power substrate is divided into a DC power positive region 111, a DC power negative region 112 and an AC power region 113, and the power terminals of the power module include a DC power terminal positive 101, a DC power terminal negative 102 and an AC power terminal 103; the DC power positive region 111 is connected with the DC power terminal positive 101, the DC power negative region 112 is connected with the DC power terminal negative 102, and the AC power region 113 is connected with the AC power terminal 103; the first distributed decoupling capacitor 301, the second distributed decoupling capacitor 302 and the third distributed decoupling capacitor 303 are sequentially arranged between the DC power positive region 111 and the DC power negative region 112.

[0066] The first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are arranged at intervals in the DC power positive region 111, and the first upper bridge arm 201, the second upper bridge arm 202 and the third upper bridge arm 203 are connected to the AC power region 113 through the first chip upper surface 121, the second chip upper surface 122 and the third chip upper surface 123 respectively.

[0067] The first lower bridge arm 204, the second lower bridge arm 205 and the third lower bridge arm 206 are arranged at intervals in the AC power region 113; the first lower bridge arm 204, the second lower bridge arm 205 and the third lower bridge arm 206 are connected to the DC power negative region 112 through the fourth chip upper surface 124, the fifth chip upper surface 125 and the sixth chip upper surface 126 respectively.

[0068] Referring to Figure 3 , the external busbar circuit board 400 comprises a first electrolytic capacitor 411, a second electrolytic capacitor 412, a third electrolytic capacitor 413, a fourth electrolytic capacitor 414, a fifth electrolytic capacitor 415, a sixth electrolytic capacitor 416, a seventh electrolytic capacitor 417, an eighth electrolytic capacitor 418 and a thin film capacitor 420; the first electrolytic capacitor 411, the second electrolytic capacitor 412, the third electrolytic capacitor 413 and the fourth electrolytic capacitor 414 are connected in series to form a first branch, the fifth electrolytic capacitor 415, the sixth electrolytic capacitor 416, the seventh electrolytic capacitor 417 and the eighth electrolytic capacitor 418 are connected in series to form a second branch, and the first branch and the second branch are connected in parallel and connected with the power module through the thin film capacitor 420 and the connecting circuit board 430.

[0069] Referring to Figure 4 , the application discloses a dynamic current sharing method for a silicon carbide power module, and comprises the following steps:

[0070] S1, setting the basic layout of the multi-chip parallel silicon carbide power module, and extracting the parasitic parameters of the circuit;

[0071] The parasitic parameters of the circuit mainly include the parasitic inductance of the circuit at the frequency corresponding to the set switching speed, and the parasitic inductance of the external busbar circuit, the busbar capacitor and the like.

[0072] S2, setting the working conditions of the silicon carbide power module, setting the bus voltage, the load current and the switching speed of the power chip;

[0073] The frequency equivalent to the switching speed of the silicon carbide power module is considered by the following formula:

[0074]

[0075] Wherein, f is the equivalent frequency corresponding to the switching process of the silicon carbide chip, t r is the current rise time.

[0076] S3, setting the maximum allowable voltage overshoot, and limiting the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot;

[0077] The number of the distributed decoupling capacitor group is the same as the number of the parallel silicon carbide chips, and is placed close to the parallel silicon carbide chips.

[0078] The voltage overshoot can be obtained through circuit simulation, and is considered by the following formula:

[0079]

[0080] Wherein, Vp1 With V p2 Vpeak is the peak value of voltage overshoot after adding decoupling capacitor, V DC Vbus is the bus voltage peak value, v F_max Vdiode is the maximum voltage drop of anti-parallel diode or body diode, L in L is the internal power loop inductance of power module, L out Lext is the external loop inductance of power module, i ds I is the current through silicon carbide chip, C 0 is the total capacitance of decoupling capacitor, I L Iload is the current of load inductance, Q 1 (0) With Q 2 (0) Q is the charge amount of capacitor during turn-off process.

[0081] Charge amount of capacitor during turn-off process Q 1 (0) With Q 2 (0) Consider by the following formula:

[0082]

[0083] Wherein, t 2 is the time when voltage reaches bus voltage, t p1 T1 is the time when bus voltage reaches the first overshoot peak value, t 3 is the time when current reaches 0.

[0084] The maximum allowed voltage overshoot limit selects the minimum value of the total capacitance of distributed decoupling capacitor, and the selected total capacitance value needs to be greater than this value to limit the voltage overshoot within the required range.

[0085] The maximum value of the total capacitance of the distributed decoupling capacitor group is recommended to be the point at which the first overshoot peak value is equal to the second overshoot peak value, and beyond this point, the improvement of decoupling capacitor on voltage overshoot is limited.

[0086] The distributed decoupling capacitor group includes but is not limited to ceramic capacitor, silicon chip capacitor.

[0087] S4, according to the equivalent impedance of the parallel branch at the set switching speed after adding the distributed decoupling capacitor group, adjust the capacitance value of the distributed decoupling capacitor, so that the equivalent impedances of each branch are the same.

[0088] The method for selecting the distributed decoupling capacitor with the minimum impedance imbalance degree includes but is not limited to a traversal method, a gradient descent method, and a neural network method.

[0089] The equivalent impedance mainly refers to an equivalent source impedance, which is considered by the following formula:

[0090]

[0091] Wherein, z s1 、 z s2 ... z sn are equivalent source impedances of the first-n silicon carbide chips after adding the distributed decoupling capacitors in parallel, z s1 ’、 z s2 ’... z sn ’are equivalent source impedances of the first-n silicon carbide chips before adding the distributed decoupling capacitors in parallel, σ 1... σ n-1 are impedance adjustment items after adding the distributed decoupling capacitors, and the specific values need to be determined according to the circuit layout.

[0092] The impedance imbalance degree is set as δ The impedance imbalance degree is minimized by adjusting the capacitance value of the distributed decoupling capacitor to realize dynamic current sharing. δ The impedance imbalance degree is considered by the following formula:

[0093]

[0094] Wherein, max{ z n} is the maximum value of the equivalent source impedance, min{ z n} is the minimum value of the equivalent source impedance, is the average value of the equivalent source impedance.

[0095] At this point, the dynamic current sharing of the silicon carbide power module based on the distributed decoupling capacitor is realized by balancing the equivalent source impedance.

[0096] In another embodiment of the present application, a silicon carbide power module dynamic current sharing system is provided, which can be used to realize the above-mentioned silicon carbide power module dynamic current sharing method. Specifically, the silicon carbide power module dynamic current sharing system includes an extraction module, a condition module, a restriction module, and a current sharing module.

[0097] Wherein, the extraction module sets the basic layout of the multi-chip parallel silicon carbide power module, and extracts the circuit parasitic parameters;

[0098] The condition module sets the working condition of the silicon carbide power module, sets the bus voltage, load current, and power chip switching speed.

[0099] The limiting module sets the maximum allowable voltage overshoot, and limits the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot.

[0100] The current sharing module adjusts the capacitance value of the distributed decoupling capacitor according to the equivalent impedance of the parallel branch after adding the distributed decoupling capacitor group under the set switching speed, so that the equivalent impedances of the branches are the same.

[0101] In an embodiment, the application provides a terminal device, which comprises a processor and a memory, the memory is used to store a computer program, the computer program comprises program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to realize the corresponding method flow or corresponding function. The processor in the embodiment of the application can be used for the operation of the silicon carbide power module dynamic current sharing method, which comprises:

[0102] The basic layout of the multi-chip parallel silicon carbide power module is set, the circuit parasitic parameters are extracted, the working condition of the silicon carbide power module is set, the bus voltage, load current and power chip switching speed are set, the maximum allowable voltage overshoot is set, the total capacitance value of the distributed decoupling capacitor group is limited according to the voltage overshoot, and the capacitance value of the distributed decoupling capacitor is adjusted according to the equivalent impedance of the parallel branch after adding the distributed decoupling capacitor group under the set switching speed, so that the equivalent impedances of the branches are the same.

[0103] Please refer to Figure 5, the terminal device is a computer device, the computer device 60 of the embodiment includes a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61, and the computer program 63, when executed by the processor 61, implements the method for calculating the fluid composition in the reservoir stimulation wellbore in the embodiment. To avoid repetition, details are not described here. Alternatively, the computer program 63, when executed by the processor 61, implements the functions of each model / unit in the silicon carbide power module dynamic current sharing system of the embodiment. To avoid repetition, details are not described here.

[0104] The computer device 60 can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The computer device 60 can include, but is not limited to, the processor 61 and the memory 62. Those skilled in the art can understand that the computer device 60 can include more or fewer components, or some components are combined, or different components, for example, the computer device can also include an input / output device, a network access device, a bus, and the like. Figure 5 The computer device 60 is only an example and does not constitute a limitation on the computer device 60, and can include more or fewer components than the illustration, or combine certain components, or different components, for example, the computer device can also include an input / output device, a network access device, a bus, and the like.

[0105] The processor 61 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, and the like. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0106] The memory 62 can be an internal storage unit of the computer device 60, such as a hard disk or a memory of the computer device 60. The memory 62 can also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like.

[0107] Further, the memory 62 can include both an internal storage unit and an external storage device of the computer device 60. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 can also be used to temporarily store data that has been output or will be output.

[0108] Referring to Figure 6 The terminal device is a chip, and the chip 600 of this embodiment includes one or more processors 622 and a memory 632 for storing a computer program executable by the processor 622. The computer program stored in the memory 632 can include one or more modules each corresponding to a set of instructions. In addition, the processor 622 can be configured to execute the computer program to perform the above-mentioned dynamic current sharing method of the silicon carbide power module.

[0109] In addition, the chip 600 can further include a power supply component 626 which can be configured to perform power management of the chip 600, and a communication component 650 which can be configured to implement communication of the chip 600, for example, wired or wireless communication. In addition, the chip 600 can further include an input / output interface 658. The chip 600 can operate based on an operating system stored in the memory 632.

[0110] In another embodiment of the present application, the present application also provides a storage medium, specifically a computer readable storage medium, which is a memory device in a terminal device, used for storing programs and data. It can be understood that the computer readable storage medium herein can include an internal storage medium of the terminal device, and of course can also include an expansion storage medium supported by the terminal device. The computer readable storage medium provides a storage space which stores an operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by a processor are also stored in the storage space, and the instructions can be one or more computer programs. It should be noted that the computer readable storage medium herein can be a high-speed RAM memory or a non-volatile memory such as at least one disk memory.

[0111] The one or more instructions stored in the computer readable storage medium can be loaded and executed by the processor to implement the corresponding steps of the silicon carbide power module dynamic current sharing method in the above-mentioned embodiments; the one or more instructions in the computer readable storage medium are loaded and executed by the processor as follows:

[0112] Set the basic layout of the multi-chip parallel silicon carbide power module, and extract the circuit parasitic parameters; set the working conditions of the silicon carbide power module, set the bus voltage, the load current, and the switching speed of the power chip; set the maximum allowable voltage overshoot, and distribute the total capacitance value of the distributed decoupling capacitor group according to the voltage overshoot limit; according to the equivalent impedance of the parallel branch under the set switching speed after the distributed decoupling capacitor group is added, adjust the capacitance value of the distributed decoupling capacitor, so that the equivalent impedances of each branch are the same.

[0113] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0114] Embodiment

[0115] 1. Basic layout, extraction of parasitic parameters

[0116] The basic layout of the multi-chip parallel silicon carbide power module is set, and the circuit parasitic parameters are extracted. In this embodiment, the module external inductance is extracted as 57.8nH, and the longest commutation loop inductance inside the module is extracted as 18.66nH.

[0117] 2. Setting of working conditions

[0118] The working conditions of the silicon carbide power module are set, including bus voltage, load current, power chip switching speed, etc. The bus voltage is set to 400V; the load current is 90A, i.e. the current on each chip is 30A; and the chip turn-on time is 20ns.

[0119] 3. Allowable voltage overshoot

[0120] The highest allowable voltage overshoot is set, and the total capacitance value of the distributed decoupling capacitor is selected according to the voltage overshoot limit. The highest allowable voltage overshoot is set to 15% here, i.e. the highest voltage limit is 460V, and the lowest allowable decoupling capacitor total value is calculated to be 100nF by simulation or model calculation; when the decoupling capacitor total value is 250nF, the two voltage overshoot peak values are calculated to be equal, which is set as the highest value of the decoupling capacitor here. Finally, the decoupling capacitor total capacitance value is selected as 150nF.

[0121] 4. Equivalent impedance adjustment

[0122] According to the module layout, after adding three groups of distributed decoupling capacitors to the three groups of parallel silicon carbide chips, the equivalent impedance of the parallel branches at the set switching speed selects the capacitance value of the distributed decoupling capacitors, so that the equivalent impedances of the branches are the same. By modeling the impedance at the frequency corresponding to the set switching speed, the current imbalance degree is set to be less than 2.5% as the adjustment target, and finally the three groups of distributed decoupling capacitors are selected as 50nF, 30nF and 70nF.

[0123] 5, Effect evaluation

[0124] Voltage overshoot limitation: after using the method of the application, the voltage overshoot is limited from 43.5% to 14.5%;

[0125] Dynamic current imbalance: the dynamic current imbalance is limited from 47.5% to 0.9%;

[0126] Loss reduction: the method of the application can limit the voltage overshoot while greatly reducing the dynamic current imbalance, reducing the loss of the parallel silicon carbide chips and achieving balanced switching loss.

[0127] In summary, the silicon carbide power module dynamic current sharing method and system of the application uses the limiting condition of the maximum amplitude of the voltage overshoot to obtain the total capacitance value of the decoupling capacitor, and determines the capacitance value of the distributed decoupling capacitor according to the equivalent impedance matching of the parallel branches. While reducing the voltage overshoot of the silicon carbide power module, the parallel silicon carbide chips can obtain balanced switching current.

[0128] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above functional units and modules is exemplified, and in actual application, the above functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above integrated unit can be realized in the form of hardware or software. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the application. The specific working process of the units and modules in the system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0129] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0130] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed in the present application can be realized in electronic hardware or in combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0131] In the embodiments provided by the present application, it should be understood that the disclosed apparatus / terminal and method can be implemented in other ways. For example, the apparatus / terminal embodiments described above are merely schematic. The division of the modules or units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or in other forms.

[0132] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0133] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0134] The integrated module / unit, if realized in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, all or part of the processes in the above-mentioned embodiment methods can also be completed by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of each method embodiment when executed by a processor. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or some intermediate forms, etc. The computer-readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the computer-readable medium can include or exclude contents according to the requirements of legislation and patent practice in the jurisdiction, for example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0135] The present application is described with reference to flowcharts and / or block diagrams of methods, devices, and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0136] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0137] These computer program instructions can also be loaded into a computer or other programmable data processing devices, so that a series of operational steps are performed on the computer or other programmable data processing devices to generate a computer implemented process, so that the instructions executed on the computer or other programmable data processing devices provide a process for implementing the functions specified in the flowchart Figure 1 one flow or a plurality of flows and / or the functions specified in the block Figure 1 one block or a plurality of blocks.

[0138] The above is only to illustrate the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical scheme falls within the protection scope of the claims of the present application.

Claims

1. A dynamic current sharing method for silicon carbide power modules, characterized in that, Includes the following steps: Set the basic layout of multi-chip parallel silicon carbide power modules and extract circuit parasitic parameters; Set the operating conditions of the silicon carbide power module, including the bus voltage, load current, and power chip switching speed. The equivalent frequency corresponding to the switching process of the silicon carbide chip is as follows: in, t r The current rise time; A maximum allowable voltage overshoot is set, and the total capacitance of the distributed decoupling capacitor bank is limited based on the voltage overshoot. The voltage overshoot is obtained through circuit simulation, and the peak value of the voltage overshoot after adding the decoupling capacitors is calculated. V p1 and V p2 They are respectively: in, V DC This represents the peak value of the bus voltage. v F_max This represents the maximum voltage drop of the anti-parallel diode or body diode. L in The inductor is the internal power circuit inductor of the power module. L out For the external circuit inductance of the power module, i ds This refers to the current passing through the silicon carbide chip. C 0 represents the total capacitance of the decoupling capacitors. I L The current in the load inductor is... Q 1 (0) and Q 2 (0) This represents the amount of charge applied to the capacitor during the turn-off process. Based on the equivalent impedance of the parallel branches after adding the distributed decoupling capacitor bank at the set switching speed, adjust the capacitance value of the distributed decoupling capacitor bank to make the equivalent impedance of each branch the same.

2. The dynamic current sharing method for silicon carbide power modules according to claim 1, characterized in that, The parasitic parameters of the extracted circuit include the parasitic inductance of the circuit at the frequency corresponding to the set switching speed, and the parasitic inductance of the external busbar circuit and busbar capacitors.

3. The dynamic current sharing method for silicon carbide power modules according to claim 1, characterized in that, The amount of charge on the capacitor during the turn-off process Q 1 (0) and Q 2 (0) They are respectively: in, t 2 represents the time it takes for the voltage to reach the bus voltage. t p1 The time when the bus voltage reaches the first overshoot peak value. t 3 represents the time it takes for the current to reach 0.

4. The dynamic current sharing method for silicon carbide power modules according to claim 1, characterized in that, The maximum permissible voltage overshoot corresponds to the minimum total capacitance value of the distributed decoupling capacitors.

5. The dynamic current sharing method for silicon carbide power modules according to claim 4, characterized in that, The maximum value of the total capacitance of the distributed decoupling capacitor corresponds to the point where the first overshoot peak value is equal to the second overshoot peak value.

6. The dynamic current sharing method for silicon carbide power modules according to claim 1, characterized in that, The equivalent impedance is specifically: in, z s1 , z s2 ... z sn These are the equivalent source impedances of the first to nth parallel silicon carbide chips after adding distributed decoupling capacitors. z s1 '、 z s2 '... z sn 'These are the equivalent source impedances of the first to nth parallel silicon carbide chips before the addition of the distributed decoupling capacitors.' σ 1... σ n-1 These are the impedance adjustment terms after adding distributed decoupling capacitors; the specific values ​​need to be determined based on the circuit layout.

7. The dynamic current sharing method for silicon carbide power modules according to claim 6, characterized in that, The impedance imbalance is reduced by adjusting the capacitance value of the distributed decoupling capacitors. δ Minimum impedance imbalance δ The calculation is as follows: Where, max{ z n } represents the maximum value of the equivalent source impedance, min{ z n } represents the minimum value of the equivalent source impedance. This represents the average value of the equivalent source impedance.

8. A dynamic current sharing system for silicon carbide power modules, characterized in that, include: Extraction module: Set the basic layout of multi-chip parallel silicon carbide power module and extract circuit parasitic parameters; The conditions module sets the operating conditions of the silicon carbide power module, including the bus voltage, load current, and power chip switching speed. The equivalent frequency corresponding to the switching process of the silicon carbide chip is as follows: in, t r The current rise time; The limiting module sets a maximum permissible voltage overshoot and limits the total capacitance of the distributed decoupling capacitor bank based on the voltage overshoot. The voltage overshoot is obtained through circuit simulation, and the peak value of the voltage overshoot after adding the decoupling capacitors is shown. V p1 and V p2 They are respectively: in, V DC This represents the peak value of the bus voltage. v F_max This represents the maximum voltage drop of the anti-parallel diode or body diode. L in The inductor is the internal power circuit inductor of the power module. L out For the external circuit inductance of the power module, i ds This refers to the current passing through the silicon carbide chip. C 0 represents the total capacitance of the decoupling capacitors. I L The current in the load inductor is... Q 1 (0) and Q 2 (0) This represents the amount of charge applied to the capacitor during the turn-off process. The current sharing module adjusts the capacitance value of the distributed decoupling capacitors based on the equivalent impedance of the parallel branches at a set switching speed after adding the distributed decoupling capacitor bank, so that the equivalent impedance of each branch is the same.

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