Inverter control method, system and device, storage medium and computer equipment

Abstract

The invention discloses an inverter control method, system and device, a storage medium and computer equipment. The method is applied to an interleaved multi-level inverter with a plurality of phase voltage output circuits, and comprises the following steps: determining a voltage target vector of a voltage to be output by the interleaved multi-level inverter, and determining a voltage phase vector sequence corresponding to each phase voltage output circuit based on the voltage target vector; based on the level type of the vector level in the voltage phase vector sequence, determining whether various redundant level states exist in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level; and when the phase voltage output circuit has multiple redundant level states within the vector action time, current output of each parallel bridge arm in the phase voltage output circuit is controlled, so that the output state of the phase voltage output circuit is a target state in the multiple redundant level states. According to the scheme, the efficiency of selecting the redundant level state of the interleaved multi-level inverter can be improved.

Description

Technical Field

[0001] The present invention relates to the field of inverter control technology, and in particular to an inverter control method, system, device, storage medium and computer equipment. Background Art

[0002] With the gradual maturity of interleaved parallel multilevel inverters, interleaved parallel multilevel inverters are increasingly used in power systems. Each phase of the interleaved parallel multilevel inverter is composed of multiple parallel bridge arms in parallel. The output ends of these parallel bridge arms are combined into a total output end through multiple filter inductors as the total output of this phase of the inverter. Among them, each parallel bridge arm in the interleaved parallel multilevel inverter is in a two-level working state, that is, when the upper bridge arm of the parallel bridge arm is turned on, it outputs a "1" level, and when the lower bridge arm of the parallel bridge arm is turned on, it outputs a "0" level.

[0003] At present, the selection and optimization of redundant level states is a key issue that needs to be solved in staggered parallel three-level and multi-level space vector control technology, and it is also a difficult issue. For example, a three-level inverter has 19 valid voltage vectors, and the circuit topology of the staggered parallel three-level inverter has 6 parallel bridge arms with two-level output, which can be in 64 output states in total, while the three-level inverter circuit can only have 19 valid voltage vectors. The inverter may output a valid voltage vector through multiple output states. Here, multiple output states are redundant level states.

[0004] Therefore, when the inverter may output a valid voltage vector through multiple redundant level states, it is necessary to select a specific target state from the multiple redundant level states so that the inverter outputs the voltage vector through the target state. At present, the existing redundant level state selection method is through space vector pulse width modulation (SVPWM) control technology, but the traditional SVPWM control technology cannot be directly adapted to the staggered parallel multi-level inverter. It needs to be combined with carrier staggered parallel technology to achieve it. As the number of staggered parallel branches increases, the selection of redundant level states will be very complicated. Therefore, the existing staggered parallel multi-level inverter has low efficiency in selecting redundant level states. Summary of the invention

[0005] In view of this, the present application provides a control method, system, device, storage medium and computer equipment for an inverter, the main purpose of which is to solve the technical problem of low efficiency in redundant level selection of existing staggered parallel multi-level inverters.

[0006] According to a first aspect of the present invention, there is provided a control method for an inverter, which is applied to an interleaved parallel multi-level inverter with a plurality of phase voltage output circuits, each of which is used to output a phase voltage, and is characterized in that the method comprises:

[0007] Determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels;

[0008] Based on the level type of the vector level in the voltage phase vector sequence, determining whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level;

[0009] When there are multiple redundant level states in the phase voltage output circuit within the vector action time, the current output state of each parallel bridge arm in the phase voltage output circuit is controlled so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

[0010] According to a second aspect of the present invention, there is provided an inverter control system, which is applied to an interleaved parallel multi-level inverter with a plurality of phase voltage output circuits, each of which is used to output a phase voltage, and the system comprises a system controller and a plurality of redundant level selection circuits, wherein the redundant level selection circuits correspond one to one with the phase voltage output circuits;

[0011] The system controller is used to determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels;

[0012] The redundant level selection circuit is used to receive the voltage phase vector sequence corresponding to the redundant level selection circuit, and determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence;

[0013] The redundant level selection circuit is also used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within the vector action time, so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

[0014] According to a third aspect of the present invention, there is provided a control device for an inverter, the device comprising:

[0015] A sequence generation module, used to determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels;

[0016] A redundancy determination module, configured to determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence;

[0017] A level selection module is used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within the vector action time, so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

[0018] According to a fourth aspect of the present invention, there is provided a storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the control method of the inverter described above, wherein the storage medium may be ROM, EPROM, EEPROM, FLASH, etc.

[0019] According to a fifth aspect of the present invention, there is provided a computer device, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the control method of the inverter when executing the program, wherein the execution unit of the computer program is not limited to a computer, but may also include a single-chip microcomputer MCU, a data signal processor DSP, a programmable logic array (CPLD or FPGA), etc.

[0020] The present invention provides an inverter control method, system, device, storage medium and computer equipment. First, a voltage target vector corresponding to a voltage to be output by an interleaved parallel multi-level inverter is determined. Then, based on the voltage target vector, it is determined that the interleaved parallel multilevel inverter outputs the above voltage, wherein each phase voltage output circuit thereof respectively presents a voltage phase vector sequence corresponding to the phase voltage to be output, wherein the voltage phase vector sequence is composed of a plurality of vector levels arranged in sequence; then, based on the level type of the vector level in the voltage phase vector sequence, it is determined whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level, wherein the vector level includes an intermediate level; further, when there are multiple redundant level states in the phase voltage output circuit within the vector action time, the current output of each parallel bridge arm in the phase voltage output circuit is controlled, and multiple redundant level states are reasonably selected to meet the control target of achieving the convergence of the current output of each parallel bridge arm of the phase voltage output circuit, so that the output current of one parallel bridge arm with a larger output current in the phase voltage output circuit is reduced, and the output current of one parallel bridge arm with a smaller output current is increased, so as to select the target state from the multiple redundant level states according to the principle of convergence of the current output of each parallel bridge arm in the same phase voltage output circuit, so as to achieve the selection of the redundant level state. The technical solution of the present application can significantly improve the efficiency of selecting redundant level states for staggered parallel multi-level inverters.

[0021] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0023] Figure 1 A schematic structural diagram of a parallel bridge arm provided by an embodiment of the present invention is shown;

[0024] Figure 2 A schematic structural diagram of a phase voltage output circuit provided as an example in an embodiment of the present invention is shown;

[0025] Figure 3 A schematic diagram of a space voltage vector diagram provided by an embodiment of the present invention is shown;

[0026] Figure 4A schematic flow chart of a control method for an inverter provided by an embodiment of the present invention is shown;

[0027] Figure 5 A schematic flow chart of a method for determining a voltage phase vector sequence corresponding to each phase voltage output circuit based on a voltage target vector provided by an embodiment of the present invention is shown;

[0028] Figure 6 A schematic diagram showing a voltage target vector in a space voltage vector diagram provided by an embodiment of the present invention is shown;

[0029] Figure 7 A schematic diagram of a voltage phase vector sequence provided by an embodiment of the present invention is shown;

[0030] Figure 8 One of the structural schematic diagrams of a control system of an inverter provided by an embodiment of the present invention is shown;

[0031] Fig. 9 A second structural schematic diagram of a control system of an inverter provided by an embodiment of the present invention is shown;

[0032] Fig.10 A schematic diagram showing the structure of a redundant level selection circuit provided by an embodiment of the present invention is shown;

[0033] Fig.11 A third structural schematic diagram of a control system of an inverter provided by an embodiment of the present invention is shown;

[0034] Fig.12 A schematic structural diagram showing a connection between a switching circuit and a bridge arm control circuit provided by an embodiment of the present invention is shown;

[0035] Fig.13 A schematic structural diagram of a four-level phase voltage output circuit provided by an embodiment of the present invention is shown;

[0036] Fig.14 A schematic structural diagram of a control device for an inverter provided in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0037] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0038] At present, the selection and optimization of redundant level states is a key issue that needs to be addressed in the interleaved parallel three-level and multi-level space vector control technology. Here, the existing interleaved parallel multilevel inverter has multiple phase voltage output circuits, each phase voltage output circuit is used to output a phase voltage. If the interleaved parallel multilevel inverter is a three-phase inverter, the interleaved parallel multilevel inverter includes three phase voltage output circuits, each phase voltage output circuit is used to output a phase voltage. Furthermore, according to the number of levels that the interleaved parallel multilevel inverter can output, each phase voltage output circuit includes multiple parallel bridge arms, such as Figure 1 As shown, each parallel bridge arm includes an upper bridge arm and a lower bridge arm, each of which has a power switch, and the output end of the parallel bridge arm is connected to an inductor, and the filtered voltage and bridge arm current are output to the outside through the inductor; here, if the staggered parallel multi-level inverter is a three-level inverter, then each phase voltage output circuit in the staggered parallel multi-level inverter includes two parallel bridge arms, and if the staggered parallel multi-level inverter is a four-level inverter, then each phase voltage output circuit in the staggered parallel multi-level inverter includes three parallel bridge arms. Further, the output end of each parallel bridge arm is respectively connected to the first end of an inductor, and the output end of each parallel bridge arm corresponds to an inductor, and the second end of each inductor is combined into an output end to constitute the total output of the phase, and output current to the motor or grid side.

[0039] In the embodiment of the present application, an interleaved parallel multilevel inverter is taken as an example for explanation of an inverter with three-phase output (three phases include U phase, V phase and W phase), the inverter includes three phase voltage output circuits, each phase voltage output circuit is formed by n parallel bridge arms in parallel, and the output ends of the n parallel bridge arms are respectively combined into a total output end through n inductors as the total output of this phase of the inverter. Interleaved parallel multilevel inverters with other phase numbers are also applicable to this embodiment.

[0040] Furthermore, each parallel bridge arm in the staggered parallel multi-level inverter is in a two-level working state, that is, outputting a "1" level (the power switch in the upper bridge arm of the parallel bridge arm is turned on, so that the upper bridge arm is turned on) or a "0" level (the power switch in the lower bridge arm of the parallel bridge arm is turned on, so that the lower bridge arm is turned on). Furthermore, when the power switch in the upper bridge arm of the parallel bridge arm is turned on, the current output by the parallel bridge arm increases, and when the power switch in the lower bridge arm of the parallel bridge arm is turned on, the current output by the parallel bridge arm decreases. The power switches in the upper and lower bridge arms cannot be turned on at the same time.

[0041] Furthermore, the total output of the three phases of the staggered parallel multi-level inverter can synthesize and output multiple levels, namely, the output of "1" level, "0" level and (n-1) intermediate levels, namely (n-1) / n, (n-2) / n, ..., 1 / n, where "1" level is a high level and "0" is a low level. Here, when the upper bridge arms of all parallel bridge arms of the phase voltage output circuit are turned on, the phase voltage output circuit outputs a "1" level, and when the lower bridge arms of all parallel bridge arms of the phase voltage output circuit are turned on, the phase voltage output circuit outputs a "0" level. The output state of the phase voltage output circuit is the state in which a specific parallel bridge arm in the phase voltage output circuit outputs a "1" level and other parallel bridge arms output a "0" level.

[0042] Furthermore, the generation of n-1 intermediate levels of the phase voltage output circuit is formed by the combination of some parallel bridge arm circuits used for the phase voltage output circuit outputting the "1" level and some parallel bridge arm circuits outputting the "0" level. For example, the phase voltage output circuit has n parallel bridge arms, and the (n-5) / n level is obtained by the combination of (n-5) parallel bridge arms outputting the "1" level and 5 parallel bridge arms outputting the "0" level. Furthermore, when the phase voltage output circuit outputs an intermediate level, the phase voltage output circuit can be in a variety of output states to output the intermediate level, and the number of output states that the phase voltage output circuit can be in when outputting the intermediate level is the number of redundant level states when the phase voltage output circuit outputs the intermediate level. Therefore, the above-mentioned (n-1) intermediate levels will become an important optimization factor for the control of the interleaved parallel multi-level inverter. How to design and select the control circuit in the space vector control is more complicated than the traditional multi-level inverter.

[0043] Further, taking a three-level interleaved parallel multi-level inverter as an example, Figure 2 As shown, a phase voltage output circuit of a three-level interleaved parallel multi-level inverter includes two parallel bridge arms, wherein the first parallel bridge arm is composed of a first power switch T1 in an upper bridge arm and a second power switch T2 in a lower bridge arm, and the output end of the first parallel bridge arm is connected to the first end of the first inductor L1; further, the second parallel bridge arm is composed of a third power switch T3 in an upper bridge arm and a fourth power switch T4 in a lower bridge arm, and the output end of the second parallel bridge arm is connected to the first end of the second inductor L2; further, the second end of the first inductor L1 is connected to the second end of the second inductor L2, forming the total output of the phase voltage output circuit, which is used to output a phase voltage. Wherein, the first power switch T1, the second power switch T2, the third power switch T3 and the fourth power switch T4 can be switch tubes respectively.

[0044] Further, when the first power switch T1 and the third power switch T3 are turned on and the other power switches are turned off, the level state of the phase voltage output circuit output is a high level, and the level state of the high level is U here; when the first power switch T1 and the fourth power switch T4 are turned on and the other power switches are turned off, the level state of the phase voltage output circuit output is an intermediate level, and the level state of the intermediate level is U / 2 here; when the second power switch T2 and the third power switch T3 are turned on and the other power switches are turned off, the level state of the phase voltage output circuit output is also an intermediate level, and the level state of the intermediate level is U / 2 here; when the second power switch T2 and the fourth power switch T4 are turned on and the other power switches are turned off, the level state of the phase voltage output circuit output is a low level, and the level state of the low level is 0 here. The interleaved parallel multi-level inverter here can achieve three-level output, and the interleaved parallel inverter can generate more level outputs by simply increasing the parallel bridge arms in the phase voltage output circuit.

[0045] Here, when the level state of the phase voltage output circuit output is an intermediate level, the output state of the phase voltage output circuit includes output state 1 and output state 2, wherein output state 1 is that the first power switch T1 and the fourth power switch T4 are turned on, and the other power switches are turned off, and output state 2 is that the second power switch T2 and the third power switch T3 are turned on, and the other power switches are turned off. It can be seen that the phase voltage output circuit outputs an intermediate level, and its output state can be in output state 1 or output state 2. Here, output state 1 and output state 2 are redundant level states of the phase voltage output circuit. When the phase voltage output circuit is to output an intermediate level, it is necessary to select a target state from the redundant level state, and this process is the redundant level state selection process.

[0046] Furthermore, taking the interleaved parallel three-level inverter as an example, the existing interleaved parallel three-level inverter has low efficiency in selecting redundant level states, and it is necessary to utilize the mature NPC three-level inverter control method to optimize the efficiency of redundant level state selection of the interleaved parallel three-level inverter.

[0047] Here, the NPC three-level inverter is also called a neutral point clamped (NPC) inverter, which is a relatively mature multi-level topology structure. It also has the problem of redundant level state selection, but because there are only 27 level state combinations in the NPC three-level inverter, the number of redundant level states is much smaller than that of the staggered parallel three-level inverter. At present, the control method of the NPC three-level inverter is very mature, and the method usually selected is through the space vector pulse width modulation (SVPWM) control technology, but the traditional SVPWM control technology used for the NPC three-level inverter cannot be directly adapted to the staggered parallel three-level inverter because of the different number of redundant level states.

[0048] However, through reasonable control strategy optimization, the mature control strategy of the NPC three-level inverter can be utilized, combined with the selection principle of the redundant level state of the staggered parallel inverter, to form a selection method and circuit that meets the redundant level state of the staggered parallel three-level inverter.

[0049] like Figure 3 The spatial voltage vector diagram of the NPC three-level inverter is given, in which 19 effective voltage vectors are represented by 19 arrows, and these vector arrows form a number of triangular sectors.

[0050] Furthermore, since the NPC three-level inverter has 27 output combinations of level states, called NPC vertex vectors, assigned to Figure 3 19 voltage vectors.

[0051] Taking the vertex vector opn pointing directly upward as an example, its meaning is: the U phase of the three-level inverter outputs the intermediate level o, the V phase outputs the high level p, and the W phase outputs the low level n. The three output level vectors are further called vertex sub-vectors corresponding to the U, V, and W phases of the vertex vector.

[0052] Further, according to the above control strategy, the triangular sector where the voltage target vector is located in the spatial voltage vector diagram of the NPC three-level inverter can be determined first, and the NPC vertex vector of the triangular sector can be determined, and each NPC vertex vector of the phase voltage output by the phase voltage output circuit can be further determined, and the action time of the NPC vertex vector and the vertex vector can be calculated. Further, the vector levels corresponding to each NPC vertex vector of the phase voltage output circuit are arranged to obtain the voltage phase vector sequence corresponding to the phase voltage output circuit.

[0053] Further, according to the voltage phase vector sequence, there is an NPC vertex vector with an intermediate level "o", which is a vector with multiple redundant level state vector action times. Because the circuit topology of the staggered parallel three-level inverter has 6 half-bridge circuits with two-level output, a total of 64 output level states can be generated. However, there are only 19 valid voltage vectors corresponding to the three-level inverter circuit, and each valid voltage vector corresponds to more redundant level states than the NPC three-level inverter. Specifically, the intermediate level "o" of the NPC three-level inverter circuit can correspond to the redundant levels of 2 staggered parallel inverters.

[0054] Furthermore, Figure 3 In the spatial voltage vector diagram of the NPC three-level inverter shown in FIG, 27 NPC vertex vectors are assigned to the vertices of each triangle. If each NPC vertex vector contains an intermediate level "o", it can correspond to the two redundant level states of the staggered parallel three-level inverter. Based on this relationship principle, Table 1 lists the corresponding quantity relationship of the redundant levels of the second type of three-level inverter.

[0055]

[0056] Table 1

[0057] Based on the above-mentioned prior art control strategy, in one embodiment, Figure 4 As shown, a control method for an inverter is provided, and the method is described by taking the application of the method to an interleaved parallel multi-level inverter with multiple phase voltage output circuits as an example, and includes the following steps:

[0058] 101. Determine a voltage target vector corresponding to a voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector.

[0059] Among them, the voltage phase vector of the voltage to be output by the staggered parallel multi-level inverter is calculated according to the requirements of the corresponding control object; further, the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels, and the vector action time of each vector level is the continuous action time of the vector level.

[0060] Specifically, the existing method of calculating the voltage target vector of the voltage to be outputted by the staggered parallel multilevel inverter is as follows: based on the mathematical model and control strategy of the inverter's control object (such as a motor or a power grid), the motor position signal or the three-phase input voltage of the power grid is calculated, and the space vector control calculation is performed using the output current and other signals of the inverter to obtain the current voltage target vector. Here, the method of calculating the voltage target vector may also use other existing calculation methods, which are not limited here and are also applicable to this embodiment. Furthermore, the voltage to be outputted by the staggered parallel multilevel inverter may be continuously determined within the space vector control cycle and the voltage target vector of the voltage may be calculated, and the frequency of the voltage target vector may be determined to be used as the calculation frequency of the space vector operation.

[0061] Further, after determining the voltage target vector of the voltage to be output by the interleaved parallel multilevel inverter, for each phase voltage output circuit in the interleaved parallel multilevel inverter, a voltage phase vector sequence corresponding to each phase voltage output circuit is determined based on the voltage target vector, such as Figure 5 As shown, based on the voltage target vector, a voltage phase vector sequence corresponding to each phase voltage output circuit is determined, including:

[0062] S201. Determine the triangular sector where the voltage target vector is located in the spatial voltage vector diagram, determine the NPC vertex vector of the triangular sector, and determine multiple NPC vertex vectors of the phase voltage output by each phase voltage output circuit based on the NPC vertex vector.

[0063] As an example, this embodiment is described by taking an interleaved parallel multilevel inverter that is a three-level three-phase interleaved parallel multilevel inverter as an example. The calculation of vertex vector components of other types of interleaved parallel multilevel inverters may refer to this embodiment.

[0064] As an example, the three-level inverter space voltage vector diagram is composed of multiple triangular sectors. Figure 6As shown, the triangle sector where the voltage target vector is located in the space voltage vector diagram is triangle sector 5, and the NPC vertex vectors of triangle sector 5 are "pon", "pnn", "poo" and "onn" respectively; wherein the NPC vertex vector "poo" and the NPC vertex vector "onn" belong to the same vertex of triangle sector 5, and the two are called NPC redundant level vectors. Further, based on the space voltage vector diagram, it can be determined that the NPC vertex vectors of the phase voltage output circuit of the U-phase electricity are p, p, p and o respectively, the NPC vertex vectors of the phase voltage output circuit of the V-phase electricity are o, n, o and n respectively, and the NPC vertex vectors of the phase voltage output circuit of the W-phase electricity are n, n, o and n respectively. Among them, the NPC vertex vector p represents a high level, the NPC vertex vector o represents an intermediate level, and the NPC vertex vector n represents a low level.

[0065] Furthermore, "poo" and "onn" are used as NPC redundant level vectors. Among the multiple NPC vertex sub-vectors of the phase voltage output circuit of the U-phase electricity, the NPC vertex sub-vectors corresponding to the NPC redundant level vectors are p and o, among the multiple NPC vertex sub-vectors of the phase voltage output circuit of the V-phase electricity, the NPC vertex sub-vectors corresponding to the NPC redundant level vectors are o and n, and among the multiple NPC vertex sub-vectors of the phase voltage output circuit of the W-phase electricity, the NPC vertex sub-vectors corresponding to the NPC redundant level vectors are o and n.

[0066] S202: Determine the vector action time of each of the NPC vertex component vectors of the phase voltage output by the phase voltage output circuit.

[0067] Specifically, in the existing technology, the volt-second balance principle of vector action is often used to calculate the vertex vector action time of each vertex of the triangular sector where the voltage target vector is located. When there are multiple NPC redundant level vectors at a vertex of the triangular sector, these NPC redundant level vectors evenly or unevenly distribute the vertex vector action time corresponding to the vertex.

[0068] As an example, Figure 6The NPC vertex vectors of the triangle sector 5 shown are "pon", "pnn", "poo" and "onn", respectively, wherein the NPC vertex vector "pon" and the NPC vertex vector "pnn" are not NPC redundant level vectors, therefore, the action time of the NPC vertex vector "pon" is the same as the vertex vector action time of the vertex corresponding to it, and similarly, the action time of the NPC vertex vector "pnn" is the same as the vertex vector action time of the vertex corresponding to it. For example, if the vertex vector action time of the vertex corresponding to the NPC vertex vector "pon" is A milliseconds, and the vertex vector action time of the vertex corresponding to the NPC vertex vector "pnn" is B milliseconds, then the vector action time of the U-phase electric phase voltage output circuit and the NPC vertex sub-vector p corresponding to the NPC vertex vector "pon" is A milliseconds, and the vector action time of the U-phase electric phase voltage output circuit and the NPC vertex sub-vector p corresponding to the NPC vertex vector "pnn" is B milliseconds.

[0069] In contrast, the NPC vertex vectors "poo" and "onn" are a set of NPC redundant level vectors, and the NPC vertex vectors "poo" and "onn" correspond to the same vertex of the triangle sector 5, and the sum of the action times of the NPC vertex vectors "poo" and "onn" is equal to the vertex vector action time of the vertex. Here, the NPC vertex sub-vectors corresponding to the NPC vertex vectors "poo" and "onn" of the phase voltage output circuit of the U-phase electricity are NPC vertex sub-vectors p and NPC vertex sub-vector o, respectively, and the sum of the vector action times of the NPC vertex sub-vector p and NPC vertex sub-vector o is equal to the vertex vector action time of the vertex corresponding to the NPC vertex vectors "poo" and "onn". For example, if the vertex vector action time of the vertex corresponding to the NPC vertex vectors "poo" and "onn" is 30 milliseconds, then the vector action times of the NPC vertex sub-vector p and NPC vertex sub-vector o can be 10 milliseconds and 20 milliseconds, and the vector action times of the NPC vertex sub-vector p and NPC vertex sub-vector o can also be 15 milliseconds and 15 milliseconds.

[0070] Furthermore, if the number of NPC redundant level vectors corresponding to a vertex of the triangular sector is greater than 2, the sum of the action times of each NPC vertex vector in the NPC redundant level vector is equal to the vertex vector action time of the vertex, and the sum of the vector action times of the NPC vertex sub-vectors corresponding to the vertex in each phase voltage output circuit is equal to the vertex vector action time of the vertex, wherein the distribution method of the vector action time of each NPC vertex sub-vector can be determined according to actual conditions.

[0071] Furthermore, the method for determining the vector action time of each NPC vertex vector in other phase voltage output circuits can refer to the above description process, which will not be repeated here.

[0072] Here, the vector action time of the NPC vertex component vector is correspondingly decomposed into the duration of the NPC vertex component vector of each phase voltage output circuit. Further, for each phase voltage output circuit, each NPC vertex component vector corresponding to the phase voltage output circuit acts in turn within the vector action time corresponding to the NPC vertex component vector, and a voltage target vector corresponding to the phase voltage output circuit can be generated.

[0073] S203 , arranging the vector levels corresponding to each of the NPC vertex vector components of the phase voltage output circuit to obtain the voltage phase vector sequence corresponding to the phase voltage output circuit.

[0074] As an example, if the NPC vertex vectors of the phase voltage output circuit outputting U-phase electricity are p, p, p and o, according to different control requirements, the vertex vector action time of the three vertices of the triangle in the space voltage vector diagram can be allocated in 4-segment allocation, 5-segment allocation and 7-segment allocation. This example adopts the 7-segment allocation method, and the result is as follows Figure 7 The voltage phase vector sequence of the phase voltage output circuit of the output U-phase electricity is shown.

[0075] By means of the above method, the voltage phase vector sequence of each phase voltage output circuit of the interleaved parallel multilevel inverter can be quickly determined, thereby improving the efficiency of selecting the redundant level state of the interleaved parallel multilevel inverter.

[0076] 102. Based on the level type of the vector level in the voltage phase vector sequence, determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level.

[0077] Specifically, for a voltage phase vector sequence of a phase voltage output circuit, it is possible to determine whether the vector levels in the voltage phase vector sequence are intermediate levels according to the arrangement order of the vector levels in the voltage phase vector sequence. If the vector level is the intermediate level o, it is determined that there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level. Conversely, if the vector level is a high level p or a low level n, it is determined that there are no multiple redundant level states in the phase voltage output circuit within the vector action time corresponding to the vector level.

[0078] Furthermore, for other phase voltage output circuits of the interleaved parallel multi-level inverter, the above method can be used to determine whether there are multiple redundant level states in the output state of other phase voltage output circuits during the vector action time corresponding to the vector level in the voltage phase vector sequence, which will not be elaborated here.

[0079] 103. When there are multiple redundant level states in the phase voltage output circuit during the vector action time, the current output state of each parallel bridge arm in the phase voltage output circuit is controlled to make the output state of the phase voltage output circuit be in a target state among the multiple redundant level states.

[0080] Wherein, when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases during the vector action time. Specifically, the strategy for selecting the redundant level state is to select the redundant level state according to the principle that the currents output by each parallel bridge arm of the same phase converge. During the vector action time period of this half-bridge complementary output state, the output current of the parallel bridge arm with a larger current is reduced and the output current of the parallel bridge arm with a smaller current is increased by selecting the upper and lower bridge arms of the complementary parallel bridge arm, so that the difference between the output currents of each parallel bridge arm in the phase voltage output circuit is reduced during the vector action time, and then the redundant level state in which the currents output by each parallel bridge arm converge is selected as the target state. Furthermore, for each phase voltage output circuit, when the phase voltage output circuit has multiple redundant level states during the vector action time of a vector level in the voltage phase vector sequence, the target state can be selected from multiple redundant level states in the above manner.

[0081] The present invention provides a control method for an inverter. First, a voltage target vector corresponding to a voltage to be output by an interleaved parallel multi-level inverter is determined. Then, based on the voltage target vector, it is determined that the interleaved parallel multilevel inverter outputs the above voltage, wherein each phase voltage output circuit thereof respectively presents a voltage phase vector sequence corresponding to the phase voltage to be output, wherein the voltage phase vector sequence is composed of a plurality of vector levels arranged in sequence; then, based on the level type of the vector level in the voltage phase vector sequence, it is determined whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level, wherein the vector level includes an intermediate level; further, when there are multiple redundant level states in the phase voltage output circuit within the vector action time, the current output of each parallel bridge arm in the phase voltage output circuit is controlled, and multiple redundant level states are reasonably selected to meet the control target of achieving the convergence of the current output of each parallel bridge arm of the phase voltage output circuit, so that the output current of one parallel bridge arm with a larger output current in the phase voltage output circuit is reduced, and the output current of one parallel bridge arm with a smaller output current is increased, so as to select the target state from the multiple redundant level states according to the principle of convergence of the current output of each parallel bridge arm in the same phase voltage output circuit, so as to achieve the selection of the redundant level state. The technical solution of the present application can significantly improve the efficiency of selecting redundant level states for staggered parallel multi-level inverters.

[0082] In an optional embodiment, the implementation method of controlling the current output state of each parallel bridge arm in the phase voltage output circuit in step S103 includes:

[0083] First, during the vector action time of the NPC vertex vector with an intermediate level, when the output state of the phase voltage output circuit has multiple redundant level states, the bridge arm currents output by all the parallel bridge arms in the phase voltage output circuit are received, and based on the bridge arm currents output by all the parallel bridge arms, overcurrent parallel bridge arms and undercurrent parallel bridge arms are determined among all the parallel bridge arms.

[0084] Specifically, at least one parallel bridge arm with a larger output current among all the parallel bridge arms can be used as an overcurrent parallel bridge arm, and at least one parallel bridge arm with a smaller output current among all the parallel bridge arms can be used as an undercurrent parallel bridge arm.

[0085] Further, the bridge arm current output by the overcurrent parallel bridge arm is reduced, and the bridge arm current output by the undercurrent parallel bridge arm is increased. Here, the method of reducing the bridge arm current output by the overcurrent parallel bridge arm includes: sending a low-level signal to the base of the power switch in the upper bridge arm of the overcurrent parallel bridge arm, and sending a high-level signal to the base of the power switch in the lower bridge arm of the overcurrent parallel bridge arm. Further, increasing the bridge arm current output by the undercurrent parallel bridge arm includes: sending a high-level signal to the base of the power switch in the upper bridge arm of the undercurrent parallel bridge arm, and sending a low-level signal to the base of the power switch in the lower bridge arm of the undercurrent parallel bridge arm. In the embodiment provided by the present application, based on the principle of "relative convergence" of the output current values ​​of each parallel bridge arm, the parallel bridge arm with a larger output current is determined as an overcurrent parallel bridge arm, and the parallel bridge arm with a smaller output current is determined as an undercurrent parallel bridge arm, and the output current of the overcurrent parallel bridge arm is reduced within the vector action time, and the output current of the undercurrent parallel bridge arm is increased within the vector action time, so as to select a redundant level state according to the principle of current convergence, thereby improving the efficiency of selecting the redundant level state of the staggered parallel multi-level inverter.

[0086] In an optional embodiment, the receiving of the bridge arm current outputted by all the parallel bridge arms in the phase voltage output circuit is implemented by: taking a preset time interval as a receiving period, continuously receiving the bridge arm current outputted by all the parallel bridge arms in the phase voltage output circuit. The preset time interval is less than the vector action time, and the time length of the preset time interval can be determined according to actual conditions. Furthermore, the frequency of receiving the bridge arm current outputted by all the parallel bridge arms in the phase voltage output circuit can be used as the calculation frequency of the redundant level state selection, so that the calculation frequency of the redundant level state selection is much greater than the calculation frequency of the space vector operation.

[0087] Specifically, when there are multiple redundant level states within the vector action time, the bridge arm current output by each parallel bridge arm is collected once at a preset time interval, and the overcurrent parallel bridge arm and the undercurrent parallel bridge arm are determined in the parallel bridge arm, the bridge arm current of the undercurrent parallel bridge arm is increased and the bridge arm current of the overcurrent parallel bridge arm is reduced; further, after the preset time interval, the bridge arm current output by each parallel bridge arm is collected again, and the overcurrent parallel bridge arm and the undercurrent parallel bridge arm are determined in the parallel bridge arm, the bridge arm current of the undercurrent parallel bridge arm is increased and the bridge arm current of the overcurrent parallel bridge arm is reduced, so as to repeat the above steps within the vector action time, so that the bridge arm currents of each parallel bridge arm of the phase voltage output circuit converge within the vector action time. Then, the redundant level state of "current convergence" is selected.

[0088] The embodiments provided in the present application enable a phase voltage output circuit to select a target state from multiple redundant level states based on the principle of "comparative convergence" when multiple redundant level states appear within one vector action time, thereby improving the effectiveness of redundant level state selection of an interleaved parallel multi-level inverter.

[0089] In an optional embodiment, the method of determining the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in all the parallel bridge arms based on the bridge arm current output by all the parallel bridge arms includes: first, obtaining the bridge arm current output by each of the parallel bridge arms. Then, all the bridge arm currents are arranged into a bridge arm current queue in descending order of current value; as an example, if the staggered parallel multi-level inverter is a three-level inverter, one of the phase voltage output circuits includes two parallel bridge arms, one of which outputs a bridge arm current of 1A and the other outputs a bridge arm current of 0.5A, then the bridge arm current of 1A in the bridge arm current queue is arranged at the first position in the bridge arm current queue, and the bridge arm current of 0.5A is arranged at the second position in the bridge arm current queue. Similarly, if the staggered parallel multi-level inverter is a four-level inverter, one of the phase voltage output circuits includes three parallel bridge arms, and the three parallel bridge arms output bridge arm currents of 1A, 0.5A and 0.3A respectively, then the bridge arm current of 1A in the bridge arm current queue is arranged at the first place in the bridge arm current queue, the bridge arm current of 0.5A is arranged at the second place in the bridge arm current queue, and the bridge arm current of 0.3A is arranged at the third place in the bridge arm current queue.

[0090] Finally, the parallel bridge arms corresponding to the first preset number of bridge arm currents arranged in the bridge arm current queue are determined as overcurrent parallel bridge arms, and all parallel bridge arms except the overcurrent parallel bridge arms in all the parallel bridge arms are determined as undercurrent parallel bridge arms. Among them, the value of the preset number can be determined according to the actual situation. Among them, the value of the preset number can be determined according to the level grade of the intermediate level. For the intermediate levels of different level grades, a preset number of specific values ​​can be preset for the intermediate level. Within the vector action time of the NPC vertex vector of the intermediate level, the level grade of the intermediate level can be determined, and the preset number corresponding to the level grade is determined, and the parallel bridge arms corresponding to the first preset number of bridge arm currents are selected in the bridge arm current queue as overcurrent parallel bridge arms.

[0091] Furthermore, taking the parallel output of the phase voltage output circuit through n parallel bridge arms as an example, the phase voltage output circuit can synthesize and output multiple levels, namely, level 1 (high level), level 0 (low level) and (n-1) intermediate level outputs, and the level grades of the intermediate levels include (n-1) / n, (n-2) / n,..., 1 / n.

[0092] Among them, the 1 level or "0" level output by the phase voltage output circuit is realized by the circuits of all parallel bridge arms outputting 1 level or all half-bridge circuits outputting "0" level. Further, the implementation mode of the n-1 intermediate levels output by the phase voltage output circuit is that some parallel bridge arms of all parallel parallel bridge arms output "1" level, and some parallel bridge arms output "0" level. Here, the parallel bridge arm outputting 1 level can be an undercurrent parallel bridge arm, and the parallel bridge arm outputting "0" level can be an overcurrent parallel bridge arm. For example, the (n-5) / n level is obtained by combining (n-5) undercurrent parallel bridge arms outputting 1 and 5 overcurrent parallel bridge arms outputting "0" level. This intermediate level requires redundant level state selection. The principle of redundant level state selection of the above intermediate level is to realize the principle of "relative convergence" of the output current value of each parallel bridge arm by dividing the n parallel bridge arms into undercurrent parallel bridge arms and overcurrent parallel bridge arms.

[0093] When selecting undercurrent parallel bridge arms and overcurrent parallel bridge arms, it is first necessary to sort the bridge arm currents of the n parallel bridge arms from large to small, and then the required number of parallel bridge arms in the high current area are called overcurrent parallel bridge arms, and the rest are undercurrent parallel bridge arms.

[0094] For example, a four-level interleaved parallel inverter has two undercurrent bridge arms and one overcurrent bridge arm when outputting a 0.67U level, and one undercurrent bridge arm and two overcurrent bridge arms when outputting a 0.33U level.

[0095] As an example, if the interleaved parallel multi-level inverter is a three-level inverter, the preset number can be determined as 1, the parallel bridge arm that outputs a larger bridge arm current in the phase voltage output circuit is determined as an overcurrent parallel bridge arm, and the parallel bridge arm that outputs a smaller bridge arm current in the phase voltage output circuit is determined as an undercurrent parallel bridge arm. Similarly, if the interleaved parallel multilevel inverter is a four-level inverter, the interleaved parallel multilevel inverter can output two intermediate levels, namely 0.67U level and 0.33U level, then the preset number corresponding to the 0.67U level can be set to 1, and the preset number corresponding to the 0.33U level can be set to 2. Within the vector action time of the NPC vertex sub-vector of 0.67U, the parallel bridge arm corresponding to the bridge arm current with the highest current value in the bridge arm current queue can be determined as the overcurrent parallel bridge arm. Within the vector action time of the NPC vertex sub-vector of 0.33U, the parallel bridge arms corresponding to the bridge arm current with the highest current value and the bridge arm current with the second highest current value in the bridge arm current queue can be determined as the overcurrent parallel bridge arms.

[0096] The embodiments provided in the present application can quickly determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in the phase voltage output circuit, thereby improving the efficiency of selecting the redundant level state of the staggered parallel multi-level inverter.

[0097] The control method of the inverter provided in this embodiment controls the bridge arm current of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within a specific vector action time, and selects the redundant level state based on the principle of current convergence, so that the space vector calculation cycle is decoupled from the redundant level conversion cycle, thereby significantly improving the efficiency of selecting the redundant level state of the staggered parallel multi-level inverter. Further, the space vector calculation cycle is decoupled from the redundant level conversion cycle, and the redundant level conversion cycle can be increased without increasing the space vector calculation cycle, which is conducive to reducing the output current harmonics of the staggered parallel inverter. Further, the control method of the inverter given in this embodiment can be implemented by software, and the execution unit of the software is not limited to a computer, but can also include a single-chip microcomputer MCU, a data signal processor DSP, a programmable logic array (CPLD or FPGA), etc. Further, the storage medium can be ROM, EPROM, EEPROM, FLASH, etc.

[0098] Further, such as Figure 8As shown, the embodiment of the present application also provides a control system for an inverter, which is applied to an interleaved parallel multi-level inverter with multiple phase voltage output circuits, each of which is used to output a phase voltage. The system includes a system controller 810 and multiple redundant level selection circuits 820, and the redundant level selection circuits 820 correspond to the phase voltage output circuits one by one. Here, the system controller 810 can be a computer device with certain computing capabilities such as a single-chip microcomputer, a digital signal processor, and a central processing unit (CPU).

[0099] Furthermore, the system controller 810 is used to determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels.

[0100] Furthermore, the redundant level selection circuit 820 is used to receive the voltage phase vector sequence corresponding to the redundant level selection circuit, and based on the level type of the vector level in the voltage phase vector sequence, determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level.

[0101] Here, after the system controller 810 determines a voltage phase vector sequence corresponding to a phase voltage output circuit, the voltage phase vector sequence is sent to the redundant level selection circuit 820 corresponding to the phase voltage output circuit, so that the redundant level selection circuit 820 determines whether there are multiple redundant level states in the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence.

[0102] Furthermore, the redundant level selection circuit 820 is also used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within the vector action time, so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

[0103] Specifically, the redundant level selection circuit is used to control the bridge arm current output by each parallel bridge arm in the corresponding phase voltage output circuit; here, the redundant level selection circuit is connected to the base of the power switch in the upper bridge arm and the base of the power switch in the lower bridge arm in the parallel bridge arm in the phase voltage output circuit. When it is necessary to increase the bridge arm current output by the parallel bridge arm, a high level signal is sent to the power switch of the upper bridge arm of the parallel bridge arm, and a low level signal is sent to the power switch of the lower bridge arm of the parallel bridge arm, so that the power switch of the upper bridge arm is turned on and the power switch of the lower bridge arm is turned off, thereby increasing the bridge arm current output by the parallel bridge arm; conversely, when it is necessary to reduce the bridge arm current output by the parallel bridge arm, a high level signal is sent to the power switch of the lower bridge arm of the parallel bridge arm, and a low level signal is sent to the power switch of the upper bridge arm of the parallel bridge arm, so that the power switch of the lower bridge arm is turned on and the power switch of the upper bridge arm is turned off, thereby reducing the bridge arm current output by the parallel bridge arm.

[0104] Further, such as Fig. 9 As shown, the redundant level selection circuit 820 includes a switch circuit 821 and a plurality of bridge arm control circuits 822. Specifically, the switch circuit 821 is connected to the system controller 810 to obtain a voltage phase vector sequence. Each of the bridge arm control circuits 822 is used to control the level output state of a parallel bridge arm (not shown in the figure); specifically, each bridge arm control circuit 822 is connected to the base of the power switch of the upper bridge arm and the base of the power switch of the lower bridge arm in the parallel bridge arm corresponding to the bridge arm control circuit 822, and is used to control the conduction and disconnection of the upper bridge arm and the lower bridge arm of the parallel bridge arm by sending a high level signal or a low level signal to the base of the power switch. Further, the switch circuit 821 is used to receive the voltage phase vector sequence, and based on the level type of the vector level in the voltage phase vector sequence, determine whether there are multiple redundant level states in the output state of the phase voltage output circuit during the vector action time corresponding to the vector level.

[0105] Specifically, the switch quantity circuit 821 can receive a voltage phase vector sequence, and determine in turn whether the level type of each vector level in the voltage phase vector sequence is an intermediate level. When it is determined that the level type of a certain vector level is an intermediate level, it is determined that there are multiple redundant level states in the output state of the phase voltage output circuit during the vector action time corresponding to the vector level. Conversely, when it is determined that the level type of a certain vector level is a high level or a low level, it is determined that there are no multiple redundant level states in the output state of the phase voltage output circuit during the vector action time corresponding to the vector level. Further, during the vector action time, when there are multiple redundant level states in the phase voltage output circuit, the switch quantity circuit 821 is also used to receive the bridge arm current output by each parallel bridge arm in the phase voltage output circuit, and based on the bridge arm current, determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in all the parallel bridge arms.

[0106] Furthermore, the switch quantity circuit 821 is also connected to each bridge arm control circuit 822, and the switch quantity circuit 821 is also used to send a low-level output signal to the bridge arm control circuit 822 corresponding to the overcurrent parallel bridge arm, so that the bridge arm control circuit 822 corresponding to the overcurrent parallel bridge arm controls the overcurrent parallel bridge arm to output a low level, so that the bridge arm current output by the overcurrent parallel bridge arm is reduced. At the same time, the switch quantity circuit 821 is also used to send a high-level output signal to the bridge arm control circuit 822 corresponding to the undercurrent parallel bridge arm, so that the bridge arm control circuit 822 corresponding to the undercurrent parallel bridge arm controls the undercurrent parallel bridge arm to output a high level, so that the bridge arm current output by the undercurrent parallel bridge arm is increased. Based on this, the output state of the phase voltage output circuit can be adjusted so that the bridge arm currents output by each parallel bridge arm in the phase voltage output circuit converge, so as to select multiple redundant level states existing in the phase voltage output circuit, and select the target state from multiple redundant level states according to the principle of convergence of currents output by each parallel bridge arm in the same phase voltage output circuit.

[0107] Specifically, if the interleaved parallel multi-level inverter is a three-phase three-level inverter, the phase voltage output circuit of the three-phase three-level inverter for outputting the U-phase voltage is as follows: Figure 2 As shown, the redundant level selection circuit is in the form of Fig.10 As shown, the redundant level selection circuit corresponding to the phase voltage output circuit for outputting the U-phase voltage includes a switch circuit and two bridge arm control circuits, the two bridge arm control circuits are respectively a first bridge arm control circuit and a second bridge arm control circuit, the first bridge arm control circuit is used to control Figure 2 The parallel bridge arm where the first power switch T1 and the second power switch T2 are located outputs the first bridge arm current I1; at the same time, the second bridge arm control circuit is used to control Figure 2The parallel bridge arm where the third power switch T3 and the fourth power switch T4 are located outputs the second bridge arm current I2.

[0108] Further, the first bridge arm control circuit includes a first diode D1, a second diode D2, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first circuit NOT gate U11, a second circuit NOT gate U12 and a third circuit NOT gate U15. Specifically, the output end of the first circuit NOT gate U11 is connected to the base of the first power switch T1. Further, the input end of the third circuit NOT gate U15 is connected to the first control end of the switch quantity circuit; further, the cathode end of the second diode D2 and the second end of the second resistor R2 are connected in parallel to the input end of the second circuit NOT gate U12, the output end of the second circuit NOT gate U12 is connected to the base of the second power switch T2, the first end of the second capacitor C2 is connected to the input end of the second circuit NOT gate U12, and the second end of the second capacitor C2 is grounded.

[0109] Furthermore, when the first bridge arm control circuit receives a high level from the first control end of the switching circuit, the first power switch T1 is controlled to be turned on and the second power switch T2 is controlled to be turned off. When the first bridge arm control circuit receives a low level from the first control end of the switching circuit, the first power switch T1 is controlled to be turned off and the second power switch T2 is controlled to be turned on.

[0110] Further, the second bridge arm control circuit includes a third diode D3, a fourth diode D4, a third resistor R3, a fourth resistor R4, a third capacitor C3, a fourth capacitor C4, a fourth circuit NOT gate U13, a fifth circuit NOT gate U14 and a sixth circuit NOT gate U16. Specifically, the output end of the fourth circuit NOT gate U13 is connected to the base of the third power switch T3. Further, the input end of the sixth circuit NOT gate U16 is connected to the second control end of the switch quantity circuit; further, the cathode end of the fourth diode D4 and the second end of the fourth resistor R4 are connected in parallel to the input end of the fifth circuit NOT gate U14, and the output end of the fifth circuit NOT gate U14 is connected to the base of the fourth power switch T4.

[0111] Further, when the second bridge arm control circuit receives a high level from the second control end of the switching circuit, the third power switch T3 is controlled to be turned on and the fourth power switch T4 is controlled to be turned off; when the second bridge arm control circuit receives a low level from the second control end of the switching circuit, the third power switch T3 is controlled to be turned off and the fourth power switch T4 is controlled to be turned on.

[0112] Furthermore, the switching circuit includes a first XOR gate U1, a first three-state in-direction buffer U2, a second three-state in-direction buffer U3, a third three-state in-direction buffer U4, a fourth three-state in-direction buffer U5, a first NOT gate U6, a second NOT gate U7, a third NOT gate U8, a first voltage comparator U9, a first D trigger U10, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10.

[0113] Specifically, the first end of the fifth resistor R5 is used to receive the first bridge arm current I1, the two ends of the fifth resistor R5 are connected to the inverting input end of the first voltage comparator U9, the first end of the sixth resistor R6 is used to receive the second bridge arm current I2, the two ends of the sixth resistor R6 are connected to the non-inverting input end of the first voltage comparator U9, the power input end of the first voltage comparator U9 is connected to the external power supply VCC, and the ground end of the first voltage comparator U9 is grounded; further, the power input end of the first voltage comparator U9 is also connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is respectively connected to the output end of the first voltage comparator U9 and the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is connected to the second end of the sixth resistor R6. The resistance value of the seventh resistor R7 is reasonably selected so that the first voltage comparator U9 works in a comparator state with hysteresis; further, the output end of the first voltage comparator U9 is connected to the data input end D of the first D flip-flop U10, and the output end Q of the first D flip-flop U10 is used to send the current comparison signal C. Furthermore, the clock input terminal of the first D flip-flop U10 is used to receive a trigger pulse CP.

[0114] Here, the trigger pulse CP is a frequency-adjustable PWM wave, which can realize the modulation of redundant level output when the vector level is an intermediate level. When the staggered parallel multi-level inverter outputs an intermediate level state, in order to improve the current ripple, it is necessary to switch between several different redundant level states that can be selected multiple times, and the switching frequency is determined by the trigger pulse CP. The selection of the redundant level state follows the principle of "relative convergence" of the output current value of each parallel bridge arm. Further, the frequency value of the trigger pulse CP needs to balance the indicators of the working frequency, inductance size, and current ripple requirements of the power switch. At the same time, the frequency of the trigger pulse CP can be greater than the calculation frequency of the voltage target vector calculated by the system controller, and the time length of the cycle of the trigger pulse CP is less than the time length of the vector action time to improve the current ripple. Further, the first D flip-flop U10 can collect the output level of the first voltage comparator U9 at each rising edge of the trigger pulse CP, and latch it in a subsequent trigger pulse CP cycle, thereby forming an output pulse, with the same frequency of the trigger pulse CP The output level changes, and each changing level comes from the output of the voltage comparator.

[0115] In the actual working process, the first bridge arm current I1 generates a voltage at the fifth resistor R5, and the second bridge arm current I2 generates a voltage at the sixth resistor R6. The first voltage comparator U9 compares the voltage at the fifth resistor R5 and the voltage at the sixth resistor R6 in real time. Here, when the first bridge arm current I1 is greater than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a low-level signal, and sends the low-level signal to the first D flip-flop U10. The low-level signal received by the first D flip-flop U10 is a continuous analog signal. In order to convert the continuous analog signal into a digital signal composed of high and low levels, a trigger pulse CP is sent to the clock input end of the first D flip-flop U10. At each rising edge of the trigger pulse CP, the first D flip-flop U10 outputs the signal received from the output end of the first voltage comparator U9 during the previous trigger pulse CP cycle. Similarly, when the first bridge arm current I1 is less than the second bridge arm current I2, the output end of the first voltage comparator U9 outputs a high level signal and sends the high level signal to the first D flip-flop U10. The high level signal received by the first D flip-flop U10 is a continuous analog signal. By sending a trigger pulse CP to the clock input end of the first D flip-flop U10, at each rising edge of the trigger pulse CP, the first D flip-flop U10 outputs the signal received from the output end of the first voltage comparator U9 during the previous trigger pulse CP cycle. The signal output from the output end of the first D flip-flop U10 is the current comparison signal C in the form of a digital signal.

[0116] Furthermore, the first input terminal and the second input terminal of the first XOR gate U1 are respectively used to receive the level identifier of the vector level in the voltage phase vector sequence. Here, each level type of the vector level corresponds to a preset level identifier, and the level identifier is composed of two identification signals. When the level type of the vector level is a high level, the two identification signals that determine the level identifier are "1", "1" respectively; when the level type of the vector level is a low level, the level identifier of the vector level is "0", "0", and when the level type of the vector level is an intermediate level, the level identifier of the vector level is "1", "0" or "0", "1". Here, the voltage phase vector sequence sent by the system controller to the switching circuit can be the level identifier corresponding to each vector level in the voltage phase vector sequence. Furthermore, the first input terminal and the second input terminal of the first XOR gate U1 are respectively used to receive two identification signals corresponding to the level identification. Here, the first input terminal of the first XOR gate U1 can receive the first identification signal of the level identification, and the second input terminal of the first XOR gate U1 can receive the second identification signal of the level identification. When the level type of the vector level is the intermediate level, the two identification signals connected to the first XOR gate U1 will cause the first XOR gate U1 to output a high level. When the level type of the vector level is not the intermediate level, the two identification signals connected to the first XOR gate U1 will cause the first XOR gate U1 to output a low level.

[0117] Further, the output end of the first XOR gate U1 is respectively connected to the control end of the first three-state non-inverting buffer U2, the control end of the third three-state non-inverting buffer U4, the input end of the first NOT gate U6 and the input end of the third NOT gate U8, the output end of the first NOT gate U6 is connected to the control end of the second three-state non-inverting buffer U3, and the output end of the third NOT gate U8 is connected to the control end of the fourth three-state non-inverting buffer U5. Further, the first input end of the first XOR gate U1 is connected to the input end of the first three-state non-inverting buffer U2, and the second input end of the first XOR gate U1 is connected to the input end of the third three-state non-inverting buffer U4. Further, the input end of the second NOT gate U7 and the input end of the second three-state in-phase buffer U3 are used to receive the current comparison signal C, the output end of the second NOT gate U7 is connected to the input end of the fourth three-state in-phase buffer U5, the output end of the first three-state in-phase buffer U2 and the output end of the second three-state in-phase buffer U3 are connected in parallel as the first control end of the switch quantity circuit, and the output end of the third three-state in-phase buffer U4 and the output end of the fourth three-state in-phase buffer U5 are connected in parallel as the second control end of the switch quantity circuit. Further, the first end of the ninth resistor R9 is connected to the external power supply VCC, the second end of the ninth resistor R9 is connected between the output end of the first three-state in-phase buffer U2 and the output end of the second three-state in-phase buffer U3, the first end of the tenth resistor R10 is connected to the external power supply VCC, and the second end of the tenth resistor R10 is connected between the output end of the third three-state in-phase buffer U4 and the output end of the fourth three-state in-phase buffer U5.

[0118] Here, when the control ends of the first three-state non-inverting buffer U2, the second three-state non-inverting buffer U3, the third three-state non-inverting buffer U4 and the fourth three-state non-inverting buffer U5 receive a "0" level, the three-state non-inverting buffers receiving the "0" level are turned on; when the control ends of the first three-state non-inverting buffer U2, the second three-state non-inverting buffer U3, the third three-state non-inverting buffer U4 and the fourth three-state non-inverting buffer U5 receive a "1" level, the three-state non-inverting buffers receiving the "1" level are turned off and present a high-impedance output.

[0119] Further, when the first input terminal and the second input terminal of the first XOR gate U1 receive the same level, the output level of the first XOR gate U1 is "0". At this time, the first three-state in-phase buffer U2 and the third three-state in-phase buffer U4 are opened, and the second three-state in-phase buffer U3 and the fourth three-state in-phase buffer U5 are closed; conversely, when the output level of the first XOR gate U1 is "1", the second three-state in-phase buffer U3 and the fourth three-state in-phase buffer U5 are opened, and the first three-state in-phase buffer U2 and the third three-state in-phase buffer U4 are closed.

[0120] Specifically, when the output level of the first XOR gate U1 is "0", the output signals of the first control terminal of the switching circuit and the second control terminal of the switching circuit are determined by the levels received by the first input terminal and the second input terminal of the first XOR gate U1, the level output by the first control terminal of the switching circuit is the same as the signal level received by the first input terminal of the first XOR gate U1, and the level output by the second control terminal of the switching circuit is the same as the signal level received by the second input terminal of the first XOR gate U1.

[0121] Conversely, when the output level of the first XOR gate U1 is "1", the output signals of the first control terminal of the switching circuit and the second control terminal of the switching circuit are determined by the level of the current comparison signal C, the level output by the first control terminal of the switching circuit is the same as the signal level of the current comparison signal C, and the level output by the second control terminal of the switching circuit is opposite to the signal level of the current comparison signal C.

[0122] In the actual working process, if the first bridge arm current I1 is greater than the second bridge arm current I2, the first voltage comparator U9 outputs a "0" level, the current comparison signal C is a "0" level, the lower bridge arm of the parallel bridge arm where the first power switch T1 and the second power switch T2 are located is turned on, and the first bridge arm current I1 decreases. At the same time, the upper bridge arm of the parallel bridge arm where the third power switch T3 and the fourth power switch T4 are located is turned on, and the second bridge arm current I2 increases. After the period of this trigger pulse CP, the difference between the currents of the first bridge arm current I1 and the second bridge arm current I2 decreases.

[0123] Conversely, if the first bridge arm current I1 is less than the second bridge arm current I2, the first voltage comparator U9 outputs a "1" level, the current comparison signal C is a "1" level, the upper bridge arm of the parallel bridge arm where the first power switch T1 and the second power switch T2 are located is turned on, and the first bridge arm current I1 increases. At the same time, the lower bridge arm of the parallel bridge arm where the third power switch T3 and the fourth power switch T4 are located is turned on, and the second bridge arm current I2 decreases. After the period of this trigger pulse CP, the difference between the currents of the first bridge arm current I1 and the second bridge arm current I2 decreases.

[0124] In an optional embodiment, if Fig.11 As shown, the switching circuit 821 includes a redundancy determination circuit 100 and a current comparison circuit 200 .

[0125] Specifically, the redundancy determination circuit 100 is used to receive the voltage phase vector sequence from the system controller 810, and based on the level identifier of the level type of the vector level, determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level, wherein each level type corresponds to a preset level identifier. Here, if the level identifier of the level type is "1", "1" or "0", "0" composed of two identification signals, it can be determined that there are no multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level. Conversely, if the level identifier of the level type is "1", "0" or "0", "1" composed of two identification signals, it can be determined that there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level.

[0126] Furthermore, the current comparison circuit 200 is used to receive the bridge arm current output by each parallel bridge arm (not shown in the figure) in the phase voltage output circuit and the level identifier of the level type of the vector level, and generate an order indication signal based on the bridge arm current and the level identifier to characterize the order of the current magnitudes of each bridge arm current.

[0127] Furthermore, the redundancy determination circuit 100 is also used to receive the order indication signal when there are multiple redundant level states in the phase voltage output circuit within the vector action time, and based on the order indication signal and the level identifier, determine the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in all the parallel bridge arms, and send a low-level output signal to the bridge arm control circuit corresponding to the overcurrent parallel bridge arm, and send a high-level output signal to the bridge arm control circuit corresponding to the undercurrent parallel bridge arm.

[0128] Further, such as Fig.12 As shown, the switch circuit includes a current comparison circuit and a redundancy determination circuit. The switch circuit is suitable for Fig.13 The four-level phase voltage output circuit shown is used as an example for explanation. The four-level phase voltage output circuit includes a parallel bridge arm composed of an eleventh power switch K11 and a twelfth power switch K12, and the parallel bridge arm outputs a first four-level bridge arm current I11 through an eleventh inductor L11; the four-level phase voltage output circuit also includes a parallel bridge arm composed of a twenty-first power switch K21 and a twenty-second power switch K22, and the parallel bridge arm outputs a second four-level bridge arm current I12 through a twelfth inductor L12; the four-level phase voltage output circuit also includes a parallel bridge arm composed of a thirty-first power switch K31 and a thirty-second power switch K32, and the parallel bridge arm outputs a third four-level bridge arm current I13 through a thirteenth inductor L13.

[0129] Further, such as Fig.12 The switching circuit shown corresponds to three bridge arm control circuits, including a third bridge arm control circuit, a fourth bridge arm control circuit, and a fifth bridge arm control circuit. Specifically, the third bridge arm control circuit includes a fifth diode D5, a sixth diode D6, an eleventh resistor R11, a twelfth resistor R12, a fifth capacitor C5, a sixth capacitor C6, a seventh circuit NOT gate U52, an eighth circuit NOT gate U53, and a ninth circuit NOT gate U54, and the connection method thereof is as follows: Fig.12 shown.

[0130] Further, when the third bridge arm control circuit receives a high level from the first control end of the redundant determination circuit, the eleventh power switch K11 is controlled to be turned on and the twelfth power switch K12 is controlled to be turned off; when the third bridge arm control circuit receives a low level from the first control end of the redundant determination circuit, the twelfth power switch K12 is controlled to be turned on and the eleventh power switch K11 is controlled to be turned off.

[0131] Further, the fourth bridge arm control circuit includes a seventh diode D7, an eighth diode D8, a thirteenth resistor R13, a fourteenth resistor R14, a seventh capacitor C7, an eighth capacitor C8, a tenth circuit NOT gate U55, an eleventh circuit NOT gate U56 and a twelfth circuit NOT gate U57, and the connection method thereof is as follows: Fig.12 shown.

[0132] Further, when the fourth bridge arm control circuit receives a high level from the second control terminal of the redundant determination circuit, it controls the twenty-first power switch K21 to be turned on and the twenty-second power switch K22 to be turned off; when the fourth bridge arm control circuit receives a low level from the second control terminal of the redundant determination circuit, it controls the twenty-second power switch K22 to be turned on and the twenty-first power switch K21 to be turned off.

[0133] Further, the fifth bridge arm control circuit includes a ninth diode D9, a tenth diode D10, a fifteenth resistor R15, a sixteenth resistor R16, a ninth capacitor C9, a tenth capacitor C10, a thirteenth circuit NOT gate U58, a fourteenth circuit NOT gate U59 and a fifteenth circuit NOT gate U60, and the connection method thereof is as follows: Fig.12 shown.

[0134] Further, when the fifth bridge arm control circuit receives a high level from the third control terminal of the redundant judgment circuit, the thirty-first power switch K31 is controlled to be turned on and the thirty-second power switch K32 is controlled to be turned off; when the fifth bridge arm control circuit receives a low level from the third control terminal of the redundant judgment circuit, the thirty-second power switch K32 is controlled to be turned on and the thirty-first power switch K31 is controlled to be turned off.

[0135] Further, the current comparison circuit includes a second voltage comparator U19, a third voltage comparator U21, a fourth voltage comparator U23, a second D flip-flop U20, a third D flip-flop U22, a fourth D flip-flop U24, a fiftieth resistor R50, a fifty-first resistor R51, a fifty-second resistor R52, a fifty-third resistor R53, a fifty-fourth resistor R54, a fifty-fifth resistor R55, a fifty-sixth resistor R56, a fifty-seventh resistor R57, a fifty-eighth resistor R58, a fifty-ninth resistor R59, a sixth The sixty-first resistor R60, the sixty-first resistor R61, the sixty-second resistor R62, the sixty-third resistor R63, the sixty-fourth resistor R64, the second XOR gate U25, the third XOR gate U26, the fourth XOR gate U27, the fourth NOT gate U28, the fifth NOT gate U29, the sixth NOT gate U30, the fifth three-state same-direction buffer U31, the sixth three-state same-direction buffer U32, the seventh three-state same-direction buffer U33, the eighth three-state same-direction buffer U34, the ninth three-state same-direction buffer U35 and the thirteenth three-state same-direction buffer U36.

[0136] Specifically, the first end of the 50th resistor R50 and the first end of the 54th resistor R54 are respectively used to receive the third four-level bridge arm current I13, the first end of the 51st resistor R51 and the first end of the 58th resistor R58 are respectively used to receive the second four-level bridge arm current I12, and the first end of the 55th resistor R55 and the first end of the 59th resistor R59 are respectively used to receive the first four-level bridge arm current I11.

[0137] Further, the power supply access terminal of the second voltage comparator U19 is connected to the external power supply VCC, and the ground terminal of the second voltage comparator U19 is grounded. Further, the power supply access terminal of the third voltage comparator U21 is connected to the external power supply VCC, and the ground terminal of the third voltage comparator U21 is grounded. Further, the power supply access terminal of the fourth voltage comparator U23 is connected to the external power supply VCC, and the ground terminal of the fourth voltage comparator U23 is grounded.

[0138] Further, the clock input end of the second D flip-flop U20, the clock input end of the third D flip-flop U22 and the clock input end of the fourth D flip-flop U24 are used to receive the trigger pulse CP. Further, the output end of the fifth three-state non-inverting buffer U31 and the output end of the sixth three-state non-inverting buffer U32 are connected in parallel as the third order indication signal output end of the current comparison circuit, which is used to output the third order indication signal S3. Further, the output end of the seventh three-state non-inverting buffer U33 and the output end of the eighth three-state non-inverting buffer U34 are connected in parallel as the second order indication signal output end of the current comparison circuit, which is used to output the second order indication signal S2. Further, the output end of the ninth three-state non-inverting buffer U35 and the output end of the thirteenth three-state non-inverting buffer U36 are connected in parallel as the first order indication signal output end of the current comparison circuit, which is used to output the first order indication signal S1. Among them, the first order indication signal S1, the second order indication signal S2 and the third order indication signal S3 constitute the order indication signal.

[0139] Further, the redundant determination circuit includes a fifth XOR gate U41, a forty-first resistor R41, a forty-second resistor R42, a forty-third resistor R43, a seventh NOT gate U49, an eighth NOT gate U50, a ninth NOT gate U51, an eleventh three-state unidirectional buffer U42, a twelfth three-state unidirectional buffer U43, a thirteenth three-state unidirectional buffer U45, a fourteenth three-state unidirectional buffer U46, a fifteenth three-state unidirectional buffer U47 and a sixteenth three-state unidirectional buffer U48.

[0140] Specifically, the first input end of the fifth XOR gate U41 is used to receive the first identification signal A of the two identification signals constituting the level identification of the level type, and the first input end of the fifth XOR gate U41 is also connected to the input end of the fifth three-state non-inverting buffer U31, the input end of the eighth three-state non-inverting buffer U34, and the input end of the ninth three-state non-inverting buffer U35. Further, the first input end of the fifth XOR gate U41 is also connected to the input end of the eleventh three-state non-inverting buffer U42, the input end of the thirteenth three-state non-inverting buffer U45, and the input end of the fifteenth three-state non-inverting buffer U47. Further, the second input end of the fifth XOR gate U41 is used to receive the second identification signal B of the two identification signals constituting the level identification of the level type.

[0141] Further, the output end of the fifth XOR gate U41 is respectively connected to the control end of the eleventh three-state in-phase buffer U42, the control end of the thirteenth three-state in-phase buffer U45, the control end of the fifteenth three-state in-phase buffer U47, the input end of the seventh NOT gate U49, the input end of the eighth NOT gate U50, and the input end of the ninth NOT gate U51. Further, the output end of the seventh NOT gate U49 is connected to the control end of the twelfth three-state in-phase buffer U43, and the output end of the eleventh three-state in-phase buffer U42 and the output end of the twelfth three-state in-phase buffer U43 are connected in parallel as the first control end of the redundancy determination circuit. Further, the output end of the eighth NOT gate U50 is connected to the control end of the fourteenth three-state in-phase buffer U46, and the output end of the thirteenth three-state in-phase buffer U45 and the output end of the fourteenth three-state in-phase buffer U46 are connected in parallel as the second control end of the redundancy determination circuit. Furthermore, the output end of the ninth NOT gate U51 is connected to the control end of the sixteenth three-state non-inverting buffer U48, and the connection end of the output end of the fifteenth three-state non-inverting buffer U47 and the output end of the sixteenth three-state non-inverting buffer U48 in parallel serves as the third control end of the redundancy determination circuit.

[0142] In the actual working process, when the level type of a vector level in the voltage phase vector sequence corresponds to the two identification signals, the first identification signal A and the second identification signal B, which are "1" and "1" respectively, the first control terminal, the second control terminal and the third control terminal of the redundancy determination circuit respectively output high levels, so that Fig.13 The power switch in the upper bridge arm of the three parallel bridge arms in the voltage phase vector sequence is turned on, and the power switch in the lower bridge arm is turned off; correspondingly, when the level type of the level identifier of a vector level in the voltage phase vector sequence corresponds to the two-way identification signal first identification signal A and the second identification signal B are respectively "0" and "0", the first control terminal, the second control terminal and the third control terminal of the redundancy determination circuit respectively output low levels, so that Fig.13 The power switch in the lower bridge arm of the three parallel bridge arms is turned on, and the power switch in the upper bridge arm is turned off.

[0143] Furthermore, when the two identification signals, the first identification signal A and the second identification signal B, corresponding to the level identification of the level type of a vector level in the voltage phase vector sequence are "1", "0" or "0", "1" respectively, the transition selection is realized by the current comparison circuit, and the redundant judgment circuit uses the first order indication signal S1, the second order indication signal S2 and the third order indication signal S3 of the output current comparison circuit of the switch selection chip to control the output levels of the first control terminal, the second control terminal and the third control terminal of the redundant judgment circuit.

[0144] Specifically, because Fig.13The inverter in is a four-level inverter, and its phase voltage output circuit has two intermediate level states of 0.33U and 0.67U, wherein when the level type of the vector level is 0.33U, the two identification signals corresponding to the level identifier of the level type, the first identification signal A and the second identification signal B, are respectively "1" and "0"; conversely, when the level type of the vector level is 0.67U, the two identification signals corresponding to the level identifier of the level type, the first identification signal A and the second identification signal B, are respectively "0" and "1". When the level type of the vector level is 0.67U, it is achieved by turning on two upper bridge arms and one lower bridge arm in the three parallel bridge arms of the phase voltage output circuit. When the level type of the vector level is 0.33U, it is achieved by turning on one upper bridge arm and two lower bridge arms in the three parallel bridge arms of the phase voltage output circuit.

[0145] Therefore, whether two upper bridge arms are turned on and one lower bridge arm is turned on, or one upper bridge arm is turned on and two lower bridge arms are turned on, there are many distribution principles for the upper bridge arms and lower bridge arms of the three parallel bridge arms of the phase voltage output circuit, that is, there are redundant level states. This patent adopts the "principle of output current convergence" to select the redundant level state.

[0146] The output current sorting function of the three parallel bridge arms of the phase voltage output circuit is realized by the second voltage comparator U19, the third voltage comparator U21 and the fourth voltage comparator U23. The second voltage comparator U19 outputs a first comparison signal U03, the third voltage comparator U21 outputs a second comparison signal U02, and the fourth voltage comparator U23 outputs a third comparison signal U01. The relationship between the first comparison signal U01, the second comparison signal U02 and the third comparison signal U03 and the sorting (large, medium and small order) of the first four-level bridge arm current I11, the second four-level bridge arm current I12 and the third four-level bridge arm current I13 is as follows:

[0147] As shown in Table 2:

[0148]

[0149] Table 2: Comparison table of voltage comparator output and bridge arm current ranking

[0150] Further, according to the principle of redundant level state selection for current convergence, the states of the first sequence indication signal S1, the second sequence indication signal S2, and the third sequence indication signal S3 output by the current comparison circuit are not only related to the sorting result of the voltage comparator, but also related to the states of the two-way identification signals corresponding to the level identifier. Because in the redundant selection state, the two-way identification signals corresponding to the level identifier have only two states of "1", "0" or "0", "1", so the current comparison circuit only introduces the first-way identification signal A or the second-way identification signal B corresponding to the level identifier, and in this example, only the first-way identification signal A is introduced.

[0151] According to the redundant level state selection principle of current convergence, the output state relationship of the current comparison circuit shown in Table 3 below can be obtained:

[0152]

[0153] Table 3: Comparison table of voltage comparator output and bridge arm current ranking

[0154] According to Table 1, the logical relationship between the output first sequence indication signal S1, the second sequence indication signal S2 and the third sequence indication signal S3 and the first path identification signal, the first comparison signal U01, the second comparison signal U02 and the third comparison signal U03 corresponding to the input level identification can be analyzed to meet the following:

[0155] When the first comparison signal U01 is the same as the second comparison signal U02, the level of the first order indication signal S1 is equal to the level of the first comparison signal U01; when the first comparison signal U01 is different from the second comparison signal U02, the level of the first order indication signal S1 is equal to the level of the first path identification signal A corresponding to the level identifier; when the first comparison signal U01 is different from the third comparison signal U03, the level of the second order indication signal S2 is equal to the level of the third comparison signal U03; when the first comparison signal U01 is the same as the third comparison signal U03, the level of the second order indication signal S2 is equal to the level of the first path identification signal A corresponding to the level identifier; when the second comparison signal U02 is the same as the third comparison signal U03, the level of the third order indication signal S3 is equal to the non-level of the level of the second comparison signal U02; when the second comparison signal U02 is different from the third comparison signal U03, the level of the third order indication signal S3 is equal to the level of the first path identification signal corresponding to the level identifier. Based on the above relationship, the relevant circuit of the current comparison circuit is designed, which adopts a level switch control circuit chip similar to the redundant determination circuit, and its principle is not repeated here.

[0156] Further, as Figure 4 , Figure 5 The specific implementation of the method shown in the embodiment provides a control device for an inverter, such as Fig.14As shown, the device includes: a sequence generation module 141, a redundancy determination module 142 and a level selection module 143. The sequence generation module 141 can be used to determine the voltage target vector corresponding to the voltage to be output by the staggered parallel multi-level inverter, and determine the voltage phase vector sequence corresponding to each phase voltage output circuit based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels; the redundancy determination module 142 can be used to determine whether there are multiple redundant level states in the output state of the phase voltage output circuit during the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; the level selection module 143 can be used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit during the vector action time, so that the output state of the phase voltage output circuit is in the target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit is reduced during the vector action time.

[0157] It should be noted that for other corresponding descriptions of the functional units involved in the inverter control device provided in this embodiment, reference can be made to Figure 4 , Figure 5 The corresponding description in will not be repeated here.

[0158] Based on the above Figure 4 , Figure 5 The method shown in the embodiment also provides a storage medium on which a computer program is stored. When the program is executed by a processor, the above-mentioned Figure 4 , Figure 5 Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, and the software product to be identified can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, a ROM, an EEPROM, a FLASH, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each implementation scenario of the present application.

[0159] Based on the above Figure 4 , Figure 5 The method shown, and Fig.14The control device embodiment of the inverter shown in the figure, in order to achieve the above purpose, this embodiment also provides a computer device for controlling the inverter, which can be a personal computer, a single-chip microcomputer, a DSP, a FPGA, a server, a smart phone, a tablet computer, a smart watch, or other network devices, etc. The computer device includes a storage medium and a processor; the storage medium is used to store a computer program and an operating system; the processor is used to execute the computer program to achieve the above Figures 4 to 5 The method shown. Optionally, the computer device may also include an internal memory, a communication interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a WI-FI module, a display screen (Display), an input device such as a keyboard (Keyboard), etc. Optionally, the communication interface may also include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc. It will be appreciated by those skilled in the art that the computer device structure for identifying an operation action provided in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components, or a combination of certain components, or different component arrangements. The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the above-mentioned computer device hardware and software resources to be identified, and supports the operation of information processing programs and other software and / or programs to be identified. The network communication module is used to realize communication between components inside the storage medium, and to communicate with other hardware and software in the information processing computer device.

[0160] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware platforms, or by hardware. By applying the technical solution of the present application, first, the voltage target vector corresponding to the voltage to be output by the staggered parallel multi-level inverter is determined, and the voltage phase vector sequence corresponding to each phase voltage output circuit is determined based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels; then, based on the level type of the vector level in the voltage phase vector sequence, it is determined whether there are multiple redundant level states in the output state of the phase voltage output circuit during the vector action time corresponding to the vector level; finally, when there are multiple redundant level states in the phase voltage output circuit during the vector action time, the current output state of each parallel bridge arm in the phase voltage output circuit is controlled so that the output state of the phase voltage output circuit is in the target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit is reduced during the vector action time. Compared with the prior art, the efficiency of selecting the redundant level state of the staggered parallel multi-level inverter can be improved.

[0161] Those skilled in the art will appreciate that the accompanying drawings are only schematic diagrams of a preferred implementation scenario, and the modules or processes in the accompanying drawings are not necessarily necessary for implementing the present application. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario can be distributed in the devices of the implementation scenario according to the description of the implementation scenario, or can be changed accordingly and located in one or more devices different from the present implementation scenario. The modules of the above-mentioned implementation scenario can be combined into one module, or can be further split into multiple submodules.

[0162] The above serial numbers of this application are only for description and do not represent the advantages and disadvantages of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of this application, but this application is not limited to them, and any changes that can be thought of by technicians in this field should fall within the scope of protection of this application.

Claims

1. A control method for an inverter, applied to an interleaved parallel multi-level inverter with a plurality of phase voltage output circuits, each of the phase voltage output circuits being used to output a phase voltage, characterized in that: The method comprises: Determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels; Based on the level type of the vector level in the voltage phase vector sequence, determining whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level; When there are multiple redundant level states in the phase voltage output circuit within the vector action time, the current output state of each parallel bridge arm in the phase voltage output circuit is controlled so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

2. The inverter control method according to claim 1, characterized in that: The step of determining a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector comprises: Determine the triangular sector where the voltage target vector is located in the space voltage vector diagram, determine the NPC vertex vector of the triangular sector, and determine a plurality of NPC vertex vectors of the phase voltage output by each of the phase voltage output circuits based on the NPC vertex vector; Determining the vector action time of each of the NPC vertex component vectors of the phase voltage output by the phase voltage output circuit; The vector levels corresponding to each of the NPC vertex vectors of the phase voltage output circuit are arranged to obtain the voltage phase vector sequence corresponding to the phase voltage output circuit.

3. The control method of the inverter according to claim 2, characterized in that: The controlling the current output state of each parallel bridge arm in the phase voltage output circuit comprises: When the output state of the phase voltage output circuit has multiple redundant level states during the vector action time of the NPC vertex vector with an intermediate level, receiving the bridge arm currents output by all the parallel bridge arms in the phase voltage output circuit, and determining the overcurrent parallel bridge arm and the undercurrent parallel bridge arm in all the parallel bridge arms based on the bridge arm currents output by all the parallel bridge arms; The bridge arm current output by the overcurrent parallel bridge arm is reduced, and the bridge arm current output by the undercurrent parallel bridge arm is increased.

4. The control method of the inverter according to claim 3, characterized in that: The receiving the bridge arm current output by all the parallel bridge arms in the phase voltage output circuit comprises: The bridge arm currents output by all the parallel bridge arms in the phase voltage output circuit are continuously received with a preset time interval as a receiving period, wherein the preset time interval is less than the vector action time, so that the phase voltage output circuit can switch the redundant level state multiple times within the vector action time of the NPC vertex vector with an intermediate level.

5. The control method of the inverter according to claim 3, characterized in that: The method of determining an overcurrent parallel bridge arm and an undercurrent parallel bridge arm in all the parallel bridge arms based on the bridge arm currents output by all the parallel bridge arms comprises: Obtaining a bridge arm current output by each of the parallel bridge arms; Arranging all the bridge arm currents into a bridge arm current queue in descending order of current value; The parallel bridge arms corresponding to the first preset number of bridge arm currents arranged in the bridge arm current queue are determined as overcurrent parallel bridge arms, and all parallel bridge arms except the overcurrent parallel bridge arms among all the parallel bridge arms are determined as undercurrent parallel bridge arms.

6. The control method of the inverter according to claim 3, characterized in that: The step of reducing the bridge arm current output by the overcurrent parallel bridge arm comprises: Sending a low level signal to the base of the power switch in the upper bridge arm of the overcurrent parallel bridge arm, and sending a high level signal to the base of the power switch in the lower bridge arm of the overcurrent parallel bridge arm; The step of increasing the bridge arm current output by the undercurrent parallel bridge arm comprises: A high level signal is sent to the base of the power switch in the upper bridge arm of the undercurrent parallel bridge arm, and a low level signal is sent to the base of the power switch in the lower bridge arm of the undercurrent parallel bridge arm.

7. An inverter control system, applied to an interleaved parallel multi-level inverter with a plurality of phase voltage output circuits, each of the phase voltage output circuits being used to output a phase voltage, characterized in that: The system includes a system controller and a plurality of redundant level selection circuits, wherein the redundant level selection circuits correspond one-to-one to the phase voltage output circuits; The system controller is used to determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels; The redundant level selection circuit is used to receive the voltage phase vector sequence corresponding to the redundant level selection circuit, and determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; The redundant level selection circuit is also used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within the vector action time, so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

8. A control device for an inverter, characterized in that: The device comprises: A sequence generation module, used to determine a voltage target vector corresponding to the voltage to be output by the interleaved parallel multi-level inverter, and determine a voltage phase vector sequence corresponding to each of the phase voltage output circuits based on the voltage target vector, wherein the voltage phase vector sequence is composed of a plurality of sequentially arranged vector levels; A redundancy determination module, configured to determine whether there are multiple redundant level states in the output state of the phase voltage output circuit within the vector action time corresponding to the vector level based on the level type of the vector level in the voltage phase vector sequence; A level selection module is used to control the current output state of each parallel bridge arm in the phase voltage output circuit when there are multiple redundant level states in the phase voltage output circuit within the vector action time, so that the output state of the phase voltage output circuit is in a target state among the multiple redundant level states, wherein when the output state of the phase voltage output circuit is in the target state, the difference between the output currents of each parallel bridge arm in the phase voltage output circuit decreases within the vector action time.

9. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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