Two-dimensional LDPC error correction method suitable for flash memory, flash memory controller and storage device

Abstract

The invention discloses a two-dimensional LDPC (Low Density Parity Check) error correction method suitable for a flash memory, a flash memory controller and storage equipment, and belongs to the technical field of flash memories, and the encoding steps are as follows: after performing two-dimensional LDPC encoding on every K information bits in a flash memory page, storing obtained check bits in an OOB area of the flash memory page to complete encoding of the flash memory page; the two-dimensional LDPC coding comprises the following steps: equally dividing K information bits into B information bit blocks with the size of k, and taking every c continuous information bit blocks as one row in an information matrix to obtain an information matrix with r rows and c columns; for each row in the information matrix, coding by using a first LDPC code to generate a transverse check bit corresponding to each row; and for each column in the information matrix, coding is carried out by using the second LDPC code, and a longitudinal check bit corresponding to each column is generated. According to the method, the decoding delay of the flash memory system adopting the LDPC code can be remarkably reduced on the premise of ensuring that redundant space is not additionally increased.

Description

Technical Field

[0001] The present invention belongs to the technical field of flash memory, and more specifically, relates to a two-dimensional LDPC error correction method suitable for flash memory, a flash memory controller and a storage device. Background Art

[0002] Due to advantages such as small size, high performance, low energy consumption and non-volatility, flash-based solid-state drives are gradually becoming the mainstream storage medium in various embedded systems, personal computers and high-performance platforms. In order to increase storage capacity and reduce unit (cell) costs, manufacturers are also constantly reducing cell spacing and storing more bits of information in a single cell. From MLC to the commonly used TLC, the number of bits stored in a single cell has increased, and the number of error bits in flash memory has increased by more than 10 times. Therefore, while flash memory capacity and storage density are increasing rapidly, crosstalk between memory cells greatly threatens data storage reliability. Error correction code is an effective means to resist flash channel interference and ensure data storage reliability.

[0003] Traditional BCH codes are widely used in commercial solid-state drives, but are limited by the capacity of the OOB (Out of Band) area in the flash memory page, and the amount of verification information that can be stored is limited. Therefore, the data storage reliability of large-capacity flash memory cannot be guaranteed.

[0004] LDPC codes have attracted widespread attention from academia and industry for their superior error correction capabilities. LDPC codes use soft decoding to achieve high reliability, but at the cost of a surge in decoding delays. In this case, it will lead to a loss of high performance of flash memory and reduce service quality. Summary of the invention

[0005] In view of the defects of the prior art and the need for improvement, the present invention provides a two-dimensional LDPC error correction method, a flash memory controller and a storage device suitable for flash memory, the purpose of which is to significantly reduce the decoding delay of a flash memory system using LDPC code without increasing additional redundant space.

[0006] To achieve the above object, according to one aspect of the present invention, a two-dimensional LDPC error correction method applicable to a flash memory is provided, comprising: an encoding step; the encoding step comprises:

[0007] After performing two-dimensional LDPC encoding on each K information bits in the flash memory page, the obtained check bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page;

[0008] Two-dimensional LDPC coding includes:

[0009] Constructing an information matrix: divide the K information bits into B information bit blocks of size k, and take each c consecutive information bit blocks as a row in the information matrix, thus obtaining an information matrix with r rows and c columns;

[0010] Horizontal coding: For each row of information bit blocks in the information matrix, the first LDPC code is used to encode them respectively to generate m1 horizontal check bits corresponding to each row;

[0011] Longitudinal coding: for each column of information bit blocks in the information matrix, the second LDPC code is used to encode them respectively to generate m2 longitudinal check bits corresponding to each column;

[0012] The check bits include horizontal check bits and vertical check bits; the code rate R≥S info / S page , S page Indicates the flash page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

[0013] Furthermore, the two-dimensional LDPC error correction method applicable to flash memory provided by the present invention further includes: a decoding step; the decoding step includes:

[0014] For each K information bits in the flash memory page, two-dimensional LDPC decoding is performed to complete the encoding of the flash memory page;

[0015] Two-dimensional LDPC decoding includes:

[0016] Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits;

[0017] Horizontal decoding: For each row of information bit blocks in the information matrix M, after obtaining the corresponding m1 horizontal check bits from the OOB area of ​​the flash memory page, the current LLR information is used as the LLR information for LDPC decoding, and the first LDPC code is used for decoding. After the decoding of each row is completed, the LLR information is updated;

[0018] Vertical decoding: For each column of information bit blocks in the information matrix M, after obtaining the corresponding m2 vertical check bits from the OOB area of ​​the flash memory page, the current LLR information is used as the LLR information for LDPC decoding, and the second LDPC code is used for decoding. After the decoding of each column is completed, the LLR information is updated;

[0019] Iteration control: Iteratively execute horizontal decoding and vertical decoding until any preset iteration termination condition is reached.

[0020] Furthermore, the iteration termination conditions include:

[0021] In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

[0022] Furthermore, the preset iteration termination conditions include:

[0023] Reach the maximum number of iterations Cycle;

[0024] Among them, if r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

[0025] Furthermore, if min(r,c)>th, the preset iteration termination condition also includes:

[0026] Reach the preset number of iterations T;

[0027] Among them, th and T are both preset positive integers, T <Cycle。

[0028] Furthermore, the method for determining the number of iterations T includes:

[0029] Select multiple information matrices of the same size as the information matrix M as observation matrices;

[0030] For each measurement matrix, perform horizontal decoding and vertical decoding iteratively, and record the change of the bit error rate of each measurement matrix with the number of iterations;

[0031] The number of iterations corresponding to when the bit error rate of each observation matrix drops to a preset reliable threshold is obtained and the average value is calculated as the pre-iteration number T.

[0032] Furthermore, in the horizontal coding, the coding of each row of information bit blocks in the information matrix is ​​performed in parallel; in the vertical coding, the coding of each column of information bit blocks in the information matrix is ​​performed in parallel;

[0033] In horizontal decoding, decoding of information bit blocks in each row of the information matrix M is performed in parallel; in vertical decoding, decoding of information bit blocks in each column of the information matrix M is performed in parallel.

[0034] Further, the first LDPC code and the second LDPC code are the same LDPC code.

[0035] According to another aspect of the present invention, there is provided a flash memory controller, comprising:

[0036] A computer-readable storage medium for storing a computer program;

[0037] And a processor, used for reading a computer program stored in a computer-readable storage medium, and executing the above-mentioned two-dimensional LDPC error correction method applicable to flash memory provided by the present invention.

[0038] According to another aspect of the present invention, there is provided a flash memory based storage device, comprising:

[0039] A flash memory chip and the flash memory controller provided by the present invention.

[0040] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0041] (1) The traditional LDPC code is a one-dimensional LDPC code, that is, all information bits in the entire flash memory are uniformly encoded, and the codeword is relatively long, which will lead to a large decoding delay in the entire decoding process. The present invention controls the code rate to ensure that the check information generated by the encoding can be completely stored in the OOB area. K information bits in the entire flash memory page are encoded each time. During encoding, the K information bits are further organized into an information matrix. The K information bits are encoded by performing LDPC encoding on the rows and columns of the information matrix respectively, thereby realizing a two-dimensional LDPC encoding. Through such an encoding method, the codeword length is greatly shortened, thereby effectively improving the decoding efficiency and reducing the decoding delay.

[0042] (2) In the decoding process, the present invention will iteratively perform horizontal decoding and vertical decoding, so that horizontal decoding and vertical decoding will be continuously and alternately performed. When horizontal decoding or vertical decoding fails in a certain iteration, it may be that the vertical decoding or horizontal decoding performed subsequently corrects some error bits, so that in the next iteration, horizontal decoding or vertical decoding plays a role again, effectively ensuring the validity of the entire decoding step. When in a certain iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0, it means that after the previous iteration, all error bits in the information matrix have been corrected, or there are still error bits in the information matrix, but new error bits cannot be corrected through subsequent iterations. The present invention uses this as one of the preset iteration termination conditions, which can avoid invalid iterations without affecting the error correction capability, further improve decoding efficiency, and reduce iteration overhead.

[0043] (3) According to the two-dimensional coding method adopted in the present invention, the number of iterations required to correct all correctable error bits during decoding can be calculated. Specifically, when the number of rows and columns of the information matrix is ​​equal, the number of iterations is the number of rows or columns. When the number of rows and columns of the information matrix is ​​not equal, the number of iterations is the sum of the smaller value of the number of rows or columns and 1. In a preferred embodiment of the present invention, the number of iterations is calculated and set to the maximum number of iterations as one of the iteration termination conditions in the decoding process. Compared with terminating the iteration according to the number of rows and columns successfully corrected in the iteration, the number of iterations can be further reduced without affecting the error correction capability, thereby improving the decoding efficiency.

[0044] (4) When the scale of the information matrix is ​​large, and the errors are randomly distributed in the information matrix, most of the error bits can often be corrected in the first few iterations, and in the subsequent iterations, each iteration can only correct a few bit errors; in the preferred solution of the present invention, if the scale of the information matrix is ​​large, the number of iterations at which the iteration is terminated is set to be less than the maximum number of iterations, that is, the iteration process is terminated before all the errors that can be corrected are corrected, thereby better balancing the error correction capability and the number of iterations, effectively reducing the number of iterations without significantly affecting the error correction capability, and further improving the decoding efficiency. In its further preferred solution, the number of iterations at which the iteration is terminated is specifically determined based on the change in the bit error rate of multiple information matrices of the same size with the number of iterations, ensuring that the reliability of data storage can be effectively guaranteed while improving the decoding efficiency.

[0045] (5) In the preferred embodiment of the present invention, the encoding / decoding of the information bit blocks in each row of the information matrix is ​​performed in parallel, and the encoding / decoding of the information bit blocks in each column of the information matrix is ​​performed in parallel, thereby achieving a parallelism that one-dimensional LDPC codes do not have, and further improving the encoding / decoding efficiency.

[0046] (6) In the preferred embodiment of the present invention, the same LDPC code is used in the horizontal and vertical directions, thereby simplifying the overall encoding and decoding logic. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of a two-dimensional LDPC error correction method applicable to flash memory provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of two-dimensional LDPC coding provided by an embodiment of the present invention;

[0049] Figure 3 A schematic diagram of two-dimensional LDPC decoding provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0051] In the present invention, the terms "first", "second", etc. (if any) in the present invention and the accompanying drawings are used to distinguish similar objects but not necessarily to describe a specific order or sequence.

[0052] In order to solve the problem that the existing LDPC error correction method has a large decoding delay and affects the performance of the flash memory when improving the data reliability of the flash memory, the present invention provides a two-dimensional LDPC error correction method, a flash memory controller and a storage device suitable for the flash memory. The overall idea is to improve the traditional one-dimensional LDPC error correction method and propose a new two-dimensional coding structure. Under the condition of ensuring that the code rate does not increase, the codeword length of LDPC encoding / decoding is greatly shortened, thereby effectively improving the decoding efficiency, and then improving the performance of the flash memory.

[0053] In order to make the technical solution provided by the present invention clearer and more detailed, the relevant principles of LDPC (Low-Density Parity-Check codes) codes are briefly introduced as follows:

[0054] LDPC code is a linear code defined by a sparse non-systematic check matrix H, which is used to correct errors that occur during transmission. The error correction capability of this code is very close to the Shannon limit, and it has a strong ability to correct multiple random errors. It is widely used in the fields of communication and storage. Before performing LDPC coding, it is necessary to construct a check matrix H in advance. The matrix contains only two elements, 0 and 1, and the number of 0s is much greater than the number of 1s. The number of 1s in each row of the matrix is ​​called the row weight, and the number of 1s in each column is called the column weight.

[0055] Each column in the check matrix corresponds to a codeword bit, called a variable node, and each row corresponds to a check equation, called a check node. The check matrix can be converted into a corresponding Tanner graph. Each element 1 in the check matrix corresponds to an edge in the Tanner graph. During decoding, the information of the variable node and the check node is updated through the edge loop in the Tanner graph.

[0056] The encoding process of LDPC code mainly includes two steps: first, construct a check matrix H of size (NK) × K, where N is used to represent the length of the transmitted codeword C, K is the length of the information bit, and NK is the length of the check information; then, construct a generator matrix G through the check matrix H, multiply the received information bit and each element of each row of the matrix correspondingly and then add them to satisfy H·C T =0, the encoding is successful.

[0057] There are two decoding schemes for LDPC codes: hard decision decoding and soft decision decoding. Hard decision decoding directly estimates the value of the bit node and then makes a threshold decision, while soft decision decoding extracts LLR information and iteratively updates it to achieve the purpose of error correction. Nowadays, the commonly used decoding scheme in flash memory is hybrid decoding. First, hard decision decoding is used for preliminary decoding. If the decoding fails, soft decision decoding technology is further used to further accurately decode according to the quantization level from 1 to 7. Commonly used decoding algorithms include the minimum sum algorithm. The specific decoding process includes: inputting initial LLR information, updating check nodes, updating variable nodes, and decoding decisions.

[0058] The specific LDPC code can be expressed as LDPC(n i ,j i ,k i ), where n i 、j i and k i denote the number of columns, column weight and row weight of the subcode check matrix respectively. i represents the function of the check matrix, then the relevant parameters satisfy m i =n i ×j i / k i ,j i <k i ,j i <<m i ,k i <<n i .

[0059] The following are examples.

[0060] Embodiment 1:

[0061] A two-dimensional LDPC error correction method suitable for flash memory, such as Figure 1 As shown, it includes: encoding step and decoding step.

[0062] like Figure 1 As shown, in this embodiment, the encoding step includes:

[0063] After performing two-dimensional LDPC encoding on each K information bits in the flash memory page, the obtained check bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page;

[0064] Two-dimensional LDPC coding includes:

[0065] Constructing an information matrix: divide the K information bits into B information bit blocks of size k, and take every c consecutive information bit blocks as a row in the information matrix, so as to obtain an information matrix with r rows and c columns; B = r*c;

[0066] Horizontal coding: For each row of information bit blocks in the information matrix, the first LDPC code is used to encode them respectively to generate m1 horizontal check bits corresponding to each row;

[0067] Longitudinal coding: for each column of information bit blocks in the information matrix, the second LDPC code is used to encode them respectively to generate m2 longitudinal check bits corresponding to each column;

[0068] The check bits include horizontal check bits and vertical check bits; the code rate R≥S info / S page , S page Indicates the flash page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

[0069] like Figure 1 As shown, in this embodiment, the decoding step includes:

[0070] For each K information bits in the flash memory page, two-dimensional LDPC decoding is performed to complete the encoding of the flash memory page;

[0071] Two-dimensional LDPC decoding includes:

[0072] Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits;

[0073] Horizontal decoding: For each row of information bit blocks in the information matrix M, after obtaining the corresponding m1 horizontal check bits from the OOB area of ​​the flash memory page, the current LLR information is used as the LLR information for LDPC decoding, and the first LDPC code is used for decoding. After the decoding of each row is completed, the LLR information is updated;

[0074] Vertical decoding: For each column of information bit blocks in the information matrix M, after obtaining the corresponding m2 vertical check bits from the OOB area of ​​the flash memory page, the current LLR information is used as the LLR information for LDPC decoding, and the second LDPC code is used for decoding. After the decoding of each column is completed, the LLR information is updated;

[0075] Iteration control: Iteratively execute horizontal decoding and vertical decoding until any preset iteration termination condition is reached.

[0076] This embodiment controls the code rate to ensure that the check information generated by the encoding can be completely stored in the OOB area. K information bits in the entire flash memory page are encoded each time. During encoding, the K information bits are further organized into an information matrix. The encoding of the K information bits is achieved by performing LDPC encoding on the rows and columns in the information matrix respectively, thereby realizing a two-dimensional LDPC encoding. Through such an encoding method, the codeword length is greatly shortened, thereby effectively improving the decoding efficiency and reducing the decoding delay.

[0077] Optionally, in this embodiment, the size of each flash memory page is 4KB, and the size of the OOB area in the flash memory page is 512B; in this embodiment, when encoding, half of the flash memory page data is selected each time, that is, K=2*1024*8=16384.

[0078] like Figure 2 As shown, for K information bits, this embodiment divides each 512B information bit into an information bit block, and obtains 4 information bit blocks in total. Every two consecutive information bit blocks are taken as a row, and an information matrix of 2 rows and 2 columns is constructed, that is, r = 2, c = 2. The number of information bits in each row is 1KB, and the number of information bits corresponding to each column is also 1KB.

[0079] To simplify the overall encoding / decoding logic, when the present invention performs two-dimensional LDPC encoding on K information bits, the first LDPC encoding and the second LDPC encoding use the same LDPC encoding, which are respectively denoted as LDPC1 and LDPC2. After encoding each row and each column, 512b of check bits are generated respectively, that is, m1=m2=512. Specifically, after encoding each row in the information matrix using LDPC1, 2×512b of horizontal check bits are generated, and after encoding each column in the information matrix using LDPC2, 2×512b of vertical check bits are generated.

[0080] The code length of the codeword generated by encoding is:

[0081] N=K+r×m1+c×m2=16384+1024+1024=18432;

[0082] Therefore, the encoding rate is R=K / N=16384 / 18432=8 / 9, and therefore, the generated parity bits can be completely stored in the OOB area of ​​the flash memory page.

[0083] After performing the above two-dimensional LDPC encoding on each K information bits in the flash memory page, the horizontal parity bits and the vertical parity bits generated by the encoding are both stored in the OOB area of ​​the flash memory page.

[0084] This embodiment performs two-dimensional LDPC decoding on K information bits in the flash memory page each time, such as Figure 3 As shown, the decoding process includes multiple iterations, each of which includes one horizontal decoding and one vertical decoding, so that the horizontal decoding and vertical decoding are continuously and alternately performed during the entire iteration. When the horizontal decoding or vertical decoding fails in a certain iteration, the vertical decoding or horizontal decoding performed subsequently may correct some error bits, so that the horizontal decoding or vertical decoding can play a role again in the next iteration, effectively ensuring the validity of the entire decoding step. In addition, each time the horizontal decoding or vertical decoding is successful, the LLR information will be updated, so that the next vertical decoding or horizontal decoding process has more accurate LLR information, further improving the LDPC decoding efficiency.

[0085] In the above-mentioned two-dimensional LDPC decoding process proposed in this embodiment, when in a certain iteration, the number of error rows successfully corrected in the horizontal decoding FlagRow=0 and the number of error columns successfully corrected in the vertical decoding FlagCol=0, it means that after the previous iteration, all error bits in the information matrix have been corrected, or there are still error bits in the information matrix, but new error bits can no longer be corrected through subsequent iterations.

[0086] Figure 3 The flowchart shown is a flowchart of performing multiple iterations of the two-dimensional LDPC decoding based on the number of rows when each information bit block in the above 2-row 2-column information matrix has an error. Figure 3 It can be seen that each round of horizontal and vertical decoding must achieve at least one row or one column of correction, otherwise the iteration stops.

[0087] Based on the above findings, in order to avoid invalid iterations without affecting the error correction capability, further improve the decoding efficiency, and reduce the iteration overhead, as a preferred implementation, in this embodiment, the iteration termination condition includes:

[0088] In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

[0089] In this implementation, since each time horizontal coding is performed, multiple rows in the information matrix are independently encoded, and each time vertical coding is performed, multiple categories in the information matrix are independently encoded, therefore, as a preferred implementation, in this embodiment, the encoding of each row of information bit blocks in the information matrix is ​​performed in parallel, and the encoding of each column of information bit blocks in the information matrix is ​​performed in parallel, thereby achieving a parallelism that one-dimensional LDPC codes do not have, further improving the coding efficiency. Similarly, since each time horizontal decoding is performed, multiple rows in the information matrix are independently decoded, and each time vertical decoding is performed, multiple categories in the information matrix are independently decoded, therefore, as a preferred implementation, in this embodiment, the decoding of each row of information bit blocks in the information matrix is ​​performed in parallel, and the decoding of each column of information bit blocks in the information matrix is ​​performed in parallel, further improving the decoding efficiency.

[0090] Similarly, the encoding / decoding process between K information bits and K information bits in the flash memory page can also be executed in parallel to further improve the encoding / decoding efficiency.

[0091] It is easy to understand that the above parallelism can be achieved by improving the flash memory controller.

[0092] It should be noted that the above-mentioned selection of flash memory page size, information matrix parameters, LDPC code, etc. are only exemplary descriptions and should not be understood as the only limitation on the present invention. In other embodiments of the present invention, the relevant parameters can be flexibly adjusted according to the actual flash memory error correction requirements, and the first LDPC code and the second LDPC code may also use different LDPC codes.

[0093] In general, this embodiment realizes horizontal and vertical LDPC encoding / decoding of information bits in flash memory based on one-dimensional LDPC code. On the one hand, it greatly shortens the codeword length and effectively improves the decoding efficiency. On the other hand, it can further improve the decoding efficiency through parallel operation. Under the premise of ensuring that no additional redundant space is added, the decoding delay of the flash memory system using LDPC code is significantly reduced.

[0094] Embodiment 2:

[0095] A two-dimensional LDPC error correction method applicable to flash memory. This embodiment is similar to the above-mentioned embodiment 1, except that this embodiment further optimizes the iteration termination condition in the two-dimensional LDPC decoding process.

[0096] According to the two-dimensional coding method adopted by the present invention, the number of iterations required to correct all correctable error bits during decoding can be calculated. Specifically, when the number of rows and columns of the information matrix is ​​equal, the number of iterations is the number of rows or columns. When the number of rows and columns of the information matrix is ​​not equal, the number of iterations is the sum of the smaller value of the number of rows and columns and 1. Based on this consideration, the present embodiment pre-calculates the number of iterations required to correct all correctable error bits, sets it as the maximum number of iterations Cycle, and uses the number of iterations reaching the maximum number of iterations Cycle as one of the iteration termination conditions.

[0097] The maximum number of iterations Cycle is calculated as follows:

[0098] If r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

[0099] This embodiment stops iteration after all the correctable error bits in the information matrix are corrected; while in Embodiment 1, after all the correctable error bits in the information matrix are corrected, one more iteration is required to determine FlagRow=0 and FlagCol=0, thereby stopping iteration. In comparison, this embodiment can further improve decoding efficiency and reduce iteration overhead without affecting error correction capability.

[0100] by Figure 3 For example, after two iterations, all the erroneous bits in the information matrix can be corrected. According to the iteration termination condition set in Example 1, the iteration will not be stopped until the third iteration is executed; and according to the iteration termination condition set in this embodiment, the maximum number of iterations can be calculated as Cycle=2, that is, the iteration is terminated after executing 2 iterations, which further reduces the number of iterations.

[0101] In this embodiment, the specific implementation of other steps can refer to the description in the above-mentioned embodiment 1 and will not be repeated here.

[0102] Embodiment 3:

[0103] A two-dimensional LDPC error correction method applicable to flash memory. This embodiment is similar to the above-mentioned embodiment 2, except that this embodiment further optimizes the iteration termination condition in the two-dimensional LDPC decoding process.

[0104] When the scale of the information matrix is large and the errors are randomly distributed in the information matrix, since it is difficult for the correction of a single row or column to affect the entire information matrix, it is difficult to carry out the iteration to the end. Most of the error bits can often be corrected in the previous few iterations. In subsequent iterations, only a few bit errors can be corrected each time, but more iterations will lead to an increase in decoding delay. Based on this discovery, in order to balance the error correction ability and decoding efficiency, in this embodiment, for an information matrix with a large scale, its iteration termination condition is set as follows:

[0105] Reaching the preset number of iterations T;

[0106] Where T is a preset positive integer, and T < Cycle. Cycle is the number of iterations required to correct all the correctable error bits, and its calculation method can refer to the description in Embodiment 2 above.

[0107] In this embodiment, for an information matrix with a small scale, the same iteration termination condition as in Embodiment 2 above is adopted.

[0108] In practical applications, a threshold th can be set to distinguish the scale of the information matrix. If min(r, c)>th, it is determined that the information matrix is an information matrix with a large scale; otherwise, it is determined that the information matrix is an information matrix with a small scale.

[0109] For an information matrix with a large scale, in order to effectively ensure the reliability of data storage while improving the decoding efficiency, this embodiment will determine the number of iterations T according to the actual data storage reliability requirements. Specifically, multiple information matrices with the same scale as the information matrix M are selected as observation matrices;

[0110] For each observation matrix, horizontal decoding and vertical decoding are iteratively executed respectively, and the change of the bit error rate of each observation matrix with the number of iterations is recorded;

[0111] Obtain the number of iterations corresponding to when the bit error rate of each observation matrix drops to the preset reliable threshold and calculate the average value as the pre-iteration number T.

[0112] In this embodiment, the specific implementation manners of other steps can refer to the description in Embodiment 1 above and will not be repeated here.

[0113] Embodiment 4:

[0114] A flash memory controller, comprising:

[0115] A computer-readable storage medium for storing a computer program;

[0116] and a processor, configured to read a computer program stored in a computer-readable storage medium and execute the two-dimensional LDPC error correction method applicable to a flash memory provided in any one of the above-mentioned embodiments 1 to 3.

[0117] Embodiment 5:

[0118] A storage device based on flash memory, comprising:

[0119] A flash memory chip and a flash memory controller provided in the above-mentioned embodiment 4.

[0120] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A two-dimensional LDPC error correction method suitable for flash memory, characterized in that: include: Coding steps; The encoding step comprises: After performing two-dimensional LDPC encoding on each K information bits in the flash memory page, the obtained check bits are stored in the OOB area of ​​the flash memory page to complete the encoding of the flash memory page; The two-dimensional LDPC encoding includes: Constructing an information matrix: divide the K information bits into B information bit blocks of size k, and take each c consecutive information bit blocks as a row in the information matrix, thus obtaining an information matrix with r rows and c columns; Horizontal coding: for each row of information bit blocks in the information matrix, use the first LDPC code to encode them respectively, and generate m1 horizontal check bits corresponding to each row; Longitudinal coding: for each column of information bit blocks in the information matrix, respectively encode using the second LDPC code to generate m2 longitudinal check bits corresponding to each column; The check bits include horizontal check bits and vertical check bits; the code rate R≥S info / S page , S page Indicates the flash page size, S info Indicates the size of the information bit storage area in the flash memory page; K is divisible by S info is a positive integer, and k is a positive integer that can divide K.

2. The two-dimensional LDPC error correction method for flash memory according to claim 1, characterized in that: Also includes: Decoding steps: The decoding step comprises: For each K information bits in the flash memory page, two-dimensional LDPC decoding is performed to complete the encoding of the flash memory page; The two-dimensional LDPC decoding includes: Initialization: Calculate the initial LLR information and obtain the information matrix M corresponding to the K information bits; Horizontal decoding: for each row of information bit blocks in the information matrix M, after obtaining the corresponding m1 horizontal check bits from the OOB area of ​​the flash memory page, using the current LLR information as the LLR information of LDPC decoding, and using the first LDPC code for decoding, after each row of decoding is completed, updating the LLR information; Vertical decoding: for each column of information bit blocks in the information matrix M, after obtaining the corresponding m2 longitudinal check bits from the OOB area of ​​the flash memory page, using the current LLR information as the LLR information of LDPC decoding, and using the second LDPC code for decoding, after each column decoding is completed, updating the LLR information; Iteration control: iteratively executing the horizontal decoding and the vertical decoding until any preset iteration termination condition is reached.

3. The two-dimensional LDPC error correction method applicable to flash memory as claimed in claim 2, characterized in that: The iteration termination conditions include: In the current iteration, the number of error rows successfully corrected in horizontal decoding FlagRow=0 and the number of error columns successfully corrected in vertical decoding FlagCol=0.

4. The two-dimensional LDPC error correction method applicable to flash memory as claimed in claim 2, characterized in that: The preset iteration termination condition includes: Reach the maximum number of iterations Cycle; Among them, if r=c, then Cycle=r; if r≠c, Cycle=min(r,c)+1; min means taking the minimum value.

5. The two-dimensional LDPC error correction method applicable to flash memory as claimed in claim 4, characterized in that: If min(r,c)>th, the preset iteration termination condition also includes: Reach the preset number of iterations T; Among them, th and T are both preset positive integers, T <Cycle。 6. The two-dimensional LDPC error correction method applicable to flash memory as claimed in claim 5, characterized in that: The method for determining the number of iterations T includes: Selecting multiple information matrices of the same size as the information matrix M as observation matrices; For each measurement matrix, iteratively perform the horizontal decoding and the vertical decoding respectively, and record the change of the bit error rate of each measurement matrix with the number of iterations; The number of iterations corresponding to when the bit error rate of each observation matrix drops to a preset reliable threshold is obtained and the average value is calculated as the pre-iteration number T.

7. The two-dimensional LDPC error correction method applicable to flash memory according to any one of claims 2 to 5, characterized in that: In the horizontal coding, the coding of each row of information bit blocks in the information matrix is ​​performed in parallel; in the vertical coding, the coding of each column of information bit blocks in the information matrix is ​​performed in parallel; In the horizontal decoding, the decoding of each row of information bit blocks in the information matrix is ​​performed in parallel; in the vertical decoding, the decoding of each column of information bit blocks in the information matrix is ​​performed in parallel.

8. The two-dimensional LDPC error correction method applicable to flash memory according to any one of claims 1 to 6, characterized in that: The first LDPC code and the second LDPC code are the same LDPC code.

9. A flash memory controller, characterized in that: include: A computer-readable storage medium for storing a computer program; and a processor, configured to read the computer program stored in the computer-readable storage medium and execute the two-dimensional LDPC error correction method applicable to flash memory as claimed in any one of claims 1 to 8.

10. A storage device based on flash memory, characterized in that: include: A flash memory chip, and a flash memory controller as claimed in claim 9.

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