Method of writing to flash memory cells

Abstract

The present disclosure provides a write method for a flash memory cell. The flash memory cell includes a storage transistor and a select transistor connected in series. The write method according to the present disclosure includes applying write voltages to electrodes of the flash memory cell and gate electrodes of the transistors, wherein the write method applies a lower write voltage to a gate electrode of a storage transistor to be written in a first write step and a higher write voltage to the gate electrode of the storage transistor to be written in a second write step based on a channel hot carrier injection mechanism. The write method for the flash memory cell according to the present disclosure adopts a write step of a double channel hot carrier injection mechanism, which can reduce the impact of trap charge mismatch effect (TCME) compared to existing write methods, thereby improving durability and retention reliability.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a write method of a flash memory cell. BACKGROUND

[0002] Flash memory, abbreviated as flash, is a kind of non-volatile memory, i.e. the stored data will not be lost in the case of power off, which is particularly suitable for mobile communication and computer storage components and other fields. In addition, some flash memories also have high-density storage capacity, which is suitable for applications in large-capacity mobile storage media and other aspects.

[0003] The conventional flash memory adopts a floating gate type cell structure. The floating gate type non-volatile memory originates from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. The structure increases a metal floating gate and an ultra-thin tunneling oxide layer on the basis of the conventional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), so as to store charges by using the metal floating gate. Based on this, Masuoka et al. first proposed the concept of flash memory in 1984, i.e. to realize high-speed erasing ability by erasing by blocks and writing (programming) by bits, and to eliminate the necessary selection tube in EEPROM (Erasable Programmable Read-only memory), so as to have smaller storage cell size. After the emergence of flash memory, it has been rapidly developed due to its high write speed, high integration and superior performance. Intel Corporation proposed an ETOX structure flash memory cell (ETOX: Electron Tunneling Oxide device) in 1988, which has become the basis for the development of most floating gate type flash memory cell structures to date.

[0004] However, the floating gate type flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory cell increases the vertical height of the gate structure, which is not conducive to the scaling of the process size and the cell area; and because of the conductivity of the floating gate, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory. To solve the problems of the floating gate type flash memory, such as complex process and poor reliability, researchers have proposed a charge trapping memory (CTM) using a silicon nitride medium to store charge, also known as a SONOS type (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory. Based on this, B. Eitan et al. proposed a two-bit memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, which uses the non-conductive property of the insulating silicon nitride storage medium to realize two storage bits at the source end and the drain end of a storage transistor, respectively. However, this cell structure has the disadvantages of mutual interference between the two storage bits, and the device size cannot be scaled down. On the other hand, the existing SONOS type flash memory cell generally uses the channel hot electron injection (CHE) physical effect for writing operation, and uses the band-to-band hot hole injection (BBHH) physical effect or the FN tunneling physical effect for erasing operation. Because the physical mechanisms used for writing and erasing are different, the distribution of the trapped electron charges injected by the writing operation and the trapped hole charges injected by the erasing operation is inconsistent, i.e., the trapped charge mismatch effect (TCME) is prone to occur, which leads to the degradation of the endurance and retention reliability of the flash memory cell.

[0005] However, the existing floating gate type ETOX flash memory and SONOS type NROM flash memory both have the problems of unable to scale down the process size, large cell area, high writing power consumption, and large array area overhead, and cannot realize high-density integration of gigabit (Gb) capacity or above.

[0006] With the rapid development of mobile intelligent terminals, wearable devices, intelligent sensor networks and other applications, higher requirements are put forward for the power consumption, storage capacity and cost of flash memory. Therefore, a flash memory technology with low power consumption, small cell area, scalable process size, high array integration density, large capacity and other advantages is needed. SUMMARY

[0007] The above information disclosed in the background section of the present disclosure is only for understanding the background of the inventive concept, and therefore it can contain information that does not constitute the prior art.

[0008] To solve the above problems existing in the prior art, the present disclosure proposes a writing method of a flash memory cell, also known as a programming method.

[0009] According to an aspect of the present disclosure, there is provided a write method of a flash memory cell including a substrate including a deep well region and a well region disposed on the deep well region, a memory transistor disposed on the well region and configured to store data, and a pass transistor disposed on the well region at a side of the memory transistor in a horizontal direction and configured to perform a pass operation on the memory transistor, wherein the memory transistor and the pass transistor are connected in series, wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell, and a drain region of the pass transistor is connected to a second electrode of the flash memory cell, the write method including: a first write step of performing a write operation on the memory transistor by applying a first write voltage to the first electrode, applying a second write voltage to the second electrode, applying a third write voltage to a gate electrode of the memory transistor, and applying a fourth write voltage to a gate electrode of the pass transistor; and a second write step of performing a write operation on the memory transistor by applying the first write voltage to the first electrode, applying the second write voltage to the second electrode, applying a sixth write voltage higher than the third write voltage to the gate electrode of the memory transistor, and applying the fourth write voltage to the gate electrode of the pass transistor, wherein the fourth write voltage is equal to or lower than a first power supply voltage, the second write voltage is equal to or higher than a second power supply voltage, the first write voltage is higher than a preset voltage, the third write voltage is higher than the first write voltage, wherein the first power supply voltage is higher than the second power supply voltage, wherein the preset voltage is previously set according to a carrier barrier height at an interface between the substrate and a gate dielectric stack of the memory transistor, wherein the first write voltage and the fourth write voltage are higher than the second write voltage, and wherein both the memory transistor and the pass transistor are turned on during the write operation of the flash memory cell.

[0010] According to another aspect of the present disclosure, there is provided a write method of a flash memory cell, the flash memory cell including a substrate including a deep well region and a well region disposed on the deep well region; a first storage transistor disposed on the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; and a pass transistor disposed between the first storage transistor and the second storage transistor in a horizontal direction on the well region, configured to isolate and perform a pass operation on the first storage transistor and the second storage transistor, wherein the first storage transistor, the pass transistor, and the second storage transistor are connected in series, wherein a source region of the first storage transistor is connected to a first electrode of the flash memory cell, a drain region of the second storage transistor is connected to a second electrode of the flash memory cell, the write method including: a first write step of performing a write operation on the first storage transistor or the second storage transistor by applying a first write voltage to the first electrode or the second electrode, applying a second write voltage to the second electrode or the first electrode, applying a third write voltage to a gate electrode of the first storage transistor or the second storage transistor, applying a fourth write voltage to a gate electrode of the pass transistor, and applying a fifth write voltage to a gate electrode of the second storage transistor or the first storage transistor; and a second write step of performing a write operation on the first storage transistor or the second storage transistor by applying the first write voltage to the first electrode or the second electrode, applying the second write voltage to the second electrode or the first electrode, applying a sixth write voltage higher than the third write voltage to the gate electrode of the first storage transistor or the second storage transistor, applying the fourth write voltage to the gate electrode of the pass transistor, and applying the fifth write voltage to the gate electrode of the second storage transistor or the first storage transistor, wherein the fourth write voltage is equal to or lower than a first power voltage, the second write voltage is equal to or higher than a second power voltage, the first write voltage is higher than a preset voltage, the third write voltage is higher than the first write voltage, wherein the first power voltage is higher than the second power voltage, wherein the preset voltage is previously set according to a carrier barrier height at an interface between the substrate and a gate medium stack of the first storage transistor and the second storage transistor, wherein the first write voltage, the fourth write voltage, and the fifth write voltage are higher than the second write voltage, and wherein the first storage transistor, the second storage transistor, and the pass transistor are all turned on during the write operation of the flash memory cell.

[0011] The write method of the flash memory cell according to the present disclosure adopts a write step of a double channel hot carrier injection mechanism, which can form a lower trap charge concentration on a side close to the pass transistor and a higher trap charge concentration on a side away from the pass transistor in a storage medium layer of the storage transistor, compared to existing write methods, thereby increasing a storage window and reducing the influence of trap charge mismatch effect (TCME), and thus improving durability and retention reliability.

[0012] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing General Description and the following Detailed Description are exemplary and explanatory, and are intended to provide further explanation of the application as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description serve to explain the principles of the application.

[0014] Figure 1 A cross-sectional view of a flash memory cell according to an embodiment of the present disclosure is shown.

[0015] Figure 2 An equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram showing a write operation performed on a first storage transistor by a first write step of a write method according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram showing a write operation performed on a first storage transistor by a second write step of a write method according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A schematic diagram showing a write operation performed on a second storage transistor by a first write step of a write method according to an embodiment of the present disclosure is shown.

[0019] Figure 6 A schematic diagram showing a write operation performed on a second storage transistor by a second write step of a write method according to an embodiment of the present disclosure is shown.

[0020] Figure 7 A cross-sectional view of a flash memory cell according to another embodiment of the present disclosure is shown.

[0021] Figure 8 An equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure is shown.

[0022] Figure 9 A schematic diagram showing a write operation performed on a storage transistor by a first write step of a write method according to another embodiment of the present disclosure is shown.

[0023] Figure 10A schematic diagram showing a write operation performed on a storage transistor by a second write step of a write method according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more exemplary embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable terms, and are non-limiting examples of an apparatus or method employing one or more inventive concepts disclosed herein. It will be evident, however, that exemplary embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to not obscure the understanding of this description. Also, the exemplary embodiments can be different, but not necessarily mutually exclusive. For example, specific shapes, configurations, and characteristics of an exemplary embodiment can be used or implemented in other exemplary embodiments without departing from the inventive concepts.

[0025] Unless otherwise indicated, the exemplary embodiments described are to be understood as providing examples of the variations of some of the ways in which the inventive concepts can be implemented in practice. Accordingly, unless otherwise indicated, the features, components, modules, layers, films, substrates, regions and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged, without departing from the inventive concepts.

[0026] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries and / or regions of elements. As such, no hatching or shading is insinuating any preference or requirement for any particular material, material property, size, proportion, commonality of the depicted elements, and / or any other characteristic, attribute, shape, etc. of the elements being presented, unless otherwise indicated. Moreover, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be practiced differently, a particular processing sequence can be performed differently than described. For example, two consecutively described processes can be executed substantially simultaneously or in an order opposite to that described. Also, like reference numerals denote like elements.

[0027] When an element such as a layer "is on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intermediate elements or layers can be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, then there are no intermediate elements or layers present. It will be appreciated that for purposes of this disclosure, the term "connected" can include physical, electrical, and / or fluidic connections as well as any intermediate elements that do not substantially alter the physical, electrical, and / or fluidic connection. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0029] Spatially relative terms, such as "beneath," "below," "lower," "under," "above," "upper," "higher," and "sidewall" (as in "sidewall"), and the like, can be used herein for descriptive purposes, for example, to describe one element's relationship to another element(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an orientation of above and below. Moreover, the device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "a" or "an," or the like are used in the detailed description and / or claims, such terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition term without precluding any additional or other elements.

[0031] Embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of idealized embodiments and / or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments disclosed herein are not to be construed as being limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for example, manufacturing. In this manner, regions illustrated in the figures can have a somewhat inexact shape that is not to be construed as limiting.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms, such as "though" and "although," are used as interrogative forms so as to reflect that a statement made not definitely or to call attention to a prior statement that has been made. The terms of degree such as "substantially," "about," and "approximately" which are used herein, are used to indicate an action, attribute, or characteristic that can not be completely exact, but that is understood to be close to the action, attribute, or characteristic for the specific context of the action, attribute, or characteristic. Nothing in the foregoing is to be construed as limiting the present disclosure to a single embodiment.

[0033] Figure 1 A cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown.

[0034] As Figure 1 shown, a flash memory cell MC 100 according to an embodiment of the present disclosure can include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

[0035] Although the first doping type is defined as P-type and the second doping type is defined as N-type in Figure 1 the embodiments as an example, it will be appreciated by those skilled in the art that the present disclosure is not limited thereto, and the first doping type can also be N-type, in which case the second doping type can be P-type.

[0036] According to embodiments of the present disclosure, the substrate 101 can be, for example, a silicon (Si) substrate.

[0037] Further, the flash memory cell MC 100 includes a first memory transistor MS 110, a gate transistor MG 120, and a second memory transistor MD 130 connected in series. The first memory transistor MS 110 can be disposed on the well region PW 102 and store first data DATA1. The second memory transistor MD 130 can be disposed on the well region PW 102 and store second data DATA2. The gate transistor MG 120 is disposed between the first memory transistor MS 110 and the second memory transistor MD 130 along the horizontal direction DR1 on the well region PW 102, for isolating and performing a gate operation on the first memory transistor MS 110 and the second memory transistor MD 130.

[0038] According to embodiments of the present disclosure, the flash memory cell MC 100 includes two memory transistors MS 110 and MD 130, and thus the flash memory cell MC 100 is capable of realizing the function of two-bit storage, i.e., storing the first data DATA1 and the second data DATA2 at the same time.

[0039] Further, as shown in FIG. 1, the source region of the first memory transistor MS 110 is connected to a first electrode S of the flash memory cell MC 100, which can also be referred to as a source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to a second electrode D of the flash memory cell MC 100, which can also be referred to as a drain D of the flash memory cell MC 100. Figure 1

[0040] Those skilled in the art will appreciate that the source and the drain of the flash memory cell are defined herein for ease of description, however, the definition of the source and the drain of the flash memory cell is relative, and the terms "source" and "drain" can be used interchangeably under different working conditions.

[0041] Further, as shown in FIG. 1, the source region of the first memory transistor MS 110 is connected to a first electrode S of the flash memory cell MC 100, which can also be referred to as a source S of the flash memory cell MC 100, and the drain region of the second memory transistor MD 130 is connected to a second electrode D of the flash memory cell MC 100, which can also be referred to as a drain D of the flash memory cell MC 100. Figure 1 ​As shown, the first storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially arranged along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. Furthermore, the second storage transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask blocking portion 137 sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked along the vertical direction.

[0042] According to embodiments of this disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, thus enabling two-bit storage functionality.

[0043] According to embodiments of this disclosure, such as Figure 1 As shown, the flash memory cell MC 100 for two-bit storage can be composed of three closely arranged transistors: a gating transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS110 located at the first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at the second end of the flash memory cell MC 100.

[0044] like Figure 1 As shown, the flash memory cell MC 100 can be formed on the well region PW 102 within the semiconductor substrate 101. Furthermore, in order to isolate the well region PW 102 from the substrate 101 so that a voltage can be applied to the well region PW 102 under certain operating conditions, such as... Figure 1 As shown, the well region PW 102 can be formed in the deep well region DNW 103.

[0045] like Figure 1 As shown, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 100. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0046] According to embodiments of this disclosure, the first electrode S and the second electrode D may comprise metal or highly doped polycrystalline silicon. When the first electrode S and the second electrode D are formed of metal, they may comprise at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0047] As mentioned above, Figure 1 As shown, the gate structure of the first storage transistor MS110 may, from bottom to top, include a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 for sidewall self-alignment. According to embodiments of this disclosure, the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials. According to embodiments of this disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, silicon glass material, or a combination of the above materials.

[0048] In addition, such as Figure 1 As shown, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (barrier oxide layer) 115 stacked sequentially from bottom to top along the vertical direction DR2. According to embodiments of this disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide. According to embodiments of this disclosure, the thickness of the first oxide layer (tunneling oxide layer) 113 may be 1 to 15 nm.

[0049] According to embodiments of this disclosure, the storage medium layer 114 may include one or more layers of storage media. Furthermore, according to embodiments of this disclosure, the storage medium forming the storage medium layer 114 may include: mono- or multi-component oxides, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; mono- or multi-component nitrides, such as silicon nitride; mono- or multi-component nitrides, such as silicon oxynitride; polycrystalline silicon or nanocrystalline materials; or combinations of the above materials.

[0050] According to embodiments of this disclosure, when the storage medium layer 114 is formed of, for example, silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS110 can be a SONOS (silicon-oxide-nitride-oxide-silicon) type storage transistor.

[0051] Furthermore, according to embodiments of this disclosure, the first storage transistor MS110 may be another trap charge-trapping storage transistor with a similar operating mechanism to the SONOS type storage transistor. This type of storage transistor uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., to replace the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0052] Furthermore, according to embodiments of the present disclosure, the first memory transistor MS 110 can also be a floating gate memory transistor, which type of memory transistor employs a polysilicon material to replace the silicon nitride material in a SONOS memory to form a floating gate for storing charges as the storage medium layer 114.

[0053] Furthermore, according to embodiments of the present disclosure, the first memory transistor MS 110 can also be a nano-crystal memory, which type of memory transistor employs a nano-crystal material with quantum dots to replace the silicon nitride material in a SONOS memory as the storage medium layer 114.

[0054] According to embodiments of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS 110 can be defined by the length of the hard mask stopper 117 provided on the gate electrode 116 through a self-alignment process. It is noted by those skilled in the art that the "length" mentioned herein means the size of the stated object in the first direction DR1.

[0055] According to embodiments of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS 110 and can be manufactured by the same process as the first memory transistor MS 110 except that it is provided on the opposite side of the gate transistor MG 120, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted here for brevity.

[0056] The gate structure of the gate transistor MG 120 can include, in order from bottom to top, a channel region 121, a gate dielectric layer 122, and a gate electrode 123. According to embodiments of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process size of a photolithography process. According to embodiments of the present disclosure, the gate dielectric layer 122 can include, for example, a material such as silicon oxide, silicon oxynitride, hafnium oxide, etc. Furthermore, according to embodiments of the present disclosure, the gate electrode 123 can include, for example, a polysilicon, a metal gate, a metal silicide material, or a combination of the above-mentioned materials.

[0057] According to embodiments of the present disclosure, the channel regions 111, 131, and 121 of the first memory transistor MS 110, the second memory transistor MD 130, and the gate transistor MG 120 can all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first memory transistor MS 110 and the second memory transistor MD 130 can be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

[0058] Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may have a second doping type or an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0059] For example, such as Figure 1 As shown, when the first doping type is P-type and the second doping type is N-type, the doping concentration of the P-type channels 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 is lower than the doping concentration of the P-type channel 121 of the gate transistor MG120. Furthermore, according to embodiments of this disclosure, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0060] According to embodiments of this disclosure, the flash memory cell MC 100 may further include: a first isolation portion 124, which is disposed horizontally DR1 between the first storage transistor MS110 and the gate transistor MG 120, for isolating the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125, which is disposed horizontally DR1 between the gate transistor MG 120 and the second storage transistor MD 130, for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130.

[0061] Specifically, such as Figure 2 As shown, a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120. They are used to electrically isolate the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length, respectively. According to an embodiment of this disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

[0062] The flash memory cell according to the embodiments of this disclosure can realize two storage transistors in one flash memory cell, thus greatly reducing the equivalent area of ​​each storage bit, thereby achieving lower cost and higher integration density.

[0063] Furthermore, the storage transistors in the flash memory cells according to the embodiments of this disclosure can adopt a simple SONOS-type device structure, which has the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.

[0064] In addition, in the flash memory cell according to the embodiment of the present disclosure, the mutual influence of two storage bits is isolated by the gate transistor, and the distribution width and lateral diffusion of the storage charge are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, and the problems of wide charge distribution, large mutual interference, and inability to reduce the gate length of the existing NROM memory cell with two-bit storage are avoided, and the storage window and data reliability are significantly improved.

[0065] In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the length of the gate electrode of the gate transistor is defined by the process feature size of the photolithography process, and is usually equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithography process, which is usually denoted as F (or CF). In addition, the lengths of the gate electrodes of the first storage transistor and the second storage transistor are defined by the lengths of the self-aligned sidewall hard mask blocking portions, and thus can be smaller than F. Therefore, according to the embodiment of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, and the area and manufacturing cost of the flash memory cell can be reduced.

[0066] In addition, in the flash memory cell array composed of the flash memory cell according to the embodiment of the present disclosure, for the flash memory cells that are not selected for operation, the gate electrodes of the gate transistor and the first and second storage transistors are grounded, so that the entire series channel of the flash memory cell is completely turned off, the equivalent channel length is expanded, and thus the source-drain punchthrough of the flash memory cell under high operating voltage can be avoided under a smaller process feature size, thereby overcoming the problem that the length of the gate electrode of the existing flash memory cell cannot be reduced with the reduction of the process feature size. Therefore, the flash memory cell according to the embodiment of the present disclosure has better process scaling capability, and thus smaller cell area and manufacturing cost can be obtained by reducing the process feature size.

[0067] In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first storage transistor and the second storage transistor or designing it as an N-type doped channel region, the threshold voltage of the storage transistor and the gate electrode operating voltage during the erase and read operations can be reduced, and thus the reliability of the storage transistor can be improved. At the same time, by increasing the doping concentration of the P-type channel region of the gate transistor, the punchthrough voltage resistance of the flash memory cell can be improved, and the leakage current between the source and the drain of the unselected flash memory cell can be reduced.

[0068] Figure 3 An equivalent circuit diagram of the flash memory cell MC 100 according to the embodiment of the present disclosure is shown. Figure 4A diagram showing a write operation performed on the first memory transistor MS 110 by a first write step of a write method according to an embodiment of the present disclosure is shown. Figure 3 A diagram showing a write operation performed on the first memory transistor MS 110 by a second write step of a write method according to an embodiment of the present disclosure is shown. In Figure 4 and Figure 5 and the following Figure 6 and Figure 2 In the drawings described below,

[0069] Specifically, as shown in Figure 2 , the flash memory cell MC 100 includes the first memory transistor MS 110, the gate transistor MG 120, and the second memory transistor MD 130 connected in series. The gate transistor MG 120 can isolate the first memory transistor MS 110 and the second memory transistor MD 130 and perform a gate-on operation on the first memory transistor MS 110 and the second memory transistor MD 130. As shown in Figure 3 , by controlling the voltages applied to the source region (i.e., the first electrode S) of the first memory transistor MS 110, the gate electrode 116 of the first memory transistor MS 110, the gate electrode 123 of the gate transistor MG 120, the gate electrode 136 of the second memory transistor MD 130, and the drain region (i.e., the second electrode D) of the second memory transistor MD 130, a write operation on the first memory transistor MS 110 or the second memory transistor MD 130 can be achieved, respectively.

[0070] According to an embodiment of the present disclosure, a write operation on the first memory transistor MS 110 or the second memory transistor MD 130 can be performed by two steps, i.e., a first write step and a second write step, in sequence, respectively.

[0071] According to an embodiment of the present disclosure, when performing a write operation on the flash memory cell MC 100, the P-well 102 of the flash memory cell MC 100 can be grounded or a negative voltage lower than the ground voltage can be applied.

[0072] Specifically, according to an embodiment of the present disclosure, as shown in Figure 1 , a write operation on the first memory transistor MS 110 of the flash memory cell MC 100 is first performed by a first write step. At this time, the first write voltage VW1 is applied to the first electrode S, the second write voltage VW2 is applied to the second electrode D, the third write voltage VW3 is applied to the gate electrode 116 of the first memory transistor MS 110, the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120, and the fifth write voltage VW5 is applied to the gate electrode 136 of the second memory transistor MD 130.

[0073] According to embodiments of the present disclosure, the first write voltage VW1 can be higher than a preset voltage, where the preset voltage is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the first memory transistor MS110. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 can be in a range of 3 V to 6 V. For example, according to embodiments of the present disclosure, the first write voltage VW1 can be 4.4 V. According to embodiments of the present disclosure, the first write voltage VW1 can be provided by an external constant voltage source. Figure 4 In the flash memory cell MC100 shown, the preset voltage can enable an electron to overcome an electron barrier at an interface between the P-type channel region 111 and a lower first oxide layer (tunnel oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 can be in a range of 3 V to 6 V. For example, according to embodiments of the present disclosure, the first write voltage VW1 can be 4.4 V. According to embodiments of the present disclosure, the first write voltage VW1 can be provided by an external constant voltage source.

[0074] According to embodiments of the present disclosure, the second write voltage VW2 can be equal to or higher than a second supply voltage VSS, where the second supply voltage VSS can be a ground voltage GND. For example, according to embodiments of the present disclosure, the second write voltage VW2 can be 0.2 V. Further, according to embodiments of the present disclosure, the second write voltage VW2 can be connected to the second supply voltage VSS through a constant current load.

[0075] According to embodiments of the present disclosure, the third write voltage VW3 can be higher than the first write voltage VW1. According to embodiments of the present disclosure, the third write voltage VW3 can be in a range of 4 V to 10 V. For example, according to embodiments of the present disclosure, the third write voltage VW3 can be 5.4 V.

[0076] According to embodiments of the present disclosure, the fourth write voltage VW4 can be equal to or lower than a first supply voltage VDD, where the first supply voltage VDD is higher than the second supply voltage VSS and can be in a range of 0.8 V to 5 V. For example, according to embodiments of the present disclosure, the fourth write voltage VW4 can be 1 V.

[0077] According to embodiments of the present disclosure, the first write voltage VW1, the fourth write voltage VW4, and the fifth write voltage VW5 can be higher than the second write voltage VW2. According to embodiments of the present disclosure, the fifth write voltage VW5 can be in a range of 3 V to 8 V. For example, according to embodiments of the present disclosure, the fifth write voltage VW5 can be 5 V.

[0078] Furthermore, according to embodiments of this disclosure, during the first write step of the flash memory cell MC 100, the first to fifth write voltages VW1 to VW5 turn on the first storage transistor MS110, the second storage transistor MD 130, and the gating transistor MG120.

[0079] Subsequently, according to embodiments of this disclosure, such as Figure 5 As shown, a write operation is then performed on the first storage transistor MS110 of the flash memory cell MC100 through a second write step. At this time, the first write voltage VW1 applied to the first electrode S, the second write voltage VW2 applied to the second electrode D, the fourth write voltage VW4 applied to the gate electrode 123 of the gate transistor MG 120, and the fifth write voltage VW5 applied to the gate electrode 136 of the second storage transistor MD 130 remain unchanged, and a sixth write voltage VW6 is applied to the gate electrode 116 of the first storage transistor MS110. According to an embodiment of this disclosure, the sixth write voltage VW6 can be greater than the third write voltage VW3. According to an embodiment of this disclosure, the sixth write voltage VW6 can be in the range of 5V to 12V. For example, as described above, the third write voltage VW3 can be 5.4V, and the sixth write voltage VW6 can be 6.2V.

[0080] Furthermore, according to embodiments of this disclosure, during the second write step of the flash memory cell MC 100, the first, second, sixth, fourth and fifth write voltages VW1, VW2, VW6, VW4 and VW5 turn on the first storage transistor MS110, the second storage transistor MD 130 and the gating transistor MG 120.

[0081] Figure 6 A schematic diagram is shown of a write operation performed on a second storage transistor MD 130 by a first write step of a write method according to an embodiment of the present disclosure. Figure 5 A schematic diagram is shown of performing a write operation on a second storage transistor MD 130 by a second write step of a write method according to an embodiment of the present disclosure.

[0082] Similarly, according to embodiments of this disclosure, such as Figure 6 As shown, when performing a write operation on the second storage transistor MD 130 of the flash memory cell MC 100, the second write voltage VW2 is first applied to the first electrode S through the first write step, the first write voltage VW1 is applied to the second electrode D, the fifth write voltage VW5 is applied to the gate electrode 116 of the first storage transistor MS110, the fourth write voltage VW4 is applied to the gate electrode 123 of the gate transistor MG 120, and the third write voltage VW3 is applied to the gate electrode 136 of the second storage transistor MD 130.

[0083] Subsequently, as shown in FIG. 2B, a write operation is performed on the first memory transistor MS 110 of the flash memory cell MC 100 by a second write step. At this time, the second write voltage VW2 applied to the first electrode S, the first write voltage VW1 applied to the second electrode D, the fourth write voltage VW4 applied to the gate electrode 123 of the pass transistor MG 120, and the fifth write voltage VW5 applied to the gate electrode 116 of the first memory transistor MS 110 remain unchanged, and a sixth write voltage VW6 is applied to the gate electrode 136 of the second memory transistor MD 130. Figure 3

[0084] As can be seen, due to the symmetric structure of the flash memory cell MC 100, the write voltages VW1 to VW5 applied during the write operation of the first memory transistor MS 110 and the second memory transistor MD 130, i.e., during the execution of the first write step and the second write step, also have a symmetric relationship. Therefore, for the sake of brevity, the write voltages applied during the write operation of the second memory transistor MD 130 are not repeatedly described here.

[0085] According to the embodiments of the present disclosure, the write operation of the first memory transistor MS 110 and the second memory transistor MD 130 described above adopts a double-channel hot electron injection mechanism.

[0086] Specifically, taking the first memory transistor MS 110 as an example, when a write operation is performed on the first memory transistor MS 110 by the first write step, the gate electrode 123 of the pass transistor MG 120 is applied with the fourth write voltage VW4 slightly higher than its threshold voltage, so it is in a weakly on state, thereby suppressing the on current (generally in the order of microamperes) of the flash memory cell MC 100, which greatly reduces the voltage difference of the series channel (121 and 131) of the pass transistor MG 120 and the second memory transistor MD 130. Therefore, the voltage difference VW1-VW2 between the first electrode S and the second electrode D of the flash memory cell MC 110 is mostly applied to the on channel region 111 of the first memory transistor MS 110, so that the channel hot electron injection physical effect occurs, and under the attraction of the relatively low (e.g., 5.4V) third write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS 110, electrons are injected into the storage medium layer 114, so that the threshold voltage of the first memory transistor MS 110 rises.

[0087] At this time, as shown in FIG. 2B, a write operation is performed on the first memory transistor MS 110 of the flash memory cell MC 100 by a second write step. At this time, the second write voltage VW2 applied to the first electrode S, the first write voltage VW1 applied to the second electrode D, the fourth write voltage VW4 applied to the gate electrode 123 of the pass transistor MG 120, and the fifth write voltage VW5 applied to the gate electrode 116 of the first memory transistor MS 110 remain unchanged, and a sixth write voltage VW6 is applied to the gate electrode 136 of the second memory transistor MD 130. Figure 1 ​As shown, in the first write step, the channel hot electron injection spreads from the side of the gate transistor MG 120 to the first storage transistor MS 110, and the electrons are trapped along the entire channel region of the first storage transistor MS 110 being written. However, in the first write step, in the storage medium layer 114, the electrons can accumulate at the side close to the gate transistor MG 120, causing difficulty to be effectively erased in the subsequent hot hole erase operation, thus inducing the trap charge mismatch effect (TCME) in the program-erase cycling operation. In particular, the local residual electrons cause the threshold voltage of the first storage transistor MS 110 to increase and the read current to decrease, while the recombination of the residual charge causes the retention performance to decrease.

[0088] In the prior art, simply by reducing the third write voltage VW3 in the first write step can weaken the accumulation concentration of the electrons at the side close to the gate transistor MG 120, thus mitigating the impact of the TCME, but this can cause the threshold voltage window of the write to be smaller, and there is a problem of retention performance degradation.

[0089] Therefore, according to the embodiments of the present disclosure, a second write step is introduced after the first write step. As described above, according to the embodiments of the present disclosure, in the second write step, a sixth write voltage VW6 (e.g., 6.2V) higher than the third write voltage VW3 is applied to the gate electrode 116 of the first storage transistor MS 110. It needs to be particularly pointed out that in the storage medium layer 114, a small amount of electron charge has accumulated at the side close to the gate transistor MG 120 by the first write step, and due to the shielding effect of this electron charge on the longitudinal gate electric field, the electrons injected in the second write step will only accumulate at the side away from the gate transistor MG 120, thus only increasing the trap charge concentration of the local region away from the gate transistor MG 120 and increasing the storage window, while the trap electrons in this region are more easily effectively erased in the subsequent hot hole erase operation.

[0090] According to embodiments of the present disclosure, a lower third write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS 110 in the first write step can be used to write (program) the first memory transistor MS 110 to a lower threshold voltage to avoid accumulation of too many electrons on the side of the gate transistor MG 120. Subsequently, according to embodiments of the present disclosure, a higher sixth write voltage VW3 applied to the gate electrode 116 of the first memory transistor MS 110 in the second write step can be used to increase the trap electron density near the opposite side (i.e. the source side) of the gate transistor MG 120 to expand the threshold voltage window of the write. In particular, for charge-trapping type memory devices, the charge programmed into the storage medium has a localized distribution characteristic, i.e. different trap charge concentration distribution along the channel. The dual-channel hot electron write mechanism (DCHE) according to the present disclosure can form a lower trap charge concentration near one side of the gate transistor MG 120 and a higher trap charge concentration away from the other side of the gate transistor MG 120, so that a one-sided Gaussian distribution of trapped charges can be formed, thereby mitigating the impact of TCME, improving durability and retention reliability.

[0091] Furthermore, since the gate electrode length of the first memory transistor MS 110 is much smaller than the equivalent channel length of the flash memory cell MC 100, the lateral electric field and the channel hot electron injection efficiency of the on channel of the first memory transistor MS 110 can be significantly increased. Therefore, the write method according to embodiments of the present disclosure has the advantages of low operating power consumption and fast write speed compared to the existing channel hot electron injection write method, and can improve the memory data write throughput by increasing the number of cells written in parallel.

[0092] Therefore, those skilled in the art should recognize that, although the above describes the write method (including the multi-value write method) of the flash memory cell of the present disclosure in conjunction with Figure 1 the flash memory cell MC 100 shown in the figures, the write method of the flash memory cell of the present disclosure is not limited to Figure 7 the flash memory cell MC 100 shown in the figures. Those skilled in the art can conceive, according to the teachings of the present disclosure, to apply the write method of the flash memory cell of the present disclosure to other types of flash memory cells, such as flash memory cells including only one memory transistor, and all these variants should be covered within the scope of the present disclosure.

[0093] Figure 8 A cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure is shown. Figure 7 An equivalent circuit diagram of the flash memory cell MC 200 according to another embodiment of the present disclosure is shown.

[0094] AsFigure 8 and Figure 1 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 2 and Figure 7 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 8 and Figure 1 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 2 and Figure 7 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included.

[0095] As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 7 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included.

[0096] Figure 8 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 7 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included.

[0097] Figure 7 As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included.

[0098] As shown in FIG. 20, the flash memory cell MC 200 differs from the flash memory cell MC 100 described above with reference to FIG. 1 only in that the flash memory cell MC 200 includes only one storage transistor, which can correspond to the first storage transistor MS 110 in the flash memory cell MC 100, and thus in the flash memory cell MC 200, the second storage transistor MS 210 in the flash memory cell MC 100 is not included. Figure 7 ​​As shown, according to another embodiment of this disclosure, the storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially disposed along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. According to an embodiment of this disclosure, when the storage dielectric layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO composite storage dielectric. In this case, the storage transistor MS110 can be a SONOS-type storage transistor.

[0099] like Figure 7 As shown, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include, from bottom to top, a channel region 121, a gate dielectric layer 122, and a gate electrode 123.

[0100] like Figure 7 As shown, according to another embodiment of this disclosure, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 200. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0101] like Figure 9 As shown, according to another embodiment of the present disclosure, the flash memory cell MC 200 may further include an isolation section 124, which is disposed in the horizontal direction DR1 between the storage transistor MS110 and the gate transistor MG 120, for isolating the gate electrode 116 of the storage transistor MS110 and the gate electrode 123 of the gate transistor MG 120.

[0102] Figure 10 A schematic diagram is shown of performing a write operation on a storage transistor MS110 by a first write step of a write method according to another embodiment of the present disclosure. Figure 9 A schematic diagram illustrates a write operation performed on a storage transistor MS110 via a second write step of a write method according to another embodiment of this disclosure. Figure 10 and Figure 8 In the diagram, hollow circles represent holes, and solid circles represent electrons.

[0103] Specifically, such as Figure 8As shown, the flash memory cell MC 200 includes a storage transistor MS110 and a gating transistor MG 120 connected in series. The gating transistor MG 120 can perform a gating operation on the storage transistor MS110. Figure 9 As shown, by controlling the voltage applied to the source region (i.e., the first electrode S) of the storage transistor MS110, the gate electrode 116 of the storage transistor MS110, the gate electrode 123 of the gate transistor MG 120, and the drain region (i.e., the second electrode D) of the gate transistor MG 120, the write operation of the storage transistor MS110 can be realized.

[0104] According to another embodiment of this disclosure, the write operation of the storage transistor MS110 can be performed by two steps executed in sequence, namely a first write step and a second write step.

[0105] According to another embodiment of this disclosure, when performing a write operation on the flash memory cell MC 200, the P-well 102 of the flash memory cell MC 200 can be grounded or a negative voltage lower than the ground voltage can be applied.

[0106] Specifically, according to another embodiment of this disclosure, such as Figure 7 As shown, a write operation is first performed on the storage transistor MS110 of the flash memory cell MC 200 through the first write step. At this time, a first write voltage VW1 is applied to the first electrode S, a second write voltage VW2 is applied to the second electrode D, a third write voltage VW3 is applied to the gate electrode 116 of the storage transistor MS110, and a fourth write voltage VW4 is applied to the gate electrode 123 of the gating transistor MG 120.

[0107] According to embodiments of this disclosure, the first write voltage VW1 can be higher than a preset voltage, wherein the preset voltage is preset based on the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the storage transistor MS110. For example, in Figure 4 In the flash memory cell MC 200 shown, a preset voltage allows electrons to overcome the electron barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, if the P-type channel region 111 comprises silicon and the first oxide layer 113 comprises silicon dioxide, the barrier height is 3.2 electron volts (eV). In this case, the first write voltage VW1 is typically greater than 3 volts (V). For example, the first write voltage VW1 can be in the range of 3V to 6V. For example, according to an embodiment of this disclosure, the first write voltage VW1 can be 4.4V. According to an embodiment of this disclosure, the first write voltage VW1 can be provided by an external constant voltage source.

[0108] According to embodiments of this disclosure, the second write voltage VW2 can be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS can be ground (GND). For example, according to embodiments of this disclosure, the second write voltage VW2 can be 0.2V. Furthermore, according to embodiments of this disclosure, the second write voltage VW2 can be connected to the second power supply voltage VSS via a constant current load.

[0109] According to embodiments of this disclosure, the third write voltage VW3 can be higher than the first write voltage VW1. According to embodiments of this disclosure, the third write voltage VW3 can be in the range of 4V to 10V. For example, according to embodiments of this disclosure, the third write voltage VW3 can be 5.4V.

[0110] According to embodiments of this disclosure, the fourth write voltage VW4 may be equal to or lower than the first power supply voltage VDD, wherein the first power supply voltage VDD is higher than the second power supply voltage VSS, and may be in the range of 0.8V to 5V. For example, according to embodiments of this disclosure, the fourth write voltage VW4 may be 1V.

[0111] According to embodiments of this disclosure, the first write voltage VW1 and the fourth write voltage VW4 may be higher than the second write voltage VW2.

[0112] Furthermore, according to embodiments of this disclosure, in the first write step of the flash memory cell MC 200, the first to fourth write voltages VW1 to VW4 turn on both the storage transistor MS110 and the gating transistor MG 120.

[0113] Subsequently, according to embodiments of this disclosure, such as ​ As shown, a write operation is then performed on the storage transistor MS110 of the flash memory cell MC200 through a second write step. At this time, the first write voltage VW1 applied to the first electrode S, the second write voltage VW2 applied to the second electrode D, and the fourth write voltage VW4 applied to the gate electrode 123 of the gate transistor MG 120 remain unchanged, and a sixth write voltage VW6 is applied to the gate electrode 116 of the storage transistor MS110. According to embodiments of this disclosure, the sixth write voltage VW6 can be greater than the third write voltage VW3. For example, as described above, the third write voltage VW3 can be 5.4V, and the sixth write voltage VW6 can be 6.2V.

[0114] Furthermore, according to embodiments of this disclosure, during the second write step of the flash memory cell MC 100, the first, second, sixth, and fourth write voltages VW1, VW2, VW6, and VW4 turn on the storage transistor MS110 and the gating transistor MG 120.

[0115] The write method according to another embodiment of the present disclosure is also based on the dual-channel hot electron write mechanism, and thus is not further described in detail here for the sake of brevity.

[0116] The write method of the flash memory cell according to the present disclosure adopts the write step of the dual-channel hot carrier injection mechanism, and can form a lower trap charge density in the storage medium layer of the storage transistor on the side close to the selection transistor and a higher trap charge density on the side away from the selection transistor, compared with the prior art write method. Therefore, the storage window can be increased, the influence of the trap charge mismatch effect (TCME) can be reduced, and thus the durability and retention reliability can be improved.

[0117] Although the present disclosure has been described with reference to the embodiments thereof, it is to be understood that various modifications and changes can be made thereto without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

Claims

1. A write method of a flash memory cell, the flash memory cell comprising: a substrate including a deep well region and a well region disposed on the deep well region; a memory transistor disposed on the well region and configured to store data; and a gate transistor disposed on the well region in a horizontal direction at a side of the memory transistor and configured to perform a gate operation on the memory transistor, wherein the memory transistor and the gate transistor are connected in series, wherein a source region of the memory transistor is connected to a first electrode of the flash memory cell and a drain region of the gate transistor is connected to a second electrode of the flash memory cell, the write method comprising: a first write step of performing a write operation on the memory transistor by applying a first write voltage to the first electrode, applying a second write voltage to the second electrode, applying a third write voltage to a gate electrode of the memory transistor, and applying a fourth write voltage to a gate electrode of the gate transistor; and a second write step of performing a write operation on the memory transistor by applying the first write voltage to the first electrode, applying the second write voltage to the second electrode, applying a sixth write voltage higher than the third write voltage to the gate electrode of the memory transistor, and applying the fourth write voltage to the gate electrode of the gate transistor, wherein the fourth write voltage is equal to or lower than a first power voltage, the second write voltage is equal to or higher than a second power voltage, the first write voltage is higher than a preset voltage, and the third write voltage is higher than the first write voltage, wherein the first power voltage is higher than the second power voltage, wherein the preset voltage is previously set according to a carrier barrier height at an interface between the substrate and a gate dielectric stack of the memory transistor, wherein the first write voltage and the fourth write voltage are higher than the second write voltage, and wherein the memory transistor and the gate transistor are both turned on during a write operation of the flash memory cell. 2.A write method of a flash memory cell, the flash memory cell comprising: a substrate including a deep well region and a well region disposed on the deep well region; a memory transistor including a first memory transistor disposed on the well region and configured to store first data, and a second memory transistor disposed on the well region and configured to store second data; and a gate transistor disposed on the well region in a horizontal direction between the first memory transistor and the second memory transistor and configured to isolate and perform a gate operation on the first memory transistor and the second memory transistor, wherein the first memory transistor, the gate transistor, and the second memory transistor are connected in series, wherein a source region of the first memory transistor is connected to a first electrode of the flash memory cell and a drain region of the second memory transistor is connected to a second electrode of the flash memory cell, the write method comprising: ​ a first write step, by applying a first write voltage to the first electrode or the second electrode, applying a second write voltage to the second electrode or the first electrode, applying a third write voltage to a gate electrode of the first storage transistor or the second storage transistor, applying a fourth write voltage to a gate electrode of the gate transistor, and applying a fifth write voltage to a gate electrode of the second storage transistor or the first storage transistor, performing a write operation on the first storage transistor or the second storage transistor; and a second write step, by applying the first write voltage to the first electrode or the second electrode, applying the second write voltage to the second electrode or the first electrode, applying a sixth write voltage higher than the third write voltage to a gate electrode of the first storage transistor or the second storage transistor, applying the fourth write voltage to a gate electrode of the gate transistor, and applying the fifth write voltage to a gate electrode of the second storage transistor or the first storage transistor, performing a write operation on the first storage transistor or the second storage transistor, wherein the fourth write voltage is equal to or lower than a first power supply voltage, the second write voltage is equal to or higher than a second power supply voltage, the first write voltage is higher than a preset voltage, and the third write voltage is higher than the first write voltage, wherein the first power supply voltage is higher than the second power supply voltage, wherein the preset voltage is preset according to a carrier barrier height at an interface between the substrate and a gate medium stack of the first storage transistor and the second storage transistor, wherein the first write voltage, the fourth write voltage, and the fifth write voltage are higher than the second write voltage, and wherein, during the write operation of the flash memory cell, the first storage transistor, the second storage transistor, and the gate transistor are all turned on.

3. The write method of claim 1, wherein the first power supply voltage is in a range of 0.8 V to 5 V, the second power supply voltage is a ground voltage, the first write voltage is in a range of 3 V to 6 V, the third write voltage is in a range of 4 V to 10 V, and the sixth write voltage is in a range of 5 V to 12 V.

4. The write method of claim 2, wherein the first power supply voltage is in a range of 0.8 V to 5 V, the second power supply voltage is a ground voltage, the first write voltage is in a range of 3 V to 6 V, the third write voltage is in a range of 4 V to 10 V, the fifth write voltage is in a range of 3 V to 8 V, and the sixth write voltage is in a range of 5 V to 12 V.

5. The write method of claim 1 or 2, wherein during the write operation of the flash memory cell, the second write voltage is connected to the second power supply voltage through a constant current load, and a current flowing between the first electrode and the second electrode of the flash memory cell is controlled by controlling a current of the constant current load.

6. The write method of claim 1 or 2, wherein During execution of the first and second write steps, a write operation is performed on the memory transistor by a channel hot electron injection mechanism.

7. The write method according to claim 1 or 2, wherein, During a write operation of the flash memory cell, the charge injected into the storage medium layer of the memory transistor has a lower charge concentration on a side closer to the pass transistor and a higher charge concentration on a side farther from the pass transistor in the horizontal direction.

8. The write method of claim 1 or 2, wherein, The memory transistor is a charge-trapping type memory transistor whose gate dielectric stack includes a tunnel oxide layer, a storage medium layer, and a blocking oxide layer.

9. The write method of claim 8, wherein, The storage medium layer includes one or more oxides, one or more nitrides, one or more oxynitrides, polysilicon, or nanocrystal material, or a combination thereof.

10. The write method of claim 8, wherein, The storage medium layer includes a high-K material rich in charge traps.

11. The write method of claim 8, wherein, The tunnel oxide layer has a thickness of 1 to 15 nm.

12. The write method according to claim 1 or 2, further comprising: applying a voltage equal to or lower than a second power supply voltage to the well region.

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