Low-delay low-power-consumption level conversion circuit based on charge pump

Abstract

The invention discloses a low-delay low-power-consumption level conversion circuit based on a charge pump, the circuit comprises a charge pump circuit, an internal conversion circuit and a latch circuit, the output end of the charge pump circuit is connected with the input end of the internal conversion circuit, and the output end of the internal conversion circuit is connected with the input end of the latch circuit. According to the invention, the voltage conversion range can be enlarged, and low time delay and low power consumption are realized. The low-delay low-power-consumption level conversion circuit based on the charge pump can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-delay and low-power level conversion circuit based on a charge pump. Background Art

[0002] Modern integrated circuit technology mostly adopts multi-voltage power supply design to reduce chip power consumption. Level shifters (LS) are needed to connect modules in different voltage domains. In addition, the process of modern CMOS integrated circuits is getting smaller and smaller, and the power supply voltage of the processor is as low as 1V. At the same time, the power supply of peripheral devices is still 3V or even 5V. Therefore, in order to communicate between circuits in different voltage domains, a level shifter with a wide voltage conversion range is necessary. At this stage, the level shifters are mainly traditional LS based on current mirror structure, traditional LS based on differential cascode structure, and LS based on Wilson current mirror. However, the traditional LS based on current mirror structure has very high power consumption, and the traditional LS based on differential cascode structure has competition problems. The LS based on Wilson current mirror still has the problem of transistor competition, and it is more difficult to flip the output signal, which increases the uncertainty of the output signal of the circuit. Summary of the invention

[0003] In order to solve the above technical problems, the purpose of the present invention is to provide a low-delay and low-power level conversion circuit based on a charge pump, which can increase the voltage conversion range and reduce the layout area.

[0004] The technical solution adopted by the present invention is: a low-delay and low-power level conversion circuit based on a charge pump, comprising a charge pump circuit, an internal conversion circuit and a latch circuit, wherein the output end of the charge pump circuit is connected to the input end of the internal conversion circuit, and the output end of the internal conversion circuit is connected to the input end of the latch circuit, wherein:

[0005] The charge pump circuit is used to obtain the input low-level signal and boost the input voltage to obtain a 2-fold input drive voltage for driving the internal conversion circuit;

[0006] The internal conversion circuit is used to pull down the two internal signals in turn at the rising edge and falling edge of the input signal according to the 2 times input drive voltage;

[0007] The latch circuit is used to flip the output end according to the internal signal after being pulled low, so as to obtain a stable high-level signal after conversion.

[0008] Furthermore, the charge pump circuit includes an inverter, a transmission gate, a charge pump, a third NMOS tube and a fourth NMOS tube, wherein the inverter and the transmission gate are both composed of low-threshold CMOS tubes, the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal, the inverter is powered by VDDL, the two complementary control ends C of the transmission gate are connected to VDDL, and C is reversely connected to VSS, the output end of the inverter and the output end of the transmission gate are respectively connected to the first input end and the second input end of the charge pump, the first output end of the charge pump is connected to the drain of the fourth NMOS tube, and the second output end of the charge pump is connected to the drain of the third NMOS tube. The source of the third NMOS tube is connected to the source of the fourth NMOS tube and connected to the internal conversion circuit, the gate of the third NMOS tube is connected to the first output control signal, and the gate of the fourth NMOS tube is connected to the second output control signal.

[0009] Further, the charge pump includes a first capacitor, a second capacitor, a first low threshold PMOS tube and a second low threshold PMOS tube, wherein the charge pump is composed of two sub-charge pumps, the first capacitor and the first low threshold PMOS tube constitute the first sub-charge pump, and the second capacitor and the second low threshold PMOS tube constitute the second sub-charge pump. The first capacitor is a capacitor formed by a first MOS tube, and the second capacitor is a capacitor formed by a second MOS tube, wherein the source of the first MOS tube is short-circuited with the drain of the first MOS tube as the lower plate of the first capacitor, which is also the first input end of the charge pump, and the gate of the first MOS tube is used as the upper plate of the first capacitor, as the first output end of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The source of the second MOS tube is short-circuited with the drain of the second MOS tube as the lower plate of the second capacitor, which is also the second input end of the charge pump, and the gate of the second MOS tube is used as the upper plate of the second capacitor, as the second output end of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The gate of the first low threshold PMOS tube is connected to the first output end of the charge pump, which is also the output of the transmission gate. The gate of the second low threshold PMOS tube is connected to the second output end of the charge pump, which is also the output of the inverter. The source of the first low threshold PMOS tube and the source of the second low threshold PMOS tube are connected to VDDL for power supply.

[0010] Furthermore, the first low-threshold PMOS tube and the second low-threshold PMOS tube are both low-threshold transistors, the third NMOS tube and the fourth NMOS tube are both high-threshold transistors, and the first MOS tube and the second MOS tube are both Native NMOS transistors.

[0011] Further, the internal conversion circuit includes a first high threshold PMOS tube, a second high threshold PMOS tube, a first low threshold NMOS tube, a second low threshold NMOS tube, a first high threshold NMOS tube and a second high threshold NMOS tube, wherein the source of the first high threshold PMOS tube is connected to the source of the second high threshold PMOS tube and connected to the VDDH power supply signal, the gate of the first high threshold PMOS tube, the drain of the first high threshold PMOS tube and the drain of the first high threshold NMOS tube are connected to the second input end of the latch circuit, the gate of the second high threshold PMOS tube, the drain of the second high threshold PMOS tube are connected to the drain of the first high threshold NMOS tube and connected to the second input end of the latch circuit, and the gate of the second high threshold PMOS tube, the drain of the second high threshold PMOS tube The gate of the first high threshold NMOS tube is connected to the drain of the second high threshold NMOS tube and is connected to the first input end of the latch circuit, the gate of the first high threshold NMOS tube is connected to the gate of the second high threshold NMOS tube and is connected to the charge pump circuit, the source of the first high threshold NMOS tube is connected to the drain of the first low threshold NMOS tube, the source of the second high threshold NMOS tube is connected to the drain of the second low threshold NMOS tube, the source of the first low threshold NMOS tube is connected to the source of the second low threshold NMOS tube and is grounded, the gate of the first low threshold NMOS tube is connected to the output signal of the transmission gate, and the gate of the second low threshold NMOS tube is connected to the output signal of the inverter.

[0012] Furthermore, the first high threshold PMOS tube, the second high threshold PMOS tube, the first high threshold NMOS tube and the second high threshold NMOS tube are all high threshold transistors, and the first low threshold NMOS tube and the second low threshold NMOS tube are all low threshold transistors.

[0013] Further, the latch circuit includes a first NAND gate and a second NAND gate, the first input terminal of the first NAND gate is connected to the internal conversion circuit, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate and outputs a second output control signal, the second input terminal of the second NAND gate is connected to the internal conversion circuit, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate and outputs a first output control signal.

[0014] The beneficial effect of the circuit of the present invention is that the charge pump circuit is used to obtain the input low-level signal and perform a voltage-boosting process on the input voltage to obtain a 2-fold input drive voltage for driving the internal conversion circuit. Then the internal conversion circuit pulls down the two internal signals in turn at the rising edge and the falling edge of the input signal according to the 2-fold input drive voltage. The latch circuit flips the output end according to the internal signal after being pulled down to obtain a stable high-level signal after conversion. Among them, the charge pump circuit can increase the voltage conversion range, and the capacitor adopts a MOS capacitor, which can reduce the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a circuit schematic diagram of a low-delay and low-power level conversion circuit based on a charge pump of the present invention;

[0016] Figure 2 is a schematic diagram of a multi-voltage system provided by a specific embodiment of the present invention;

[0017] Figure 3 It is a structural schematic diagram of an existing current mirror-based level conversion circuit provided by a specific embodiment of the present invention;

[0018] Figure 4 It is a structural schematic diagram of an existing differential cascode-based level conversion circuit provided by a specific embodiment of the present invention;

[0019] Figure 5 It is a structural schematic diagram of an existing level conversion circuit based on Wilson current mirror provided by a specific embodiment of the present invention;

[0020] Figure 6 It is a curve diagram of the capacitance-voltage characteristic of an NMOS transistor when W / L=6u / 1.8 provided by a specific embodiment of the present invention;

[0021] Figure 7 It is a schematic diagram of a capacitance-voltage characteristic curve of a Native NMOS transistor when W / L=6u / 1.8u provided by a specific embodiment of the present invention;

[0022] Figure 8 It is a schematic diagram of voltage waveforms of various nodes when the circuit provided by a specific embodiment of the present invention is working;

[0023] Fig. 9 It is a schematic diagram of the pre-simulation results of LS delay and power consumption based on a charge pump under multiple temperatures and multiple processes provided by a specific embodiment of the present invention;

[0024] Fig.10 It is a schematic diagram of the post-simulation results based on the charge pump LS delay and power consumption under multiple temperatures and multiple processes provided by a specific embodiment of the present invention;

[0025] Fig.11 It is a schematic diagram of delay under different VDDL when VDDH is equal to 3V provided by a specific embodiment of the present invention. DETAILED DESCRIPTION

[0026] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0027] First of all, it should be noted that nowadays more and more electronic devices use multi-voltage systems to reduce system power consumption, such as Figure 2It is a multi-voltage system that connects modules in different voltage domains by a level converter. The communication between modules in different voltage domains requires the use of a level converter. Modern CMOS integrated circuit process is getting smaller and smaller, and the power supply voltage of the processor is as low as 1V. At the same time, the power supply of peripheral devices is still 3V or even 5V, so a level converter with a wide voltage conversion range is necessary.

[0028] In the prior art, such as Figure 3 As shown in the figure, it is a traditional LS based on the current mirror structure. When VIN is high, both the upper and lower tubes NM1 and PM1 are turned on, resulting in very large power consumption of the LS structure. Figure 4 As shown in the figure, it is a traditional LS based on a differential common source and common gate structure. Due to the differential structure, the power consumption of the LS of this structure is not as large as that of the LS based on the current mirror. However, when VIN changes from low to high, due to the delay of the inverter, VINB has not yet changed to low, and Q2 is still low. At this time, the pull-up tube PM1 and the pull-down tube NM1 begin to compete, and it takes a longer time to charge the capacitor at the Q1 node, resulting in a longer delay. If the input voltage is relatively low, the driving ability of NM1 is weaker than that of PM1, and it may not even be able to correctly pull down the voltage of the Q1 node; as shown in the figure, it is not suitable for the traditional LS based on the differential common source and common gate structure. Figure 5 As shown, it is based on the Wilson current mirror. The addition of PM3 tube also makes the static current of this structure relatively small and the power consumption is not large. When VIN changes from high to low, NM1 is closed and NM2 is opened, trying to pull the Q2 node low. At the same time, PM3 is turned on, and the previous state of Q1 is low, so there will be a small transient current I1 to charge the Q1 node. This current is mirrored as I2, trying to pull the Q2 node high. It can be seen that there is still a competition problem between the pull-up transistor PM2 and the pull-down transistor NM2.

[0029] Based on this, in order to solve the problem of relatively large delay or high power consumption of the traditional LS structure, the present invention proposes a level conversion circuit based on a MOS charge pump. The proposed LS has the characteristics of low delay and low power consumption, and the structure can achieve a wider voltage conversion range.

[0030] Reference Figure 1 The present invention provides a low-delay and low-power level conversion circuit based on a charge pump, comprising a charge pump circuit, an internal conversion circuit and a latch circuit, wherein the output end of the charge pump circuit is connected to the input end of the internal conversion circuit, and the output end of the internal conversion circuit is connected to the input end of the latch circuit, wherein:

[0031] The charge pump circuit is used to obtain the input voltage and boost the input voltage to obtain a 2-fold input drive voltage for driving the internal conversion circuit;

[0032] Specifically, the charge pump circuit includes an inverter INV, a transmission gate TG, a charge pump, a third NMOS tube NM3 and a fourth NMOS tube NM4, wherein the inverter and the transmission gate are both composed of low-threshold CMOS tubes, the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal VIN, the inverter is powered by VDDL, the two complementary control ends C of the transmission gate are connected to VDDL, and C is reversely connected to VSS, that is, the gate of the PMOS inside the transmission gate is connected to VDDL, and the gate of the NMOS inside the transmission gate is connected to VSS, so that the transmission gate is always turned on. The input signal VIN passes through the transmission gate and the inverter to generate two-phase clock signals VINN and VINB with opposite phases and close delays. The output end VINB of the inverter and the output end VINN of the transmission gate are respectively connected to the first input end and the second input end of the charge pump, the first output end VM of the charge pump is connected to the drain of the fourth NMOS tube NM4, and the second output end VN of the charge pump is connected to the drain of the third NMOS tube NM3. The source of the third NMOS tube and the source of the fourth NMOS tube are connected to VC and connected to the internal conversion circuit, the gate of the third NMOS tube is connected to the first output control signal OUT, and the gate of the fourth NMOS tube is connected to the second output control signal OUT_B. When NM3 or NM4 is turned on, the VC voltage is approximately equal to the voltage of VM or VN.

[0033] Further, it should be noted that the charge pump includes a first capacitor C1, a second capacitor C2, a first low threshold PMOS tube P1 and a second low threshold PMOS tube P2, wherein the charge pump is composed of two sub-charge pumps, the first capacitor C1 and the first low threshold PMOS tube P1 constitute a first sub-charge pump, and the second capacitor C2 and the second low threshold PMOS tube C2 constitute a second sub-charge pump. The first capacitor is a capacitor formed by a first MOS tube NNT1, and the second capacitor is a capacitor formed by a second MOS tube NNT2, wherein the source of the first MOS tube is short-circuited with the drain of the first MOS tube as the lower plate of the first capacitor, and is also connected to the first input terminal VINN of the charge pump, and the gate of the first MOS tube is used as the upper plate of the first capacitor, as the first output terminal VM of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The source of the second MOS tube is short-circuited with the drain of the second MOS tube as the lower plate of the second capacitor, and is also the second input terminal of the charge pump connected to VINB. The gate of the second MOS tube is used as the upper plate of the second capacitor, as the second output terminal VN of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The gate of the first low threshold PMOS tube is connected to the first output terminal of the charge pump, which is also the output VINN of the transmission gate. The gate of the second low threshold PMOS tube is connected to the second output terminal of the charge pump, which is also the output VINB of the inverter. The source of the first low threshold PMOS tube and the source of the second low threshold PMOS tube are connected to VDDL for power supply.

[0034] The first low-threshold PMOS tube and the second low-threshold PMOS tube are both low-threshold transistors, the third NMOS tube and the fourth NMOS tube are both high-threshold transistors, and the first MOS tube and the second MOS tube are both Native NMOS transistors.

[0035] Further, the charge pump in the embodiment of the present invention is described. The circuit does not require high accuracy of the capacitors C1 and C2 in the charge pump. In order to save circuit layout, the capacitors C1 and C2 in the charge pump are capacitors composed of MOS tubes. The source and drain of the Native NMOS tube are short-circuited as the lower plate of the capacitor, and the gate is used as the upper plate of the capacitor. Its capacitor-voltage characteristics are as follows: Figure 6 Only V is used here. GS When V GS In V TH When the capacitance is close to GS When it is relatively large, the capacitance value is relatively stable, and the capacitance per unit area is approximately C ox . V GS In V TH The capacitance value is relatively low near the depletion layer because the equivalent capacitance C dep and C ox In order to make the capacitance characteristics of the capacitor formed by the MOS tube more stable, a Native MOS tube can be used. The Native tube changes the ion doping concentration of the channel and the threshold voltage is close to 0. Figure 7 is a capacitance-voltage characteristic curve of a Native NMOS tube with W / L=6u / 1.8u adopted in the embodiment of the present invention. At this time, the threshold voltage is -122mV. It can be found that V GS The capacitance value of the segment greater than 0 does not change much, which is much better than the characteristic curve of ordinary NMOS capacitors. If the same function is achieved, a 15u×15u mim capacitor is needed, which greatly saves the layout area. In addition, the channel doping of the native tube is obtained through logical operations using different masks, which requires one more process in the process, but no new mask is needed. Similarly, we can use PMOS Cap to achieve similar functions, but we need to use a larger MOS and a larger layout area.

[0036] The internal conversion circuit is used to pull down the two internal signals in turn at the rising edge and falling edge of the input signal according to the 2 times input drive voltage;

[0037] Specifically, the internal conversion circuit includes a first high threshold PMOS tube PM1, a second high threshold PMOS tube PM2, a first low threshold NMOS tube N1, a second low threshold NMOS tube N2, a first high threshold NMOS tube NM1 and a second high threshold NMOS tube NM2, wherein the source of the first high threshold PMOS tube is connected to the source of the second high threshold PMOS tube and connected to VDDH for power supply, the gate of the first high threshold PMOS tube is connected to the drain of the first high threshold PMOS tube to form a diode structure, and is connected to the drain of the first high threshold NMOS tube, and then connected to the first input terminal VP of the latch circuit, and the gate of the second high threshold PMOS tube is connected to the source of the second high threshold PMOS tube. The drain of the first high threshold NMOS tube is connected to form a diode structure, and is connected to the drain of the second high threshold NMOS tube, and then connected in parallel to the second input terminal VQ of the latch circuit, the gate of the first high threshold NMOS tube is connected to the gate of the second high threshold NMOS tube and connected to the charge pump circuit, the source of the first high threshold NMOS tube is connected to the drain of the first low threshold NMOS tube, the source of the second high threshold NMOS tube is connected to the drain of the second low threshold NMOS tube, the source of the first low threshold NMOS tube is connected to the source of the second low threshold NMOS tube and grounded, the gate of the first low threshold NMOS tube is connected to the output signal VINN of the transmission gate, and the gate of the second low threshold NMOS tube is connected to the output signal VINB of the inverter.

[0038] Among them, the first high threshold PMOS tube, the second high threshold PMOS tube, the first high threshold NMOS tube and the second high threshold NMOS tube are all high threshold transistors, and the first low threshold NMOS tube and the second low threshold NMOS tube are all low threshold transistors.

[0039] The latch circuit is used to flip the output end according to the internal signal after being pulled low, so as to obtain a stable high-level signal after conversion.

[0040] Specifically, the latch circuit includes a first NAND gate NAND1 and a second NAND gate NAND2, forming an SR latch. The first input end of the first NAND gate is connected to the internal conversion circuit VP, the second input end of the first NAND gate is connected to the output end OUT of the second NAND gate and outputs the second output control signal OUT_B, the second input end of the second NAND gate is connected to the internal conversion circuit VQ, the first input end of the second NAND gate is connected to the output end OUT_B of the first NAND gate and outputs the first output control signal OUT. OUT and OUT_B also control NM3 and NM4 to form a feedback loop.

[0041] Finally, the working principle of the level conversion circuit in the embodiment of the present invention is explained. The working process of the level conversion circuit can be divided into two working states: transient and steady state. In the transient state, the input VIN of the circuit has changed state but the output OUT level has not yet flipped. In the steady state, the VIN and OUT states of the circuit are the same, both high or low. Corresponding to the rising and falling edges of the clock, the circuit can be divided into four working processes, which can be divided into low-level steady state, low-to-high transient state, high-level steady state, and high-to-low transient state according to the state of the input clock. The specific working process of the circuit in the four states will be introduced below, and the corresponding waveform diagrams are shown as follows. Figure 8 As shown, it can be found that the main delay of the circuit is mainly determined by the delay of the inverter and the gm of the conversion stage, so further increasing the size of the inverter and the conversion stage MOS tube can further reduce the delay, but it will increase power consumption. Thanks to the existence of the feedback loop, the two switch tubes NM3 and NM4 control the state flip of the circuit in the short time between the input and output level flips. Most of the tubes in the circuit are in the off state during the rest of the time, thus achieving lower power consumption.

[0042] The embodiment of the present invention adopts a 0.18 μm standard CMOS process, and the input signal VIN is a square wave with a frequency of 1 MHz, a duty cycle of 50%, a high level of VDDL and a low level of VSS, VDDL is 0.6 V, and VDDH is 3 V. Figure 8 (a) states 1, 2, 3 and 4 are explained as follows:

[0043] 1) State 1: Steady state with VIN at low level. VIN is low level, VINN is also low level, VINB is high level, at this time, P1 tube is turned on, P2 tube is turned off, VM is charged to VDDL, and output OUT is also low.

[0044] 2) State 2: VIN transient from low to high. When VIN changes from low level to high level, OUT has not yet flipped and is still at low level, and OUT_B is at high level. P2 tube turns on and VN charges to VDDL. P1 tube turns off, and the lower plate VINN of the capacitor formed by the NNT1 MOS tube changes from low level to high level VDDL, and the previous state level of the upper plate VM is VDDL. Since the voltage across the capacitor does not suddenly change, VM jumps to about 2VDDL, and OUT_B is high and NM4 tube turns on, so VC is approximately equal to VM, which is about 2VDDL. For NM1 and NM2, when N1 and N2 are turned on, considering the body effect, the threshold voltage of NM1 and NM2 is about 1V, and the maximum value of VC is 2VDDL, which is about 1.1V, which can turn on the high threshold tube NM1 or NM2 in the internal conversion stage. At this time, N1 is turned on, NM1 is turned on, VP is pulled down while VQ is still high, the output of the latch is reversed, so OUT changes from low to high, and OUT_B changes from high to low. In turn, NM4 is turned off and NM3 is turned on, so VC becomes VN, and VN is charged to VDDL, which cannot turn on NM1, and the VP voltage gradually rises to 2.5V.

[0045] 3) State 3 (steady state with VIN at high level), State 4 (transient state from high to low): The rising edge and falling edge of the clock correspond to two relatively independent circuits, that is, State 2 is the process in which the rising edge of VIN makes VM double the voltage to 2VDDL and turns on the high threshold transistor NM1 corresponding to the internal conversion stage, and State 4 is the process in which the rising edge of VIB makes VN double the voltage to 2VDDL and turns on the high threshold transistor NM2 corresponding to the internal conversion stage. Therefore, the working process of State 3 and State 4 is similar to the working process of State 1 and State 2.

[0046] Figure 8 In (b), td1 is the delay of the first-stage charge pump circuit, which mainly comes from the inverter and the transmission gate, td2 is the delay of the second-stage internal conversion circuit, and td3 is the delay of the latch. The overall delay of the level converter is tdrising / tdfalling = td1 + td2 + td3. The circuit is composed of two relatively independent branches, and there is no competition relationship. Therefore, the level conversion circuit of the embodiment of the present invention has a lower delay than the level converter of the conventional structure in the prior art.

[0047] In summary, the level conversion circuit of the embodiment of the present invention adopts 0.18μm standard CMOS process, and further adopts the traditional LS structure and the structure proposed by the present invention for comparative design. Fig. 9As shown, under the conditions of 25 degree tt process angle, the simulation results show that the delay of the traditional LS based on the current mirror structure is 1.43ns and the power consumption is 63.52μW; the delay of the traditional LS based on the differential cascode structure is 5.71ns and the power consumption is 6.57μW; while the delay of the LS proposed in the present invention is as low as 1.2ns, and the power consumption is only 0.85μW. It can be seen that the LS structure proposed in the present invention has lower power consumption than the current mirror structure, and smaller delay than the differential cascode structure, and has the advantages of delay and power consumption.

[0048] Then, a simulation experiment is conducted on the embodiment of the present invention. The input clock signal VIN is a square wave signal with a frequency of 1MHz, a high potential of VDDL, a low potential of VSS, a rise time and a fall time of 1ns, and a duty cycle of 50%. VDDL is 0.6V, and VDDH is 3V. Based on the 180nm standard CMOS process, power consumption and delay are two very important indicators of the level converter, and the following simulation will focus on these two indicators.

[0049] The simulation results of LS delay and power consumption based on MOS charge pump proposed by the present invention under multiple temperature and multiple process angles are as follows: Fig. 9 As shown, the latter Fig.10 As shown in the figure, except for the extremely bad cases, the delay of the pre-simulation is mostly between 1-2ns, and the delay of the post-simulation is between 2-4ns. It can be seen that the delay is less affected by temperature. Only under the ss process corner, the threshold voltage of the MOS tube increases, causing the circuit to work slower and the delay to increase. The power consumption of the pre-simulation and post-simulation is less than 2μW in most cases, and the power consumption will increase at high temperature.

[0050] On the other hand, due to the threshold voltage (V LVT,NMOS About 600mV) and the threshold voltage of the high threshold MOS tube (V HVT,NMOS The minimum low voltage domain VDDL that can be converted is 0.6V. The delay measured under different VDDL is as follows: Fig.11 As shown. It can be found that the higher the VDDL, the faster the LS conversion speed, and when VDDL is equal to 0.7V, the delay in all cases is reduced to about 1ns, and the rise time and fall time of the input signal VIN set for our test are both 1ns, which means that there is almost no delay between the input and output signals, but the larger the VDDL, the greater the corresponding power consumption. When VDDL is 0.7V, the power consumption is 3.3μW at room temperature tt process corner.

[0051] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A low-delay and low-power level conversion circuit based on a charge pump, characterized in that: It includes a charge pump circuit, an internal conversion circuit and a latch circuit, wherein the output end of the charge pump circuit is connected to the input end of the internal conversion circuit, and the output end of the internal conversion circuit is connected to the input end of the latch circuit, wherein: The charge pump circuit is used to obtain the input low-level signal and boost the input voltage to obtain a 2-fold input drive voltage for driving the internal conversion circuit; The internal conversion circuit is used to pull down the two internal signals at the rising edge and falling edge of the input signal respectively according to the 2 times input driving voltage; The latch circuit is used to flip the output end according to the internal signal after being pulled down, and obtain a stable high-level signal after conversion.

2. A low-delay and low-power level conversion circuit based on a charge pump according to claim 1, characterized in that: The charge pump circuit includes an inverter, a transmission gate, a charge pump, a third NMOS tube and a fourth NMOS tube, wherein the inverter and the transmission gate are both composed of low-threshold CMOS tubes, the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal, the inverter is powered by VDDL, the two complementary control ends of the transmission gate are respectively connected to VDDL and VSS, so that the transmission gate is always turned on, the output end of the inverter and the output end of the transmission gate are respectively connected to the first input end and the second input end of the charge pump, the first output end of the charge pump is connected to the drain of the fourth NMOS tube, and the second output end of the charge pump is connected to the drain of the third NMOS tube. The source of the third NMOS tube is connected to the source of the fourth NMOS tube and connected to the internal conversion circuit, the gate of the third NMOS tube is connected to the first output control signal, and the gate of the fourth NMOS tube is connected to the second output control signal.

3. A low-delay and low-power level conversion circuit based on a charge pump according to claim 2, characterized in that: The charge pump comprises a first capacitor, a second capacitor, a first low threshold PMOS tube and a second low threshold PMOS tube, wherein the charge pump is composed of two sub-charge pumps, the first capacitor and the first low threshold PMOS tube constitute the first sub-charge pump, and the second capacitor and the second low threshold PMOS tube constitute the second sub-charge pump. The first capacitor is a capacitor formed by the first MOS tube, and the second capacitor is a capacitor formed by the second MOS tube, wherein the source of the first MOS tube is short-circuited with the drain of the first MOS tube as the lower plate of the first capacitor, and also the first input end of the charge pump, the gate of the first MOS tube is the upper plate of the first capacitor, as the first output end of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The source of the second MOS tube is short-circuited with the drain of the second MOS tube as the lower plate of the second capacitor, and also the second input end of the charge pump, the gate of the second MOS tube is the upper plate of the second capacitor, as the second output end of the charge pump, and is connected to the drain of the first low threshold PMOS tube. The gate of the first low threshold PMOS tube is connected to the first input terminal of the charge pump, which is also the output of the transmission gate. The gate of the second low threshold PMOS tube is connected to the second input terminal of the charge pump, which is also the output of the inverter. The source of the first low threshold PMOS tube and the source of the second low threshold PMOS tube are connected to VDDL for power supply.

4. A low-delay and low-power level conversion circuit based on a charge pump according to claim 2, characterized in that: The first low-threshold PMOS tube and the second low-threshold PMOS tube are both low-threshold transistors, the third NMOS tube and the fourth NMOS tube are both high-threshold transistors, and the first MOS tube and the second MOS tube are both Native NMOS transistors.

5. The low-delay and low-power level conversion circuit based on a charge pump according to claim 1, characterized in that: The internal conversion circuit includes a first high threshold PMOS tube, a second high threshold PMOS tube, a first low threshold NMOS tube, a second low threshold NMOS tube, a first high threshold NMOS tube and a second high threshold NMOS tube, wherein the source of the first high threshold PMOS tube is connected to the source of the second high threshold PMOS tube and connected to VDDH power supply; the gate of the first high threshold PMOS tube, the drain of the first high threshold PMOS tube and the drain of the first high threshold NMOS tube are connected and connected to the second input end of the latch circuit; the gate of the second high threshold PMOS tube, the drain of the second high threshold PMOS tube and the second high threshold NMOS tube are connected The drain of the threshold NMOS tube is connected and connected to the first input end of the latch circuit, the gate of the first high threshold NMOS tube is connected to the gate of the second high threshold NMOS tube and connected to the charge pump circuit, the source of the first high threshold NMOS tube is connected to the drain of the first low threshold NMOS tube, the source of the second high threshold NMOS tube is connected to the drain of the second low threshold NMOS tube, the source of the first low threshold NMOS tube is connected to the source of the second low threshold NMOS tube and connected to ground VSS, the gate of the first low threshold NMOS tube is connected to the output signal of the transmission gate, and the gate of the second low threshold NMOS tube is connected to the output signal of the inverter.

6. A low-delay and low-power level conversion circuit based on a charge pump according to claim 5, characterized in that: The first high threshold PMOS tube, the second high threshold PMOS tube, the first high threshold NMOS tube and the second high threshold NMOS tube are all high threshold transistors, and the first low threshold NMOS tube and the second low threshold NMOS tube are all low threshold transistors.

7. The low-delay and low-power level conversion circuit based on a charge pump according to claim 1, characterized in that: The latch circuit includes a first NAND gate and a second NAND gate, the first input end of the first NAND gate is connected to the internal conversion circuit, the second input end of the first NAND gate is connected to the output end of the second NAND gate and outputs a second output control signal, the second input end of the second NAND gate is connected to the internal conversion circuit, the first input end of the second NAND gate is connected to the output end of the first NAND gate and outputs a first output control signal.

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