Anti-interference straight-through switching circuit of satellite transceiver

Abstract

The invention discloses an anti-interference straight-through switching circuit of a satellite transceiver. The anti-interference straight-through switching circuit comprises a first comparator, a second comparator, a B3 straight-through circuit, a B3 anti-interference circuit, an S straight-through circuit and an S anti-interference circuit, an external mode control signal is input into the input end of the first comparator and the input end of the second comparator, and the output end of the first comparator is connected with the input end of the first B3 change-over switch and the input end of the second S change-over switch. The output end of the second comparator is connected with the input ends of the second B3 change-over switch and the first S change-over switch; the first comparator and the second comparator output opposite output signals; the structure of the B3 frequency point signal processing circuit and the S frequency point signal processing circuit on the circuit board is a central symmetry structure. According to the invention, switching of the direct-through circuit and the anti-interference circuit of the B3 frequency point and the S frequency point can be controlled through the two comparator circuits, the number of components required by a control part is greatly reduced, and the size, the weight and the structural complexity of equipment are effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of isolation circuit technology, and in particular to an anti-interference pass-through switching circuit for a satellite transceiver. Background Technology

[0002] With the rapid development of satellite communication technology, its applications have spread to numerous fields such as broadcasting, global positioning, broadband internet access, the Internet of Things, and military communications. Modern satellite communication systems widely adopt multi-band, multi-beam operating modes to improve spectrum utilization and system capacity. Therefore, as a core component of satellite ground stations or user terminals, satellite transceivers need to be able to support multiple radio frequency bands, such as the common L-band (e.g., 1.2 GHz) and S-band (e.g., 2.5 GHz), to achieve interconnection with satellites in different orbits and for different purposes.

[0003] During signal reception, the transceiver's environment is often filled with various intentional or unintentional electromagnetic interferences. These interferences severely degrade the signal-to-noise ratio of the useful signal, leading to communication link interruptions, reduced data transmission rates, or even complete failure. To address this issue, the industry commonly incorporates anti-interference technology into the RF front-end circuitry. However, anti-interference technology can cause phase instability in the receiving antenna, preventing directional reception from achieving its intended function. To ensure directional functionality under interference-free conditions, anti-interference pass-through can be used for RF switching. Furthermore, some equipment requires low power consumption during operation, necessitating the disabling of anti-interference functions to reduce power consumption; therefore, anti-interference pass-through for RF switching is also required. When a high level of environmental interference is detected, the system automatically switches to "anti-interference mode," allowing the received radio frequency signal to be processed by specially designed anti-interference circuits (such as adaptive null antenna arrays, digital beamforming (DBF), frequency hopping or spread spectrum receivers, etc.) to suppress interference and extract clean, useful signals. Conversely, when environmental interference is low, the system switches to "pass-through mode," allowing the signal to bypass the complex anti-interference circuits and pass directly through low-loss preamplifier and frequency converter circuits, reducing anti-interference processing power consumption and providing a stable receiving phase center to complete the directional function.

[0004] For systems that need to support two or more independent radio frequency bands (such as 1.2 GHz and 2.5 GHz) simultaneously, traditional implementations typically equip each band with a separate complete signal processing link. This means that for the 1.2 GHz band and the 2.5 GHz band, the device internally has a separate "interference-resistant mode circuit" and a separate "pass-through mode circuit," respectively. These two circuits are physically separate and managed by their respective independent control circuits. Because each band requires its own independent control circuit, multiple control circuits mean more circuit boards, connectors, power management modules, and physical space, resulting in a larger transceiver size, weight, and power consumption, making the entire system more complex and increasing manufacturing costs. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides an anti-interference direct-switch circuit for a satellite transceiver. The technical problem to be solved by this invention is achieved through the following technical solution: The first aspect of this invention provides an anti-interference direct-through switching circuit for a satellite transceiver, comprising: a first comparator, a second comparator, a B3 frequency signal processing circuit, and an S frequency signal processing circuit; The B3 frequency signal processing circuit includes: a B3 through circuit and a B3 anti-interference circuit; The S-frequency signal processing circuit includes: an S-pass circuit and an S-anti-interference circuit; One end of the B3 anti-interference circuit is connected to the first B3 switch of the B3 direct circuit, and the other end is connected to the second B3 switch of the B3 direct circuit; one end of the S anti-interference circuit is connected to the first S switch of the S direct circuit, and the other end is connected to the second S switch of the S direct circuit. An external mode control signal is input to the input terminals of the first comparator and the second comparator. The output terminal of the first comparator is connected to the input terminal of the first B3 switch and the input terminal of the second S switch. The output of the second comparator is connected to the input of the second B3 switch and the input of the first S switch; The output signal of the first comparator is opposite to that of the second comparator, so as to control the switching of the B3 pass-through circuit and the B3 anti-interference circuit, as well as the switching of the S pass-through circuit and the S anti-interference circuit. The second switching switch of the B3 through circuit is also connected to the first power divider, the first power divider is connected to the first duplexer, the first duplexer is connected to the second duplexer, the second duplexer is connected to the second switching switch of the S through circuit, the second duplexer is also connected to the second power divider, and the second power divider is connected to the two main MCX terminals. The B3 frequency signal processing circuit and the S frequency signal processing circuit have a centrally symmetrical structure on the circuit board.

[0006] In one embodiment of the present invention, the external mode control signal is input to the input of the first comparator and the input of the second comparator through one of the total MCX terminals and the first feedthrough capacitor.

[0007] In one embodiment of the present invention, the B3 through circuit includes: a B3 antenna MCX terminal, a first B3 switch, a first B3 amplifier, a first B3 filter, a second B3 amplifier, a second B3 filter, and a second B3 switch connected in sequence.

[0008] In one embodiment of the present invention, the S-pass circuit includes: an S-antenna MCX terminal, a first S-switch, a first S-amplifier, a first S-filter, a second S-amplifier, a second S-filter, and a second S-switch connected in sequence.

[0009] In one embodiment of the present invention, a B2b frequency signal processing circuit and a B1 frequency signal processing circuit are also included; The B2b frequency signal processing circuit is connected to the first power divider; The B1 frequency signal processing circuit is connected to the first duplexer.

[0010] In one embodiment of the present invention, the B2b frequency signal processing circuit includes: a B2b antenna MCX terminal, a B2b amplifier, and a B2b filter connected in sequence. The B2b filter is connected to the first power divider; The B1 frequency signal processing circuit includes: the B1 antenna MCX terminal and the B1 filter connected in sequence; The B1 filter is connected to the first duplexer.

[0011] In one embodiment of the invention, a main power supply is also included: The main power supply is divided into a first power supply, a second power supply, and a third power supply in parallel after passing through another main MCX terminal and a second feedthrough capacitor; The first power supply is input to the B3 antenna MCX terminal, the B2b antenna MCX terminal, and the B1 antenna MCX terminal through the first load switch; the power consumption control signal controls the opening and closing of the first load switch; The second power supply is input to the S antenna MCX terminal via the second load switch; The third power supply is divided into a first step-down power supply and a second step-down power supply connected in parallel after passing through the step-down module. The power consumption control signal controls the first voltage regulator module, and the first step-down power supply is input to the first B3 amplifier, the second B3 amplifier and the B2b amplifier through the first voltage regulator module; The second step-down power supply is input to the first comparator, the second comparator, the first B3 switch, the second B3 switch, the first S switch, the first S amplifier, the second S amplifier, and the second S switch through the second voltage regulator module.

[0012] In one embodiment of the present invention, the first B3 switch, the second B3 switch, the first S switch, and the second S switch are all radio frequency switches; The circuit structures of the first B3 switch and the second B3 switch are mirror-symmetric structures.

[0013] In one embodiment of the present invention, the first B3 switching switch includes: a first radio frequency switching chip; The third pin of the first RF switch chip is connected to one end of capacitor C9, the other end of capacitor C9 is connected to one end of inductor L10 and the MCX terminal of antenna B3, the other end of inductor L10 is connected to one end of capacitor C20 and connected to the power supply output of the first load switch, and the other end of capacitor C20 is grounded. The twelfth pin of the first RF switch chip is connected to one end of inductor L3 and one end of capacitor C24. The other end of inductor L3 is connected to one end of capacitor C22. The other ends of capacitor C24 and capacitor C22 are connected to the other end of capacitor C21. One end of capacitor C21 is connected to the output terminal of the second voltage regulator module. The second, fourth, fifth, seventh, fourteenth, sixteenth, seventeenth, first, eighth, ninth, and thirteenth pins of the first RF switch chip are grounded; The eleventh pin of the first RF switch chip is connected to one end of capacitor C28 and one end of resistor R7. The other end of capacitor C28 is grounded, and the other end of resistor R7 is connected to the output of the first comparator. The tenth pin of the first RF switch chip is connected to one end of capacitor C29 and one end of resistor R5. The other end of capacitor C29 is grounded, and the other end of resistor R5 is connected to the output terminal of the second voltage regulator module. The fifteenth pin of the first RF switch chip is connected to one end of capacitor C19, the other end of capacitor C19 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the first B3 amplifier. The sixth pin of the first RF switch chip is connected to one end of capacitor C5, and the other end of capacitor C5 is connected to one end of the B3 anti-interference circuit.

[0014] In one embodiment of the present invention, the second B3 switching switch includes: a second radio frequency switching chip; The sixth pin of the second RF switch chip is connected to one end of capacitor C23, and the other end of capacitor C23 is connected to the second B3 filter; The fifteenth pin of the second RF switch chip is connected to one end of capacitor C11, the other end of capacitor C11 is connected to one end of capacitor C105, and the other end of capacitor C105 is connected to the other end of the B3 anti-interference circuit. The tenth pin of the second RF switch chip is connected to one end of capacitor C30, one end of capacitor C30 is connected to one end of resistor R6, the other end of resistor R6 is connected to the output terminal of the second voltage regulator module, and the other end of capacitor C30 is grounded. One end of the eleventh pin of the second RF switch chip is connected to one end of capacitor C31, one end of capacitor C31 is connected to one end of resistor R8, the other end of capacitor C31 is grounded, and the other end of resistor R8 is connected to the output of the second comparator. The first, eighth, ninth, thirteenth, second, fourth, fifth, seventh, fourteenth, sixteenth, and seventeenth pins of the second RF switch chip are grounded; The twelfth pin of the second RF switch chip is connected to one end of capacitor C25 and one end of inductor L4. The other end of inductor L4 is connected to one end of capacitor C26. One end of capacitor C26 is connected to one end of capacitor C27. The other ends of capacitor C25, capacitor C26, and capacitor C27 are grounded. One end of capacitor C27 is connected to the output terminal of the second voltage regulator module. The third pin of the second RF switch chip is connected to one end of capacitor C12, the other end of capacitor C12 is connected to one end of capacitor C88, and the other end of capacitor C88 is connected to the first power divider.

[0015] The beneficial effects of this invention are: This invention utilizes two comparator circuits to control the switching between the pass-through and anti-interference circuits at both the B3 and S frequencies, simultaneously controlling the switching between these two circuits for both frequencies. This significantly reduces the number of components required for the control section, resulting in a substantial reduction in the printed circuit board (PCB) layout area. This effectively lowers the device's size, weight, and structural complexity, providing crucial technical support for portable, embedded, and space- and weight-sensitive applications (such as drones, handheld terminals, and spaceborne equipment). The reduction in component count directly leads to a decrease in bill of materials (BOM) costs. Simultaneously, the simplified hardware design reduces the complexity of production assembly, testing and calibration time, and subsequent maintenance costs.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0017] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 A schematic diagram of the comparator circuit principle of an anti-interference direct-through switching circuit for a satellite transceiver provided in an embodiment of the present invention; Figure 2 A schematic diagram of the circuit principle of an anti-interference pass-through switching circuit for a satellite transceiver provided in an embodiment of the present invention; Figure 3 A schematic diagram of the circuit principle of another anti-interference direct switching circuit for a satellite transceiver provided in an embodiment of the present invention; Figure 4 This is a schematic block diagram of the main power supply circuit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the first B3 switching circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the second B3 switching circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] like Figure 1 and Figure 2 As shown, this embodiment of the invention provides an anti-interference direct-through switching circuit for a satellite transceiver, including: a first comparator 11, a second comparator 21, a B3 frequency signal processing circuit, and an S frequency signal processing circuit.

[0021] The B3 frequency signal processing circuit includes a B3 pass-through circuit 31 and a B3 anti-interference circuit 32. The S frequency signal processing circuit includes an S pass-through circuit 41 and an S anti-interference circuit 42.

[0022] One end of the B3 anti-interference circuit 32 is connected to the first B3 switching switch 311 of the B3 direct circuit 31, and the other end is connected to the second B3 switching switch 312 of the B3 direct circuit 31; one end of the S anti-interference circuit 42 is connected to the first S switching switch 411 of the S direct circuit 41, and the other end is connected to the second S switching switch 412 of the S direct circuit 41.

[0023] The external mode control signal MODE_CTRL is input to the input terminal of the first comparator 11 and the input terminal of the second comparator 21. The output terminal of the first comparator 11 is connected to the input terminal of the first B3 switch 311 and the input terminal of the second S switch 412. The output terminal of the second comparator 21 is connected to the input terminal of the second B3 switch 312 and the input terminal of the first S switch 411.

[0024] The output signal of the first comparator 11 is opposite to that of the second comparator 21, so as to control the switching of the B3 direct circuit 31 and the B3 anti-interference circuit 32, as well as the switching of the S direct circuit 41 and the S anti-interference circuit 42.

[0025] The second switch of the B3 through circuit 31 is also connected to the first power divider 51. The first power divider 51 is connected to the first duplexer 52. The first duplexer 52 is connected to the second duplexer 53. The second duplexer 53 is connected to the second switch of the S through circuit 41. The second duplexer 53 is also connected to the second power divider 54. The second power divider 54 is connected to the two main MCX terminals 61.

[0026] The B3 frequency signal processing circuit and the S frequency signal processing circuit have a centrally symmetrical structure on the circuit board. That is, the B3 frequency signal processing circuit can coincide with the S frequency signal processing circuit after rotating the plane of the circuit board by 180 degrees. At the same time, the circuit connection structure between the first B3 switch 311 and the second B3 switch 312 is a mirror symmetrical structure on the circuit board, and the circuit connection structure between the first S switch 411 and the second S switch 412 is also a mirror symmetrical structure on the circuit board.

[0027] In this embodiment, when the pass-through mode or anti-interference mode is required, the external mode control signal MODE_CTRL is input to the first comparator 11 and the second comparator 21 respectively. The external mode control signal enables the first comparator 11 and the second comparator 21 to output opposite output signals. For example, if the first comparator 11 outputs a high level, then the second comparator 21 outputs a low level, and vice versa. When the two comparators output opposite signals, the B3 frequency signal processing circuit and the S frequency signal processing circuit simultaneously switch to the same mode, that is, simultaneously switch between the pass-through mode and the anti-interference mode. For example, if the first comparator 11 outputs a high level VCTL+, then the second comparator 21 outputs a low level VCTL-, and both frequency signal processing circuits are in pass-through mode. When the anti-interference mode is required, the external mode control signal MODE_CTRL is input, causing the first comparator 11 to output a low level VCTL-, and the second comparator 21 to output a high level VCTL+, and both frequency signal processing circuits simultaneously switch to anti-interference mode. Since the B3 frequency signal processing circuit and the S frequency signal processing circuit have a centrally symmetrical structure on the circuit board, and the switching switch has a mirror symmetrical structure, with one input and one output for the two switching switches on the same circuit, opposite signals are used to control them simultaneously to avoid interference.

[0028] Here, the B3 frequency signal processing circuit and the S frequency signal processing circuit are combined and output by a single output circuit consisting of the first power divider 51, the first duplexer 52, the second duplexer 53, and the second power divider 54.

[0029] Furthermore, the external mode control signal MODE_CTRL is input to the input terminals of the first comparator 11 and the second comparator 21 through one of the total MCX terminals 61 and the first feedthrough capacitor 62. When it is necessary to switch between pass-through and anti-interference modes, the external mode control signal input causes the first comparator 11 and the second comparator 21 to output opposite signals to control the switching between pass-through and anti-interference modes of the B3 frequency signal processing circuit and the S frequency signal processing circuit.

[0030] In one feasible implementation, such as Figure 3 As shown, it also includes a B2b frequency signal processing circuit and a B1 frequency signal processing circuit; the B2b frequency signal processing circuit is connected to the first power divider 51; the B1 frequency signal processing circuit is connected to the first duplexer 52. Specifically, the B2b frequency signal processing circuit includes: a B2b antenna MCX terminal 710, a B2b amplifier 720, and a B2b filter 730 connected in sequence. The B2b filter 730 is connected to the first power divider 51.

[0031] The B1 frequency signal processing circuit includes: a B1 antenna MCX terminal 81 and a B1 filter 82 connected in sequence; the B1 filter 82 is connected to the first duplexer 52.

[0032] The signal processing circuits at frequencies B3, S, B2b, and B1 are all combined into a single output signal.

[0033] Furthermore, such as Figure 3 As shown, the B3 through circuit 31 includes: a B3 antenna MCX terminal 313, a first B3 switch 311, a first B3 amplifier 314, a first B3 filter 315, a second B3 amplifier 316, a second B3 filter 317, and a second B3 switch 312 connected in sequence. The input terminal of the B3 anti-interference circuit 32 is connected to the first B3 switch 311 via the first MCX terminal 318, and the output terminal of the B3 anti-interference circuit 32 is connected to the second B3 switch 312 via the second MCX terminal 319.

[0034] The S-pass circuit 41 includes: an S-antenna MCX terminal 413, a first S-switch 411, a first S-amplifier 414, a first S-filter 415, a second S-amplifier 416, a second S-filter 417, and a second S-switch 412 connected in sequence. The input terminal of the S-anti-interference circuit 42 is connected to the first S-switch 411 via a third MCX terminal 418, and the output terminal of the S-anti-interference circuit 42 is connected to the second S-switch 412 via a fourth MCX terminal 419.

[0035] Furthermore, such as Figure 3 and Figure 4 As shown, in this embodiment, high-power and low-power modes can also be switched. The main power supply is divided into a first power supply, a second power supply, and a third power supply connected in parallel after passing through another main MCX terminal 61 and a second feedthrough capacitor 63, which are then input to the PCB circuit board to power all components. For example, the main power supply voltage is 5V.

[0036] The first power supply is input to the MCX terminals 313 of antenna B3, 710 of antenna B2b, and 81 of antenna B1 via the first load switch 71, supplying power to antennas B3, B2b, and B1. The power consumption control signal POWER_CTRL controls the opening and closing of the first load switch 71. When the first load switch 71 is open, antennas B3, B2b, and B1 are operational. In low-power mode, the power consumption control signal closes the first load switch 71, and antennas B3, B2b, and B1 are inactive. For example, when the first load switch 71 is open, it outputs a controlled 5V_POWER_CTRL power supply, which is input to the MCX terminals 313 of antenna B3, 710 of antenna B2b, and 81 of antenna B1.

[0037] The second power supply is input to the S-antenna MCX terminal 413 via the second load switch 72. For example, the second load switch 72 outputs a 5V_S power supply, which is input to the S-antenna MCX terminal 413.

[0038] The third power supply is split into a first buck power supply and a second buck power supply connected in parallel after passing through the buck module 73. The power consumption control signal POWER_CTRL controls the operation of the first voltage regulator module 74. The first buck power supply is input to the first B3 amplifier 314, the second B3 amplifier 316, and the B2b amplifier 720 through the first voltage regulator module 74. Therefore, the power consumption control signal POWER_CTRL can control the power supply and de-energization of the first B3 amplifier 314, the second B3 amplifier 316, and the B2b amplifier 720. For example, the first and second buck power supplies are 4V. When the first voltage regulator module 74 is turned on, it outputs the controlled power supply A3V3_POWER_CTRL, which is input to the first B3 amplifier 314, the second B3 amplifier 316, and the B2b amplifier 720.

[0039] The second step-down power supply is input to the first comparator 11, the second comparator 21, the first B3 switch 311, the second B3 switch 312, the first S switch 411, the first S amplifier 414, the second S amplifier 416, and the second S switch 412 via the second voltage regulator module 75. For example, the second voltage regulator module 75 outputs an A3V3_S power supply, which is input to the first comparator 11, the second comparator 21, the first B3 switch 311, the second B3 switch 312, the first S switch 411, the first S amplifier 414, the second S amplifier 416, and the second S switch 412.

[0040] In high-power mode, the power control signal input is enabled, and all components are powered on and operate. In low-power mode, the power control signal input is disabled, the first load switch 71 is turned off, the power supply to the B3 antenna, B2b antenna and B1 antenna is turned off, the first voltage regulator module 74 is turned off, the power supply to the first B3 amplifier 314, the second B3 amplifier 316 and the B2b amplifier 720 is turned off, and the comparator, the switching switch, the S amplifier and the S antenna are powered on. At this time, the B3 frequency signal processing circuit does not work, and only the S frequency signal processing circuit works in pass-through mode.

[0041] In this embodiment, the high-power and low-power operating modes provide powerful performance when needed and save power when not needed, thereby achieving the best balance between performance and energy consumption. This realizes "on-demand power supply" and maximizes the battery life of the battery-powered equipment, meeting the stringent requirements for long-term working capabilities in scenarios such as field operations and emergency communications.

[0042] Furthermore, the first B3 switch 311, the second B3 switch 312, the first S switch 411, and the second S switch 412 are all radio frequency switches. Here, due to the aforementioned centrally symmetrical structure, the circuits and circuit connection structures of the first B3 switch 311 and the second B3 switch 312 can overlap with the circuits and circuit connection structures of the first S switch 411 and the second S switch 412 after rotating 180 degrees on the plane of the circuit board.

[0043] Specifically, the circuit structure of the first B3 switch 311 and the second B3 switch 312 will be used as an example for explanation. Figure 5 As shown, the third pin 3 of the first RF switch chip U1 of the first B3 switching switch 311 is connected to one end of capacitor C9. The other end of capacitor C9 is connected to one end of inductor L10 and the B3 antenna MCX terminal 313. As shown in the figure, J3 is connected to the B3 antenna MCX terminal 313. The other end of inductor L10 is connected to one end of capacitor C20 and the power supply output of the first load switch 71. The other end of capacitor C20 is grounded.

[0044] Pin 12 of the first RF switch chip U1 is connected to one end of inductor L3 and one end of capacitor C24. The other end of inductor L3 is connected to one end of capacitor C22. The other ends of capacitor C24 and capacitor C22 are connected to the other end of capacitor C21. One end of capacitor C21 is connected to the power supply output of the second voltage regulator module 75.

[0045] The second pin 2, the fourth pin 4, the fifth pin 5, the seventh pin 7, the fourteenth pin 14, the sixteenth pin 16, the seventeenth pin 17, the first pin 1, the eighth pin 8, the ninth pin 9, and the thirteenth pin 13 of the first RF switch chip U1 are grounded.

[0046] Pin 11 of the first RF switch chip U1 is connected to one end of capacitor C28 and one end of resistor R7. The other end of capacitor C28 is grounded, and the other end of resistor R7 is connected to the output of the first comparator 11. For example, the output of the first comparator 11 in the figure is a low level VCTL-.

[0047] The tenth pin 10 of the first RF switch chip U1 is connected to one end of capacitor C29 and one end of resistor R5. The other end of capacitor C29 is grounded, and the other end of resistor R5 is connected to the power output of the second voltage regulator module 75.

[0048] Pin 15 of the first RF switch chip U1 is connected to one end of capacitor C19, the other end of capacitor C19 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the first B3 amplifier 314.

[0049] The sixth pin 6 of the first RF switch chip U1 is connected to one end of capacitor C5, and the other end of capacitor C5 is connected to the input terminal of B3 anti-interference circuit 32 through the first MCX terminal 318. In the figure, J1 is connected to the first MCX terminal 318.

[0050] like Figure 6 As shown, the sixth pin 6 of the second RF switch chip U2 of the second B3 switching switch 312 is connected to one end of capacitor C23, and the other end of capacitor C23 is connected to the second B3 filter 317.

[0051] The fifteenth pin 15 of the second RF switch chip U2 is connected to one end of capacitor C11. The other end of capacitor C11 is connected to one end of capacitor C105. The other end of capacitor C105 is connected to the output terminal of B3 anti-interference circuit 32 through the second MCX terminal 319. In the figure, J2 is connected to the second MCX terminal 319.

[0052] The tenth pin 10 of the second RF switch chip U2 is connected to one end of capacitor C30, one end of capacitor C30 is connected to one end of resistor R6, the other end of resistor R6 is connected to the power supply output of the second voltage regulator module 75, and the other end of capacitor C30 is grounded.

[0053] One end of pin 11 of the second RF switch chip U2 is connected to one end of capacitor C31, one end of capacitor C31 is connected to one end of resistor R8, the other end of capacitor C31 is grounded, and the other end of resistor R8 is connected to the output of the second comparator 21. For example, the output of the second comparator 21 is a high level VCTL+.

[0054] The first pin 1, the eighth pin 8, the ninth pin 9, the thirteenth pin 13, the second pin 2, the fourth pin 4, the fifth pin 5, the seventh pin 7, the fourteenth pin 14, the sixteenth pin 16, and the seventeenth pin 17 of the second RF switch chip U2 are grounded.

[0055] Pin 12 of the second RF switch chip U2 is connected to one end of capacitor C25 and one end of inductor L4. The other end of inductor L4 is connected to one end of capacitor C26. One end of capacitor C26 is connected to one end of capacitor C27. The other ends of capacitors C25, C26, and C27 are grounded. One end of capacitor C27 is connected to the power supply output of the second voltage regulator module 75.

[0056] The third pin 3 of the second RF switch chip U2 is connected to one end of capacitor C12, the other end of capacitor C12 is connected to one end of capacitor C88, and the other end of capacitor C88 is connected to the first power divider 51.

[0057] Accordingly, the first S-switch 411 and the second S-switch 412 can be connected to the corresponding components.

[0058] In this embodiment, the original multiple distributed control circuits are replaced, integrating circuit modules that previously required twice or more space. This significantly reduces the number of components on the PCB board, simplifies wiring complexity, and reduces the physical space occupied by the control circuits. Therefore, receiver devices using this invention can be made more compact and lightweight, which is of vital importance for portable devices, UAV payloads, compact vehicle platforms, and weight-sensitive aerospace applications.

[0059] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0061] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0062] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0063] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0064] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An anti-interference pass-through switching circuit for a satellite transceiver, characterized in that, include: First comparator, second comparator, B3 frequency signal processing circuit and S frequency signal processing circuit; The B3 frequency signal processing circuit includes: a B3 through circuit and a B3 anti-interference circuit; The S-frequency signal processing circuit includes: an S-pass circuit and an S-anti-interference circuit; One end of the B3 anti-interference circuit is connected to the first B3 switch of the B3 direct circuit, and the other end is connected to the second B3 switch of the B3 direct circuit; one end of the S anti-interference circuit is connected to the first S switch of the S direct circuit, and the other end is connected to the second S switch of the S direct circuit. An external mode control signal is input to the input terminals of the first comparator and the second comparator. The output terminal of the first comparator is connected to the input terminal of the first B3 switch and the input terminal of the second S switch. The output of the second comparator is connected to the input of the second B3 switch and the input of the first S switch; The output signal of the first comparator is opposite to that of the second comparator, so as to control the switching of the B3 pass-through circuit and the B3 anti-interference circuit, as well as the switching of the S pass-through circuit and the S anti-interference circuit. The second switching switch of the B3 through circuit is also connected to the first power divider, the first power divider is connected to the first duplexer, the first duplexer is connected to the second duplexer, the second duplexer is connected to the second switching switch of the S through circuit, the second duplexer is also connected to the second power divider, and the second power divider is connected to the two main MCX terminals. The B3 frequency signal processing circuit and the S frequency signal processing circuit have a centrally symmetrical structure on the circuit board.

2. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 1, characterized in that, The external mode control signal is input to the input terminals of the first comparator and the second comparator through one of the main MCX terminals and the first feedthrough capacitor.

3. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 1, characterized in that, The B3 through circuit includes: a B3 antenna MCX terminal, a first B3 switch, a first B3 amplifier, a first B3 filter, a second B3 amplifier, a second B3 filter, and a second B3 switch connected in sequence.

4. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 3, characterized in that, The S-through circuit includes: an S-antenna MCX terminal, a first S-switch, a first S-amplifier, a first S-filter, a second S-amplifier, a second S-filter, and a second S-switch connected in sequence.

5. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 4, characterized in that, It also includes B2b frequency signal processing circuitry and B1 frequency signal processing circuitry; The B2b frequency signal processing circuit is connected to the first power divider; The B1 frequency signal processing circuit is connected to the first duplexer.

6. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 5, characterized in that, The B2b frequency signal processing circuit includes: a B2b antenna MCX terminal, a B2b amplifier, and a B2b filter connected in sequence; The B2b filter is connected to the first power divider; The B1 frequency signal processing circuit includes: the B1 antenna MCX terminal and the B1 filter connected in sequence; The B1 filter is connected to the first duplexer.

7. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 6, characterized in that, Also includes the main power supply: The main power supply is divided into a first power supply, a second power supply, and a third power supply in parallel after passing through another main MCX terminal and a second feedthrough capacitor; The first power supply is input to the B3 antenna MCX terminal, the B2b antenna MCX terminal, and the B1 antenna MCX terminal through the first load switch; the power consumption control signal controls the opening and closing of the first load switch; The second power supply is input to the S antenna MCX terminal via the second load switch; The third power supply is divided into a first step-down power supply and a second step-down power supply connected in parallel after passing through the step-down module. The power consumption control signal controls the first voltage regulator module, and the first step-down power supply is input to the first B3 amplifier, the second B3 amplifier and the B2b amplifier through the first voltage regulator module; The second step-down power supply is input to the first comparator, the second comparator, the first B3 switch, the second B3 switch, the first S switch, the first S amplifier, the second S amplifier, and the second S switch through the second voltage regulator module.

8. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 7, characterized in that, The first B3 switch, the second B3 switch, the first S switch, and the second S switch are all radio frequency switches; The circuit structures of the first B3 switch and the second B3 switch are mirror-symmetric structures.

9. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 8, characterized in that, The first B3 switching switch includes: a first radio frequency switching chip; The third pin of the first RF switch chip is connected to one end of capacitor C9, the other end of capacitor C9 is connected to one end of inductor L10 and the MCX terminal of antenna B3, the other end of inductor L10 is connected to one end of capacitor C20 and connected to the power supply output of the first load switch, and the other end of capacitor C20 is grounded. The twelfth pin of the first RF switch chip is connected to one end of inductor L3 and one end of capacitor C24. The other end of inductor L3 is connected to one end of capacitor C22. The other ends of capacitor C24 and capacitor C22 are connected to the other end of capacitor C21. One end of capacitor C21 is connected to the output terminal of the second voltage regulator module. The second, fourth, fifth, seventh, fourteenth, sixteenth, seventeenth, first, eighth, ninth, and thirteenth pins of the first RF switch chip are grounded; The eleventh pin of the first RF switch chip is connected to one end of capacitor C28 and one end of resistor R7. The other end of capacitor C28 is grounded, and the other end of resistor R7 is connected to the output of the first comparator. The tenth pin of the first RF switch chip is connected to one end of capacitor C29 and one end of resistor R5. The other end of capacitor C29 is grounded, and the other end of resistor R5 is connected to the output terminal of the second voltage regulator module. The fifteenth pin of the first RF switch chip is connected to one end of capacitor C19, the other end of capacitor C19 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the first B3 amplifier. The sixth pin of the first RF switch chip is connected to one end of capacitor C5, and the other end of capacitor C5 is connected to one end of the B3 anti-interference circuit.

10. The anti-interference direct-through switching circuit for a satellite transceiver as described in claim 8, characterized in that, The second B3 switching switch includes: a second radio frequency switching chip; The sixth pin of the second RF switch chip is connected to one end of capacitor C23, and the other end of capacitor C23 is connected to the second B3 filter; The fifteenth pin of the second RF switch chip is connected to one end of capacitor C11, the other end of capacitor C11 is connected to one end of capacitor C105, and the other end of capacitor C105 is connected to the other end of the B3 anti-interference circuit. The tenth pin of the second RF switch chip is connected to one end of capacitor C30, one end of capacitor C30 is connected to one end of resistor R6, the other end of resistor R6 is connected to the output terminal of the second voltage regulator module, and the other end of capacitor C30 is grounded. One end of the eleventh pin of the second RF switch chip is connected to one end of capacitor C31, one end of capacitor C31 is connected to one end of resistor R8, the other end of capacitor C31 is grounded, and the other end of resistor R8 is connected to the output of the second comparator. The first, eighth, ninth, thirteenth, second, fourth, fifth, seventh, fourteenth, sixteenth, and seventeenth pins of the second RF switch chip are grounded; The twelfth pin of the second RF switch chip is connected to one end of capacitor C25 and one end of inductor L4. The other end of inductor L4 is connected to one end of capacitor C26. One end of capacitor C26 is connected to one end of capacitor C27. The other ends of capacitor C25, capacitor C26, and capacitor C27 are grounded. One end of capacitor C27 is connected to the output terminal of the second voltage regulator module. The third pin of the second RF switch chip is connected to one end of capacitor C12, the other end of capacitor C12 is connected to one end of capacitor C88, and the other end of capacitor C88 is connected to the first power divider.

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