Semiconductor structure and forming method thereof
By forming grooves in the suspended gate layer of the semiconductor structure and filling the control gate layer, the problem of insufficient performance of semiconductor devices in the prior art is solved, and a higher number of stored charges and storage performance is achieved.
Patent Information
- Application Number
- CN202311028216.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-25
AI Technical Summary
Existing or non-flash devices still need to be improved.
By forming grooves in the suspended gate layer and forming a control gate layer on top of the suspended gate layer, the control gate layer is filled in the groove, thereby increasing the contact area and coupling capacitance between the control gate layer and the suspended gate layer.
The coupling capacitance and coupling coefficient between the control gate layer and the suspended gate layer are increased, the number of stored charges in the suspended gate layer is improved, and the storage performance of the semiconductor structure is improved.
Smart Images
Figure CN119521665A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] Flash memory is a non-volatile memory (NVM). The main feature of flash memory is that it can retain stored information for a long time without power supply, and has the advantages of high integration, fast access speed, easy erasure and rewrite, etc. Therefore, it has been widely used in many fields such as microcomputers and automation control.
[0003] According to different structures, flash memory can be divided into two types: NOR Flash and NAND Flash. Among them, NOR Flash, also known as coded flash memory, has become the mainstream non-volatile memory in flash memory technology because of its features such as direct code execution, high reliability and fast reading speed.
[0004] However, the performance of existing or non-flash memory devices still needs to be improved. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor device.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a suspended gate layer located on the top of the substrate; a groove located in the suspended gate layer; a control gate layer located on the top of the suspended gate layer, and the control gate layer is also filled in the groove.
[0007] Optionally, the semiconductor structure further includes: a gate oxide layer located on the top of the substrate, and the gate oxide layer is located between the substrate and the floating gate layer.
[0008] Optionally, the gate oxide layer has a thickness of 8 nanometers to 12 nanometers.
[0009] Optionally, the semiconductor structure further includes: a shallow trench isolation structure located in the substrate, and the shallow trench isolation structure exposes the sidewall of the floating gate layer; the semiconductor structure further includes: a sidewall layer located on the top of the shallow trench isolation structure and covering the sidewall of the floating gate layer.
[0010] Optionally, along the normal direction of the substrate surface, the depth of the groove is 20 nanometers to 30 nanometers.
[0011] Optionally, with a direction perpendicular to the extension direction of the floating gate and parallel to the surface of the substrate as a lateral direction, a lateral dimension of the groove is 15 nanometers to 30 nanometers.
[0012] Optionally, the semiconductor structure further includes: an insulating layer located at the bottom and sidewalls of the groove and the top of the floating gate layer; and the control gate layer covers the insulating layer.
[0013] Optionally, the thickness of the insulating layer is 13 nanometers to 15 nanometers.
[0014] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, a floating gate layer formed on the top of the substrate; forming a groove in the floating gate layer; forming a control gate layer on the top of the floating gate layer, and the control gate layer is also filled in the groove.
[0015] Optionally, in the step of providing a substrate, a gate oxide layer is further formed on the top of the substrate, and the gate oxide layer is located between the substrate and the suspended gate layer.
[0016] Optionally, in the step of providing a substrate, a shallow trench isolation structure is also formed in the substrate and the floating gate layer, and the shallow trench isolation structure penetrates the floating gate layer; after forming the groove and before forming the control gate layer, it also includes: removing part of the shallow trench isolation structure to expose the side wall of the floating gate layer; after forming the control gate layer, the method for forming the semiconductor structure also includes: forming a sidewall layer covering the side wall of the floating gate layer and the side wall of the control gate layer on top of the shallow trench isolation structure.
[0017] Optionally, the process of removing part of the shallow trench isolation structure includes a dry etching process.
[0018] Optionally, the step of forming the groove includes: forming a mask layer having a mask opening on the top of the floating gate layer, the mask opening exposing a portion of the top surface of the floating gate layer; using the mask layer as a mask, patterning the floating gate layer along the mask opening to form a groove in the floating gate layer; and removing the mask layer.
[0019] Optionally, the process of removing the mask layer includes an ashing process.
[0020] Optionally, the process of forming the groove includes a dry etching process.
[0021] Optionally, after forming the groove and before forming the control gate layer, the method further includes: forming an insulating layer on the sidewall and bottom of the groove and on the top of the floating gate layer; and during the process of forming the control gate layer, the control gate layer covers the insulating layer.
[0022] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0023] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a groove is formed in a floating gate layer, and a control gate layer is formed on top of the floating gate layer. The control gate layer is also filled in the groove, so that the contact surface between the control gate layer and the floating gate layer includes a contact surface in a horizontal direction and a contact surface in a vertical direction, thereby increasing the contact area between the control gate layer and the floating gate layer, thereby increasing the coupling capacitance between the control gate layer and the floating gate layer. When the coupling capacitance between the control gate layer and the floating gate layer increases, the coupling coefficient (Coupling Ratio) of the control gate layer to the floating gate layer is also increased, thereby increasing the amount of stored charge in the floating gate layer, thereby improving the storage performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a corresponding structural schematic diagram of a semiconductor structure;
[0025] Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;
[0026] Figures 3 to 9 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0027] At present, the performance of semiconductor structures still needs to be improved. The reasons why the performance of semiconductor structures needs to be improved are analyzed in combination with a schematic diagram of a semiconductor structure.
[0028] Figure 1 It is a corresponding structural schematic diagram of a semiconductor structure.
[0029] The semiconductor structure includes: a substrate 20; a suspended gate layer 12 protruding from the top of the substrate 20; a shallow trench isolation structure 21 located in the substrate 20 on both sides of the suspended gate layer 12; a gate oxide layer 23 located on the top of the substrate 20 and between the substrate 20 and the suspended gate layer 12; an insulating layer 11 located on the top of the suspended gate layer 12; and a control gate layer 22 located on the top of the insulating layer 11.
[0030] It is found through research that the coupling ratio of the control gate layer 22 to the floating gate layer 12 is affected by the coupling capacitance between the control gate layer 22 and the floating gate layer 12, that is, the greater the coupling capacitance between the control gate layer 22 and the floating gate layer 12, the greater the coupling ratio of the control gate layer 22 to the floating gate layer 12. The coupling capacitance between the control gate layer 22 and the floating gate layer 12 is affected by the contact area between the control gate layer 22 and the floating gate layer 12, that is, the greater the contact area between the control gate layer 22 and the floating gate layer 12, the greater the coupling capacitance between the control gate layer 22 and the floating gate layer 12. As the volume and process of the semiconductor structure are reduced, the contact area between the control gate layer 22 and the floating gate layer 12 becomes smaller and smaller, so that the coupling capacitance between the control gate layer 22 and the floating gate layer 12 becomes smaller and smaller, thereby reducing the coupling ratio of the control gate layer 22 to the floating gate layer 12, and further reducing the amount of stored charge in the floating gate layer 12, which affects the storage performance of the semiconductor structure.
[0031] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a floating gate layer formed on the top of the substrate; forming a groove in the floating gate layer; forming a control gate layer on the top of the floating gate layer, and the control gate layer is also filled in the groove.
[0032] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a groove is formed in a floating gate layer, and a control gate layer is formed on top of the floating gate layer. The control gate layer is also filled in the groove, so that the contact surface between the control gate layer and the floating gate layer includes a contact surface in a horizontal direction and a contact surface in a vertical direction, thereby increasing the contact area between the control gate layer and the floating gate layer, thereby increasing the coupling capacitance between the control gate layer and the floating gate layer. When the coupling capacitance between the control gate layer and the floating gate layer increases, the coupling coefficient (Coupling Ratio) of the control gate layer to the floating gate layer is also increased, thereby increasing the amount of stored charge in the floating gate layer, thereby improving the storage performance of the semiconductor structure.
[0033] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0034] Figure 2 It is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention.
[0035] The semiconductor structure includes: a substrate 200; a floating gate layer 202 located on the top of the substrate 200; a groove (not shown) located in the floating gate layer 202; a control gate layer 212 located on the top of the floating gate layer 202, and the control gate layer 212 is also filled in the groove.
[0036] Specifically, a groove is set in the floating gate layer 202, and the control gate layer 212 is also filled in the groove, so that the contact surface between the control gate layer 212 and the floating gate layer 202 includes a contact surface in the horizontal direction and a contact surface in the vertical direction, thereby increasing the contact area between the control gate layer 212 and the floating gate layer 202, thereby increasing the coupling capacitance between the control gate layer 212 and the floating gate layer 202. When the coupling capacitance between the control gate layer 212 and the floating gate layer 202 increases, the coupling coefficient (Coupling Ratio) of the control gate layer 212 to the floating gate layer 202 is increased, thereby increasing the amount of stored charge in the floating gate layer 202, thereby improving the storage performance of the semiconductor structure.
[0037] The substrate 200 provides a process platform for forming a flash memory.
[0038] In this embodiment, the substrate 200 is used to provide a process platform for forming a NOR Flash device.
[0039] In this embodiment, the substrate 200 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin.
[0040] The floating gate layer 202 is used to store electrons during the operation of the NOR flash memory device, so that the NOR flash memory device can perform the function of data storage.
[0041] In this embodiment, the material of the floating gate layer 202 is polysilicon.
[0042] In this embodiment, the semiconductor structure further includes: a gate oxide layer 203 located on the top of the substrate 200 , and the gate oxide layer 203 is located between the substrate 200 and the floating gate layer 202 .
[0043] Specifically, the gate oxide layer 203 is a tunnel oxide layer (Tunnel Oxide) of the NOR flash memory, which is used as an isolation layer between the suspended gate layer 202 and the substrate 200, so that when the flash memory is working, the tunneling effect is used to allow electrons to enter the suspended gate layer 202 through the gate oxide layer 203. Moreover, during the data storage process, the electrons stored in the suspended gate layer 202 are prevented from entering the silicon substrate, thereby reducing the loss of electrons. That is, the gate oxide layer 203 is suitable for preventing the data stored in the suspended gate layer 202 from being lost.
[0044] In this embodiment, the material of the gate oxide layer 203 is silicon oxide.
[0045] It should be noted that the thickness of the gate oxide layer 203 should not be too large or too small. If the thickness of the gate oxide layer 203 is too large, it is easy to cause the height of the suspended gate layer 202 to be too large, resulting in the overall height of the NOR flash memory being too high, which is not conducive to the overall scaling of the semiconductor structure; if the thickness of the gate oxide layer 203 is too small, the probability of the electrons stored in the suspended gate layer 202 entering the silicon substrate during the data storage process is increased, thereby increasing the probability of electron loss, thereby affecting the storage performance of the NOR flash memory. For this reason, in this embodiment, the thickness of the gate oxide layer 203 is 8 nanometers to 12 nanometers.
[0046] In this embodiment, the semiconductor structure further includes: a shallow trench isolation structure 201 located in the substrate 200 , and the shallow trench isolation structure 201 exposes the sidewall of the floating gate layer 202 .
[0047] Specifically, the shallow trench isolation structure 201 is used to electrically isolate adjacent floating gate layers 202 , thereby reducing the risk of electrical leakage between adjacent floating gate layers 202 .
[0048] It should be noted that the shallow trench isolation structure 201 exposes the sidewall of the floating gate layer 202 , which is conducive to the provision of a spacer layer 220 covering the sidewall of the floating gate layer 202 and the sidewall of the control gate layer 212 .
[0049] The material of the shallow trench isolation structure 201 is a dielectric material. In this embodiment, the material of the shallow trench isolation structure 201 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the shallow trench isolation structure 201 is silicon oxide.
[0050] It should be noted that the depth of the groove should not be too large or too small along the normal direction of the surface of the substrate 200. If the depth of the groove is too large, it is easy to cause the aspect ratio of the groove to be too large. In the process of setting the control gate layer 212 in the groove, the filling difficulty of the control gate layer 212 is increased, the risk of voids in the control gate layer 212 is increased, and the probability of electrical failure of the NOR flash memory is greatly increased, thereby affecting the performance of the semiconductor structure; if the depth of the groove is too small, it is easy to cause the contact area between the control gate layer 212 set in the groove and the suspended gate layer 202 to increase insignificantly, so that the coupling capacitance between the control gate layer 212 and the suspended gate layer 202 is not increased, that is, the coupling coefficient (Coupling Ratio) of the control gate layer 212 to the suspended gate layer 202 is not improved, so that the amount of stored charge in the suspended gate layer 202 is not increased, thereby affecting the storage performance of the semiconductor structure. To this end, in this embodiment, along the normal direction of the surface of the substrate 200, the depth of the groove is 20 nanometers to 30 nanometers.
[0051] Specifically, the lateral dimension of the groove should not be too large or too small, with the direction perpendicular to the extension direction of the floating gate layer 202 and parallel to the surface of the substrate 200 as the lateral dimension. If the lateral dimension of the groove is too large, it is easy to cause the lateral dimension of the floating gate layer 202 on the side of the groove to be too narrow, increasing the risk of the floating gate layer 202 on the side of the groove falling sideways. If the lateral dimension of the groove is too small, it is easy to cause the depth-to-width ratio of the groove to be too large, and in the process of setting the control gate layer 212 in the groove, the filling difficulty of the control gate layer 212 is increased, and the risk of voids in the control gate layer 212 is increased, which greatly increases the probability of electrical failure of the NOR flash memory, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, with the direction perpendicular to the extension direction of the floating gate and parallel to the surface of the substrate 200 as the lateral dimension, the lateral dimension of the groove is 15 nanometers to 30 nanometers.
[0052] In this embodiment, the semiconductor structure further includes: an insulating layer 210 located at the bottom and sidewalls of the groove and the top of the floating gate layer 202 .
[0053] It should be noted that the insulating layer 210 is used to achieve electrical isolation between the floating gate layer 202 and the control gate layer 212 .
[0054] It should also be noted that the thickness of the insulating layer 210 should not be too large or too small. If the thickness of the insulating layer 210 is too large, it is easy to cause the height of the NOR flash memory to be too large, which is not conducive to the overall scaling of the semiconductor structure; if the thickness of the insulating layer 210 is too small, it is easy to affect the effect of the insulating layer 210 used to achieve electrical isolation between the floating gate layer 202 and the control gate layer 212, increasing the probability of leakage current between the floating gate layer 202 and the control gate layer 212, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in this embodiment, the thickness of the insulating layer 210 is 13 nanometers to 15 nanometers.
[0055] In this embodiment, the insulating layer 210 is an Oxide-Nitride-Oxide (ONO) structure.
[0056] The control gate layer 212 is used to implement logic control operations of the NOR flash memory device, such as write control, read control, etc.
[0057] In this embodiment, the material of the control gate layer 212 is the same as that of the floating gate layer 202 , that is, the material of the control gate layer 212 is polysilicon.
[0058] As can be seen from the foregoing, the top of the floating gate layer 202 and the bottom and sidewalls of the groove are provided with an insulating layer 210 . Accordingly, in the process of forming the control gate layer 212 , the control gate layer 212 covers the insulating layer 210 .
[0059] In this embodiment, the semiconductor structure further includes: a spacer layer 220 , which is located on the top of the shallow trench isolation structure 201 and covers the sidewall of the floating gate layer 202 .
[0060] The spacer layer 220 is used to protect the sidewalls of the floating gate layer 202 and the control gate layer 212 .
[0061] As an example, the spacer layer 220 is a single-layer structure. Accordingly, the material of the spacer layer 220 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.
[0062] In other embodiments, the spacer layer may also be a stacked structure. Specifically, the spacer layer 220 is an ONO structure.
[0063] It should be noted that the spacer layer 220 also covers the sidewalls of the insulation layer 210 .
[0064] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.
[0065] refer to Figures 3 to 9, showing a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0066] refer to Figure 3 , providing a substrate 100 , a floating gate layer 102 is formed on the top of the substrate 100 .
[0067] The substrate 100 provides a process platform for subsequently forming a flash memory.
[0068] In this embodiment, the substrate 100 is used to provide a process platform for subsequently forming a NOR Flash device.
[0069] In this embodiment, the substrate 100 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin.
[0070] The floating gate layer 102 is used to store electrons during the operation of the NOR flash memory device, so that the NOR flash memory device can perform the function of data storage.
[0071] In this embodiment, the material of the floating gate layer 102 is polysilicon.
[0072] In this embodiment, the steps of forming the floating gate layer 102 include: forming a first gate film on the substrate 100; forming a patterned mask layer on the first gate film; using the patterned mask layer as a mask, patterning the first gate film to form the floating gate layer 102 on the substrate 100.
[0073] In this embodiment, the process of patterning the first gate film includes a dry etching process.
[0074] Specifically, the patterning of the first gate film by using a dry etching process is beneficial to improving the morphology quality of the sidewall of the floating gate layer 102 .
[0075] In this embodiment, in the step of providing the substrate 100 , a gate oxide layer 103 is further formed on the top of the substrate 100 , and the gate oxide layer 103 is located between the substrate 100 and the floating gate layer 102 .
[0076] Specifically, the gate oxide layer 103 is a tunnel oxide layer (Tunnel Oxide) of the NOR flash memory, which is used as an isolation layer between the suspended gate layer 102 and the substrate 100, so that when the flash memory is working, the tunneling effect is used to allow electrons to enter the suspended gate layer 102 through the gate oxide layer 103. Moreover, during the data storage process, the electrons stored in the suspended gate layer 102 are prevented from entering the silicon substrate, thereby reducing the loss of electrons. That is, the gate oxide layer 103 is suitable for preventing the data stored in the suspended gate layer 102 from being lost.
[0077] In this embodiment, the material of the gate oxide layer 103 is silicon oxide.
[0078] It should be noted that the thickness of the gate oxide layer 103 should not be too large or too small. If the thickness of the gate oxide layer 103 is too large, it is easy to cause the height of the suspended gate layer 102 to be too large. After the control gate layer is subsequently formed, the overall height of the NOR flash memory is too high, which is not conducive to the overall scaling of the semiconductor structure; if the thickness of the gate oxide layer 103 is too small, the probability of the electrons stored in the suspended gate layer 102 entering the silicon substrate is increased during the data storage process, thereby increasing the probability of electron loss, thereby affecting the storage performance of the NOR flash memory. For this reason, in this embodiment, the thickness of the gate oxide layer 103 is 8 nanometers to 12 nanometers.
[0079] In this embodiment, in the step of providing the substrate 100 , a shallow trench isolation structure 101 is further formed in the substrate 100 and the floating gate layer 102 , and the shallow trench isolation structure 101 penetrates the floating gate layer 102 .
[0080] Specifically, the shallow trench isolation structure 101 is used to electrically isolate adjacent floating gate layers 102 , thereby reducing the risk of electrical leakage between adjacent floating gate layers 102 .
[0081] The material of the shallow trench isolation structure 101 is a dielectric material. In this embodiment, the material of the shallow trench isolation structure 101 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the shallow trench isolation structure 101 is silicon oxide.
[0082] refer to Figures 4 to 5 , a groove 108 is formed in the floating gate layer 102 .
[0083] Specifically, a groove 108 is formed in the floating gate layer 102, and a control gate layer is subsequently formed on the top of the floating gate layer 102. The control gate layer is also filled in the groove 108, so that the contact surface between the control gate layer and the floating gate layer 102 includes a contact surface in the horizontal direction and a contact surface in the vertical direction, thereby increasing the contact area between the control gate layer and the floating gate layer 102, thereby increasing the coupling capacitance between the control gate layer and the floating gate layer 102. When the coupling capacitance between the control gate layer and the floating gate layer 102 increases, the coupling coefficient (Coupling Ratio) of the control gate layer to the floating gate layer 102 is increased, thereby increasing the amount of stored charge in the floating gate layer 102, thereby improving the storage performance of the semiconductor structure.
[0084] In this embodiment, the step of forming the groove 108 includes: forming a mask layer 104 having a mask opening 105 on the top of the floating gate layer 102, the mask opening 105 exposing a portion of the top surface of the floating gate layer 102; using the mask layer 104 as a mask, patterning the floating gate layer 102 along the mask opening 105 to form a groove 108 in the floating gate layer 102.
[0085] Specifically, during the process of forming the mask layer 104 , the mask layer 104 also covers the top of the shallow trench isolation structure 101 .
[0086] In this embodiment, the material of the mask layer 104 includes photoresist.
[0087] Specifically, photoresist is a material commonly used in etching processes and has the characteristics of low process cost. At the same time, the photoresist material is an inorganic material. In the subsequent process of removing the photoresist, the process difficulty of removing the photoresist is reduced, and the probability of residual photoresist on the top of the suspended gate layer 102 is reduced, thereby improving the performance of the semiconductor structure.
[0088] In this embodiment, the process of forming the groove 108 includes a dry etching process.
[0089] It should be noted that the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is high. When the part of the floating gate layer 102 is removed, it is easy to ensure the morphology quality of the side wall of the groove 108, which is conducive to the subsequent filling of the control gate layer in the groove 108.
[0090] It should also be noted that the depth of the groove 108 along the normal direction of the surface of the substrate 100 should not be too large or too small. If the depth of the groove 108 is too large, it is easy to cause the aspect ratio of the groove 108 to be too large, and in the subsequent process of forming the control gate layer in the groove 108, the filling difficulty of the control gate layer is increased, the risk of voids in the control gate layer is increased, and the probability of electrical failure of the NOR flash memory is greatly increased, thereby affecting the performance of the semiconductor structure; if the depth of the groove 108 is too small, it is easy to cause the contact area between the control gate layer and the suspended gate layer 102 formed in the groove 108 to increase insignificantly, so that the coupling capacitance between the control gate layer and the suspended gate layer 102 is not increased, and the coupling coefficient (Coupling Ratio) of the control gate layer to the suspended gate layer 102 is not improved, so that the amount of stored charge in the suspended gate layer 102 is not increased, thereby affecting the storage performance of the semiconductor structure. To this end, in this embodiment, along the normal direction of the surface of the substrate 100 , the depth of the groove 108 is 20 nanometers to 30 nanometers.
[0091] Specifically, the lateral dimension of the groove 108 should not be too large or too small, with the direction perpendicular to the extension direction of the floating gate layer 102 and parallel to the surface of the substrate 100 as the lateral dimension. If the lateral dimension of the groove 108 is too large, it is easy to cause the lateral dimension of the floating gate layer 102 on the side of the groove 108 to be too narrow, increasing the risk of the floating gate layer 102 on the side of the groove 108 falling sideways. If the lateral dimension of the groove 108 is too small, it is easy to cause the depth-to-width ratio of the groove 108 to be too large, and in the subsequent process of forming the control gate layer in the groove 108, the filling difficulty of the control gate layer is increased, and the risk of voids in the control gate layer is increased, which greatly increases the probability of electrical failure of the NOR flash memory, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, with the direction perpendicular to the extension direction of the floating gate and parallel to the surface of the substrate 100 as the lateral dimension, the lateral dimension of the groove 108 is 15 nanometers to 30 nanometers.
[0092] It should be noted that, after forming the groove 108 , the method for forming the semiconductor structure further includes: removing the mask layer 104 .
[0093] The mask layer 104 is removed to expose the top of the shallow trench isolation structure 101 , which is beneficial to the subsequent removal of part of the shallow trench isolation structure 101 to expose the sidewall of the floating gate layer 102 .
[0094] In this embodiment, the process of removing the mask layer 104 includes an ashing process.
[0095] Specifically, the ashing process is a commonly used process for removing the mask layer 104, and the ashing process is used to remove the mask layer 104, which can cleanly remove the mask layer 104 on the top of the floating gate layer 102 and the shallow trench isolation structure 101, thereby reducing the probability of residual mask layer 104 on the top of the floating gate layer 102 and the shallow trench isolation structure 101, thereby improving the performance of the semiconductor structure.
[0096] refer to Figure 6 After forming the groove 108 and before forming the control gate layer, the method further includes: removing a portion of the shallow trench isolation structure 101 to expose the sidewall of the floating gate layer 102 .
[0097] It should be noted that removing part of the shallow trench isolation structure 101 to expose the side wall of the floating gate layer 102 is beneficial to the subsequent formation of a sidewall layer covering the side wall of the floating gate layer 102 and the side wall of the control gate layer. At the same time, compared with the solution of removing part of the shallow trench isolation structure 101 after forming the control gate layer, this embodiment removes part of the shallow trench isolation structure 101 before forming the control gate layer, which can reduce the influence of too many etching processes on the control gate layer and reduce the probability of damage to the control gate layer, thereby improving the performance of the semiconductor structure.
[0098] In this embodiment, the process of removing part of the shallow trench isolation structure 101 includes a dry etching process.
[0099] It should be noted that the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is high. In the process of removing part of the shallow trench isolation structure 101, it is easy to ensure the morphology quality of the side wall of the floating gate layer 102, and reduce the probability of the etching process causing damage to the side wall of the floating gate layer 102.
[0100] refer to Figure 7 After forming the groove 108 and before subsequently forming the control gate layer, the method further includes: forming an insulating layer 110 on the sidewall and bottom of the groove 108 and on the top of the floating gate layer 102 .
[0101] It should be noted that the insulating layer 110 is used to achieve electrical isolation between the floating gate layer 102 and a control gate layer formed subsequently.
[0102] It should also be noted that after a portion of the shallow trench isolation structure 101 is removed, an insulating layer 110 is formed on the sidewall and bottom of the groove 108 and on the top of the floating gate layer 102 .
[0103] By forming the groove 108, the area between the subsequently formed control gate layer and the floating gate layer 102 can be increased, and the coupling coefficient between the control gate layer and the floating gate layer 102 can be increased, so that more voltage falls on the insulating layer 110, thereby increasing the number of electrons entering the floating gate layer 102, effectively improving the storage performance of the semiconductor structure.
[0104] In this embodiment, the step of forming the insulating layer 110 includes: forming an insulating material layer on the top of the shallow trench isolation structure 101, the top of the floating gate layer 102, and the bottom and sidewalls of the groove 108; removing the insulating material layer on the top of the shallow trench isolation structure 101, and the remaining insulating material layer located on the top of the floating gate layer 102 and the bottom and sidewalls of the groove 108 is used as the insulating layer 110.
[0105] It should be noted that the thickness of the insulating layer 110 should not be too large or too small. If the thickness of the insulating layer 110 is too large, it is easy to cause the height of the NOR flash memory to be too large, which is not conducive to the overall scaling of the semiconductor structure; if the thickness of the insulating layer 110 is too small, it is easy to affect the effect of the insulating layer 110 used to achieve electrical isolation between the floating gate layer 102 and the control gate layer formed subsequently, increasing the probability of leakage current between the floating gate layer 102 and the control gate layer, thereby increasing the probability of electrical failure of the semiconductor structure. For this reason, in this embodiment, the thickness of the insulating layer 110 is 13 nanometers to 15 nanometers.
[0106] In this embodiment, the insulating layer 110 is an Oxide-Nitride-Oxide (ONO) structure.
[0107] refer to Figure 8 A control gate layer 112 is formed on the top of the floating gate layer 102 , and the control gate layer 112 is also filled in the groove 108 .
[0108] The control gate layer 112 is used to implement logic control operations of the NOR flash memory device, such as write control, read control, etc.
[0109] In this embodiment, the material of the control gate layer 112 is the same as that of the floating gate layer 102 , that is, the material of the control gate layer 112 is polysilicon.
[0110] In this embodiment, the step of forming the control gate layer 112 includes: forming a second gate film on the top of the insulating layer 110 and on the top of the shallow trench isolation structure 101; removing the second gate film on the top of the shallow trench isolation structure 101, and the remaining second gate film located on the top of the insulating layer 110 is used as the control gate layer 112.
[0111] In this embodiment, the process of forming the second gate film includes at least one of an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process and a furnace process.
[0112] In this embodiment, the process of removing the second gate film on the top of the shallow trench isolation structure 101 includes a dry etching process.
[0113] As can be seen from the foregoing, the insulating layer 110 is formed on the top of the floating gate layer 102 and the bottom and sidewalls of the groove 108 . Accordingly, during the process of forming the control gate layer 112 , the control gate layer 112 covers the insulating layer 110 .
[0114] refer to Fig. 9 After forming the control gate layer 112 , the method for forming the semiconductor structure further includes: forming a sidewall layer 120 covering the sidewalls of the floating gate layer 102 and the control gate layer 112 on the top of the shallow trench isolation structure 101 .
[0115] The spacer layer 120 is used to protect the sidewalls of the floating gate layer 102 and the control gate layer 112 .
[0116] In this embodiment, the step of forming the sidewall layer 120 includes: forming a sidewall material layer on the sidewalls of the floating gate layer 102 and the control gate layer 112, on the top of the control gate layer 112, and on the top of the shallow trench isolation structure 101; removing the sidewall material layer on the top of the shallow trench isolation structure 101 and the sidewall material layer on the top of the control gate layer 112, and the remaining sidewall material layer located on the sidewalls of the floating gate layer 102 and the sidewalls of the control gate layer 112 is used as the sidewall layer 120.
[0117] As an example, the spacer layer 120 is a single-layer structure. Accordingly, the material of the spacer layer 120 can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.
[0118] In other embodiments, the sidewall layer may also be a stacked structure. Specifically, the sidewall layer is an ONO structure.
[0119] It should be noted that, in the step of forming the spacer layer 120 , the spacer layer 120 also covers the sidewalls of the insulating layer 110 .
[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A suspended gate layer, located on top of the substrate; A groove is located in the suspended gate layer; The control gate layer is located on the top of the suspension gate layer, and the control gate layer is also filled in the groove.
2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a gate oxide layer located on the top of the substrate, and the gate oxide layer is located between the substrate and the floating gate layer.
3. The semiconductor structure according to claim 2, wherein: The thickness of the gate oxide layer is 8 nanometers to 12 nanometers.
4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a shallow trench isolation structure located in the substrate, wherein the shallow trench isolation structure exposes the sidewall of the floating gate layer; The semiconductor structure further includes: a sidewall layer located on the top of the shallow trench isolation structure and covering the sidewall of the floating gate layer.
5. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the depth of the groove is 20 nanometers to 30 nanometers.
6. The semiconductor structure according to claim 1, wherein: With the direction perpendicular to the extension direction of the floating gate and parallel to the surface of the substrate as the lateral direction, the lateral dimension of the groove is 15 nanometers to 30 nanometers.
7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an insulating layer located at the bottom and sidewalls of the groove and the top of the floating gate layer; The control gate layer covers the insulating layer.
8. The semiconductor structure according to claim 7, wherein: The thickness of the insulating layer is 13 nanometers to 15 nanometers.
9. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, with a suspended gate layer formed on the top of the substrate; forming a groove in the floating gate layer; A control gate layer is formed on the top of the floating gate layer, and the control gate layer is also filled in the groove.
10. The method for forming a semiconductor structure according to claim 9, wherein: In the step of providing a substrate, a gate oxide layer is further formed on the top of the substrate, and the gate oxide layer is located between the substrate and the floating gate layer.
11. The method for forming a semiconductor structure according to claim 9, wherein: In the step of providing a substrate, a shallow trench isolation structure is also formed in the substrate and the floating gate layer, and the shallow trench isolation structure penetrates the floating gate layer; After forming the groove and before forming the control gate layer, the method further includes: removing part of the shallow trench isolation structure to expose the side wall of the floating gate layer; After forming the control gate layer, the method for forming the semiconductor structure further includes: forming a sidewall layer covering the sidewalls of the floating gate layer and the control gate layer on the top of the shallow trench isolation structure.
12. The method for forming a semiconductor structure according to claim 11, wherein: The process of removing part of the shallow trench isolation structure includes a dry etching process.
13. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming the groove includes: forming a mask layer with a mask opening on the top of the floating gate layer, the mask opening exposing a portion of the top surface of the floating gate layer; using the mask layer as a mask, patterning the floating gate layer along the mask opening to form a groove in the floating gate layer; and removing the mask layer.
14. The method for forming a semiconductor structure according to claim 13, wherein: The process of removing the mask layer includes an ashing process.
15. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the groove includes a dry etching process.
16. The method for forming a semiconductor structure according to claim 9, wherein: After forming the groove and before forming the control gate layer, the method further includes: forming a groove on the sidewall and bottom of the groove, and An insulating layer is formed on the top of the suspended gate layer; During the process of forming the control gate layer, the control gate layer covers the insulating layer.