Anti-radiation hardened phase frequency detector circuit

Abstract

The invention relates to a phase frequency detector circuit with radiation hardening. The phase frequency detector circuit comprises a first D flip-flop circuit, a second D flip-flop circuit, a C unit circuit and a frequency locking indication unit circuit, the first D flip-flop circuit and the second D flip-flop circuit are the same in structure, each of the first D flip-flop circuit and the second D flip-flop circuit comprises a first DICE latch circuit and a second DICE latch circuit which are connected in sequence, and the DICE latch circuits are controlled by zero setting signals and clock signals; two input ends of the C unit circuit are respectively connected with output ends of the first D flip-flop circuit and the second D flip-flop circuit, and an output signal of the C unit circuit is fed back to the first D flip-flop circuit and the second D flip-flop circuit as a zero setting signal; the input end of the frequency locking indication unit circuit is connected with the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output end of the frequency locking indication unit circuit outputs a frequency locking indication signal. According to the invention, the anti-radiation reinforcement design of the phase frequency detector circuit is realized.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor integrated circuits, and in particular to a radiation-resistant reinforced frequency and phase detector circuit. Background Art

[0002] Contemporary microelectronics processes follow the development of Moore's Law. Microelectronic systems are also designed using more advanced CMOS process nodes, which enables the operating frequency of microelectronic systems to increase rapidly and digital circuit systems to run at higher speeds. However, the correct operation of digital circuits depends largely on the availability of clear and uninterrupted clock signals. Temporary interruptions to the clock may also have catastrophic consequences and may lead to loss of circuit function. Since clock signals in large microelectronic systems are usually system hierarchical structures with multiple levels of distribution, a single clock source may drive hundreds or thousands of downstream circuits. Microelectronic systems continue to put forward higher requirements for the performance of clock generation circuits.

[0003] Phase-locked loop circuits are basic circuits for clock synthesis and data recovery circuits, and play a core role in most electronic systems. Phase-locked loop circuits may enter harsh working environments, such as in the aerospace field. In such environments, due to the influence of space radiation on spacecraft electronic equipment, their working life may be greatly shortened, and even lead to the failure of space missions.

[0004] As the functions and scale of equipment continue to expand, power supplies decrease, and frequencies increase, circuits are easily affected by radiation, such as single-event effects (SEE), total ionizing dose (TID), etc. Therefore, it is necessary to design radiation-hardened circuits that have been used so far to avoid harmful effects caused by radiation. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a frequency and phase detector circuit with radiation resistance reinforcement, thereby realizing the radiation resistance reinforcement design of the frequency and phase detector circuit.

[0006] The technical solution adopted by the present invention to solve the technical problem is: to provide a radiation-resistant reinforced frequency and phase detector circuit, including: a first D flip-flop circuit, a second D flip-flop circuit, a C unit circuit and a frequency lock indication unit circuit; the first D flip-flop circuit and the second D flip-flop circuit have the same structure, both including a first DICE latch circuit and a second DICE latch circuit connected in sequence, the first DICE latch circuit and the second DICE latch circuit are both controlled by a zeroing signal and a clock signal, when the clock signal is at a first level, the input data is transmitted to the output end of the first DICE latch circuit, and when the clock signal is at a second level, the input data is transmitted to the output end of the second The output end of the DICE latch circuit, when the zeroing signal is at the first level, the outputs of the first D flip-flop circuit and the second D flip-flop circuit are at a low level, and when the zeroing signal is at the second level, it has no effect on the first D flip-flop circuit and the second D flip-flop circuit; the two input ends of the C unit circuit are respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output signal of the C unit circuit is fed back to the first D flip-flop circuit and the second D flip-flop circuit as the zeroing signal; the input end of the frequency lock indication unit circuit is respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output end outputs a frequency lock indication signal.

[0007] The first DICE latch circuit and the second DICE latch circuit both include an inverter, a first transmission gate, a second transmission gate and a DICE structure, wherein the input end of the inverter is connected to the input data, and the output end is respectively connected to the input end of the first transmission gate and the input end of the second transmission gate; the DICE structure includes a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MP6, a transistor MP7, a transistor MP8, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MN5, a transistor MN6, a transistor MN7 and a transistor MN8; the gate of the transistor MP1 is connected to the DICE structure. The output end of the CE structure is connected, the source is connected to the voltage end, the drain is connected to the source of the transistor MP2, the gate of the transistor MP2 is connected to the first control signal, and the drain is connected to the output end of the second transmission gate; the gate of the transistor MP3 is connected to the output end of the second transmission gate, the source is connected to the voltage end, and the drain is connected to the drain of the transistor MP4; the gate of the transistor MP4 is connected to the zeroing signal, and the drain is connected to the drain of the transistor MN4; the gate of the transistor MP5 is connected to the drain of the transistor MP4, the source is connected to the voltage end, and the drain is connected to the source of the transistor MP6; the gate of the transistor MP6 is connected to the first control signal, and the drain is connected to the output end of the second transmission gate; The gate of the transistor MP7 is connected to the output end of the first transmission gate, the source is connected to the voltage terminal, and the drain is connected to the source of the transistor MP8; the gate of the transistor MP8 is connected to the zeroing signal, and the drain is connected to the drain of the transistor MN8, serving as the output end of the DICE structure; the gate of the transistor MN1 is connected to the second control signal, the source is connected to the drain of the transistor MN2, and the drain is connected to the output end of the second transmission gate; the gate of the transistor MN2 is connected to the drain of the transistor MN3, and the source is grounded; the gate of the transistor MN3 is connected to the zeroing signal , the source is grounded; the gate of the transistor MN4 is connected to the output end of the first transmission gate, and the source is grounded; the gate of the transistor MN5 is connected to the second control signal, the drain is connected to the output end of the first transmission gate, and the source is connected to the drain of the transistor MN6; the gate of the transistor MN6 is connected to the drain of the transistor MN7, and the source is grounded; the gate of the transistor MN7 is connected to the zeroing signal, the source is grounded, and the drain is connected to the drain of the transistor MN8; the gate of the transistor MN8 is connected to the output end of the first transmission gate, and the source is grounded; the first control end of the first transmission gate is connected to the second control signal, and the second control end is connected to the first control signal.

[0008] The first control signal in the first DICE latch circuit is an inverted clock signal, and the second control signal is a full-wave clock signal; the first control signal in the second DICE latch circuit is a full-wave clock signal, and the second control signal is an inverted clock signal.

[0009] The inverted clock signal is obtained by passing the clock signal through an inverter, and the rectified clock signal is obtained by passing the inverted clock signal through an inverter.

[0010] The C unit circuit includes a C unit part, a data holding part and a delay device. The C unit part includes a transistor MP34, a transistor MP35, a transistor MN33 and a transistor MN34; the gate of the transistor MP34 is connected to the output end of the first D flip-flop circuit, the source is connected to the voltage end, and the drain is connected to the source of the transistor MP35; the gate of the transistor MP35 is connected to the output end of the second D flip-flop circuit, the drain is connected to the drain of the transistor MN33, and serves as the output of the C unit part; the gate of the transistor MN33 is connected to the output end of the second D flip-flop circuit, the drain is connected to the drain of the transistor MN33, and serves as the output of the C unit part; the gate of the transistor MN33 is connected to the second D flip-flop circuit. The output end of the trigger circuit is connected, and the source is connected to the drain of the transistor MN34; the gate of the transistor MN34 is connected to the output end of the first D trigger circuit, and the source is grounded; the data maintenance part includes a transistor MP33 and a maintenance inverter, the input end of the maintenance inverter is connected to the output of the C unit part, and the output end is connected to the gate of the transistor MP33; the source of the transistor MP33 is connected to the voltage end, and the drain is connected to the input end of the maintenance inverter; the input end of the delay device is connected to the output end of the maintenance inverter, and the output end serves as the zeroing signal.

[0011] The frequency lock indication unit circuit includes a first Schmitt trigger, a second Schmitt trigger, a NAND gate, a transistor MN35, a capacitor and a buffer. The input end of the first Schmitt trigger is connected to the output end of the first D flip-flop circuit, the input end of the second Schmitt trigger is connected to the output end of the second D flip-flop circuit, the two input ends of the NAND gate are respectively connected to the output end of the first Schmitt trigger and the output end of the second Schmitt trigger, the output end is connected to the gate of the transistor MN35, the source of the transistor MN35 is grounded, the drain is connected to the current source, the capacitor is also connected in parallel between the source and drain of the transistor MN35, the drain of the transistor MN35 is also connected to the input end of the buffer, and the output end of the buffer serves as the output of the frequency and phase detector circuit.

[0012] Beneficial Effects

[0013] Due to the adoption of the above-mentioned technical scheme, the present invention has the following advantages and positive effects compared with the prior art: the present invention adopts a D flip-flop with zeroing and clock control functions and a C unit circuit with a data holding structure to realize the radiation-resistant reinforcement design of the frequency detector and phase detector circuit, thereby being able to perform radiation shielding on the potential of each storage node and the output signal in the frequency detector and avoiding the harmful effects caused by the radiation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the basic components of a phase-locked loop;

[0015] Figure 2 is a block diagram of a radiation hardened phase frequency detector circuit according to an embodiment of the present invention;

[0016] Figure 3 is a circuit diagram of a first D flip-flop and a second D flip-flop in an embodiment of the present invention;

[0017] Figure 4 is a circuit diagram of a first DICE latch circuit and a second DICE latch circuit in an embodiment of the present invention;

[0018] Figure 5 is a circuit diagram of a C unit circuit in an embodiment of the present invention;

[0019] Figure 6 is a circuit diagram of a frequency lock indication unit circuit in an embodiment of the present invention;

[0020] Figure 7 Schematic representation of the truth value of the C unit circuit in the embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0022] Embodiments of the present invention relate to a radiation hardened phase frequency detector circuit, which can be applied to Figure 1 In the phase-locked loop shown, the frequency detector circuit is a digital circuit module that is more sensitive to the radiation environment among all the modules of the phase-locked loop. It is necessary and important to carry out radiation hardening design on it, which can improve the competitiveness of related products containing radiation hardened phase-locked loop circuits in the high-performance chip product market.

[0023] like Figure 2As shown, the radiation-hardened frequency detector circuit of this embodiment includes a first D flip-flop circuit, a second D flip-flop circuit, a C unit circuit and a frequency lock indication unit circuit. The two input ends of the C unit circuit are respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output signal of the C unit circuit is fed back to the first D flip-flop circuit and the second D flip-flop circuit as a zeroing signal; the input end of the frequency lock indication unit circuit is respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output end outputs a frequency lock indication signal.

[0024] like Figure 3 As shown, the first D flip-flop circuit and the second D flip-flop circuit have the same structure, and both include a first DICE latch circuit and a second DICE latch circuit connected in sequence. In this embodiment, the first DICE latch circuit and the second DICE latch circuit are both controlled by a reset signal (RESET) and a clock signal. When the clock signal is at a first level, the input data is transmitted to the output end of the first DICE latch circuit. When the clock signal is at a second level, the input data is transmitted to the output end of the second DICE latch circuit. When the reset signal is at a first level, the outputs of the first D flip-flop circuit and the second D flip-flop circuit are at a low level. When the reset signal is at a second level, the first D flip-flop circuit and the second D flip-flop circuit have no effect.

[0025] In this embodiment, the first DICE latch circuit and the second DICE latch circuit have the same structure. Figure 4As shown, it includes an inverter INV1, a first transmission gate TG1, a second transmission gate TG2 and a dual interlocked storage cell (DICE) structure, wherein the input end of the inverter INV1 is connected to the input data Data, and the output end is respectively connected to the input end of the first transmission gate TG1 and the input end of the second transmission gate TG2; the DICE structure includes transistors MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MN1, MN2, MN3, MN4, MN5, MN6, MN7 and MN8; the gate of the transistor MP1 is connected to the output end of the DICE structure, and the source is connected to the voltage terminal VDD, the drain is connected to the source of the transistor MP2, the gate of the transistor MP2 is connected to the first control signal, and the drain is connected to the output end of the second transmission gate TG2; the gate of the transistor MP3 is connected to the output end of the second transmission gate TG2, the source is connected to the voltage terminal VDD, and the drain is connected to the drain of the transistor MP4; the gate of the transistor MP4 is connected to the zeroing signal, and the drain is connected to the drain of the transistor MN4; the gate of the transistor MP5 is connected to the drain of the transistor MP4, the source is connected to the voltage terminal VDD, and the drain is connected to the source of the transistor MP6; the gate of the transistor MP6 is connected to the output end of the second transmission gate TG2, the source is connected to the voltage terminal VDD, and the drain is connected to the drain of the transistor MP4; The gate of the transistor MP7 is connected to the output end of the first transmission gate TG1, the source is connected to the voltage terminal, and the drain is connected to the source of the transistor MP8; the gate of the transistor MP8 is connected to the zeroing signal, the drain is connected to the drain of the transistor MN8, and serves as the output end of the DICE structure; the gate of the transistor MN1 is connected to the second control signal, the source is connected to the drain of the transistor MN2, and the drain is connected to the output end of the second transmission gate TG2; the gate of the transistor MN2 is connected to the drain of the transistor MN3 ... ground; the gate of the transistor MN3 is connected to the zeroing signal, and the source is grounded; the gate of the transistor MN4 is connected to the output end of the first transmission gate TG1, and the source is grounded; the gate of the transistor MN5 is connected to the second control signal, the drain is connected to the output end of the first transmission gate TG1, and the source is connected to the drain of the transistor MN6; the gate of the transistor MN6 is connected to the drain of the transistor MN7, and the source is grounded; the gate of the transistor MN7 is connected to the zeroing signal, the source is grounded, and the drain is connected to the drain of the transistor MN8; the gate of the transistor MN8 is connected to the output end of the first transmission gate TG1, and the source is grounded;The first control terminal of the first transmission gate TG1 is connected to the second control signal, and the second control terminal is connected to the first control signal.

[0026] like Figure 3 As shown, in this embodiment, the first control signal in the first DICE latch circuit is the inverted clock signal CLKn, and the second control signal is the rectified clock signal CLKa; the first control signal in the second DICE latch circuit is the rectified clock signal CLKa, and the second control signal is the inverted clock signal CLKn. The inverted clock signal CLKn is obtained by passing the clock signal CLK through an inverter, and the rectified clock signal CLKa is obtained by passing the inverted clock signal CLKn through an inverter.

[0027] When the clock signal CLK is at a high level "1", the inverted clock signal CLKn is at a low level "0", the rectified clock signal CLKa is at a high level "1", the transmission gate TG3 and the transmission gate TG4 are turned on, the transmission gates TG1 and TG2 are turned off, the transistors MP10, MP14, MN9 and MN13 are turned on, the transistors MP2, MP6, MN1 and MN5 are turned off, and the input signals are respectively transmitted to the front of the transmission gates TG3 and TG4; when the clock signal CLK is at a low level "0", the inverted clock signal CLKn is at a high level "1", the rectified clock signal CLKa is at a low level "0", the transmission gates TG1 and TG2 are turned on, the transmission gates TG3 and TG4 are turned off, the transistors MP2, MP6, MN1 and MN5 are turned on, the transistors MP10, MP14, MN9 and MN13 are turned off, and the input signals are respectively transmitted to the output ends of the D flip-flop.

[0028] When the Reset signal is at a high level "1", transistors MN3, MN7, MN11 and MN15 are turned on, and transistors MP4, MP8, MP12 and MP16 are turned off. Regardless of whether the input signal at the input end of the D flip-flop is at a high level "1" or a low level "0", the output signal at the output end is at a low level "0". At this time, the Reset end is effective, and the PMOS transistor and the NMOS transistor will not be turned on at the same time, thereby avoiding excessive current in the circuit; when the Reset signal is at a low level "0", transistors MP4, MP8, MP12 and MP16 are turned on, and transistors MN3, MN7, MN11 and MN15 are turned off. At this time, the Reset end has no effect on the circuit.

[0029] like Figure 5 As shown, the C unit circuit includes a C unit part, a data holding part and a delay device.

[0030] Among them, the C unit part includes transistor MP34, transistor MP35, transistor MN33 and transistor MN34; the gate of the transistor MP34 is connected to the output end of the first D flip-flop circuit, the source is connected to the voltage end, and the drain is connected to the source of the transistor MP35; the gate of the transistor MP35 is connected to the output end of the second D flip-flop circuit, the drain is connected to the drain of the transistor MN33, and serves as the output of the C unit part; the gate of the transistor MN33 is connected to the output end of the second D flip-flop circuit, and the source is connected to the drain of the transistor MN34; the gate of the transistor MN34 is connected to the output end of the first D flip-flop circuit, and the source is grounded.

[0031] The gates of transistor MP35 and transistor MN33 in the C unit part are connected together, and the gates of transistor MP34 and transistor MN34 are connected together, respectively receiving the output signal Up of the first D flip-flop and the output signal Down of the second D flip-flop; the output signal of the C unit part is output from the drain node connected to transistor MP35 and transistor MN33.

[0032] The data maintenance part includes a transistor MP33 and a maintenance inverter INV9, the gate of the transistor MP33 is connected to the output end of the maintenance inverter INV9, and the drain of the transistor MP33 is connected to the input end of the maintenance inverter INV9, forming a feedback loop connected in parallel with the maintenance inverter INV9. The output of the C unit part is output through the output end of the maintenance inverter INV9, and then input to the delay device, and the output of the delay device is used as a zeroing signal.

[0033] When the output signal Up of the first D flip-flop and the output signal Down of the second D flip-flop are at the same level, the C unit part functions as a NOT gate. When the output signal Up of the first D flip-flop and the output signal Down of the second D flip-flop are both at a high level "1", the output signal of the C unit part is at a low level "0"; when the output signal Up of the first D flip-flop and the output signal Down of the second D flip-flop are both at a low level "0", the output signal of the C unit part is at a high level "1"; when the output signal Up of the first D flip-flop and the output signal Down of the second D flip-flop are at different levels, the output signal of the C unit part maintains the previous state. The output signal of the C unit part is fed back to the first D flip-flop circuit and the second D flip-flop circuit as a Reset signal after passing through an inverter INV9 and a delay device. Figure 2As shown in FIG. 1 , when the Reset signal is at a high level "1", transistors MN6 and MN13 are turned on, and the output signal of the D flip-flop circuit becomes a low level "0"; when the Reset signal is at a low level "0", transistors MN6 and MN13 are turned off, and the output signal of the D flip-flop circuit is not affected. The truth table of the C unit circuit in this embodiment is as follows: Figure 7 shown.

[0034] like Figure 6 As shown, the frequency lock indication unit circuit in this embodiment includes a first Schmitt trigger Schmitt trigger 1, a second Schmitt trigger Schmitt trigger 2, a NAND gate Nand2, a transistor MN35, a capacitor C1 and a buffer Buffer. The input end of the first Schmitt trigger Schmitt trigger 1 is connected to the output end of the first D flip-flop circuit, the input end of the second Schmitt trigger Schmitt trigger 2 is connected to the output end of the second D flip-flop circuit, the two input ends of the NAND gate Nand2 are respectively connected to the output end of the first Schmitt trigger Schmitt trigger 1 and the output end of the second Schmitt trigger Schmitt trigger 2, the output end is connected to the gate of the transistor MN35, the source of the transistor MN35 is grounded, and the drain is connected to the current source I CP The capacitor C1 is also connected in parallel between the source and drain of the transistor MN35, the drain of the transistor MN35 is also connected to the input end of the buffer Buffer, and the output end of the buffer Buffer serves as the output of the frequency and phase detector circuit.

[0035] The output signal Up of the first D flip-flop circuit and the output signal Down of the second D flip-flop circuit are respectively input into the first Schmitt trigger 1 and the second Schmitt trigger 2 to obtain the output signal Upn and the output signal Downn, which are then input into the NAND gate Nand2. The output end of the NAND gate Nand2 is connected to the gate of the transistor MN35 to control the on or off of the transistor MN35. When the transistor MN35 is turned on, the current source I CP The current source I completely flows into the transistor MN35 and does not charge the capacitor C1, so the output signal PFD_Lock of the frequency lock indication unit circuit is low level "0", which means that the signal is not locked; when the transistor MN35 is turned off, the current source I CP The capacitor C1 is charged, so the output signal PFD_Lock of the frequency lock indication unit circuit is a high level "1", indicating that the signal is locked.

[0036] It is not difficult to find that the radiation-resistant reinforcement design of the present invention adopts an improved DICE structure, and multiple DICE structures and C unit structures are used in the D flip-flop, which increases the redundancy of the circuit, thereby improving the stability of the circuit when it is exposed to radiation, and can effectively resist SEE, and prevent any node from being affected by radiation and causing the output to flip. The output signal of the frequency detector and phase detector affected by radiation is then shielded by the C unit, and finally the output level PFD_Lock is used as a frequency lock indication signal, completing the radiation-resistant reinforcement of the frequency detector and phase detector.

Claims

1. A radiation-hardened phase frequency detector circuit, characterized in that: include: A first D flip-flop circuit, a second D flip-flop circuit, a C unit circuit and a frequency lock indication unit circuit; The first D flip-flop circuit and the second D flip-flop circuit have the same structure, and both include a first DICE latch circuit and a second DICE latch circuit connected in sequence. The first DICE latch circuit and the second DICE latch circuit are both controlled by a zeroing signal and a clock signal. When the clock signal is at a first level, the input data is transmitted to the output end of the first DICE latch circuit. When the clock signal is at a second level, the input data is transmitted to the output end of the second DICE latch circuit. When the zeroing signal is at a first level, the outputs of the first D flip-flop circuit and the second D flip-flop circuit are low levels. When the zeroing signal is at a second level, the first D flip-flop circuit and the second D flip-flop circuit have no effect. The two input ends of the C unit circuit are respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output signal of the C unit circuit is fed back to the first D flip-flop circuit and the second D flip-flop circuit as the zeroing signal. The input end of the frequency lock indication unit circuit is respectively connected to the output ends of the first D flip-flop circuit and the second D flip-flop circuit, and the output end outputs a frequency lock indication signal.

2. The radiation hardened phase frequency detector circuit according to claim 1, characterized in that: The first DICE latch circuit and the second DICE latch circuit both include an inverter, a first transmission gate, a second transmission gate and a DICE structure, wherein the input end of the inverter is connected to the input data, and the output end is respectively connected to the input end of the first transmission gate and the input end of the second transmission gate; the DICE structure includes a transistor MP1, a transistor MP2, a transistor MP3, a transistor MP4, a transistor MP5, a transistor MP6, a transistor MP7, a transistor MP8, a transistor MN1, a transistor MN2, a transistor MN3, a transistor MN4, a transistor MN5, a transistor MN6, a transistor MN7 and a transistor MN8; the gate of the transistor MP1 is connected to the DICE structure. The output end of the CE structure is connected, the source is connected to the voltage end, the drain is connected to the source of the transistor MP2, the gate of the transistor MP2 is connected to the first control signal, and the drain is connected to the output end of the second transmission gate; the gate of the transistor MP3 is connected to the output end of the second transmission gate, the source is connected to the voltage end, and the drain is connected to the drain of the transistor MP4; the gate of the transistor MP4 is connected to the zeroing signal, and the drain is connected to the drain of the transistor MN4; the gate of the transistor MP5 is connected to the drain of the transistor MP4, the source is connected to the voltage end, and the drain is connected to the source of the transistor MP6; the gate of the transistor MP6 is connected to the first control signal, and the drain is connected to the output end of the second transmission gate; The gate of the transistor MP7 is connected to the output end of the first transmission gate, the source is connected to the voltage terminal, and the drain is connected to the source of the transistor MP8; the gate of the transistor MP8 is connected to the zeroing signal, and the drain is connected to the drain of the transistor MN8, serving as the output end of the DICE structure; the gate of the transistor MN1 is connected to the second control signal, the source is connected to the drain of the transistor MN2, and the drain is connected to the output end of the second transmission gate; the gate of the transistor MN2 is connected to the drain of the transistor MN3, and the source is grounded; the gate of the transistor MN3 is connected to the zeroing signal , the source is grounded; the gate of the transistor MN4 is connected to the output end of the first transmission gate, and the source is grounded; the gate of the transistor MN5 is connected to the second control signal, the drain is connected to the output end of the first transmission gate, and the source is connected to the drain of the transistor MN6; the gate of the transistor MN6 is connected to the drain of the transistor MN7, and the source is grounded; the gate of the transistor MN7 is connected to the zeroing signal, the source is grounded, and the drain is connected to the drain of the transistor MN8; the gate of the transistor MN8 is connected to the output end of the first transmission gate, and the source is grounded; the first control end of the first transmission gate is connected to the second control signal, and the second control end is connected to the first control signal.

3. The radiation hardened phase frequency detector circuit according to claim 2, characterized in that: The first control signal in the first DICE latch circuit is an inverted clock signal, and the second control signal is a full-wave clock signal; the first control signal in the second DICE latch circuit is a full-wave clock signal, and the second control signal is an inverted clock signal.

4. The radiation hardened phase frequency detector circuit according to claim 3, characterized in that: The inverted clock signal is obtained by passing the clock signal through an inverter, and the rectified clock signal is obtained by passing the inverted clock signal through an inverter.

5. The radiation hardened phase frequency detector circuit according to claim 1, characterized in that: The C unit circuit includes a C unit part, a data holding part and a delay device. The C unit part includes a transistor MP34, a transistor MP35, a transistor MN33 and a transistor MN34; the gate of the transistor MP34 is connected to the output end of the first D flip-flop circuit, the source is connected to the voltage end, and the drain is connected to the source of the transistor MP35; the gate of the transistor MP35 is connected to the output end of the second D flip-flop circuit, the drain is connected to the drain of the transistor MN33, and serves as the output of the C unit part; the gate of the transistor MN33 is connected to the output end of the second D flip-flop circuit, the drain is connected to the drain of the transistor MN33, and serves as the output of the C unit part; the gate of the transistor MN33 is connected to the second D flip-flop circuit. The output end of the trigger circuit is connected, and the source is connected to the drain of the transistor MN34; the gate of the transistor MN34 is connected to the output end of the first D trigger circuit, and the source is grounded; the data maintenance part includes a transistor MP33 and a maintenance inverter, the input end of the maintenance inverter is connected to the output of the C unit part, and the output end is connected to the gate of the transistor MP33; the source of the transistor MP33 is connected to the voltage end, and the drain is connected to the input end of the maintenance inverter; the input end of the delay device is connected to the output end of the maintenance inverter, and the output end serves as the zeroing signal.

6. The radiation hardened phase frequency detector circuit according to claim 1, characterized in that: The frequency lock indication unit circuit includes a first Schmitt trigger, a second Schmitt trigger, a NAND gate, a transistor MN35, a capacitor and a buffer. The input end of the first Schmitt trigger is connected to the output end of the first D flip-flop circuit, the input end of the second Schmitt trigger is connected to the output end of the second D flip-flop circuit, the two input ends of the NAND gate are respectively connected to the output end of the first Schmitt trigger and the output end of the second Schmitt trigger, the output end is connected to the gate of the transistor MN35, the source of the transistor MN35 is grounded, the drain is connected to the current source, the capacitor is also connected in parallel between the source and drain of the transistor MN35, the drain of the transistor MN35 is also connected to the input end of the buffer, and the output end of the buffer serves as the output of the frequency and phase detector circuit.

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