Data processing method, data processing module, device, equipment, chip and medium

Abstract

The invention provides a data processing method, a data processing module, a data processing device, equipment, a chip and a medium, and relates to the technical field of data processing. Comprising the following steps: if a data reading instruction for a read-only memory (ROM) is obtained, obtaining a first address from the data reading instruction; matching the first address with a replacement address in a register; and under the condition that any replacement address is matched with the first address, determining replacement data corresponding to any replacement address and stored in the register as target data of the data reading instruction. Therefore, the address of the data needing to be modified in the ROM and the replacement data are stored in the register associated with the ROM, so that under the condition that the first address in the data reading instruction is detected to be matched with any replacement address in the register, the replacement data in the register is used as the target data, the data stored in the ROM does not need to be modified, and the data reading efficiency is improved. The error data in the ROM is indirectly modified, and the timeliness and efficiency of modifying the error data in the ROM are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data processing method, a data processing module, a device, an equipment, a chip and a medium. Background Art

[0002] Read-Only Memory (ROM) is a non-volatile memory device. The content stored in ROM is available when the system is powered on, without the need for additional loading operations. Therefore, the processor used for system startup and the initialization program executed after power-on are generally stored in ROM. However, ROM has the characteristic of being unchangeable. Once produced, its content cannot be changed. Therefore, if there is an error in the initialization program in the chip's ROM, how to modify the error program so that the processor executes the correct initialization program has become a key research direction. Summary of the invention

[0003] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0004] The first embodiment of the present disclosure provides a data processing method, including:

[0005] When a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction;

[0006] matching the first address with a replacement address in a register;

[0007] In the case where any replacement address matches the first address, the replacement data corresponding to the any replacement address stored in the register is determined as the target data of the read instruction.

[0008] The second aspect of the present disclosure provides a data processing method, including:

[0009] Acquire a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in the ROM;

[0010] The replacement address and the replacement data are stored in registers associated with the ROM.

[0011] The third aspect of the present disclosure provides a data processing module, including: a register, a hit judgment module, and a selector;

[0012] The register is used to store the replacement address and the replacement data corresponding to the replacement address;

[0013] The hit judgment module is used for obtaining a first address from the read instruction when a data read instruction for the read-only memory ROM is obtained, matching the first address with the replacement address in the register to obtain a matching result, and sending the matching result to the selector;

[0014] The selector is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the read instruction when the matching result indicates that any replacement address matches the first address.

[0015] A fourth aspect of the present disclosure provides a data processing device, including:

[0016] An acquisition module, configured to acquire a first address from a data read instruction for a read-only memory ROM when the data read instruction for the read-only memory ROM is acquired;

[0017] a matching module, configured to match the first address with a replacement address in a register;

[0018] A determination module is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the read instruction when any replacement address matches the first address.

[0019] A fifth aspect of the present disclosure provides a data processing device, including:

[0020] An acquisition module, configured to acquire a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in the ROM;

[0021] The processing module is used for storing the replacement address and the replacement data in a register associated with the ROM.

[0022] The sixth aspect embodiment of the present disclosure proposes an electronic device, comprising: a data processing module, a processor, and a ROM, wherein the data processing module is configured to execute the data processing method proposed in the first aspect embodiment, and the processor is configured to execute the data processing method proposed in the second aspect embodiment.

[0023] The seventh aspect embodiment of the present disclosure proposes a chip, which includes a data processing module, a processor, and a ROM. The data processing module is configured to execute the data processing method proposed in the first aspect embodiment, and the processor is configured to execute the data processing method proposed in the second aspect embodiment.

[0024] The eighth aspect embodiment of the present disclosure proposes a computer-readable storage medium, and when the computer program is executed by a data processing module, it implements the data processing method proposed in the first aspect embodiment, or when the computer program is executed by a processor, it implements the data processing method proposed in the second aspect embodiment.

[0025] The data processing method, data processing module, device, equipment, chip and medium provided by the present disclosure have the following beneficial effects:

[0026] In the disclosed embodiment, when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction, and then the first address is matched with a replacement address in a register, and when any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the read instruction. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data can be stored in a register associated with the ROM, so that when it is detected that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, without modifying the data stored in the ROM, thereby indirectly realizing the modification of the erroneous data in the ROM, and improving the timeliness and efficiency of modifying the erroneous data in the ROM.

[0027] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 A flowchart of a data processing method provided by an embodiment of the present disclosure;

[0030] Figure 2 A flowchart of a data processing method provided by another embodiment of the present disclosure;

[0031] Figure 3 A flowchart of a data processing method provided by an embodiment of the present disclosure;

[0032] Figure 4 A flowchart of a data processing method provided by another embodiment of the present disclosure;

[0033] Figure 5 An interactive schematic diagram of a data processing method provided by an embodiment of the present disclosure;

[0034] Figure 6 A schematic diagram of the structure of a data processing module provided in one embodiment of the present disclosure;

[0035] Figure 7 A schematic diagram of the structure of another data processing module provided in one embodiment of the present disclosure;

[0036] Figure 8 A schematic diagram of the structure of a data processing device provided by an embodiment of the present disclosure;

[0037] Fig. 9 A schematic diagram of the structure of a data processing device provided by an embodiment of the present disclosure;

[0038] Fig.10 A block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown;

[0039] Fig.11 A schematic diagram of the structure of a chip proposed in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0041] The data processing method, data processing module, device, equipment, chip and medium of the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0042] In the related art, if an error is found in the initialization instruction, it can be repaired through an additional mechanism, which is generally called a ROM patch.

[0043] First, the mechanism sets up a storage body (Patch memory) to store replacement instructions. Second, the mechanism sets up two register groups. The first register group records the storage address of the old instructions that need to be replaced in the ROM; the second register group records the address of the new instructions corresponding to each old instruction that needs to be replaced in the Patch memory. Third, the mechanism sets up a breakpoint detector module to monitor the current execution instruction address when the processor executes instructions. Once the current execution instruction address matches the address recorded in the first register group, a breakpoint interrupt is generated. Fourth, the breakpoint interrupt prompts the processor to enter the corresponding interrupt handler. In the handler, the current execution instruction address is modified to the replacement address recorded in the second register group, pointing to the Patch memory. Finally, the processor exits the interrupt handler, jumps out of the original ROM, and starts executing instructions in the Patch memory.

[0044] The above ROM patch mechanism needs to interrupt the current instruction flow and execute the replacement instruction after at least two jumps, which is inefficient and modifies the execution logic of the processor. It is necessary to modify the instruction execution unit inside the processor, which is highly complex.

[0045] It should be noted that after the device is powered on, the processor will read the initialization program from the ROM to initialize the device. In the disclosed embodiment, a data processing module is integrated at the read-write interface of the ROM, so that the processor first sends a data read instruction for reading the initialization program from the ROM to the data processing module, and the data processing module matches the first address in the data read instruction with the replacement address in the register of the data processing module, and then when any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction, and returned to the processor. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data are stored in the register associated with the ROM, so that when it is detected that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, without changing the data stored in the ROM, and indirectly realizing the modification of the erroneous data in the ROM, thereby improving the timeliness and efficiency of the modification of the erroneous data in the ROM.

[0046] Figure 1 The following is a flow chart of a data processing method provided by an embodiment of the present disclosure. Figure 1As shown, the data processing method is executed by a data processing module, the data processing module can be integrated at the read-write interface of the ROM, the data processing module includes a register, and can include the following steps:

[0047] Step 101 : when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction.

[0048] The data reading instruction for the ROM may be an instruction sent by the processor for reading data from the ROM.

[0049] The first address is an address in the ROM for storing the initialization program.

[0050] The data read instruction is used to read data from the ROM based on the first address.

[0051] The data stored in the ROM is the initialization program required for device initialization.

[0052] Step 102, matching the first address with the replacement address in the register.

[0053] Among them, the register is a register in the data processing module.

[0054] The replacement address is the storage address corresponding to the data to be replaced in the ROM.

[0055] In some embodiments, the register may include one or more replacement addresses, which is not limited in the present disclosure.

[0056] In some embodiments, the first address is matched with each replacement address to obtain a matching result, wherein the matching result includes a match and a mismatch. When the comparison result between any replacement address and the first address matches, the matching can be stopped, thereby saving computing resources and improving matching efficiency.

[0057] Wherein, if any replacement address is the same as the first address, the matching result between any replacement address and the first address is determined to be a match. If any replacement address is different from the first address, the matching result between any replacement address and the first address is determined to be a mismatch.

[0058] In some embodiments, the priority corresponding to each data to be replaced can be determined according to the order of the data to be replaced in the initialization program. Then, the priority corresponding to each data to be replaced is determined as the priority corresponding to the storage address (i.e., replacement address) of each data to be replaced in the ROM, and then, based on the priority corresponding to each replacement address, each replacement address is stored in the register in sequence. Therefore, when matching the first address with the replacement address, the replacement address stored in the register can be matched with the first address based on the priority corresponding to the replacement address to obtain a matching result.

[0059] Furthermore, after obtaining the first first address, the first first address is first matched with the replacement address with the highest priority in the register. If the match succeeds, after obtaining the second first address, the second first address is sequentially matched with other replacement addresses except the replacement address with the highest priority based on the priority of the replacement address. This can reduce the workload of matching and improve matching efficiency.

[0060] Step 103: When any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction.

[0061] In some embodiments, the register stores not only the replacement address but also the replacement data corresponding to the replacement address.

[0062] In some embodiments, the replacement data corresponding to any replacement address may be any of the following:

[0063] a replacement instruction corresponding to the instruction stored at the first address in the ROM;

[0064] A jump instruction, wherein the jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored at the first address in the ROM.

[0065] The replacement instruction corresponding to the instruction stored at the first address in the ROM may be a new initialization instruction corresponding to the old initialization instruction stored at the first address after being modified.

[0066] In some embodiments, the replacement instruction corresponding to the instruction stored at the first address in the ROM may be one or more replacement instructions, which is not limited in the present disclosure.

[0067] In some embodiments, the jump address may be one or more than one, or may include a start address and an end address, which is not limited in the present disclosure.

[0068] In some embodiments, the jump address may be an address in a random access memory (RAM). It may also be an address in other memories in the device, such as a dynamic random access memory (DRAM). The present disclosure does not limit this.

[0069] In the disclosed embodiment, the replacement instruction corresponding to the instruction to be replaced stored in the ROM replacement address can be directly stored in the register, so that the replacement instruction corresponding to the replacement address can be directly obtained from the register. The replacement instruction can also be stored in other memories, and the corresponding jump instruction is stored in the register, so that the jump instruction can be obtained from the register, and then the replacement instruction can be obtained according to the jump address in the jump instruction.

[0070] In some embodiments, if the number of replacement instructions corresponding to an old instruction in the initialization program is small (for example, 1, 2, etc.), the storage address of the old instruction in the ROM (i.e., the replacement address) and the replacement instruction can be stored in a register, so that the replacement instruction corresponding to the replacement address can be directly obtained from the register, thereby improving efficiency.

[0071] In some embodiments, if the number of replacement instructions corresponding to an old instruction in the initialization program is large (for example, 10, 20, etc.), the replacement instruction can be stored in other memories (such as RAM, DRAM, etc.), and a jump instruction is generated according to the storage address of the replacement instruction in the other memory, and the jump instruction and the storage address of the old instruction in the ROM (i.e., the replacement address) are stored in a register. Thus, when there are many replacement instructions, the replacement instruction can be stored in other memories, and then jump to other memories to read the replacement instruction, which can save register space and reduce the size of the data processing module.

[0072] In some embodiments, a replacement address and corresponding replacement data are stored in a group of registers. In some embodiments, a group of registers can share an enable switch.

[0073] In the disclosed embodiment, when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction, and then the first address is matched with a replacement address in a register, and when any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data can be stored in a register associated with the ROM, so that when it is detected that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, without modifying the data stored in the ROM, and the modification of the erroneous data in the ROM is indirectly realized, thereby improving the timeliness and efficiency of modifying the erroneous data in the ROM.

[0074] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the data processing method, executed by the data processing module, may include the following steps:

[0075] Step 201: when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction.

[0076] Step 202, matching the first address with the replacement address in the register.

[0077] Step 203: When any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction.

[0078] The specific implementation of steps 201 to 203 can refer to the detailed description in other embodiments of the present disclosure, and will not be described in detail here.

[0079] Step 204 : when all replacement addresses stored in the register do not match the first address, obtain target data of the data read instruction from the ROM based on the first address.

[0080] It should be noted that, when all replacement addresses stored in the register do not match the first address, it means that the instruction stored at the first address in the ROM does not need to be modified. Therefore, there is no replacement address matching the first address in the register, and the instruction stored at the first address in the ROM can be directly determined as the target data read by the data read instruction.

[0081] In the disclosed embodiment, when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction, and then the first address is matched with a replacement address in a register, and when any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction, or when all replacement addresses stored in the register do not match the first address, the target data of the data read instruction is obtained from the ROM based on the first address. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data are stored in the register associated with the ROM, so that when it is detected that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, or when it does not match, the data stored in the ROM is used as the target data, without changing the data stored in the ROM, and indirectly realizing the modification of the erroneous data in the ROM, thereby improving the timeliness and efficiency of the modification of the erroneous data in the ROM.

[0082] Figure 3 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown, which is executed by a processor, such as Figure 3 As shown, the data processing method may include the following steps:

[0083] Step 301, obtaining a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in a ROM.

[0084] The first memory may be a non-volatile memory in a device including a processor. For example, the first memory may be a flash memory, etc., which is not limited in the present disclosure.

[0085] In some embodiments, the old instructions that need to be modified in the initialization program and the replacement instructions corresponding to the old instructions can be determined in advance, and then the storage address of the old instructions in the ROM (i.e., the replacement address) is determined, and the replacement data is generated according to the replacement instruction, and the replacement address and the replacement data corresponding to the replacement address are stored in the first memory. Thus, the replacement address and the replacement data corresponding to the replacement address can be obtained from the first memory.

[0086] In some embodiments, the replacement data may be any of the following:

[0087] The replacement instruction corresponding to the instruction stored at the replacement address in the ROM;

[0088] A jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored in the replacement address in the ROM.

[0089] The replacement instruction corresponding to the instruction stored at the replacement address in the ROM may be a new initialization instruction corresponding to the old initialization instruction stored at the replacement address in the ROM after being modified.

[0090] In some embodiments, the replacement instruction corresponding to the instruction stored at the first address in the ROM may be one or more replacement instructions, which is not limited in the present disclosure.

[0091] In some embodiments, the jump address may be one or more than one, or may include a start address and an end address, which is not limited in the present disclosure.

[0092] In some embodiments, the jump address may be an address in a random access memory (RAM). It may also be an address in other memories in the device, such as a dynamic random access memory (DRAM). The present disclosure does not limit this.

[0093] In some embodiments, if the number of replacement instructions corresponding to an old instruction in the initialization program is small (for example, 1, 2, etc.), the storage address of the old instruction in the ROM (ie, the replacement address) and the replacement instruction can be stored in the first register.

[0094] In some embodiments, if the number of replacement instructions corresponding to an old instruction in the initialization program is large (for example, 10, 20, etc.), the storage address of the replacement instruction in other memories (such as RAM, DRAM, etc.) can be determined, and a jump instruction is generated according to the storage address of the replacement instruction in the other memories, and the jump instruction and the storage address of the old instruction in ROM (i.e., the replacement address) are stored in the first memory. The storage address of the replacement instruction in the other memories can be preset. This disclosure is not limited to this.

[0095] Step 302, store the replacement address and replacement data in a register associated with the ROM.

[0096] The register associated with the ROM may be a register in a data processing module integrated at the ROM read / write interface.

[0097] In some embodiments, a replacement address and corresponding replacement data may be stored in a group of registers in a ROM, which is not limited in the present disclosure.

[0098] In some embodiments, when the replacement data is a jump instruction, the jump address and the replacement instruction associated with the jump address are obtained from the first memory, and the replacement instruction is stored in the jump address of the RAM.

[0099] It should be noted that RAM is a volatile memory, and the data in the RAM will disappear after the device is powered off. Therefore, if the replacement data is a jump instruction, after the device is powered on, it is necessary to obtain the jump address contained in the jump instruction and the replacement instruction associated with the jump address from the first memory, and store the replacement instruction in the jump address of the RAM.

[0100] It should be noted that the register in the data processing module is a volatile memory, and the data in the register will disappear after the device is powered off. Therefore, the replacement address and replacement data need to be stored in a non-volatile memory, so that when the device is initialized, the replacement address and replacement data can be first stored in the register of the data processing module, so that when the data processing module receives a data read instruction, it can determine the target data of the data read instruction based on the data stored in the register and the data stored in the ROM.

[0101] In the disclosed embodiment, the processor obtains the replacement address and the replacement data corresponding to the replacement address from the first memory, wherein the first memory is a non-volatile memory, the replacement address is the storage address corresponding to the data to be replaced in the ROM, and the replacement address and the replacement data are stored in the register associated with the ROM. Thus, the replacement address and the replacement data corresponding to the replacement address are stored in the non-volatile memory, and then the replacement address and the replacement data are copied to the register associated with the ROM, providing data support for the data processing module to match the first address in the data read instruction with the replacement address in the register.

[0102] Figure 4 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown, which is executed by a processor, such as Figure 4 As shown, the data processing method may include the following steps:

[0103] Step 401: When it is detected that the device is powered on, execute a first instruction stored in a first preset address of the ROM to obtain a replacement address and replacement data from a first memory.

[0104] The first preset address is an address in the ROM for storing the first instruction.

[0105] The first instruction may be an instruction in an initialization program for instructing the processor to obtain a replacement address and replacement data from the first memory.

[0106] In some embodiments, the first instruction may include the storage address of the replacement address and the replacement data in the first memory, so that the replacement address and the replacement data may be obtained from the first memory based on the storage address in the first instruction.

[0107] In some embodiments, when it is detected that the device is powered on, a first instruction is obtained from the ROM based on a first preset address, wherein the register does not contain a replacement address that matches the first preset address; the first instruction is executed to obtain the replacement address and replacement data from the first memory.

[0108] It should be noted that after the device is powered on, it needs to start initialization, and the initialization program is stored in the ROM. The register associated with the ROM is a volatile memory. When the device is powered on, the register is empty. Therefore, the register does not contain a replacement address that matches the first preset address. Therefore, the first instruction can be directly obtained from the ROM based on the first preset address.

[0109] Step 402: based on the second preset address, obtain a second instruction from the ROM, wherein the register does not contain a replacement address matching the second preset address.

[0110] The second preset address is an address in the ROM for storing the second instruction.

[0111] The second instruction may be an instruction in the initialization program for instructing the processor to store the replacement address and replacement data obtained from the first memory into the register.

[0112] It should be noted that after the device is powered on, it needs to start initialization, and the initialization program is stored in the ROM. The register associated with the ROM is a volatile memory. When the device is powered on, the register is empty. Therefore, the register does not contain a replacement address that matches the second preset address. Therefore, the second instruction can be directly obtained from the ROM based on the second preset address.

[0113] Step 403, executing the second instruction to store the replacement address and the replacement data in a register associated with the ROM.

[0114] In some embodiments, the second instruction may also be used to indicate how the replacement address and the corresponding replacement data are stored in a register. For example, a replacement address and the corresponding replacement data may be stored in a group of registers in a ROM. This disclosure does not limit this.

[0115] In some embodiments, after the processor obtains the target data of the data read instruction, it can instruct the target data to complete the device initialization.

[0116] In the embodiment of the present disclosure, when it is detected that the device is powered on, the first instruction stored in the first preset address of the ROM is executed to obtain the replacement address and replacement data from the first memory, and based on the second preset address, the second instruction is obtained from the ROM, wherein the register does not contain a replacement address that matches the second preset address, and finally the second instruction is executed to store the replacement address and replacement data in the register associated with the ROM. Thus, the replacement address and the replacement data corresponding to the replacement address are stored in the non-volatile memory, and then after the device is powered on, the replacement address and replacement data are copied to the register associated with the ROM, providing data support for the data processing module to match the first address in the data read instruction with the replacement address in the register, so that each time the device is initialized, the processor can obtain the latest initialization program.

[0117] Figure 5 An interactive schematic diagram of a data processing method provided by an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the data processing method may include the following steps:

[0118] Step 501, when the processor detects that the device is powered on, the processor obtains a first instruction from the ROM based on a first preset address, wherein the register does not contain a replacement address matching the first preset address;

[0119] In step 502, the processor executes a first instruction to obtain a replacement address and replacement data from a first memory.

[0120] Step 503, the processor obtains a second instruction from the ROM based on the second preset address, wherein the register does not contain a replacement address matching the second preset address;

[0121] In step 504, the processor executes a second instruction to store the replacement address and the replacement data in a register associated with the ROM.

[0122] Step 505: The processor sends a data read instruction to the data processing module, wherein the data read instruction includes a first address.

[0123] Step 506: When the data processing module obtains a data read instruction for the read-only memory ROM, the data processing module obtains a first address from the data read instruction.

[0124] Step 507: The data processing module matches the first address with the replacement address in the register.

[0125] Step 508: When any replacement address matches the first address, the data processing module determines the replacement data corresponding to any replacement address stored in the register as the target data of the data read instruction.

[0126] Step 509: The data processing module returns the target data to the processor.

[0127] Step 510: The processor executes the target data.

[0128] In order to implement the above embodiments, the present disclosure also proposes a data processing module.

[0129] Figure 6 This is a schematic diagram of the structure of the data processing module provided in the embodiment of the present disclosure. Figure 6 As shown, the data processing device 600 may include: a register 601, a hit determination module 602, and a selector 603;

[0130] Wherein, register 601 is used to store the replacement address and the replacement data corresponding to the replacement address;

[0131] A hit determination module 602 is used for obtaining a first address from the data read instruction when a data read instruction for the read-only memory ROM is obtained, matching the first address with the replacement address in the register to obtain a matching result, and sending the matching result to the selector;

[0132] The selector 603 is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the data read instruction when the matching result indicates that any replacement address matches the first address.

[0133] In some embodiments, the selector 603 is further used to: when all replacement addresses stored in the register do not match the first address, determine the instruction stored at the first address in the ROM as the target data of the data read instruction.

[0134] Figure 7 FIG. 1 is a schematic diagram of the structure of another data processing module provided in an embodiment of the present disclosure. Figure 7 As shown, the data processing device may include 16 groups of registers 601, each group of registers storing a replacement address, a replacement instruction and an enable switch. The processor may modify the register content through an advanced peripheral bus interface (APB). In some embodiments, a group of registers also includes a check code for the replacement address and the replacement data.

[0135] The hit judgment module 602 in the data processing device can be activated when receiving an activation signal (ROM-CS) from the processor, and then when obtaining a data read instruction sent by the processor, obtain the first address from the data read instruction, obtain the replacement address in the register with the enable signal turned on, match the first address with the replacement address in the register, and send the matching result to the selector. The hit judgment module can read the replacement address from the register by means of a hard-wired signal.

[0136] After receiving the matching result, the selector 603 in the data processing device determines the replacement data corresponding to any replacement address stored in the register as the target data of the data read instruction when the matching result indicates that any replacement address matches the first address, and determines the instruction stored at the first address in the ROM as the target data of the data read instruction when all replacement addresses stored in the register do not match the first address. The selector 603 can read the replacement data from the register by means of a hard-wired signal.

[0137] In the disclosed embodiment, when the hit judgment module in the data processing module obtains the data read instruction for the read-only memory ROM, it obtains the first address from the data read instruction, then matches the first address with the replacement address in the register to obtain the matching result, and sends the matching result to the selector. When any replacement address matches the first address, the selector determines the replacement data corresponding to any replacement address stored in the register as the target data of the data read instruction. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data are stored in the register of the data processing module, so that when the data processing module detects that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, without changing the data stored in the ROM, and indirectly realizes the modification of the erroneous data in the ROM, thereby improving the timeliness and efficiency of the modification of the erroneous data in the ROM.

[0138] In order to implement the above embodiments, the present disclosure also proposes a data processing device.

[0139] Figure 8 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure.

[0140] like Figure 8 As shown, the data processing device 800 is configured in a data processing module and may include:

[0141] The acquisition module 801 is used to acquire a first address from the data read instruction when a data read instruction for a read-only memory ROM is acquired;

[0142] A matching module 802, configured to match the first address with a replacement address in a register;

[0143] The determination module 803 is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the data read instruction when any replacement address matches the first address.

[0144] In some embodiments, the determination module 803 is configured to obtain target data of the data read instruction from the ROM based on the first address when all replacement addresses stored in the register do not match the first address.

[0145] In some embodiments, the replacement data is any of the following:

[0146] a replacement instruction corresponding to the instruction stored at the first address in the ROM;

[0147] A jump instruction, wherein the jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored at the first address in the ROM.

[0148] In some embodiments, the jump address is an address in a random access memory RAM.

[0149] In some embodiments, a replacement address and corresponding replacement data are stored in a set of registers.

[0150] The functions and specific implementation principles of the above modules in the embodiments of the present disclosure can be referred to the above method embodiments, and will not be repeated here.

[0151] In the embodiment of the present disclosure, when a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction, and then the first address is matched with a replacement address in a register, and when any replacement address matches the first address, the replacement data corresponding to any replacement address stored in the register is determined as the target data of the data read instruction. Thus, when the data in the ROM needs to be modified, the address of the data to be modified in the ROM and the replacement data can be stored in a register associated with the ROM, so that when it is detected that the first address in the data read instruction matches any replacement address in the register, the replacement data in the register is directly used as the target data, without changing the data stored in the ROM, and the modification of the erroneous data in the ROM is indirectly realized, thereby improving the timeliness and efficiency of modifying the erroneous data in the ROM.

[0152] Fig. 9 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure.

[0153] like Fig. 9 As shown, the data processing device 900 is configured in a processor and may include:

[0154] The acquisition module 901 is used to acquire a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in the ROM;

[0155] The processing module 902 is used to store the replacement address and the replacement data in a register associated with the ROM.

[0156] In some embodiments, the replacement data is any of the following:

[0157] The replacement instruction corresponding to the instruction stored at the replacement address in the ROM;

[0158] A jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored in the replacement address in the ROM.

[0159] In some embodiments, the jump address is an address in a random access memory RAM, and the device further includes a determination module, which is used to:

[0160] When the replacement data is a jump instruction, obtaining a jump address and a replacement instruction associated with the jump address from the first memory;

[0161] Store the replacement instruction in RAM at the jump address.

[0162] In some embodiments, the acquisition module 901 is used to:

[0163] When it is detected that the device is powered on, a first instruction stored in a first preset address of the ROM is executed to obtain a replacement address and replacement data from the first memory.

[0164] In some embodiments, the processing module 902 is configured to:

[0165] Based on the second preset address, obtaining a second instruction from the ROM, wherein the register does not contain a replacement address that matches the second preset address;

[0166] The second instruction is executed to store the replacement address and the replacement data in the register associated with the ROM.

[0167] The functions and specific implementation principles of the above modules in the embodiments of the present disclosure can be referred to the above method embodiments, and will not be repeated here.

[0168] In the embodiment of the present disclosure, the processor obtains the replacement address and the replacement data corresponding to the replacement address from the first memory, wherein the first memory is a non-volatile memory, the replacement address is the storage address corresponding to the data to be replaced in the ROM, and the replacement address and the replacement data are stored in the register associated with the ROM. Thus, the replacement address and the replacement data corresponding to the replacement address are stored in the non-volatile memory, and then the replacement address and the replacement data are copied to the register associated with the ROM, providing data support for the data processing module to match the first address in the data read instruction with the replacement address in the register.

[0169] In order to implement the above embodiment, the present disclosure also proposes an electronic device, including: a data processing module, a processor, and a ROM, wherein the data processing module is configured to execute Figure 1 and Figure 2 In any data processing method corresponding to the embodiment, the processor is configured to execute Figure 3 and Figure 4 A data processing method corresponding to any embodiment.

[0170] Fig.10 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Fig.10 The electronic device 12 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0171] like Fig.10 As shown, the electronic device 12 is in the form of a general purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processor 16, system memory 28, and bus 18 connecting different system components (including system memory 28 and processor 16).

[0172] The system memory 28 includes a ROM 50 , and a data processing module 51 is disposed at the connection between the ROM and the processor.

[0173] The bus 18 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor or a local bus using any of a variety of bus structures. For example, these architectures include but are not limited to Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MAC) bus, Enhanced ISA bus, Video Electronics Standards Association (VESA) local bus and Peripheral Component Interconnection (PCI) bus.

[0174] The electronic device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0175] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used to read and write non-removable, non-volatile magnetic media ( Fig.10 not shown, usually called a "hard drive"). Although Fig.10 Not shown in the figure, a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a compact disc read only memory (CD-ROM), a digital versatile disc read only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 via one or more data medium interfaces. The memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the various embodiments of the present disclosure.

[0176] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28, such program modules 42 including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0177] The electronic device 12 may also communicate with one or more external devices 14 (e.g., keyboards, pointing devices, displays 24, etc.), may communicate with one or more devices that enable a user to interact with the electronic device 12, and / or may communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (e.g., network cards, modems, etc.). Such communication may be performed via an input / output (I / O) interface 22. Furthermore, the electronic device 12 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 20. As shown, the network adapter 20 communicates with other modules of the electronic device 12 via a bus 18. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 12, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0178] The processor 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the methods mentioned in the above embodiments.

[0179] In order to implement the above embodiment, the present disclosure also proposes a chip, the chip includes a data processing module, a processor, and a ROM, the data processing module is configured to execute the above Figure 1 and Figure 2 The data processing method provided in the embodiment, the processor is configured to execute the above Figure 3 and Figure 4 The data processing method provided by the embodiment.

[0180] Fig.11 is a schematic diagram of the structure of the chip proposed in the embodiment of the present disclosure. Fig.11 The structure of the chip 1100 is shown, but is not limited to this.

[0181] The chip 1100 includes a processor 1101, which is configured to execute Figure 3 and Figure 4The data processing method provided by the embodiment.

[0182] In some embodiments, the chip 1100 also includes one or more ROMs 1102 for storing instructions. Alternatively, all or part of the ROMs 1102 may be outside the chip 1100.

[0183] In some embodiments, chip 1100 also includes a data processing module 1103, which can be deployed at the interface of ROM 1102 to match the first address in the data read instruction with the replacement address in the register, and based on the matching result, determine the target data of the data read instruction from the data stored in ROM 1102 or the data stored in the register, and return it to processor 1101.

[0184] In order to implement the above embodiments, the present disclosure further proposes a computer-readable storage medium storing a computer program. When the computer program is executed, the data processing method proposed in the above embodiments of the present disclosure is implemented.

[0185] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0186] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0187] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present disclosure belong.

[0188] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute the instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or otherwise processing in a suitable manner if necessary, and then stored in a computer memory.

[0189] It should be understood that the various parts of the present disclosure can be implemented in hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0190] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0191] In addition, each functional unit in each embodiment of the present disclosure may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0192] The storage medium mentioned above may be a read-only memory, a disk or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present disclosure. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present disclosure.

Claims

1. A data processing method, characterized in that: The method comprises: When a data read instruction for a read-only memory ROM is obtained, a first address is obtained from the data read instruction; matching the first address with a replacement address in a register; In the case where any replacement address matches the first address, the replacement data corresponding to the any replacement address stored in the register is determined as the target data of the data read instruction.

2. The method according to claim 1, characterized in that The method further comprises: In a case where all replacement addresses stored in the register do not match the first address, target data of the data read instruction is acquired from the ROM based on the first address.

3. The method according to claim 1, characterized in that The replacement data is any of the following: A replacement instruction corresponding to the instruction stored at the first address in the ROM; A jump instruction, wherein the jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored at the first address in the ROM.

4. The method according to claim 3, characterized in that The jump address is an address in a random access memory RAM.

5. The method according to claim 1, characterized in that One of the replacement addresses and the corresponding replacement data is stored in a group of registers.

6. A data processing method, characterized in that: The method comprises: Acquire a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in the ROM; The replacement address and the replacement data are stored in registers associated with the ROM.

7. The method according to claim 6, characterized in that The replacement data is any of the following: A replacement instruction corresponding to the instruction stored at the replacement address in the ROM; A jump instruction, wherein the jump instruction includes a jump address, a replacement instruction is stored in the jump address, and the replacement instruction corresponds to the instruction stored in the replacement address in the ROM.

8. The method according to claim 7, characterized in that The jump address is an address in a random access memory RAM, and the method further includes: When the replacement data is a jump instruction, obtaining the jump address and a replacement instruction associated with the jump address from the first memory; The replacement instruction is stored in the jump address of the RAM.

9. The method according to claim 6, characterized in that The acquiring the replacement address and the replacement data corresponding to the replacement address from the first memory includes: When it is detected that the device is powered on, a first instruction stored in a first preset address of the ROM is executed to obtain the replacement address and the replacement data from the first memory.

10. The method according to claim 6, characterized in that The storing the replacement address and the replacement data in a register associated with the ROM comprises: Based on a second preset address, obtaining a second instruction from the ROM, wherein the register does not contain a replacement address matching the second preset address; The second instruction is executed to store the replacement address and the replacement data in a register associated with the ROM.

11. A data processing module, characterized in that: Including registers, hit judgment modules, and selectors; The register is used to store the replacement address and the replacement data corresponding to the replacement address; The hit judgment module is used for obtaining a first address from the data read instruction when a data read instruction for the read-only memory ROM is obtained, matching the first address with the replacement address in the register to obtain a matching result, and sending the matching result to the selector; The selector is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the read instruction when the matching result indicates that any replacement address matches the first address.

12. The module according to claim 11, characterized in that: The selector is also used to: In a case where all replacement addresses stored in the register do not match the first address, the instruction stored at the first address in the ROM is determined as the target data of the read instruction.

13. A data processing device, characterized in that: The device comprises: An acquisition module, configured to acquire a first address from a data read instruction for a read-only memory ROM when the data read instruction for the read-only memory ROM is acquired; a matching module, configured to match the first address with a replacement address in a register; A determination module is used to determine the replacement data corresponding to any replacement address stored in the register as the target data of the read instruction when any replacement address matches the first address.

14. A data processing device, characterized in that: The device comprises: An acquisition module, configured to acquire a replacement address and replacement data corresponding to the replacement address from a first memory, wherein the first memory is a non-volatile memory, and the replacement address is a storage address corresponding to the data to be replaced in a ROM; The processing module is used for storing the replacement address and the replacement data in a register associated with the ROM.

15. An electronic device, characterized in that: It comprises a data processing module, a processor, and a ROM, wherein the data processing module is configured to execute the data processing method as described in any one of claims 1 to 5, and the processor is configured to execute the data processing method as described in any one of claims 6 to 10.

16. A chip, characterized in that: The chip includes a data processing module, a processor, and a ROM. The data processing module is configured to execute the data processing method described in any one of claims 1 to 5, and the processor is configured to execute the data processing method described in any one of claims 6 to 10.

17. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by the data processing module, it implements the data processing method as described in any one of claims 1 to 5, or when the computer program is executed by the processor, it implements the data processing method as described in any one of claims 6 to 10.

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