Adaptive parameter control method and system based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a parameter adaptive control method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: S1, acquiring a signal waveform on a receiving line of an original transmission channel through an operational amplifier accessed to the original transmission channel; s2, performing conversion and filtering processing through an analog-to-digital converter and a digital filter on the FPGA; s3, a parameter monitoring module on the FPGA performs secondary processing on the data processed in the S2 to obtain a corresponding frequency domain signal; s4, the parameter evaluation module looks up a pre-stored parameter table in a polling mode by taking the frequency domain signal as a reference, and S5, the communication module delivers a constraint condition and a parameter adaptive result to the microprocessor to complete parameter negotiation. The invention provides a parameter adaptive control method and system based on an FPGA (Field Programmable Gate Array), and the system can automatically adjust and control parameters and evaluate the system state according to the real-time state and environment change of a monitored transmission channel, thereby achieving the effects of quickly identifying channel parameters, completing parameter negotiation and improving the adaptability and stability of the system.

Description

Technical Field

[0001] The present invention relates to the fields of communication technology and digital signal processing, and more specifically, to a parameter adaptive control method and system based on FPGA. Background Art

[0002] With the development of communication technology, multiple technical systems coexist in many application scenarios. Different transmission technology systems may be used under different requirements. When facing complex and changing external environments, traditional communication systems and digital signal processing systems can only rely on polling and stacking circuit structures to adapt, which has problems such as inflexible parameter adjustment and slow response speed. These problems limit the performance of the system in practical applications.

[0003] As a kind of programmable hardware, FPGA has strong parallel processing capability and flexible hardware resources with its high parallel processing capability and programmability, and is very suitable for realizing parameter adaptive communication system. However, it has not been applied in the case of parameter adaptive adjustment to simplify the circuit. Summary of the invention

[0004] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0005] In order to achieve these purposes and other advantages of the present invention, a parameter adaptive control method based on FPGA is provided, comprising:

[0006] S1, acquiring the signal waveform on the receiving line of the original transmission channel by accessing the operational amplifier on the original transmission channel;

[0007] S2, converting and filtering the signal waveform obtained by the operational amplifier through the analog-to-digital converter and digital filter on the FPGA;

[0008] S3, the parameter monitoring module on the FPGA performs secondary processing on the data processed by S2 to obtain the corresponding frequency domain signal;

[0009] S4, the parameter evaluation module on the FPGA uses the frequency domain signal obtained by S3 as a reference, and searches the pre-stored parameter table by polling to complete the adaptive selection of channel parameter selection;

[0010] S5. The communication module on the FPGA delivers the constraint conditions and parameter adaptation results to the microprocessor to complete the parameter negotiation.

[0011] Preferably, in S1, the operational amplifier is configured as a multi-stage differential pipeline architecture with a positive input.

[0012] Preferably, in S2, the processing speed of the analog-to-digital converter is configured to be 12-bit quantization and 65 million samples per second.

[0013] Preferably, in S3, the secondary processing is to intercept a signal in the time domain through a digital preprocessing submodule, sample and quantize the signal, and then extract and identify the signal spectrum through an adaptive processing and multiplication and addition operation submodule.

[0014] Preferably, the digital preprocessing submodule discretizes the intercepted signal into digital signals X(0) to X(n-1), and stores them one by one into the access module FIFO of the FPGA;

[0015] The adaptive processing and multiplication-addition submodule multiplies each discrete digital signal X(0)~X(n-1) of the FIFO by the corresponding weight coefficient W(n) one by one, obtains Z(n) through shift addition operation, and then converts the continuous time domain signal into a discrete frequency domain signal through Fourier transform FFT.

[0016] Preferably, for a signal XZ(n) of a given length N, the calculation formula of its discrete Fourier transform Y(k) is:

[0017] Y(k)=∑XZ(n)*exp(-j*2πnk / N)

[0018] Among them, k represents the index of the frequency series, ranging from 0 to N-1, exp is a factor in the form of a complex exponential, and n represents the index of the time series, ranging from 0 to N-1.

[0019] A parameter adaptive control system based on FPGA, applied to a parameter adaptive control method based on FPGA, comprises an operational amplifier, an analog-to-digital converter, a buffer RAM, a digital filter, a parameter monitoring module, a parameter evaluation module and a communication module;

[0020] Wherein, the parameter monitoring module is configured to include a digital preprocessing submodule, an adaptive processing and multiplication and addition operation submodule;

[0021] The communication module is in communication connection with the microprocessor.

[0022] The present invention includes at least the following beneficial effects: the present invention utilizes the advantages of FPGA (field programmable gate array) with flexible software programming and easy function expansion to realize parameter adaptive technology. Specifically, the present invention uses an operational amplifier to monitor and evaluate the system status in real time, and a real-time feedback mechanism that compares with a preset parameter table to dynamically adjust system parameters to adapt to changes in the external environment, thereby achieving rapid identification of channel parameters and completing parameter negotiation, aiming to improve the adaptability and stability of the system in different environments.

[0023] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a principle block diagram of a parameter adaptive control system based on FPGA in the present invention;

[0025] Figure 2 The circuit structure diagram of the parameter adaptive control system of the present invention adopts a multi-stage series high impedance operational amplifier;

[0026] Figure 3 This is a processing flow chart of the parameter monitoring module in the parameter adaptive control system of the present invention. DETAILED DESCRIPTION

[0027] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0028] In order to achieve these purposes and other advantages according to the present invention, a parameter adaptive control system based on FPGA can automatically adjust control parameters and evaluate system status according to the real-time status and environmental changes of the monitoring transmission channel, so as to quickly identify channel parameters, complete parameter negotiation, and improve the adaptability and stability of the system. Figure 1 As shown, it includes an operational amplifier 1, an analog-to-digital converter 2 integrated on an FPGA 8, a buffer RAM 3, a digital filter 4, a parameter monitoring module 5, a parameter evaluation module 6 and a communication module 7:

[0029] Operational amplifier 1, such as Figure 2 As shown, the signal waveform on the line is received from the original transmission channel, and the channel parameters are calculated by the subsequent circuit. S1_N and S2_N are the original line signals. After the DC components are isolated by capacitors C2 and C5, they are sent to negative feedback amplifiers A1A and A3A respectively, and then sent to differential amplifier A2A to cancel out the same-phase signals and amplify the signals with opposite phases. The amplifier involved in the invention adopts a multi-stage differential pipeline architecture with the advantages of high input impedance and sensitive response. After accessing the original transmission channel, it only monitors the transmission parameters of the original channel without affecting the inherent characteristics of the original channel or the communication performance of the original channel. It is convenient to access the original transmission channel without adding too much circuit structure.

[0030] The analog-to-digital converter 2 is powered by a single power supply, a high-performance sample-and-hold amplifier, and a reference voltage source. It converts the analog signal into 8-bit parallel high-speed data at a processing speed of 12-bit quantization and 65 megasamples per second (MSPS) and sends it to the FPGA, which is convenient for the subsequent digital filtering and digital signal processing.

[0031] Digital filter 4. In the process of digital signal processing, because the impulse response is stable at 0 value within a specific time period, a finite impulse response filter can be used to filter the time domain discrete system. The principle is to use an accumulator to filter the separated frequency signal, so that the required frequency components pass losslessly, while blocking certain frequency signals. The value of a specific frequency can be obtained through simulation.

[0032] Parameter monitoring module 5, such as Figure 3 As shown, it includes a digital preprocessing submodule 50 and an adaptive processing and multiplication-addition operation submodule 51, and realizes the extraction and identification of the signal spectrum through the fast Fourier transform of digital frequency conversion and the adaptive processing and multiplication-addition operation. Its principle is to intercept a signal of appropriate length in the time domain, sample and quantize the signal, and obtain the signal spectrum according to specific mathematical steps.

[0033] The parameter evaluation module 6 searches the pre-stored parameter table by polling to obtain the most suitable channel parameters at present.

[0034] The communication module 6 is used to communicate with the microprocessor and deliver constraint conditions and parameter adaptation results to facilitate user system management and maintenance.

[0035] The present invention provides an FPGA-based parameter adaptive control method, which can monitor the state of the transmission channel and environmental changes in real time, automatically adjust the control parameters, evaluate the system state, quickly identify channel parameters, complete parameter negotiation, and improve the adaptability and stability of the system. The method specifically includes:

[0036] S1, acquiring the signal waveform on the receiving line of the original transmission channel by accessing the operational amplifier on the original transmission channel;

[0037] S2, converting and filtering the signal waveform obtained by the operational amplifier through the analog-to-digital converter and digital filter on the FPGA;

[0038] S3, the parameter monitoring module on the FPGA performs secondary processing on the data processed by S2 to obtain the corresponding frequency domain signal; the principle of the secondary processing of the parameter monitoring module is to intercept a signal of appropriate length in the time domain, sample and quantize the signal, and the buffer RAM 3 multiplies the discrete digital signals X(0)~X(n-1) one by one with the weight coefficient W(n) and performs shift addition operation to obtain Z(n), and obtains the spectrum of the signal through Fourier transform (FFT). Among them, the buffer can be implemented using the dedicated access module FIFO provided by FPGA. Each buffer is a FIFO. The output data of the first-level buffer is used as the input data of the next level, and is cached level by level to achieve the effect of delay and shift; the Fourier transform (FFT) operation can be completed using the dedicated kernel provided by FPGA or written code to convert the continuous time domain signal into a discrete frequency domain signal. For a signal Z(n) with a given length of N, the calculation formula of its discrete Fourier transform Y(k) is:

[0039] Y(k)=∑Z(n)*exp(-j*2πnk / N)

[0040] Among them, k represents the frequency series, ranging from 0 to N-1, exp is a factor in the form of a complex exponential, and n represents the time series, ranging from 0 to N-1.

[0041] S4, the parameter evaluation module on the FPGA uses the frequency domain signal obtained by S3 as a reference, searches the pre-stored parameter tables 1 to 3 by polling, and sends the index number I corresponding to the frequency found in Table 1, the index number II corresponding to the amplitude found in Table 2, and the mode found in Table 3 to the CPU to complete the adaptive selection of channel parameter selection;

[0042] The pre-stored channel parameters take frequency and amplitude as an example, such as the frequency-based query table in Table 1 and the amplitude-based query table in Table 2. The calculated Y(k) is compared with the parameter table in turn to obtain the corresponding index number, which can be used to determine the characteristics of the signal, so that appropriate parameters can be used for communication.

[0043] Table 1

[0044] Index I 00000000 00000001 00000002 …… 00000010 00000011 00000012 …… Frequency value (kHz) 0 1 2 …… 10 11 12 …… Index I 00000050 …… 00000100 …… 00000200 …… 00005000 …… Frequency value (kHz) 50 …… 100 …… 200 …… 5000 ……

[0045] Table 2

[0046] Index II 00000000 00000001 00000002 …… 00000010 00000011 …… 00000050 Amplitude value (dB) 0 0.1 0.2 …… 1.0 1.1 …… 5.0 Index II …… 00000100 00000101 …… 00000200 …… 00000500 …… Amplitude value (dB) …… 10.0 10.1 …… 20.0 …… 50.0 ……

[0047] Table 3

[0048]

[0049]

[0050] S5. The communication module on the FPGA delivers the constraint conditions and parameter adaptation results (i.e., the results of the queries in Table 1, Table 2, and Table 3) to the microprocessor to complete the parameter negotiation.

[0051] The parameter adaptive control method of the present invention mainly utilizes FPGA to realize the parameter adaptive control system, without relying on complex circuit structure or high-performance software design implementation, thus reducing system cost. At the same time, based on the parallel processing capability and high-speed IO interface of FPGA, the real-time response capability of the control system is guaranteed, the system response time is shortened, the processing efficiency and the overall performance of the system are improved, and flexible configuration and monitoring functions are provided, making it convenient for users to manage and maintain the system.

[0052] The above solution is only an illustration of a preferred embodiment, but is not limited thereto. When implementing the present invention, appropriate replacement and / or modification can be performed according to user needs.

[0053] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily realized. Therefore, without departing from the general concept defined by the claims and equivalent scope, the present invention is not limited to the specific details and the illustrations shown and described here.

Claims

1. A parameter adaptive control method based on FPGA, characterized in that: include: S1, acquiring the signal waveform on the receiving line of the original transmission channel by accessing the operational amplifier on the original transmission channel; S2, converting and filtering the signal waveform obtained by the operational amplifier through the analog-to-digital converter and digital filter on the FPGA; S3, the parameter monitoring module on the FPGA performs secondary processing on the data processed by S2 to obtain the corresponding frequency domain signal; S4, the parameter evaluation module on the FPGA uses the frequency domain signal obtained by S3 as a reference and searches the pre-stored parameter table by polling to complete the adaptive selection of channel parameter selection; S5. The communication module on the FPGA delivers the constraint conditions and parameter adaptation results to the microprocessor to complete the parameter negotiation.

2. The FPGA-based parameter adaptive control method according to claim 1, characterized in that: In S1, the operational amplifier is configured as a multi-stage differential pipeline architecture with a positive input.

3. The FPGA-based parameter adaptive control system according to claim 1, characterized in that: In S2, the processing speed of the analog-to-digital converter is configured to be 12-bit quantization and 65 million samples per second.

4. The FPGA-based parameter adaptive control method according to claim 1, characterized in that: In S3, the secondary processing is to intercept a section of signal in the time domain through the digital preprocessing submodule, sample and quantize the signal, and then extract and identify the signal spectrum through the adaptive processing and multiplication and addition operation submodule.

5. The FPGA-based parameter adaptive control method according to claim 4, characterized in that: The digital preprocessing submodule discretizes the intercepted signal into digital signals X(0) to X(n-1), and stores them one by one into the access module FIFO of the FPGA; The adaptive processing and multiplication-addition submodule multiplies each discrete digital signal X(0)~X(n-1) of the FIFO by the corresponding weight coefficient W(n) one by one, obtains Z(n) through shift addition operation, and then converts the continuous time domain signal into a discrete frequency domain signal through Fourier transform FFT.

6. A parameter adaptive control system based on FPGA, applied to the parameter adaptive control method based on FPGA as claimed in any one of claims 1 to 4, characterized in that: It includes an operational amplifier, an analog-to-digital converter, a buffer RAM, a digital filter, a parameter monitoring module, a parameter evaluation module and a communication module; Wherein, the parameter monitoring module is configured to include a digital preprocessing submodule, an adaptive processing and multiplication and addition operation submodule; The communication module is in communication connection with the microprocessor.

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