Display device

Abstract

The invention provides a display device which comprises multiple rows of pixels and multiple stages of gate drive circuits, a first gate drive sub-circuit of the gate drive circuit comprises a first stage transmission circuit and a first output circuit, and the first output circuit comprises an eighteenth transistor, a twenty-first transistor, a twenty-second transistor and a fifth capacitor. One pole plate of the fifth capacitor is electrically connected with the first control node I, the other pole plate of the fifth capacitor is electrically connected with the first low-level signal input end or the second low-level signal input end, in the top view of the gate drive circuit, the first high-level signal line is located on the first side of the first low-level signal line, and the fifth capacitor is located on the second side of the first low-level signal line. According to the technical scheme, the coupling influence of the fifth capacitor on the potential of the signal transmitted by the high-level signal input end is avoided, so that the potential fluctuation of the first scanning signal is avoided, and the display abnormality phenomenon occurring at the boundary between different areas when the frequency division display function of the display device is started is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] In order to provide better display effects and user experience, frequency division display technology is widely used in OLED display panels. Frequency division display technology refers to the use of different refresh rates in different areas of the same display panel, such as a 120Hz refresh rate in the area displaying dynamic content and a 60Hz refresh rate in the area displaying static content, which can ensure the smoothness of dynamic images and reduce power consumption.

[0003] However, in an OLED display panel that uses frequency division display technology, when the refresh frequencies of different areas are switched, display anomalies may occur at the boundaries between different areas due to design problems with the gate drive circuit, which may affect the display effect and user experience. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a display device to improve the display abnormality phenomenon occurring at the boundary between different areas when the display device turns on the frequency division display function.

[0005] An embodiment of the present application provides a display device, including a display panel, the display panel including multiple rows of pixels and multiple levels of gate driving circuits, wherein the first level of the gate driving circuit includes: a first gate driving sub-circuit, the first gate driving sub-circuit includes a first-level transmission circuit and a first output circuit, the first output circuit includes: an eighteenth transistor, the gate of the eighteenth transistor is electrically connected to a first control node I, and the source of the eighteenth transistor is electrically connected to a second control node F of the first-level transmission circuit; a twenty-first transistor, the gate of the twenty-first transistor is electrically connected to a third control node G of the first-level transmission circuit, the source of the twenty-first transistor is electrically connected to a first low-level signal input terminal of the display panel, and the drain of the twenty-first transistor is electrically connected to the second control node F of the first-level transmission circuit. a gate driving sub-circuit electrically connected to the first scanning signal output terminal; a twenty-second transistor, the gate of the twenty-second transistor is electrically connected to the drain of the eighteenth transistor, the source of the twenty-second transistor is electrically connected to the first high-level signal input terminal of the display panel, and the drain of the twenty-second transistor is electrically connected to the first scanning signal output terminal; and a fifth capacitor, one plate of the fifth capacitor is electrically connected to the first control node I, and the other plate of the fifth capacitor is electrically connected to the first low-level signal input terminal; wherein, in the top view of the gate driving circuit, the first high-level signal line is located on a first side of the first low-level signal line, and the fifth capacitor is located on a second side of the first low-level signal line opposite to the first side.

[0006] In the above-mentioned display device, the first output circuit also includes: a nineteenth transistor, a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and a fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

[0007] In the above-mentioned display device, the first-stage transmission circuit includes: a first transistor, the gate of the first transistor is electrically connected to the node C, and the source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, the gate of the second transistor is electrically connected to the node E, the source of the second transistor is electrically connected to the first clock signal input terminal, and the drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, the gate of the third transistor is electrically connected to the second clock signal input terminal, the source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and the drain of the third transistor is electrically connected to the node D; a fourth transistor, the gate of the fourth transistor is electrically connected to the second clock signal input terminal, the source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and the drain of the third transistor is electrically connected to the node D; an input terminal, a source of the fourth transistor is electrically connected to the first low-level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A an eighth transistor, the gate of the eighth transistor is electrically connected to the node D, the source of the eighth transistor is electrically connected to the first high-level signal input terminal, and the drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, the gate of the ninth transistor is electrically connected to the third control node G, the source of the ninth transistor is electrically connected to the first low-level signal input terminal, and the drain of the ninth transistor is electrically connected to the first-stage transmission signal output terminal; a tenth transistor, the gate of the tenth transistor is electrically connected to the second control node F, the source of the tenth transistor is electrically connected to the first high-level signal input terminal, and the drain of the tenth transistor is electrically connected to the first-stage transmission signal output terminal an eleventh transistor, the gate of the eleventh transistor is electrically connected to the first low level signal input terminal, the source of the eleventh transistor is electrically connected to the node C, and the drain of the eleventh transistor is electrically connected to the node B; a twelfth transistor, the gate of the twelfth transistor is electrically connected to the first low level signal input terminal, the source of the twelfth transistor is electrically connected to the node D, and the drain of the twelfth transistor is electrically connected to the third control node G; a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the first control signal input terminal, the source of the thirteenth transistor is electrically connected to the first high level signal input terminal, and the drain of the thirteenth transistor is electrically connected to the node D;a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, the source of the fourteenth transistor is electrically connected to the first stage transmission signal input terminal; a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the first low level signal input terminal, the source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and the drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the node E, the source of the sixteenth transistor is electrically connected to the node E, and the drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, the seventeenth transistor The gate of the transistor is electrically connected to the second control signal input terminal, the source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and the drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor is electrically connected to the node A, and the other plate of the second capacitor is electrically connected to the node B; and a third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high level signal input terminal. ;

[0008] In the above display device, the first-stage transmission circuit further includes: a sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage transmission signal output terminal.

[0009] In the above-mentioned display device, the display panel also includes a second gate driving subcircuit and a second high-level signal line, the second gate driving subcircuit is electrically connected to the second high-level signal line, and in the top view of the gate driving circuit, the second high-level signal line is located on the first side of the first low-level signal line.

[0010] An embodiment of the present application also provides a display device, including a display panel, the display panel including multiple rows of pixels and multiple levels of gate driving circuits, wherein the first level of the gate driving circuit includes: a first gate driving sub-circuit, the first gate driving sub-circuit includes a first-level transmission circuit and a first output circuit, the first output circuit includes: an eighteenth transistor, the gate of the eighteenth transistor is electrically connected to the first control node I, and the source of the eighteenth transistor is electrically connected to the second control node F of the first-level transmission circuit; a twenty-first transistor, the gate of the twenty-first transistor is electrically connected to the third control node G of the first-level transmission circuit, the source of the twenty-first transistor is electrically connected to the first low-level signal input terminal of the display panel, and the drain of the twenty-first transistor is electrically connected to the first scanning signal output terminal of the first gate driving sub-circuit ; a twenty-second transistor, a gate of the twenty-second transistor being electrically connected to the drain of the eighteenth transistor, a source of the twenty-second transistor being electrically connected to the first high-level signal input terminal of the display panel, and a drain of the twenty-second transistor being electrically connected to the first scanning signal output terminal; and a fifth capacitor, one plate of the fifth capacitor being electrically connected to the first control node I, and the other plate of the fifth capacitor being electrically connected to the second low-level signal input terminal of the display panel; wherein, in a top view of the gate drive circuit, the first high-level signal line is located on a first side of the second low-level signal line, the fifth capacitor is located on a second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on a side of the first high-level signal line away from the second low-level signal line.

[0011] In the above-mentioned display device, the first output circuit also includes: a nineteenth transistor, a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high-level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and a fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

[0012] In the above-mentioned display device, the first gate driving subcircuit also includes a first-level transmission circuit, and the first-level transmission circuit includes: a first transistor, the gate of the first transistor is electrically connected to the node C, and the source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, the gate of the second transistor is electrically connected to the node E, the source of the second transistor is electrically connected to the first clock signal input terminal, and the drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, the gate of the third transistor is electrically connected to the second clock signal input terminal, the source of the third transistor is electrically connected to the first-level transmission signal input terminal, and the drain of the third transistor is electrically connected to the node D; a fourth transistor, the gate of the third transistor is electrically connected to the node E, the source of the second transistor is electrically connected to the first clock signal input terminal, and the drain of the third transistor is electrically connected to the node D; a first transistor, a second transistor, a gate of the first transistor, a source of the second transistor, a drain of the first transistor, and a node C; a fifth transistor, a gate of the fifth transistor, a gate of the fifth transistor, a source of the fifth transistor, a drain of the fifth transistor, and a node C; a sixth transistor, a gate of the sixth transistor, a source of the sixth transistor, a drain of the sixth transistor, and a node B; a seventh transistor, a gate of the seventh transistor, a source of the sixth transistor, a drain of the sixth transistor, and a node A; a seventh transistor, a gate of the seventh transistor, a gate of the seventh transistor, a source of the seventh transistor, a drain of the seventh transistor, and a node C; a fifth transistor, a gate of the fifth transistor, a gate of the fifth transistor, a source of the fifth transistor, a drain of the fifth transistor, and a node B; a seventh transistor, a gate of the seventh transistor, a source of the sixth transistor, a drain of the sixth transistor, and a node A; a seventh transistor, a gate of the seventh transistor, a gate of the seventh transistor, a source of the seventh transistor, a drain of the sixth transistor, and a node A; a fifth transistor, a gate of the fifth transistor, a gate of the fifth transistor, a source of the fifth transistor, a drain of the sixth transistor, and a node D; a sixth transistor, a gate of the sixth transistor, a source of the sixth transistor, a drain of the sixth transistor, and a node B; a seventh transistor, a gate of the seventh transistor, a source of the sixth transistor, a drain of the sixth transistor, and a node A; a first transistor, a second transistor, a second transistor, a gate of the first transistor, a source of the first transistor, and a first node A; an eighth transistor, a gate of the eighth transistor, a source of the eighth transistor, and a first high-level signal input terminal, and a drain of the eighth transistor, respectively; a ninth transistor, a gate of the ninth transistor, a source of the ninth transistor, and a first low-level signal input terminal, and a drain of the ninth transistor, respectively; a tenth transistor, a gate of the tenth transistor, a source of the tenth transistor, and a first high-level signal input terminal, and a drain of the tenth transistor, respectively; a tenth transistor, a gate of the tenth transistor, a source of the tenth transistor, and a first high-level signal input terminal, and a drain of the tenth transistor, respectively; a first control signal output terminal electrically connected to the first control signal input terminal; an eleventh transistor, a gate of the eleventh transistor electrically connected to the first low level signal input terminal, a source of the eleventh transistor electrically connected to the node C, and a drain of the eleventh transistor electrically connected to the node B; a twelfth transistor, a gate of the twelfth transistor electrically connected to the first low level signal input terminal, a source of the twelfth transistor electrically connected to the node D, and a drain of the twelfth transistor electrically connected to the third control node G; a thirteenth transistor, a gate of the thirteenth transistor electrically connected to the first control signal input terminal, a source of the thirteenth transistor electrically connected to the first high level signal input terminal, and a drain of the thirteenth transistor electrically connected to the node D;a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, the source of the fourteenth transistor is electrically connected to the first stage transmission signal input terminal; a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the first low level signal input terminal, the source of the fifteenth transistor is electrically connected to the drain of the fourteenth transistor, and the drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the node E, the source of the sixteenth transistor is electrically connected to the node E, and the drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, the seventeenth transistor The gate of the transistor is electrically connected to the second control signal input terminal, the source of the seventeenth transistor is electrically connected to the drain of the seventh transistor, and the drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, one plate of the first capacitor is electrically connected to the node E, and the other plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor is electrically connected to the node A, and the other plate of the second capacitor is electrically connected to the node B; and a third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high level signal input terminal. ;

[0013] In the above display device, the first-stage transmission circuit further includes: a sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage transmission signal output terminal.

[0014] In the above-mentioned display device, the display panel also includes a second gate driving subcircuit and a second high-level signal line, the second gate driving subcircuit is electrically connected to the second high-level signal line and the second low-level signal line, and in the top view of the gate driving circuit, the second high-level signal line is located on the first side of the second low-level signal line, and the second high-level signal line is located between the first low-level signal line and the second low-level signal line.

[0015] In the display device provided in the embodiment of the present application, since one plate of the fifth capacitor in the first output circuit of the first gate driving sub-circuit in the gate driving circuit is electrically connected to the node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driving sub-circuit or the second low-level signal input terminal of the second gate driving sub-circuit, and the first high-level signal input terminal is insulated from the fifth capacitor, when the first control signal input terminal inputs the first control signal to the node I, the fifth capacitor will not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal, thereby avoiding the problem of fluctuation of the potential of the signal transmitted by the first high-level signal input terminal due to the coupling effect between the fifth capacitor and the first high-level signal input terminal.

[0016] Furthermore, since the potential of the signal transmitted by the first high-level signal input terminal will not fluctuate due to the coupling effect of the fifth capacitor, and the first gate driving subcircuit generates the first scanning signal according to the signals transmitted by the first high-level signal input terminal and the first low-level signal input terminal, the potential of the first scanning signal will not fluctuate due to the coupling effect of the fifth capacitor. Since the potential of the first scanning signal does not fluctuate, the turning on or off of the third transistor in the pixel driving circuit of the pixel will not be affected, and the second capacitor electrically connected to the drain of the third transistor will not exert a coupling effect on the gate of the second transistor also electrically connected to the second capacitor, thereby not affecting the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0017] In addition, since the data signal can be written into the pixel normally, when the display device turns on the frequency division display function, there will be no display abnormality at the boundary between different areas due to abnormal data signal writing, thereby improving the display effect of the display device when the frequency division display function is turned on.

[0018] In addition, since one plate of the fifth capacitor is electrically connected to the node I of the first output circuit, and the other plate is electrically connected to the first low-level signal input terminal of the first gate driving subcircuit or the second low-level signal input terminal of the second gate driving subcircuit, rather than to the first high-level signal input terminal, in the layout of the gate driving circuit, the first low-level signal line of the first gate driving subcircuit or the second low-level signal line of the second gate driving subcircuit can be arranged between the whole formed by the first high-level signal line and the second high-level signal line and the fifth capacitor, so that the layout of the first high-level signal line and the second high-level signal line is more uniform, avoiding the uneven layout of the first high-level signal line and the second high-level signal line caused by the need to occupy the routing space of the first high-level signal line and / or the second high-level signal line due to the electrical connection of the fifth capacitor to the first high-level signal input terminal, thereby avoiding the problem of uneven load caused by the uneven layout of the first high-level signal line and the second high-level signal line, and improving the working stability of the gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a potential fluctuation phenomenon of a first scanning signal in a conventional display device.

[0020] Figure 2 is a schematic diagram of a display device provided in an embodiment of the present application.

[0021] Figure 3 is a circuit diagram of a pixel in a display device provided in an embodiment of the present application.

[0022] Figure 4 It is a circuit diagram of a first embodiment of a first gate driving sub-circuit in a display device provided in the present application.

[0023] Figure 5 It is a layout diagram of a first embodiment of a first gate driving sub-circuit in a display device provided in the present application.

[0024] Figure 6 4 is a circuit diagram of a second embodiment of the first gate driving sub-circuit in the display device provided in the present application.

[0025] Figure 7 It is a layout diagram of a second embodiment of the first gate driving sub-circuit in the display device provided in the present application. DETAILED DESCRIPTION

[0026] The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0028] The embodiments of the present application may be combined with each other.

[0029] like Figure 1 As shown, in a conventional display device, when the first control signal inputted by the first control signal input terminal CTRL1 switches from a low potential to a high potential, the scanning signal (such as Nout2) outputted by the multi-stage gate driving circuit <1327> To Nout2 <1338> ) There will be a potential fluctuation phenomenon CPL.

[0030] The potential fluctuation of the scanning signal may affect the opening or closing of the third transistor Tp3 in the pixel PX, thereby causing abnormal writing of the data signal. When the display device turns on the frequency division display function, due to the different refresh frequencies of the pixels PX in different areas, the abnormal writing of the data signal will be more obvious at the boundary between different areas, thereby causing abnormal display.

[0031] The embodiments of the present application aim to provide a display device to solve the above technical problems.

[0032] like Figure 2 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller, a source driving circuit and a power management chip. The display panel is an organic light emitting diode display panel.

[0033] The display panel includes a display area and a non-display area. The display area is provided with m×n pixels PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange a drive circuit and various signal lines. The display panel also includes a plurality of scan lines SCAN, a plurality of data lines DATA and a gate drive circuit. The plurality of scan lines SCAN extend along a first direction and are arranged along a second direction, and the plurality of data lines DATA extend along a second direction and are arranged along the first direction, and the first direction is perpendicular to the second direction. The gate drive circuit is arranged in the non-display area and is electrically connected to the plurality of scan lines SCAN. The source drive circuit is electrically connected to the plurality of data lines DATA through a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit, respectively.

[0034] The display panel includes an organic light emitting diode array substrate and an encapsulation layer. The organic light emitting diode array substrate includes a base substrate, a buffer layer arranged on the base substrate, an active layer arranged on the buffer layer, a gate insulating layer arranged on the active layer, a first metal layer arranged on the gate insulating layer, an interlayer insulating layer arranged on the first metal layer, a second metal layer arranged on the interlayer insulating layer, a planarization layer arranged on the second metal layer, a first electrode layer arranged on the planarization layer, a pixel defining layer arranged on the first electrode layer, an organic light emitting layer arranged in an opening area defined by the pixel defining layer, and a second electrode layer arranged on the organic light emitting layer. The first metal layer includes a scan line SCAN, a gate electrode, etc. The second metal layer includes a data line DATA, a source electrode, a drain electrode, etc. The encapsulation layer is sealed and connected to the organic light emitting diode array substrate to prevent moisture and oxygen from invading the organic light emitting layer.

[0035] Each pixel PX includes a pixel driving circuit and an organic light emitting diode OLED (light emitting device). The pixel driving circuit includes at least two thin film transistors and a storage capacitor. One of the thin film transistors is used as a switching transistor, and its gate is electrically connected to the corresponding scan line, and its source is electrically connected to the corresponding data line; the other thin film transistor is used as a driving transistor, and its gate is electrically connected to the drain of the switching transistor, the source is electrically connected to the first power supply voltage line, and the drain is electrically connected to the anode of the organic light emitting diode OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to the source or drain of the driving transistor. The cathode of the organic light emitting diode OLED is electrically connected to the second power supply voltage line. When the scan line outputs a high-potential scan signal, the switching transistor is turned on, and the data signal on the data line is written to the gate of the driving transistor and the storage capacitor through the switching transistor; when the scan line outputs a low-potential scan signal, the switching transistor is turned off, the storage capacitor maintains the voltage of the gate of the driving transistor, and the driving transistor generates a driving current corresponding to the gate voltage to drive the organic light emitting diode OLED to emit light.

[0036] Each level of gate drive circuit is electrically connected to a scan line. Under the control of the timing controller, the gate drive circuit outputs scan signals in sequence to scan the pixels PX in the display area line by line. Under the control of the timing controller, the source drive circuit generates and outputs data signals according to the image data. The timing controller is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a second power supply voltage VSS for the cathode of the organic light emitting diode OLED, providing a first power supply voltage VDD for the first power supply voltage line, and providing a gate drive voltage VGH / VGL for the gate drive circuit.

[0037] The display device provided by the embodiment of the present application includes a display panel, and the display panel includes a plurality of rows of pixels PX. Each pixel PX includes a pixel driving circuit and a light emitting device OLED, and the pixel driving circuit is electrically connected to the light emitting device OLED.

[0038] like Figure 3 As shown, the pixel driving circuit includes a thin film transistor Tp1, a thin film transistor Tp2, a thin film transistor Tp3, a thin film transistor Tp4, a thin film transistor Tp5, a thin film transistor Tp6, a thin film transistor Tp7, a thin film transistor Tp8, a capacitor Cst and a capacitor Cboost.

[0039] Among them, the thin film transistors Tp1 , Tp2 , Tp5 , Tp6 , Tp7 , and Tp8 are P-type thin film transistors, and the thin film transistors Tp3 and Tp4 are N-type thin film transistors.

[0040] The gate of the thin film transistor Tp1 is electrically connected to the node Q, the source of the thin film transistor Tp1 is electrically connected to the node P, and the drain of the thin film transistor Tp1 is electrically connected to the node R. The gate of the thin film transistor Tp2 is electrically connected to the second scan signal input terminal Pscan1, the source of the thin film transistor Tp2 is electrically connected to the data signal input terminal Data, and the drain of the thin film transistor Tp2 is electrically connected to the node P. The gate of the thin film transistor Tp3 is electrically connected to the first scan signal input terminal Nscan1 (Nout2), the source of the thin film transistor Tp3 is electrically connected to the node R, and the drain of the thin film transistor Tp3 is electrically connected to the node Q. The gate of the thin film transistor Tp4 is electrically connected to the third scan signal input terminal Nscan2, the source of the thin film transistor Tp4 is electrically connected to the first reset signal input terminal Vi1, and the drain of the thin film transistor Tp4 is electrically connected to the node Q. The gate of the thin film transistor Tp5 is electrically connected to the first light emission control signal input terminal EM, the source of the thin film transistor Tp5 is electrically connected to the first power signal input terminal VDD, and the drain of the thin film transistor Tp5 is electrically connected to the node P. The gate of the thin film transistor Tp6 is electrically connected to the first light emission control signal input terminal EM, the source of the thin film transistor Tp6 is electrically connected to the node R, and the drain of the thin film transistor Tp6 is electrically connected to the node S. The gate of the thin film transistor Tp7 is electrically connected to the fourth scan signal input terminal Pscan2, the source of the thin film transistor Tp7 is electrically connected to the second reset signal input terminal Vi2, and the drain of the thin film transistor Tp7 is electrically connected to the node S. The gate of the thin film transistor Tp8 is electrically connected to the fourth scan signal input terminal Pscan2, the source of the thin film transistor Tp8 is electrically connected to the third reset signal input terminal Vi3, and the drain of the thin film transistor Tp8 is electrically connected to the node R. One plate of the capacitor Cst is electrically connected to the node Q, and the other plate of the capacitor Cst is electrically connected to the first power signal input terminal VDD. One plate of capacitor Cboost is electrically connected to node Q, and the other plate of capacitor Cboost is electrically connected to second scan signal input terminal Pscan1. An anode of light emitting device OLED is electrically connected to node S, and a cathode of light emitting device OLED is electrically connected to second power signal input terminal VSS.

[0041] The display panel also includes a cascaded multi-stage gate driving circuit. The first-stage gate driving circuit includes a first gate driving subcircuit and a second gate driving subcircuit, wherein the first gate driving subcircuit is used to output a first scanning signal Nscan1 (Nout2), and the second gate driving subcircuit is used to output a second scanning signal Pscan1. Figure 4 and Figure 6As shown, the first gate driving subcircuit includes a first-level transmission circuit 401 and a first output circuit 402, the first-level transmission circuit 401 is electrically connected to the first output circuit 402, the first output circuit 402 is used to output a first scanning signal Nscan1 (Nout2) to a row of pixels PX, and the first-level transmission circuit 401 is used to output a level transmission signal to the first gate driving subcircuit of the gate driving circuit of other levels. The second gate driving subcircuit includes a second-level transmission circuit and a second output circuit, the second-level transmission circuit is electrically connected to the second output circuit, the second output circuit is used to output a second scanning signal Pscan1 to the row of pixels PX, and the second-level transmission circuit is used to output a level transmission signal to the second gate driving subcircuit of the gate driving circuit of other levels. The technical solution of the embodiment of the present application is mainly aimed at improving the first gate driving subcircuit.

[0042] The first output circuit 402 includes an eighteenth transistor Ts18 , a twentieth transistor Ts20 , a twenty-first transistor Ts21 , and a fifth capacitor C5 .

[0043] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first stage transmission circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to the node H. The gate of the twenty-first transistor Ts21 is electrically connected to the node G (third control node) of the first stage transmission circuit 401, the source of the twenty-first transistor Ts21 is electrically connected to the first low level signal input terminal VGL1 of the display panel, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scan signal output terminal Nout2 of the first gate driving sub-circuit. The gate of the twenty-second transistor Ts22 is electrically connected to the node H (the drain of the eighteenth transistor Ts18), the source of the twenty-second transistor Ts22 is electrically connected to the first high level signal input terminal VGH1 of the display panel, and the drain of the twenty-second transistor Ts22 is electrically connected to the first scan signal output terminal Nout2. One plate of the fifth capacitor C5 is electrically connected to the first control node I, and the other plate of the fifth capacitor C5 is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the display panel (the second low-level signal input terminal VGL2 is electrically connected to the second gate driving sub-circuit).

[0044] The first-stage transmission circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0045] The gate of the first transistor Ts1 is electrically connected to the node C, and the source of the first transistor Ts1 is electrically connected to the first high level signal input terminal VGH1. The gate of the second transistor Ts2 is electrically connected to the node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1. The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the stage transfer signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to the node D. The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor Ts4 is electrically connected to the first low level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to the node C. The gate of the fifth transistor Ts5 is electrically connected to the node D, the source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and the drain of the fifth transistor Ts5 is electrically connected to the node C. The gate of the sixth transistor Ts6 is electrically connected to the node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to the node A. The gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and the source of the seventh transistor Ts7 is electrically connected to the node A. The gate of the eighth transistor Ts8 is electrically connected to the node D, the source of the eighth transistor Ts8 is electrically connected to the first high level signal input terminal VGH1, and the drain of the eighth transistor Ts8 is electrically connected to the node F (the second control node). The gate of the ninth transistor Ts9 is electrically connected to the node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first stage transmission signal output terminal Nout1. The gate of the tenth transistor Ts10 is electrically connected to the node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the tenth transistor Ts10 is electrically connected to the first-stage transmission signal output terminal Nout1. The gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1, the source of the eleventh transistor Ts11 is electrically connected to the node C, and the drain of the eleventh transistor Ts11 is electrically connected to the node B. The gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1, the source of the twelfth transistor Ts12 is electrically connected to the node D, and the drain of the twelfth transistor Ts12 is electrically connected to the node G (the third control node). The gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1, the source of the thirteenth transistor Ts13 is electrically connected to the first high-level signal input terminal VGH1, and the drain of the thirteenth transistor Ts13 is electrically connected to the node D.The gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and the source of the fourteenth transistor Ts14 is electrically connected to the first-stage transmission signal input terminal Nin. The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1, the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14, and the drain of the fifteenth transistor Ts15 is electrically connected to the node E. The gate of the sixteenth transistor Ts16 is electrically connected to the node E, the source of the sixteenth transistor Ts16 is electrically connected to the node E, and the drain of the sixteenth transistor Ts16 is electrically connected to the node G (the third control node). The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2, the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7, and the drain of the seventeenth transistor Ts17 is electrically connected to the node F (the second control node). One plate of the first capacitor C1 is electrically connected to the node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1. One plate of the second capacitor C2 is electrically connected to the node A, and the other plate of the second capacitor C2 is electrically connected to the node B. One plate of the third capacitor C3 is electrically connected to the node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high-level signal input terminal VGH1.

[0046] The first output circuit 402 further includes a nineteenth transistor Ts19, a twentieth transistor Ts20, and a fourth capacitor C4.

[0047] The gate of the nineteenth transistor Ts19 is electrically connected to the node D, the source of the nineteenth transistor Ts19 is electrically connected to the first high level signal input terminal VGH1, and the drain of the nineteenth transistor Ts19 is electrically connected to the node H. The gate of the twentieth transistor Ts20 is electrically connected to the node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1, and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor Ts18. One plate of the fourth capacitor C4 is electrically connected to the node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high level signal input terminal VGH1.

[0048] In this embodiment, the first transistor Ts1 to the twenty-second transistor Ts22 are all P-type thin film transistors.

[0049] In the technical solution provided by the embodiment of the present application, by electrically connecting one plate of the fifth capacitor C5 to the node I (first control node) of the first output circuit 402, and the other plate to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, instead of being electrically connected to the first high-level signal input terminal VGH1, the signal transmitted by the first control signal input terminal CTRL1 is prevented from being coupled to the potential of the signal transmitted by the first high-level signal input terminal VGH1 through the fifth capacitor C5. Since the first gate driving sub-circuit generates the first scanning signal Nscan1 (Nout2) according to the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, when the potential of the signal transmitted by the first high-level signal input terminal VGH1 is not affected by the coupling of the fifth capacitor C5, the potential of the first scanning signal Nscan1 (Nout2) will not be affected by the coupling of the fifth capacitor C5.

[0050] like Figure 5 and Figure 7As shown in the layout of the gate driving circuit, the first high level signal line VGH1 and the second high level signal line VGH2 of the display panel are located on a first side of the first low level signal line VGL1 of the first gate driving sub-circuit, and the fifth capacitor C5 is located on a second side of the first low level signal line VGL1 opposite to the first side, that is, when the other plate of the fifth capacitor C5 is electrically connected to the first low level signal line VGL1, the first low level signal line VGL1 is arranged between the whole formed by the first high level signal line VGH1 and the second high level signal line VGH2 and the fifth capacitor C5, and the second low level The signal line VGL2 is arranged on a side of the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5, or, when the other plate of the fifth capacitor C5 is electrically connected to the second low-level signal line VGL2, the second low-level signal line VGL2 is arranged between the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is arranged on a side of the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5. Since one plate of the fifth capacitor C5 is electrically connected to the node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, rather than to the first high-level signal input terminal VGH1, the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the need to occupy the routing space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2 due to the electrical connection of the fifth capacitor C5 to the first high-level signal input terminal VGH1 is avoided, thereby avoiding the problem of uneven load of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the uneven layout.

[0051] The first-stage transmission circuit 401 further includes a sixth capacitor C6 , one plate of the sixth capacitor C6 is electrically connected to the node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1 .

[0052] In this embodiment, by setting the sixth capacitor C6 between the node G (the third control node) and the first-stage signal transmission output terminal Nout1, when the signal of the first-stage signal transmission output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of the node G (the third control node), and control the twenty-first transistor Ts21 to turn on through the potential of the node G (the third control node), thereby reducing the voltage of the portion of the output first scanning signal Nscan1 (Nout2) that presents a step-shaped waveform, ensuring the stability of the waveform of the first scanning signal output from the first scanning signal output terminal Nout2, and improving the circuit stability when the display device turns on the frequency division display function.

[0053] In addition, by setting the sixth capacitor C6 in the first-stage transmission circuit 401, the pulse width of the scanning signal output by each stage of the gate driving circuit can be effectively controlled, thereby avoiding the problem in the prior art that the pulse width of the first scanning signal gradually increases with the increase in the number of stages. This technical solution not only ensures that the scanning signal output by each stage of the gate driving circuit has a stable pulse width, but also avoids the signal interference problem between adjacent stages caused by the excessive pulse width of the first scanning signal Nscan1 (Nout2), thereby improving the working reliability of the gate driving circuit, and further improving the display quality of the display device.

[0054] The display device provided in the embodiments of the present application can be applied to the field of flexible organic light-emitting diode display technology, and is particularly suitable for display panel products with a frequency division display function.

[0055] A first embodiment of a display device provided in the present application includes a display panel, which is an organic light emitting diode display panel. The display panel includes multiple rows of pixels and a cascaded multi-stage gate driving circuit, wherein the first-stage gate driving circuit includes a first gate driving sub-circuit and a second gate driving sub-circuit, the first gate driving sub-circuit is used to output a first scanning signal Nscan1 (Nout2) to a row of pixels PX, and the second gate driving sub-circuit is used to output a second scanning signal to the same row of pixels PX.

[0056] The first gate driving sub-circuit includes a first stage transmission circuit 401 and a first output circuit 402 . The first output circuit 402 is used to output a first scanning signal Nscan1 (Nout2 ) to a row of pixels PX.

[0057] The first output circuit 402 includes an eighteenth transistor Ts18 , a twenty-first transistor Ts21 and a twenty-second transistor Ts22 , and a fifth capacitor C5 .

[0058] The gate of the eighteenth transistor Ts18 is electrically connected to the first control node I, the source of the eighteenth transistor Ts18 is electrically connected to the second control node F of the first-stage transfer circuit 401, and the drain of the eighteenth transistor Ts18 is electrically connected to the node H.

[0059] The gate of the twenty-first transistor Ts21 is electrically connected to the node G (the third control node) of the first-stage transfer circuit, the source of the twenty-first transistor Ts21 is electrically connected to the first low-level signal input terminal VGL1, and the drain of the twenty-first transistor Ts21 is electrically connected to the first scanning signal output terminal of the first gate driving sub-circuit.

[0060] The gate of the twenty-second transistor Ts22 is electrically connected to the node H (the drain of the eighteenth transistor Ts18 ), the source of the twenty-second transistor Ts22 is electrically connected to the first high level signal input terminal VGH1 of the display panel, and the drain of the twenty-second transistor Ts22 is electrically connected to the first scanning signal output terminal.

[0061] One plate of the fifth capacitor C5 is electrically connected to the node I (first control node) of the first output circuit 402 , and the other plate of the fifth capacitor C5 is electrically connected to the first low level signal input terminal VGL1 of the first gate driving sub-circuit.

[0062] In the top view of the gate driving circuit, the first high level signal line VGH1 is located at a first side of the first low level signal line VGL1 , and the fifth capacitor C5 is located at a second side of the first low level signal line VGL1 opposite to the first side.

[0063] In this embodiment, the first low-level signal line VGL1 of the first gate driving sub-circuit is used to transmit the low-level signal VGL1, and the gate driving circuit also includes a first high-level signal line VGH1 and a second high-level signal line VGH2. The first high-level signal line VGH1 and the second high-level signal line VGH2 are used to transmit high-level signals. The first high-level signal line VGH1 is electrically connected to the high-level signal input terminal of the odd-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit), and the second high-level signal line VGH2 is electrically connected to the high-level signal input terminal of the even-numbered gate driving circuit (including the first high-level signal input terminal VGH1 of the first gate driving sub-circuit and the second high-level signal input terminal VGH2 of the second gate driving sub-circuit).

[0064] In this embodiment, the first low level signal input terminal VGL1 of the first gate driving sub-circuit is used to receive the first low level signal VGL1, and the first high level signal input terminal VGH1 is used to receive the first high level signal VGH1. The voltage value of the first low level signal VGL1 can be, for example, -5 volts, and the voltage value of the first high level signal VGH1 can be, for example, 15 volts.

[0065] The first output circuit 402 further includes a nineteenth transistor Ts19, a twentieth transistor Ts20, and a fourth capacitor C4.

[0066] A gate of the nineteenth transistor Ts19 is electrically connected to the node D, a source of the nineteenth transistor Ts19 is electrically connected to the first high-level signal input terminal VGH1 , and a drain of the nineteenth transistor Ts19 is electrically connected to the node H.

[0067] The gate of the twentieth transistor Ts20 is electrically connected to the node D, the source of the twentieth transistor Ts20 is electrically connected to the first control signal input terminal CTRL1 , and the drain of the twentieth transistor Ts20 is electrically connected to the gate of the eighteenth transistor.

[0068] One plate of the fourth capacitor C4 is electrically connected to the node H, and the other plate of the fourth capacitor C4 is electrically connected to the first high level signal input terminal VGH1.

[0069] The first stage transmission circuit 401 is used to output a stage transmission signal to the first gate driving sub-circuit of the gate driving circuit of other stages.

[0070] The first-stage transmission circuit 401 includes a first transistor Ts1, a second transistor Ts2, a third transistor Ts3, a fourth transistor Ts4, a fifth transistor Ts5, a sixth transistor Ts6, a seventh transistor Ts7, an eighth transistor Ts8, a ninth transistor Ts9, a tenth transistor Ts10, an eleventh transistor Ts11, a twelfth transistor Ts12, a thirteenth transistor Ts13, a fourteenth transistor Ts14, a fifteenth transistor Ts15, a sixteenth transistor Ts16, a seventeenth transistor Ts17, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0071] A gate of the first transistor Ts1 is electrically connected to the node C, and a source of the first transistor Ts1 is electrically connected to the first high level signal input terminal VGH1.

[0072] The gate of the second transistor Ts2 is electrically connected to the node E, the source of the second transistor Ts2 is electrically connected to the first clock signal input terminal CK, and the drain of the second transistor Ts2 is electrically connected to the drain of the first transistor Ts1.

[0073] The gate of the third transistor Ts3 is electrically connected to the second clock signal input terminal XCK, the source of the third transistor Ts3 is electrically connected to the first-stage transmission signal input terminal Nin, and the drain of the third transistor Ts3 is electrically connected to the node D.

[0074] The gate of the fourth transistor Ts4 is electrically connected to the second clock signal input terminal XCK, the source of the fourth transistor 4Ts is electrically connected to the first low level signal input terminal VGL1, and the drain of the fourth transistor Ts4 is electrically connected to the node C.

[0075] A gate of the fifth transistor Ts5 is electrically connected to the node D, a source of the fifth transistor Ts5 is electrically connected to the second clock signal input terminal XCK, and a drain of the fifth transistor Ts5 is electrically connected to the node C.

[0076] The gate of the sixth transistor Ts6 is electrically connected to the node B, the source of the sixth transistor Ts6 is electrically connected to the first clock signal input terminal CK, and the drain of the sixth transistor Ts6 is electrically connected to the node A.

[0077] A gate of the seventh transistor Ts7 is electrically connected to the first clock signal input terminal CK, and a source of the seventh transistor Ts7 is electrically connected to the node A.

[0078] A gate of the eighth transistor Ts8 is electrically connected to the node D, a source of the eighth transistor Ts8 is electrically connected to the first high level signal input terminal VGH1 , and a drain of the eighth transistor Ts8 is electrically connected to the node F (the second control node).

[0079] The gate of the ninth transistor Ts9 is electrically connected to the node G (the third control node), the source of the ninth transistor Ts9 is electrically connected to the first low level signal input terminal VGL1, and the drain of the ninth transistor Ts9 is electrically connected to the first stage signal output terminal Nout1.

[0080] The gate of the tenth transistor Ts10 is electrically connected to the node F (the second control node), the source of the tenth transistor Ts10 is electrically connected to the first high level signal input terminal VGH1 , and the drain of the tenth transistor Ts10 is electrically connected to the first stage signal output terminal Nout1 .

[0081] The gate of the eleventh transistor Ts11 is electrically connected to the first low-level signal input terminal VGL1 , the source of the eleventh transistor Ts11 is electrically connected to the node C, and the drain of the eleventh transistor Ts11 is electrically connected to the node B.

[0082] A gate of the twelfth transistor Ts12 is electrically connected to the first low-level signal input terminal VGL1 , a source of the twelfth transistor Ts12 is electrically connected to the node D, and a drain of the twelfth transistor Ts12 is electrically connected to the node G (the third control node).

[0083] A gate of the thirteenth transistor Ts13 is electrically connected to the first control signal input terminal CTRL1 , a source of the thirteenth transistor Ts13 is electrically connected to the first high level signal input terminal VGH1 , and a drain of the thirteenth transistor Ts13 is electrically connected to the node D.

[0084] A gate of the fourteenth transistor Ts14 is electrically connected to the second clock signal input terminal XCK, and a source of the fourteenth transistor Ts14 is electrically connected to the first-stage transmission signal input terminal Nin.

[0085] The gate of the fifteenth transistor Ts15 is electrically connected to the first low-level signal input terminal VGL1 , the source of the fifteenth transistor Ts15 is electrically connected to the drain of the fourteenth transistor Ts14 , and the drain of the fifteenth transistor Ts15 is electrically connected to the node E.

[0086] A gate of the sixteenth transistor Ts16 is electrically connected to the node E, a source of the sixteenth transistor Ts16 is electrically connected to the node E, and a drain of the sixteenth transistor Ts16 is electrically connected to the node G (third control node).

[0087] The gate of the seventeenth transistor Ts17 is electrically connected to the second control signal input terminal CTRL2 , the source of the seventeenth transistor Ts17 is electrically connected to the drain of the seventh transistor Ts7 , and the drain of the seventeenth transistor Ts17 is electrically connected to the node F (the second control node).

[0088] One plate of the first capacitor C1 is electrically connected to the node E, and the other plate of the first capacitor C1 is electrically connected to the drain of the first transistor Ts1.

[0089] One plate of the second capacitor C2 is electrically connected to the node A, and the other plate of the second capacitor C2 is electrically connected to the node B.

[0090] One plate of the third capacitor C3 is electrically connected to the node F (the second control node), and the other plate of the third capacitor C3 is electrically connected to the first high level signal input terminal VGH1 .

[0091] In addition, the channel width of the ninth transistor Ts9 in the first-stage transmission circuit 401 is greater than or equal to 20 microns, preferably, the channel width of the ninth transistor Ts9 is in the range of 30 microns to 50 microns, and more preferably, the channel width of the ninth transistor Ts9 is 40 microns. By increasing the channel width of the ninth transistor Ts9, the output capacity of the ninth transistor Ts9 is improved, thereby further improving the stability of the waveform of the stage transmission signal output by the first-stage transmission signal output terminal Nout1, and improving the circuit stability when the display device turns on the frequency division display function.

[0092] The first-stage transmission circuit 401 further includes a sixth capacitor C6 , one plate of the sixth capacitor C6 is electrically connected to the node G (the third control node), and the other plate of the sixth capacitor C6 is electrically connected to the first-stage transmission signal output terminal Nout1 .

[0093] By setting the sixth capacitor C6 between the node G (the third control node) and the first-stage signal transmission output terminal Nout1, when the signal of the first-stage signal transmission output terminal Nout1 switches from a high potential to a low potential, the sixth capacitor C6 can pull down the potential of the node G (the third control node), thereby reducing the voltage of the portion of the output scanning signal that presents a step-shaped waveform, thereby ensuring the stability of the waveform of the stage transmission signal output by the first-stage signal transmission output terminal Nout1.

[0094] The display panel also includes a second high-level signal line VGH2, which is electrically connected to the second gate driving sub-circuit. In the top view of the gate driving circuit, the first high-level signal line VGH1 and the second high-level signal line VGH2 cross the first gate driving sub-circuit and the second gate driving sub-circuit, and the first low-level signal line VGL1 and the second low-level signal line VGL2 cross the first gate driving sub-circuit and the second gate driving sub-circuit.

[0095] In the top view of the gate driving circuit, the second high level signal line VGH2 is located at a first side of the first low level signal line VGL1 of the first gate driving sub-circuit.

[0096] The line width of any point of the first high-level signal line VGH1 is the same as the line width of any point of the second high-level signal line VGH2, the line width of any point of the first low-level signal line VGL1 is the same as the line width of any point of the second low-level signal line VGL2, and the resistivity of the first high-level signal line VGH1 and the second high-level signal line VGH2 is the same, and the resistivity of the first low-level signal line VGL1 and the second low-level signal line VGL2 is the same, so that the load of each signal line can be more uniform, thereby improving the working stability of the gate drive circuit.

[0097] The second embodiment of the display device provided in the present application is similar to the first embodiment, except that: One plate of the fifth capacitor C5 is electrically connected to the node I (the first control node) of the first output circuit 402 , and the other plate of the fifth capacitor C5 is electrically connected to the second low level signal input terminal VGL2 of the display panel.

[0098] In the top view of the gate driving circuit, the first high level signal line VGH1 is located on a first side of the second low level signal line VGL2, the fifth capacitor C5 is located on a second side of the second low level signal line VGL2 opposite to the first side, and the first low level signal line VGL1 is located on a side of the first high level signal line VGH1 away from the second low level signal line VGL2.

[0099] By electrically connecting the other electrode plate of the fifth capacitor C5 to the second low-level signal input terminal VGL2 , it is also possible to avoid the fifth capacitor C5 from having a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal VGH1 .

[0100] The display panel further includes a second high-level signal line VGH2, and in the top view of the gate driving circuit, the second high-level signal line VGH2 is located between the second low-level signal line VGL2 and the first low-level signal line VGL1. That is, in the top view of the gate driving circuit, the second low-level signal line VGL2 of the second gate driving sub-circuit is arranged between the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 and the fifth capacitor C5, and the first low-level signal line VGL1 is arranged on a side of the whole formed by the first high-level signal line VGH1 and the second high-level signal line VGH2 away from the fifth capacitor C5.

[0101] In the display device provided in the embodiment of the present application, since one plate of the fifth capacitor C5 in the first output circuit 402 of the first gate driving sub-circuit in the gate driving circuit is electrically connected to the node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, and the first high-level signal input terminal VGH1 is insulated from the fifth capacitor C5, when the first control signal input terminal CTRL1 inputs the first control signal to the node I (first control node), the fifth capacitor C5 will not have a coupling effect on the potential of the signal transmitted by the first high-level signal input terminal VGH1, thereby avoiding the problem of fluctuation of the potential of the signal transmitted by the first high-level signal input terminal VGH1 due to the coupling effect between the fifth capacitor C5 and the first high-level signal input terminal VGH1.

[0102] Furthermore, since the potential of the signal transmitted by the first high-level signal input terminal VGH1 will not fluctuate due to the coupling effect of the fifth capacitor C5, and the first gate driving subcircuit generates the first scanning signal Nscan1 (Nout2) according to the signals transmitted by the first high-level signal input terminal VGH1 and the first low-level signal input terminal VGL1, the potential of the first scanning signal Nscan1 (Nout2) will not fluctuate due to the coupling effect of the fifth capacitor C5. Since the potential of the first scanning signal Nscan1 (Nout2) does not fluctuate, the turning on or off of the third transistor in the pixel driving circuit of the pixel PX will not be affected, and the second capacitor electrically connected to the drain of the third transistor will not exert a coupling effect on the gate of the second transistor also electrically connected to the second capacitor, thereby not affecting the turning on or off of the second transistor, thereby avoiding the problem of abnormal data signal writing.

[0103] In addition, since the data signal can be written into the pixel PX normally, when the display device turns on the frequency division display function, there will be no display abnormality at the boundary between different areas due to abnormal data signal writing, thereby improving the display effect of the display device when the frequency division display function is turned on.

[0104] In addition, since one plate of the fifth capacitor C5 is electrically connected to the node I (first control node) of the first output circuit 402, and the other plate is electrically connected to the first low-level signal input terminal VGL1 of the first gate driving sub-circuit or the second low-level signal input terminal VGL2 of the second gate driving sub-circuit, instead of being electrically connected to the first high-level signal input terminal VGH1, in the layout of the gate driving circuit, the first low-level signal line VGL1 of the first gate driving sub-circuit or the second low-level signal line VGL2 of the second gate driving sub-circuit can be set in the first high-level signal line VGH1 and the second high-level signal line VGH2. and between the entirety of the first high-level signal line VGH1 and the fifth capacitor C5, thereby making the layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 more uniform, avoiding the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2 caused by the fifth capacitor C5 being electrically connected to the first high-level signal input terminal VGH1 and occupying the routing space of the first high-level signal line VGH1 and / or the second high-level signal line VGH2, thereby avoiding the uneven load problem caused by the uneven layout of the first high-level signal line VGH1 and the second high-level signal line VGH2, and improving the working stability of the gate drive circuit.

[0105] The embodiments of the present application are described in detail above, and the contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display panel includes a plurality of rows of pixels and a plurality of gate drive circuits, wherein the gate drive circuit at one level includes: A first gate driving sub-circuit, wherein the first gate driving sub-circuit includes a first stage transmission circuit and a first output circuit, wherein the first output circuit includes: an eighteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the first control node I, and a source of the eighteenth transistor is electrically connected to the second control node F of the first-stage transmission circuit; a twenty-first transistor, wherein a gate of the twenty-first transistor is electrically connected to a third control node G of the first-stage transmission circuit, a source of the twenty-first transistor is electrically connected to a first low-level signal input terminal of the display panel, and a drain of the twenty-first transistor is electrically connected to a first scanning signal output terminal of the first gate driving sub-circuit; a twenty-second transistor, a gate of the twenty-second transistor being electrically connected to the drain of the eighteenth transistor, a source of the twenty-second transistor being electrically connected to the first high-level signal input terminal of the display panel, and a drain of the twenty-second transistor being electrically connected to the first scanning signal output terminal; and a fifth capacitor, wherein one plate of the fifth capacitor is electrically connected to the first control node I, and another plate of the fifth capacitor is electrically connected to the first low-level signal input terminal; Wherein, in the top view of the gate driving circuit, the first high-level signal line is located on a first side of the first low-level signal line, and the fifth capacitor is located on a second side of the first low-level signal line opposite to the first side.

2. The display device according to claim 1, characterized in that The first output circuit further includes: a nineteenth transistor, wherein a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, wherein a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and A fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

3. The display device according to claim 1, characterized in that The first stage transmission circuit comprises: a first transistor, wherein a gate of the first transistor is electrically connected to the node C, and a source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, wherein a gate of the second transistor is electrically connected to the node E, a source of the second transistor is electrically connected to the first clock signal input terminal, and a drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, wherein a gate of the third transistor is electrically connected to the second clock signal input terminal, a source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and a drain of the third transistor is electrically connected to a node D; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the second clock signal input terminal, a source of the fourth transistor is electrically connected to the first low level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the node D, a source of the eighth transistor is electrically connected to the first high-level signal input terminal, and a drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the third control node G, a source of the ninth transistor is electrically connected to the first low-level signal input terminal, and a drain of the ninth transistor is electrically connected to the first-stage signal output terminal; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second control node F, a source of the tenth transistor is electrically connected to the first high level signal input terminal, and a drain of the tenth transistor is electrically connected to the first stage signal output terminal; an eleventh transistor, a gate of the eleventh transistor being electrically connected to the first low-level signal input terminal, a source of the eleventh transistor being electrically connected to the node C, and a drain of the eleventh transistor being electrically connected to the node B; a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to the first low-level signal input terminal, a source of the twelfth transistor is electrically connected to the node D, and a drain of the twelfth transistor is electrically connected to the third control node G; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to the first control signal input terminal, a source of the thirteenth transistor is electrically connected to the first high level signal input terminal, and a drain of the thirteenth transistor is electrically connected to the node D; a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and a source of the fourteenth transistor is electrically connected to the first stage transmission signal input terminal; a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, a source of the fifteenth transistor is electrically connected to a drain of the fourteenth transistor, and a drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the node E, a source of the sixteenth transistor is electrically connected to the node E, and a drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the second control signal input terminal, a source of the seventeenth transistor is electrically connected to a drain of the seventh transistor, and a drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, wherein one plate of the first capacitor is electrically connected to the node E, and another plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor being electrically connected to the node A, and another plate of the second capacitor being electrically connected to the node B; and A third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high level signal input terminal.

4. The display device according to claim 3, characterized in that: The first stage transmission circuit also includes: A sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage signal output terminal.

5. The display device according to claim 1, characterized in that The display panel also includes a second gate driving subcircuit and a second high-level signal line, the second gate driving subcircuit is electrically connected to the second high-level signal line, and in a top view of the gate driving circuit, the second high-level signal line is located on a first side of the first low-level signal line.

6. A display device, characterized in that: The display panel includes a plurality of rows of pixels and a plurality of gate drive circuits, wherein the gate drive circuit at one level includes: A first gate driving sub-circuit, wherein the first gate driving sub-circuit includes a first stage transmission circuit and a first output circuit, wherein the first output circuit includes: an eighteenth transistor, wherein a gate of the eighteenth transistor is electrically connected to the first control node I, and a source of the eighteenth transistor is electrically connected to the second control node F of the first-stage transmission circuit; a twenty-first transistor, wherein a gate of the twenty-first transistor is electrically connected to a third control node G of the first-stage transmission circuit, a source of the twenty-first transistor is electrically connected to a first low-level signal input terminal of the display panel, and a drain of the twenty-first transistor is electrically connected to a first scanning signal output terminal of the first gate driving sub-circuit; a twenty-second transistor, a gate of the twenty-second transistor being electrically connected to the drain of the eighteenth transistor, a source of the twenty-second transistor being electrically connected to the first high-level signal input terminal of the display panel, and a drain of the twenty-second transistor being electrically connected to the first scanning signal output terminal; and a fifth capacitor, wherein one plate of the fifth capacitor is electrically connected to the first control node I, and another plate of the fifth capacitor is electrically connected to the second low-level signal input terminal of the display panel; Among them, in the top view of the gate drive circuit, the first high-level signal line is located on a first side of the second low-level signal line, the fifth capacitor is located on a second side of the second low-level signal line opposite to the first side, and the first low-level signal line is located on a side of the first high-level signal line away from the second low-level signal line.

7. The display device according to claim 6, characterized in that: The first output circuit further includes: a nineteenth transistor, wherein a gate of the nineteenth transistor is electrically connected to the node D, a source of the nineteenth transistor is electrically connected to the first high level signal input terminal, and a drain of the nineteenth transistor is electrically connected to the node H; a twentieth transistor, wherein a gate of the twentieth transistor is electrically connected to the node D, a source of the twentieth transistor is electrically connected to the first control signal input terminal, and a drain of the twentieth transistor is electrically connected to the gate of the eighteenth transistor; and A fourth capacitor, one plate of the fourth capacitor is electrically connected to the node H, and the other plate of the fourth capacitor is electrically connected to the first high-level signal input terminal.

8. The display device according to claim 6, characterized in that: The first gate driving sub-circuit further includes a first-stage transmission circuit, and the first-stage transmission circuit includes: a first transistor, wherein a gate of the first transistor is electrically connected to the node C, and a source of the first transistor is electrically connected to the first high-level signal input terminal; a second transistor, wherein a gate of the second transistor is electrically connected to the node E, a source of the second transistor is electrically connected to the first clock signal input terminal, and a drain of the second transistor is electrically connected to the drain of the first transistor; a third transistor, wherein a gate of the third transistor is electrically connected to the second clock signal input terminal, a source of the third transistor is electrically connected to the first-stage transmission signal input terminal, and a drain of the third transistor is electrically connected to a node D; a fourth transistor, wherein a gate of the fourth transistor is electrically connected to the second clock signal input terminal, a source of the fourth transistor is electrically connected to the first low level signal input terminal, and a drain of the fourth transistor is electrically connected to the node C; a fifth transistor, wherein a gate of the fifth transistor is electrically connected to the node D, a source of the fifth transistor is electrically connected to the second clock signal input terminal, and a drain of the fifth transistor is electrically connected to the node C; a sixth transistor, wherein a gate of the sixth transistor is electrically connected to the node B, a source of the sixth transistor is electrically connected to the first clock signal input terminal, and a drain of the sixth transistor is electrically connected to the node A; a seventh transistor, wherein a gate of the seventh transistor is electrically connected to the first clock signal input terminal, and a source of the seventh transistor is electrically connected to the node A; an eighth transistor, wherein a gate of the eighth transistor is electrically connected to the node D, a source of the eighth transistor is electrically connected to the first high-level signal input terminal, and a drain of the eighth transistor is electrically connected to the second control node F; a ninth transistor, wherein a gate of the ninth transistor is electrically connected to the third control node G, a source of the ninth transistor is electrically connected to the first low-level signal input terminal, and a drain of the ninth transistor is electrically connected to the first-stage signal output terminal; a tenth transistor, wherein a gate of the tenth transistor is electrically connected to the second control node F, a source of the tenth transistor is electrically connected to the first high level signal input terminal, and a drain of the tenth transistor is electrically connected to the first stage signal output terminal; an eleventh transistor, a gate of the eleventh transistor being electrically connected to the first low-level signal input terminal, a source of the eleventh transistor being electrically connected to the node C, and a drain of the eleventh transistor being electrically connected to the node B; a twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to the first low-level signal input terminal, a source of the twelfth transistor is electrically connected to the node D, and a drain of the twelfth transistor is electrically connected to the third control node G; a thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to the first control signal input terminal, a source of the thirteenth transistor is electrically connected to the first high level signal input terminal, and a drain of the thirteenth transistor is electrically connected to the node D; a fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the second clock signal input terminal, and a source of the fourteenth transistor is electrically connected to the first stage transmission signal input terminal; a fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to the first low-level signal input terminal, a source of the fifteenth transistor is electrically connected to a drain of the fourteenth transistor, and a drain of the fifteenth transistor is electrically connected to the node E; a sixteenth transistor, wherein a gate of the sixteenth transistor is electrically connected to the node E, a source of the sixteenth transistor is electrically connected to the node E, and a drain of the sixteenth transistor is electrically connected to the third control node G; a seventeenth transistor, wherein a gate of the seventeenth transistor is electrically connected to the second control signal input terminal, a source of the seventeenth transistor is electrically connected to a drain of the seventh transistor, and a drain of the seventeenth transistor is electrically connected to the second control node F; a first capacitor, wherein one plate of the first capacitor is electrically connected to the node E, and another plate of the first capacitor is electrically connected to the drain of the first transistor; a second capacitor, one plate of the second capacitor being electrically connected to the node A, and another plate of the second capacitor being electrically connected to the node B; and A third capacitor, one plate of the third capacitor is electrically connected to the second control node F, and the other plate of the third capacitor is electrically connected to the first high level signal input terminal.

9. The display device according to claim 8, characterized in that: The first stage transmission circuit also includes: A sixth capacitor, one plate of the sixth capacitor is electrically connected to the third control node G, and the other plate of the sixth capacitor is electrically connected to the first-stage signal output terminal.

10. The display device according to claim 6, characterized in that: The display panel also includes a second gate driving subcircuit and a second high-level signal line, the second gate driving subcircuit is electrically connected to the second high-level signal line and the second low-level signal line, and in a top view of the gate driving circuit, the second high-level signal line is located on a first side of the second low-level signal line, and the second high-level signal line is located between the first low-level signal line and the second low-level signal line.

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