Memory cells, integrated circuits, and methods of forming same

Abstract

Some embodiments relate to a memory cell comprising: a write transistor on a substrate comprising a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor on the substrate including a second gate terminal coupled to the storage node and a gate dielectric having a first capacitance; and a capacitor spaced apart from the first read transistor and the write transistor and also spaced apart from the substrate by the first read transistor and the write transistor, where the capacitor is coupled to the storage node and has a second capacitance greater than twice the first capacitance. The embodiment of the invention also relates to an integrated circuit and a method of forming a gain cell random access memory cell.

Description

Technical Field

[0001] Embodiments of the present application relate to memory cells, integrated circuits, and methods of forming gain cell random access memory cells. Background Art

[0002] The integrated circuit (IC) manufacturing industry has experienced exponential growth over the past few decades. As integrated circuits have evolved, a variety of different memory storage methods have been developed to meet different requirements. One advancement in the evolution of memory storage includes random access memory (RAM). RAM is a type of memory that can be read or written in any order. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory cell is provided, comprising: a write transistor, located on a substrate, comprising a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor, located on the substrate, and comprising a second gate terminal coupled to the storage node; and a capacitor, spaced apart from the first read transistor and the write transistor, and further spaced apart from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node, wherein the memory cell has a first area, the capacitor has a second area, and wherein a ratio of the second area to the first area is equal to or less than 0.8.

[0004] According to another aspect of an embodiment of the present application, an integrated circuit is provided, comprising: a plurality of memory cells having a first area located in a plurality of rows and a plurality of columns, wherein each memory cell comprises: a write transistor comprising a first gate terminal electrically coupled to a storage node, a first source / drain region, and a second source / drain region; a first read transistor comprising a second gate terminal electrically coupled to the storage node, a third source / drain region, and a fourth source / drain region; and a capacitor electrically coupled to the storage node, wherein the capacitor has a second area, and wherein a ratio of the second area to the first area is equal to or less than 0.8; a write bit line electrically coupled to the first source / drain region for each of the plurality of memory cells in a first column of the plurality of columns; and a write word line electrically coupled to the first gate terminal for each of the plurality of memory cells in a first row of the plurality of rows.

[0005] According to another aspect of an embodiment of the present application, a method for forming a gain unit random access memory cell is provided, comprising: forming an isolation region in a substrate; forming a write transistor, a first read transistor, and a second read transistor on the substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by the isolation region; forming a first wiring level on the substrate, the first wiring level comprising a write bit line, a read bit line, and a plurality of interconnect lines, wherein the write bit line is coupled to a first source / drain region of the write transistor, and the read bit line is coupled to a first drain / source region of the second read transistor; forming a second wiring level on the first wiring level, the second wiring level comprising a storage node, wherein the storage node is coupled to the second source / drain region of the write transistor and a gate terminal of the first read transistor; and forming a capacitor on the second wiring level, the capacitor having a lower electrode coupled to the storage node, a high-k dielectric layer covering the lower electrode, and an upper electrode covering the high-k dielectric layer; and performing thermal annealing after forming the capacitor, the thermal annealing causing the material of the high-k dielectric layer to transform into a highly symmetric crystalline phase. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A-1E Circuit diagrams of various different embodiments of a gain cell random access memory (GCRAM) cell having a capacitor coupled to a storage node are shown.

[0008] Figure 2A-2B Top and three-dimensional views of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two parallel read transistors are shown.

[0009] Figure 3A-3B Top and three-dimensional views of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two read transistors coupled in series are shown.

[0010] Figure 4A-4E Cross-sectional views of various different embodiments of capacitors of a GCRAM cell are shown.

[0011] Figure 5A-Figure 5C A three-dimensional view of some embodiments of the crystalline phase of a high-k dielectric within a capacitor coupled to a GCRAM cell is shown.

[0012] Figure 6A-6BGraphs showing some embodiments of voltage measured within a GCRAM cell using a capacitor at a storage node and voltage measured within a GCRAM cell not using a capacitor on a storage node.

[0013] Figure 7 Circuit diagrams of some embodiments of a GCRAM array including multiple rows and multiple columns of GCRAM cells are shown.

[0014] Figure 8 Shows Figure 1C Timing diagrams for read and write operations performed by some embodiments of the illustrated circuits.

[0015] Figure 9-Figure 15 A series of three-dimensional views of some embodiments of methods of forming a GCRAM cell having a capacitor coupled to a storage node are shown.

[0016] Fig.16 A flow chart illustrating some embodiments of a method of forming a GCRAM cell having a capacitor coupled to a storage node. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0019] A gain cell random access memory (GCRAM) cell includes a write transistor and a read transistor. A first source / drain region of the write transistor is coupled to a write bit line, and a gate of the write transistor is coupled to a write word line. A second source / drain region of the write transistor is coupled to a gate of the read transistor, forming a storage node. The data value is represented by a charge at the storage node, which is stored by a capacitor on the storage node. In addition, the capacitance at the storage node is defined by the capacitance formed by the gate dielectric of the read transistor. During operation, data is written to the GCRAM cell by activating the write transistor, which forms a conductive channel between the write bit line and the storage node and stores charge at the storage node. The amount of charge is based on the voltage of the write bit line and the capacitance at the storage node.

[0020] Because a GCRAM cell can use only two transistors, it occupies less space (e.g., the space occupied by the memory cell on the substrate) than other types of memory. The smaller footprint results in GCRAM cells forming smaller memory arrays and / or denser memory arrays than other types of memory. For example, compared to a six-transistor static RAM (SRAM) array, a two-transistor or three-transistor GCRAM array can be half the size and twice as dense. Therefore, GCRAM arrays are suitable for a wide range of digital applications, including embedded memory, artificial intelligence applications, machine learning applications, L2 cache, L3 cache, etc.

[0021] While the CGRAM cell has many advantages, the GCRAM cell in its simplest form also has many disadvantages. Due to the low capacitance at the storage node, the charge retention of the GCRAM cell is lower than that of other memory cells. In addition, the read transistor and the write transistor have leakage currents (e.g., subthreshold leakage across the write transistor and gate leakage from either transistor) that may deplete or introduce unwanted charge at the storage node. The relatively small charge maintained at the storage node, combined with the leakage current, causes the GCRAM cell to have a lower charge retention rate than other types of memory. One solution is to introduce one or more refresh circuits to maintain the charge of the GCRAM cells in the array. However, the use of refresh circuits increases the space on the substrate dedicated to the GCRAM array and increases the power used to maintain the array, resulting in reduced power efficiency. A GCRAM cell with enhanced retention time is ideal without sacrificing the relatively small footprint of the GCRAM cell.

[0022] The present disclosure provides a GCRAM cell having a capacitor with a read transistor and a write transistor stacked vertically. For example, the capacitor may overlie the read and write transistors in the back end of line (BEOL) of an integrated circuit (IC), while the read and write transistors may be the front end of line (FEOL) of the IC.

[0023] The capacitor is coupled to the storage node in parallel with the capacitance formed by the gate dielectric of the read transistor. This increases the capacitance at the storage node, thereby increasing the charge at the storage node during writing. This increase results in a longer retention time because it takes longer for this secondary current to deplete the charge at the storage node. In addition, because the voltage at the storage node is proportional to the charge, the voltage at the gate of the read transistor remains at the written value for a longer time. In some embodiments, the improved retention time is more than 100 times the retention time of a GCRAM cell that does not use a capacitor. In addition, the capacitor does not increase the GCRAM cell because the lateral area is less than the lateral area of ​​a GCRAM cell without a capacitor.

[0024] Figure 1A-1E Circuit diagrams of various different embodiments of a GCRAM cell having a capacitor coupled to a storage node are shown. Figure 1A and Figure 1C corresponds to the two transistor embodiment, while Figure 1B and Figure 1D Corresponding to the three transistor embodiment.

[0025] like Figure 1A As shown in the circuit diagram 100a of FIG. 1 , the write transistor 102 and the first read transistor 104a are coupled together at the storage node 106. The write transistor 102 includes a first source / drain region 108, a first gate terminal 110, and a second source / drain region 112. As used herein, the source / drain region may refer to a source region or a drain region individually or collectively, depending on the context. The first source / drain region 108 is coupled to a write bit line 114. The first gate terminal 110 is coupled to a write word line 116. The second source / drain region 112 is coupled to the storage node 106. The first read transistor 104a includes a third source / drain region 118, a second gate terminal 120, and a fourth source / drain region 122. In some embodiments, the third source / drain region 118 is coupled to a read word line 124. In further embodiments, the fourth source / drain region 122 is coupled to a read bit line 126. The second gate terminal 120 is coupled to the storage node 106.

[0026] Capacitor 128 is coupled to storage node 106 and ground 130. In some embodiments, capacitor 128 is a three-dimensional BEOL capacitor. In other embodiments, capacitor 128 is a two-dimensional BEOL capacitor that includes a high-k dielectric having a highly symmetric crystallographic phase. In other embodiments, capacitor 128 is a three-dimensional BEOL capacitor that includes a high-k dielectric having a highly symmetric crystallographic phase. Capacitor 128 has a first capacitance. The first read transistor 104a has a gate dielectric and a second capacitance 129. For clarity, second capacitance 129 is shown as separate from the first read transistor 104a; second capacitance 129 is not a separate capacitor and is measured across the gate dielectric of the first read transistor 104a. The first capacitance is more than twice the second capacitance 129, and capacitor 128 is electrically coupled in parallel with the second capacitance 129. Therefore, the introduction of capacitor 128 increases the capacitance at storage node 106 by at least three times. The increase in capacitance at storage node 106 increases the charge stored at storage node 106 during a write operation. The increase in stored charge causes the leakage current of the write transistor 102 and the first read transistor 104a to take longer to reduce the stored charge. Therefore, the data retention rate is improved.

[0027] The GCRAM cell can store a "1" bit or a "0" bit. A "1" bit is stored during a write operation where the write bit line 114 is at a voltage (e.g., V dd ). A "0" bit is stored during a write operation, where the write bit line 114 is at a voltage (e.g., 0 volts) below the threshold voltage of the first read transistor 104a. During a write operation, the write transistor 102 is activated and charge flows between the write bit line 114 and the storage node 106, causing the storage node 106 to remain at the voltage on the write bit line 114. After the write operation, the write transistor 102 is deactivated, isolating the write bit line 114 from the storage node 106. The charge remains at the storage node 106, causing the storage node 106 to maintain the voltage introduced by the write bit line 114. During a read operation, by applying a voltage (e.g., V dd ) precharges the read bit line 126 and then sets the voltage of the read word line 124 to zero to read the stored bit. The resulting signal is then read by reading the voltage of the read bit line 126 after a read time interval. If the voltage measured at the read bit line 126 is equal to or approximately equal to the applied voltage, the voltage at the storage node is not above the threshold voltage and the stored voltage is determined to be a "0" bit. If the voltage measured at the read bit line 126 is at or approximately zero volts, the voltage at the storage node is above the threshold voltage and the stored voltage is determined to be a "1" bit.

[0028] The voltage at the storage node 106 is based on the voltage provided by the write bit line 114 during the write operation. The voltage at the storage node 106 is maintained by the presence of the charge held at the storage node 106 and is proportional to the charge held by the storage node 106. Therefore, when leakage current (e.g., gate leakage, subthreshold leakage, junction leakage, etc.) from the write transistor 102 and the first read transistor 104a changes the charge held at the storage node 106, the voltage is also affected.

[0029] When the voltage at the storage node 106 is at or near the threshold voltage of the first read transistor, noise in the IC accommodating the GCRAM cell may make the result of the read operation uncertain. That is, if the leakage current causes the maintained voltage to be close to the threshold voltage, the determination of the stored signal is mainly dominated by noise. The time required for the leakage current to introduce or take away enough charge to make the voltage at the storage node 106 reach the threshold voltage is called the retention time of the GCRAM cell. Due to the introduction of capacitor 128, the increase in capacitance and charge at the storage node 106 leads to a longer retention time. This can further reduce the footprint of the GCRAM array by reducing the number of refresh circuits used to maintain the storage node charge. The reduction of refresh circuits can further reduce power consumption.

[0030] like Figure 1B As shown in the circuit diagram 100b of FIG. 1 , in some embodiments, the second read transistor 104b is coupled to the first read transistor 104a. The second read transistor 104b has a fifth source / drain region 132 coupled to the fourth source / drain region 122, a third gate terminal 134 coupled to the read word line 124, and a sixth source / drain region 136 coupled to the read bit line 126. The third source / drain region 118 is coupled to a reset line 138, which is grounded during a read operation.

[0031] During a read operation, a voltage (e.g., V dd ) and applies a high voltage to the read word line 124 to select a GCRAM cell from the GCRAM array, thereby reading the GCRAM cell. The high voltage is high because it exceeds the threshold voltage of the second read transistor 104b. The voltage on the read bit line 126 is then measured. If the voltage measured at the read bit line 126 is equal to or approximately equal to the applied voltage, the voltage at the storage node is not higher than the threshold voltage, and the stored voltage is determined to be a "0" bit. If the voltage measured at the read bit line 126 is at or approximately zero volts, the voltage at the storage node is higher than the threshold voltage, and the stored voltage is determined to be a "1" bit.

[0032] like Figure 1C and Figure 1DAs shown in the circuit diagrams 100c and 100d, in some embodiments, Figure 1A and 1B The circuit depicted in FIG. 1 has an N-type write transistor 102. The write transistor 102 and the first read transistor 104a are or include P-type transistors or N-type transistors. In some embodiments, the write transistor 102 and the first read transistor 104a are the same transistor type (e.g., both are N-type transistors). In other embodiments, Figure 1A and Figure 1B As shown, the write transistor 102 and the first read transistor 104a are different transistor types (eg, the write transistor 101 is a P-type transistor and the first read transistor 104 is an N-type transistor).

[0033] like Figure 1E As shown in the circuit diagram 100e of FIG. 1 , in some embodiments, the GCRAM cell may include a plurality of transistors connected in parallel between a read bit line 126 and a read word line 124, the plurality of transistors including a first read transistor 104a and a parallel transistor 140. A second gate terminal 120 of the first read transistor 104a and a fourth gate terminal 142 of the parallel transistor 140 are coupled in parallel to the storage node 106. The parallel transistor 140 has a seventh source / drain region 144 coupled in parallel to the fourth source / drain region 122 of the first read transistor 104a to the read bit line 126. The first read transistor 104a and the parallel transistor 140 share a third source / drain region 118.

[0034] Figure 2A-2B A top view 200a and a three-dimensional view 200b of some embodiments of a GCRAM cell having a capacitor coupled to a storage node and two parallel read transistors are shown. Figure 2A-2B The GCRAM cell shown is Figure 1E An embodiment of the circuit shown. Figure 2A and Figure 2B .

[0035] The second gate terminal 120 of the first read transistor 104a and the fourth gate terminal 142 of the shunt transistor 140 are connected to each other through a plurality of contacts 206 ( Figure 2A The first through-hole level 208 (shown in dashed lines) and the first through-hole level 208 (shown in dashed lines) Figure 2B ) is connected to the storage node 106. The seventh source / drain region 144 of the shunt transistor 140 is coupled to the read bit line 126 in parallel with the fourth source / drain region 122 of the first read transistor 104a. The first read transistor 104a and the shunt transistor 140 share the third source / drain region 118.

[0036] The plurality of contacts 206 also extend to the first gate terminal 110 and the first, second, third and fourth source / drain regions 108, 112, 118, 122. The plurality of contacts 206 extend to a first wiring level including the write bit line 114, the read bit line 126 and the interconnect 207. The read bit line 126 and the write bit line 114 extend along a first direction 228. The first via level 208 extends between the first wiring level and a second wiring level including the storage node 106. In some embodiments, the write word line 116 and / or the read word line 124 are located on the second wiring level. The write word line 116 and the read word line 124 extend in a second direction 230 perpendicular to the first direction 228.

[0037] Capacitor 128( Figure 2A The third conductor level 212 is a conductive layer 214 (shown as a dashed line in the middle) that overlies the storage node 106 in the third direction 232 and is coupled to the storage node 106 through the second via level 210. The capacitor 128 also overlies the write transistor 102, the first read transistor 104a, and the shunt transistor 140. In some embodiments, the third conductive layer 212 extends between the capacitor 128 and the storage node 106. The third conductive layer 212 is used as a landing for a third via level 214 that extends between the third conductive layer 212 and the capacitor 128. The capacitor 128 is also coupled to the ground line 130 through the fourth via level 216.

[0038] In some embodiments, capacitor 128 includes a lower electrode 218, a high-k dielectric 220, and an upper electrode 222. In alternative embodiments, high-k dielectric 220 is replaced by a dielectric that does not have a high k. Lower electrode 218 and upper electrode 222 include conductive materials such as aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), platinum (Pt), tungsten (W), nickel (Ni), iridium (Ir), titanium nitride (TiN), tantalum nitride (Ta), etc. x N y ), iridium oxide (IrO2), negatively doped polysilicon material, positively doped polysilicon material, etc. High-k dielectrics include one or more metal oxides (e.g., hafnium oxide (Hf x O y , HfO2), hafnium silicon oxide (Hf x Si y O z ), Hafnium Aluminum Oxide (Hf x Al y O z ), Hafnium Oxide (Hf x G y O z ), hafnium zirconium oxide (Hf x Zr y O z ), Hafnium lanthanum oxide (Hfx La y O z ), hafnium strontium oxide (Hf x Sr y O z ), Hafnium Yttrium Oxide (Hf x Y y O z ), strontium titanium oxide (STO, SrTiO3), zirconium oxide (ZrO2), titanium oxide (TiO2), barium titanate (BaTiO3), etc.), metal nitride oxides (for example, hafnium oxynitride (HfON), zirconium oxynitride (ZrON), etc.), etc.

[0039] In some embodiments, the high-k dielectric has a highly symmetric crystalline phase, such as a cubic phase, a tetragonal phase, or a hexagonal phase. High-k dielectric materials having a highly symmetric crystalline phase have a greater dielectric constant than high-k dielectric materials in a non-highly symmetric crystalline phase. The dielectric constant of the high-k dielectric depends on the material used for the high-k dielectric and the symmetry of the material's crystalline phase. In some embodiments, the high-k dielectric 220 has a dielectric constant greater than 35. A dielectric constant greater than 35 results in the capacitance of capacitor 128 being more than twice the capacitance across the gate dielectric of the first read transistor 104a and the shunt transistor 140 without increasing the area of ​​the capacitor to more than 60% to 80% of the area of ​​the GCRAM cell. In some embodiments, if the dielectric constant is less than 35, capacitor 128 will have a lower capacitance, thereby reducing the charge held at the storage node and the resulting retention time of the GCRAM cell. When a three-dimensional capacitor configuration is used (see Figure 4B-Figure 4E ), the capacitance can be further increased.

[0040] In some embodiments, the write transistor 102, the first read transistor 104a, and the shunt transistor 140 are FEOL devices embedded in the substrate 224. The write transistor 102 and the first read transistor 104a are also separated from each other by the isolation region 226. In some embodiments, the FEOL device is or includes one or more of a planar FET, a FinFET (fin field effect transistor), a gate-all-around (GAA) device, etc. In some embodiments, when viewed from top to bottom, the first read transistor 104a, the write transistor 102, and the second read transistor 104b together span a first area, and wherein when viewed from top to bottom, the capacitor 128 spans a second area, which is between 60% and 80% of the first area.

[0041] Figure 3A-3B A top-down view 300a and a three-dimensional view 300b of some embodiments of a GCRAM cell are shown, where a capacitor is coupled to a storage node and two read transistors are coupled in series. Figure 3A-3B The GCRAM cell shown is Figure 1B One embodiment of the circuit shown. Figure 3A and Figure 3B For clarity, Figure 3A and Figure 3B The write word line 116 and the read word line 124 are not shown.

[0042] In some embodiments, the first read transistor 104a and the second read transistor 104b are coupled in series. In further embodiments, the fourth source / drain region 122 of the first read transistor 104a and the fifth source / drain region 132 of the second read transistor 104b overlap each other to form a shared source / drain region 302. The shared source / drain region 302 extends from the channel of the first read transistor 104a to the channel of the second read transistor 104b. The storage node 106 is coupled to the second source / drain region 112 of the write transistor 102 and the second gate terminal 120 of the first read transistor 104a, but is not coupled to the third gate terminal 134 of the second read transistor 104b. The third gate terminal 134 of the second read transistor 104b is instead coupled to the read word line 124.

[0043] In some embodiments, the first read transistor 104a, the write transistor 102, and the second read transistor 104b are located within a first GCRAM cell region 304 having a first area measured parallel to the upper surface of the substrate 224. The capacitor 128 has a second area measured parallel to the upper surface of the substrate 224. The second area is between 60% and 80% of the first area. In some embodiments, the first GCRAM cell region 304 has an outer boundary along the second direction 230 between the outermost sidewall of the first write transistor 102 and the outermost sidewall of the first read transistor 104a, and is confined between the outer edge of the first source / drain region 108 and the outer edge of the third source / drain region 118 in the first direction.

[0044] The area of ​​capacitor 128 is lower than the area of ​​first GCRAM cell region 304, resulting in the remaining area at the level of capacitor 128 being available for routing vias (e.g., first via 306) between capacitor 128 and other capacitors in the GCRAM cell array. In embodiments using routing between capacitors, the availability of space around capacitor 128 and routing first via 306 on first GCRAM cell region 304 increases implementation flexibility while reducing footprint. First via 306 is flush with capacitor 128 and extends between third wiring level 212 and fourth wiring level 308 that is flush with ground 130.

[0045] Figure 4A-4ECross-sectional views 400a, 400b, 400c, 400d, 400e of various different embodiments of capacitors of GCRAM cells having different configurations are shown.

[0046] like Figure 4A As shown, in some embodiments, capacitor 128 has a planar layout. Lower electrode 218 has a first thickness t1 between about 0.1 nanometers and 30 nanometers, between about 1 nanometer and 20 nanometers, or another similar range. High-k dielectric 220 has a second thickness t2 between about 1 nanometer and 10 nanometers, between about 2 nanometers and 8 nanometers, or another similar range. Upper electrode 222 has a third thickness t3 between about 0.1 nanometers and 30 nanometers, between about 1 nanometer and 20 nanometers, or another similar range. Capacitor 128 on substrate and other components of GCRAM cell (see Figure 2B 224) is surrounded by an interlayer dielectric 406. In order to maintain clarity, the interlayer dielectric 406 is not shown in the previous views.

[0047] like Figure 4B As shown, in some embodiments, capacitor 128 has a three-dimensional layout in which protrusions 404 extend from base 402 of upper electrode 222. The addition of protrusions 404 expands the surface area of ​​the electrodes in capacitor 128, thereby increasing the capacitance. In some embodiments, high-k dielectric 220 does not have a highly symmetric crystalline phase because the three-dimensional layout increases the capacitance of capacitor 128 to a value greater than that of the first read transistor (see Figure 1A 104a) and parallel transistors (see Figure 2A Twice the 140) (if present) capacitance.

[0048] like Figure 4C As shown, in some embodiments, capacitor 128 has a three-dimensional layout of a cylindrical configuration, wherein lower electrode 218 surrounds cylindrical protrusion 408 of upper electrode 222. Figure 4D As shown, in some embodiments, capacitor 128 has a three-dimensional layout of a multi-fin configuration, where lower electrode 218 includes multiple fins 410 surrounded by upper electrode 222. Figure 4E As shown, in some embodiments, the capacitor 128 has a three-dimensional layout of a multi-finger configuration, wherein the lower electrode 218 surrounds a dielectric structure 412 including a plurality of protrusions 414 , and the upper electrode 222 also surrounds the plurality of protrusions 404 .

[0049] Figure 5A-Figure 5C A plurality of three-dimensional views 500a, 500b, 500c of some embodiments of a crystalline phase of a high-k dielectric within a capacitor coupled to a GCRAM cell are shown. In some embodiments, the highly symmetric crystalline phase includes one of a cubic phase, a tetragonal phase, or a hexagonal phase.

[0050] like Figure 5A As shown in the three-dimensional view 500a of FIG. 5 , in some embodiments, a high-k dielectric (e.g., see Figure 2B or Figure 3B 220) has a cubic phase. In the cubic phase, the first lattice constant a1, the second lattice constant a2, and the third lattice constant a3 have equal lengths. The lattice constants a1, a2, and a3 represent the lengths of the unit cells along different repeating axes. In the cubic phase, the first lattice angle α, the second lattice angle β, and the third lattice angle γ are equal to 90 degrees. The lattice angles α, β, and γ represent the angles between the lattice constants of the unit cells.

[0051] like Figure 5B As shown in the three-dimensional view 500b of FIG. 5 , in some embodiments, a high-k dielectric (e.g., see Figure 2B or Figure 3B 220) has a tetragonal phase. In the tetragonal phase, the first lattice constant a1 and the second lattice constant a2 have equal lengths, and the third lattice constant a3 has a length different from the first lattice constant a1 and the second lattice constant a2. In addition, the first lattice angle α, the second lattice angle β, and the third lattice angle γ of the unit cell in the tetragonal phase are equal to 90 degrees.

[0052] like Figure 5C As shown in the three-dimensional view 500c of FIG. 5 , in some embodiments, a high-k dielectric (e.g., see Figure 2B or Figure 3B 220) has a hexagonal phase. In the hexagonal phase, the first lattice constant a1, the second lattice constant a2, and the third lattice constant a3 have equal lengths, and the fourth lattice constant C has a length different from the first lattice constant a1. In addition, the first lattice angle α, the second lattice angle β, and the third lattice angle γ of the unit cell in the hexagonal phase are equal to 120 degrees, and the fourth lattice angle θ is equal to 90 degrees.

[0053] Figure 6A-6B Graphs 600a, 600b illustrate some embodiments of voltage measured within a GCRAM cell using a capacitor and voltage measured within a GCRAM cell not using a capacitor at a storage node.

[0054] like Fig. 6A As shown in the curve diagram 600a, at the storage node (see Figure 1A 106) has a capacitor (see Figure 1A In the embodiment of 128 in FIG. 128 , for the first time period 603, when a “1” bit is written to the GCRAM cell, a first voltage 602 measured at the storage node is higher than a second voltage 604 measured at the storage node when a “0” bit is written to the GCRAM cell. Figure 1A 106) without capacitor (see Figure 1A 128), for the second time period 607, the third voltage 606 measured at the storage node when a "1" bit is written to the GCRAM cell is higher than the fourth voltage 608 measured at the storage node when a "0" bit is written to the GCAM cell. That is, after the second time period 607, in the embodiment without the capacitor, the third voltage 606 measured at the storage node when a "1" bit is written to the GCRAM cell is higher than the fourth voltage 608 measured at the storage node when a "0" bit is written to the GCAM cell. Figure 1A The voltage measured at 106 of the capacitor no longer indicates the value initially stored. The first time period 603 is greater than the second time period 607. In some embodiments, the first capacitance of the capacitor (see Figure 1A 128) is more than twice the second capacitance measured on the gate dielectric of the first read transistor, and the first time period 603 is more than 100 times the second time period 607.

[0055] like Figure 6B As shown in the curve diagram 600b, at the storage node (see Figure 1B 106 and a second read transistor (see Figure 1B 104b) has a capacitor (see Figure 1B In an embodiment of 128), when a "1" bit is stored and a "0" bit is stored, a first difference 610 of the voltage measurement performed at the read bit line is a first value 614 after a first time period 615. When the storage node stores a "1" bit and is not refreshed, the difference 610 of the voltage measurement is obtained by measuring the read bit line at multiple time intervals (see Figure 1B The voltage of 126 is found. Then the voltage of the storage node storing a "0" bit is measured at multiple time intervals. The bit line is read (see Figure 1B The resulting "0" bit voltage measurement is subtracted from the "1" bit voltage measurement to obtain the difference 610 of the voltage measurements shown in the graph 600b.

[0056] On the storage node (see Figure 1A 106) without a capacitor, the second difference 612 of the voltage measurement performed at the read bit line when storing a "1" bit and storing a "0" bit is a second value 616 after the first time period 615. In both embodiments, the voltage difference between the "1" bit reading and the "0" bit reading decays over time. However, in the case of a capacitor (see Figure 1A 128) coupled to the storage node (see Figure 1A 106), the initial voltage difference between the two measurements is greater than that without the capacitor (see Figure 1A In the embodiment of 128) the voltage difference is measured. In addition, in the capacitor (see Figure 1A 128) coupled to the storage node (see Figure 1A In the embodiment of 106), the voltage difference between the two measurements at the subsequent measurement interval is also greater than that without the capacitor (see Figure 1A 128) in the embodiment of the invention. With a capacitor (see Figure 1A The voltage measurement difference 610 of the embodiment of 128) is greater than that without the capacitor (see Figure 1A 128) embodiment, the voltage measurement difference 612 decays at a slower rate.

[0057] Figure 7 Circuit diagram 700 of some embodiments of a GCRAM array including multiple rows and multiple columns of GCRAM cells is shown.

[0058] The GCRAM array includes a plurality of GCRAM cells 702a-702f in a plurality of rows 704a, 704b, 704c and columns 706a, 706b. The GCRAM cells in the first column 706a (e.g., the first GCRAM cell 702a, the second GCRAM cell 702b, and the third GCRAM cell 702c) are coupled to the first write bit line 114a and the first read bit line 126a. The GCRAM cells in the second column 706b (e.g., the fourth GCRAM cell 702d, the fifth GCRAM cell 702e, and the sixth GCRAM cell 702f) are coupled to the second write bit line 114b and the second read bit line 126b. The GCRAM cells in the first row 704a (e.g., the first GCRAM cell 702a and the fourth GCRAM cell 702d) are coupled to the first write word line 116a and the first read word line 124a. The GCRAM cells in the second row 704b (e.g., the second GCRAM cell 702b and the fifth GCRAM cell 702e) are coupled to the second write word line 116b and the second read word line 124b. The GCRAM cells in the third row 704c (e.g., the third GCRAM cell 702c and the sixth GCRAM cell 701f) are coupled to the third write word line 116c and the third read word line 124c.

[0059] The first GCRAM cell 702a is shown coupled to the first write bit line 114a, the first write word line 116a, the first read bit line 126a, and the first read word line 124a. The second GCRAM cell 702b and the third GCRAM cell 702c are located in a first column 706a of the plurality of columns along with the first GCRAM cell 702a. The second GCRAM cell 702b and the third GCRAM cell 702c are coupled to the first write bit line 114a and the first read bit line 126a, the second GCAM cell 702b is coupled to the second read word line 116b and the second read word line 124b, and the third GCAM cell 702c is coupled to the third write word line 116c and the third read word line 124c. The first GCRAM cell 702a and the fourth GCRAM cell 702d are located in a first row 704a of the plurality of rows. The first GCRAM cell 702a and the fourth GCRAM cell 702d are coupled to the first write word line 116a and the first read word line 124a, but the fourth GCRAM cell 702d is coupled to the second write word line 116b and the first read word line 124a.

[0060] Figure 8 Shown by Figure 1C A timing diagram 800 of read and write operations performed by some embodiments of the illustrated circuit.

[0061] Timing diagram 800 shows the signals provided to the GCRAM cell during operation. When writing a "1" bit, during write operation 802, the write bit line (see Figure 1B 114) is driven to a high voltage (e.g. V dd ), as shown by write bit line signal 114sa. When writing a "0" bit, during write operation 802, the write bit line (see Figure 1B 114) is driven to a low voltage (e.g., 0 volts), as indicated by a second write bit line signal 114sb. In some embodiments, when the write transistor (see Figure 1B 102) is a p-type transistor, write word line (see Figure 1B 116) is driven below the write transistor ( Figure 1B 102) threshold voltage low voltage (e.g. -V dd ), as shown by the write word line signal 116s, the write bit line (see Figure 1B 114) coupled to the storage node (see Figure 1B The write word line signal 116s then returns to its original voltage (eg, 0 volts) until another write operation is required.

[0062] Prior to the read operation 804, the bit lines are read (see Figure 1B 126) is driven to a high voltage (e.g. Vdd ), as shown in the precharge phase 806 of the read bit line signal 126s. The read operation 804 begins by reading the word line (see Figure 1B 124) is driven to a high voltage (eg, V dd ), as shown by the read word line signal 124s. Figure 1B The read word line signal 124s above the threshold voltage of 104b) couples the read bit line signal 126s to the first read transistor (see Figure 1B 104a) of the fourth source / drain region 122. Subsequently, if at the storage node (see Figure 1B 106) stores a "1" bit, due to the reset line (see Figure 1B 138), the read bit line signal 126s will be driven to a low voltage (e.g., 0 volts) during time period 808, and the reset line remains at 0 volts during the read operation 804. If a "0" bit is stored at the storage node (see Figure 1B 106), the read bit line signal 126s will remain at a high voltage (e.g., V dd ), since the first read transistor will not be activated and the reset line (see Figure 1B 138) will not couple to the read bit line (see Figure 1B In another precharge phase, the read bit line signal 126s is restored to a high voltage (e.g., V dd ) after which the read operation may be repeated in time periods T1 and T2.

[0063] Figure 9-Figure 15 A series of three-dimensional views 900-1500 of some embodiments of methods of forming a GCRAM cell having a capacitor coupled to a storage node are shown. Figure 9-Figure 15 Described as a series of actions, it should be understood that these actions are not limiting, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0064] like Fig. 9 As shown in the three-dimensional view 900 of FIG. 2 , the isolation region 226 is formed in the substrate 224. In some embodiments, the isolation region 226 is a shallow trench isolation region, a deep trench isolation region, or another type of isolation region. In some embodiments, the substrate 224 is or includes silicon, sapphire, etc., or any combination of the above materials. In some embodiments, the isolation region 226 is or includes an insulating material, such as silicon oxide (SiO2), silicon nitride (Si3N4), etc. The isolation region 226 is formed by etching an opening in the substrate and then subsequently filling the opening with an insulating material.

[0065] like Fig.10 As shown in the three-dimensional view 1000 of FIG. 1 , the write transistor 102, the first read transistor 104a, and the parallel transistor 140 are formed on the substrate 224. The transistors (e.g., the write transistor 102, the first read transistor 104a, and the parallel transistor 140) are formed by stacking gate dielectrics and gate terminals (e.g., the first gate terminal 110, the second gate terminal 120, and the fourth gate terminal 142) above the channel region in the substrate 224. The gate dielectric and the gate terminal are formed by depositing a conformal gate dielectric layer and a conformal gate material (e.g., polysilicon) layer on the substrate 224. The conformal gate dielectric layer and the conformal gate material layer are then patterned to form the gate dielectric and the gate terminal. After the gate dielectric and the gate terminal are formed, dopants are implanted into the substrate 224 to form source / drain regions (e.g., the first, second, third, fourth, and seventh source / drain regions 108, 112, 118, 122, 144). In some embodiments, an additional gate replacement step is performed to form a gate terminal, the gate terminal comprising a conductive metal or metal nitride, such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), etc. In some embodiments, the first gate terminal 110 , the second gate terminal 120 , and the fourth gate terminal 142 extend over the isolation region 226 .

[0066] like Fig.11 As shown in the three-dimensional view 1100 of FIG. 1 , a plurality of contacts 206 and a first wiring level are formed on the substrate 224. In some embodiments, the first wiring level includes a read bit line 126, a write bit line 114, and an interconnect 207. In some embodiments, the plurality of contacts 206 and / or the first wiring level include a conductive material, such as aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), platinum (Pt), tungsten (W), nickel (Ni), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), negatively doped polysilicon material, positively doped polysilicon material, etc. In some embodiments, the plurality of contacts 206 and the first wiring level are formed using a dual damascene process, one or more single damascene processes, etc.

[0067] like Fig.12 As shown in the three-dimensional view 1200 of FIG. 1 , a first via level 208 and a second wiring level are formed above a substrate 224. The second wiring level includes a storage node 106. In some embodiments, the second wiring level also includes a read word line 124 and a write word line 116. In some embodiments, the first via level 208 and the second wiring level are or include the same material as the plurality of contacts 206 and / or the first wiring level. In some embodiments, the first via level 208 and the second wiring level are formed using a dual damascene process, one or more single damascene processes, and the like.

[0068] like Fig.13 As shown in the three-dimensional view 1300 of FIG. 1 , a second via level 210 and a third wiring level 212 are formed over the substrate 224. The second via level 210 couples the storage node to the third wiring level 212. In some embodiments, the second via level 210 and the third wiring level 212 are or include the same material as the plurality of contacts 206 and / or the first wiring level. In some embodiments, the second via level 210 and the third wiring level 212 are formed using a dual damascene process, one or more single damascene processes, or the like.

[0069] like Fig.14 As shown in the three-dimensional view 1400 of FIG. 1 , the third via level 214 and the capacitor 128 are formed above the third wiring level 212. The third via level 214 couples the lower electrode 218 of the capacitor 128 to the third wiring level 212. In some embodiments, the third via level 214 is or includes the same material as the plurality of contacts 206 and / or the first wiring level. In some embodiments, the third via level 214 and the capacitor 128 are formed using one or more damascene processes, one or more deposition processes (e.g., atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition).

[0070] That is, capacitor 128 may be formed by multiple deposition processes to form a conformal lower electrode layer, a conformal high-k dielectric layer, and a conformal upper electrode layer. The conformal lower electrode layer, the conformal high-k dielectric layer, and the conformal upper electrode layer are then patterned to form capacitor 128. In other embodiments, such as Figure 4A-4E As shown, additional dry etching, wet etching, and deposition steps may be used to form a 3D capacitor over the third via level 214 .

[0071] In some embodiments, the high-k dielectric 220 includes an amorphous structure when initially deposited. A thermal anneal is performed to transform the amorphous structure into a crystalline high-k dielectric 220. In further embodiments, in order to form a highly symmetric crystalline phase having a dielectric constant greater than 35, a conformal top electrode layer is formed before the thermal anneal is performed. During the thermal anneal, the top electrode 222 induces additional stress in the high-k dielectric 220. The additional stress causes the material of the high-k dielectric 220 to transform into a highly symmetric crystalline phase, such as a cubic phase, a tetragonal phase, or a hexagonal phase.

[0072] like Fig.15As shown in the three-dimensional view 1500 of FIG. 1 , the fourth via level 216 and the ground line 130 are formed above the capacitor 128. The fourth via level 216 couples the ground line 130 to the upper electrode 222 of the capacitor 128. In some embodiments, the fourth via level 216 and the ground line 130 are or include the same material as the plurality of contacts 206 and / or the first wiring level. In some embodiments, the first via level 208 and the second wiring level are formed using a dual damascene process, one or more single damascene processes, and the like.

[0073] Fig.16 A flow chart of some embodiments of a method 1600 for forming a GCRAM cell having a capacitor coupled to a storage node is shown. Although the method and other methods shown and / or described herein are shown as a series of actions or events, it should be understood that the present disclosure is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from that shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0074] At 1602, an isolation region is formed in a substrate. For example, see Fig. 9 .

[0075] At 1604, a write transistor, a first read transistor, and a second read transistor are formed on a substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by an isolation region. Fig.10 .

[0076] At 1606, a first wiring level is formed on the substrate, the first wiring level including a write bit line, a read bit line, and a plurality of interconnect lines, wherein the write bit line is coupled to the source / drain region of the write transistor, and the read bit line is coupled to the source / drain region of the second read transistor. For example, see Fig.11 .

[0077] At 1608, a second wiring level is formed above the first wiring level, the second wiring level including a storage node, wherein the storage node is coupled to the second source / drain region of the write transistor and the gate terminal of the first read transistor. Fig.12 .

[0078] At 1610, a capacitor is formed above the second wiring level, the capacitor having a lower electrode coupled to the storage node and an upper electrode coupled to the ground line. Fig.14 .

[0079] At 1612, a thermal anneal is performed, which causes the material of the high-k dielectric layer to transform into a highly symmetric crystalline phase. For example, see Fig.14 .

[0080] The present disclosure describes an integrated capacitor structure coupled to a storage node of a GCRAM device. The capacitor structure provides ultra-high k dielectric performance by having a highly symmetric crystal phase, a maximum area overlying the transistor structure in the GCRAM, and a minimum area contained within the GCRAM cell boundary. This provides better GCRAM retention time and power, performance, and area (PPA) improvements. In addition, the GCRAM device has strategic metal layer wiring for spacing improvements. To achieve this, the read word line metal, write bit line metal, read word line, and write word line metal can be located in the first two wiring levels above the transistor device (e.g., the read bit line and write bit line metal are located in the first wiring level, and the read word line and write word line metal are located in the second wiring level). Each of these read word line metal, write bit line metal, read word line metal, and write word line metal can be a global line connection coupled to multiple GCRAM cells. In order to achieve sufficient thermal budget for crystallization, lower metal locations (e.g., the third or fourth wiring level) are used for ultra-high k capacitors, such as metal insulator metal (MIM) capacitors (e.g., see Figure 4A ). The capacitor structures are strategically located at lower metal locations, such as at the third or fourth wiring level, to increase the thermal budget available for forming the high-k dielectric.

[0081] Some embodiments relate to a memory cell, comprising: a write transistor located on a substrate, comprising a first gate terminal, a first source / drain region, and a second source / drain region coupled to a storage node; a first read transistor located on the substrate and comprising a second gate terminal coupled to the storage node; and a capacitor spaced apart from the first read transistor and the write transistor and further spaced apart from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node, wherein the memory cell has a first area, the capacitor has a second area, and wherein a ratio of the second area to the first area is equal to or less than 0.8. In some embodiments, the capacitor comprises a high-k dielectric having a dielectric constant greater than 35. In some embodiments, the memory cell further comprises: a second read transistor located on the substrate; wherein, when viewed from a top-down perspective, the first area is defined by a span of a memory cell region including the first read transistor, the write transistor, and the second read transistor, wherein, when viewed from a top-down perspective, the second area is defined by a span of the capacitor, and wherein the second area is between 60% and 80% of the first area. In some embodiments, the second read transistor has a third gate terminal extending in a first direction and extending parallel to the second gate terminal of the first read transistor, and wherein the second gate terminal and the third gate terminal are connected to a storage node. In some embodiments, the capacitor includes an upper electrode, a lower electrode, and a high-k dielectric having a symmetrical crystalline phase. In some embodiments, the symmetrical crystalline phase is a cubic phase, a tetragonal phase, or a hexagonal phase. In some embodiments, the capacitor includes an upper electrode, a lower electrode, and an insulator between the upper electrode and the lower electrode, and wherein the capacitor is a three-dimensional capacitor, wherein the insulator extends along corresponding side walls of the lower electrode and the upper electrode. In some embodiments, the first read transistor also includes a gate dielectric having a first capacitance, and wherein the capacitor has a second capacitance that is more than twice the first capacitance. In some embodiments, a wire located above the write transistor and the first read transistor, wherein the wire has an L-shaped top-down geometry and forms a storage node.

[0082] Other embodiments relate to an integrated circuit comprising: a plurality of memory cells having a plurality of first areas arranged in a plurality of rows and a plurality of columns, wherein each memory cell comprises: a write transistor comprising a first gate terminal, a first source / drain region, and a second source / drain region electrically coupled to a storage node; a first read transistor comprising a second gate terminal, a third source / drain region, and a fourth source / drain region electrically coupled to the storage node; and a capacitor electrically coupled to the storage node, wherein the capacitor has a second area, and wherein a ratio of the second area to a first area of ​​the plurality of first areas is equal to or less than 0.8; a write bit line electrically coupled to the first source / drain region for each of the plurality of memory cells in a first column of the plurality of columns; and a write word line electrically coupled to the first gate terminal for each of the plurality of memory cells in a first row of the plurality of rows. In some embodiments, the integrated circuit further comprises: a read bit line electrically coupled to a fourth source / drain region for each of the plurality of memory cells in a first column of the plurality of columns; and a read word line electrically coupled to a third source / drain region for each of the plurality of memory cells in a first row of the plurality of rows. In some embodiments, each of the plurality of memory cells comprises a second read transistor having a third gate terminal, a fifth source / drain region electrically coupled to the third source / drain region, and a sixth source / drain region, and wherein the integrated circuit further comprises: a read bit line electrically coupled to a sixth source / drain region for each of the plurality of memory cells in a first column of the plurality of columns. In some embodiments, the first read transistor is an N-type transistor, and wherein the write transistor is a P-type transistor. In some embodiments, the plurality of memory cells are located on a semiconductor substrate and include a first memory cell, wherein the write transistor of the first memory cell and the first read transistor of the first memory cell are inserted into the top of the semiconductor substrate, and wherein the capacitor of the first memory cell overlies and is separated from the write transistor of the first memory cell and the first read transistor of the first memory cell. In some embodiments, the plurality of memory cells includes a first memory cell, and wherein a capacitor of the first memory cell includes a high-k dielectric having a dielectric constant greater than 35. In some embodiments, the plurality of memory cells includes a first memory cell having only three transistors.

[0083] Still other embodiments relate to a method of forming a gain cell random access memory (GCRAM) cell, comprising: forming an isolation region in a substrate; forming a write transistor, a first read transistor, and a second read transistor on the substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by the isolation region; forming a first wiring level on the substrate, the first wiring level including a write bit line, a read bit line, and a plurality of interconnect lines, wherein the write bit line is coupled to a first source / drain region of the write transistor, and the read bit line is coupled to a first drain / source region of the second read transistor; forming a second wiring level on the first wiring level, the second wiring level including a storage node, wherein the storage node is coupled to the second source / drain region of the write transistor and to a gate terminal of the first read transistor; forming a capacitor above the second wiring level, the capacitor having a lower electrode coupled to the storage node, a high-k dielectric layer overlying the lower electrode, and an upper electrode located above the high-k dielectric layer; performing a thermal anneal after forming the capacitor, the thermal annealing causing the material of the high-k dielectric layer to transform into a highly symmetric crystalline phase. In some embodiments, the first read transistor and the second read transistor are formed as a source / drain region in a shared substrate. In some embodiments, the storage node is also formed to be coupled to a gate terminal of the second read transistor. In some embodiments, the method of forming a GCRAM cell further comprises forming a third wiring level above the second wiring level before forming the capacitor, wherein the third wiring level contacts a first via extending between the third wiring level and the storage node, and wherein the capacitor formed contacts a second via extending between the third wiring level and the lower electrode of the capacitor.

[0084] It should be understood that in this written description and the claims that follow, the terms "first," "second," and "third," etc., are merely general identifiers used for ease of description to distinguish different elements of a figure or series of figures. By themselves, these terms do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrated embodiments and / or embodiments not shown. For example, a "first dielectric layer" described in conjunction with a first figure may not necessarily correspond to a "first dielectric layer" described in conjunction with another figure, and may not necessarily correspond to a "first dielectric layer" in an embodiment not shown.

[0085] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory cell, comprising: a write transistor disposed on the substrate and including a first gate terminal, a first source / drain region, and a second source / drain region coupled to the storage node; a first read transistor disposed on the substrate and including a second gate terminal coupled to the storage node; as well as A capacitor is spaced apart from the first read transistor and the write transistor and further spaced apart from the substrate by the first read transistor and the write transistor, wherein the capacitor is coupled to the storage node, wherein the memory cell has a first area, the capacitor has a second area, and wherein a ratio of the second area to the first area is equal to or less than 0.

8.

2. The memory cell according to claim 1 , further comprising: a second read transistor located on the substrate; wherein the first area is defined by a span of a memory cell region including the first read transistor, the write transistor, and the second read transistor when viewed from a top-down perspective, wherein the second area is defined by a span of the capacitor when viewed from a top-down perspective, and wherein the second area is between 60% and 80% of the first area.

3. The memory cell according to claim 2, wherein: The second read transistor has a third gate terminal extending in a first direction and parallel to the second gate terminal of the first read transistor, and wherein the second gate terminal and the third gate terminal are connected to the storage node.

4. The memory cell according to claim 1, wherein: The capacitor includes an upper electrode, a lower electrode, and an insulator between the upper electrode and the lower electrode, and wherein the capacitor is a three-dimensional capacitor, wherein the insulator extends along corresponding side walls of the lower electrode and the upper electrode.

5. The memory cell according to claim 1, wherein: The first read transistor also includes a gate dielectric having a first capacitance, and wherein the capacitor has a second capacitance that is more than twice the first capacitance.

6. The memory cell according to claim 1, further comprising: A conductive line is located above the write transistor and the first read transistor, wherein the conductive line has an L-shaped top-view geometry and forms the storage node.

7. An integrated circuit comprising: A plurality of memory cells having a plurality of first areas arranged in a plurality of rows and a plurality of columns, wherein each of the memory cells comprises: a write transistor including a first gate terminal, a first source / drain region, and a second source / drain region electrically coupled to a storage node; a first read transistor including a second gate terminal electrically coupled to the storage node, a third source / drain region, and a fourth source / drain region; and a capacitor electrically coupled to the storage node, wherein the capacitor has a second area, and wherein a ratio of the second area to a first area of ​​the plurality of first areas is equal to or less than 0.8; a write bit line electrically coupled to the first source / drain region for each of the plurality of memory cells in a first column of the plurality of columns; and A write word line is electrically coupled to the first gate terminal for each of the plurality of memory cells in a first row of the plurality of rows.

8. The integrated circuit of claim 7, further comprising: a read bit line electrically coupled to a fourth source / drain region for each of the plurality of memory cells in a first column of the plurality of columns; as well as A read word line is electrically coupled to the third source / drain region for each of the plurality of memory cells in a first row of the plurality of rows.

9. The integrated circuit according to claim 7, wherein: Each of the plurality of memory cells includes a second read transistor having a third gate terminal, a fifth source / drain region electrically coupled to the third source / drain region, and a sixth source / drain region, and wherein the integrated circuit further includes: A read bit line is electrically coupled to the sixth source / drain region for each of the plurality of memory cells in a first column of the plurality of columns.

10. A method of forming a gain cell random access memory cell, comprising: forming an isolation region in the substrate; forming a write transistor, a first read transistor, and a second read transistor on the substrate, wherein the write transistor is separated from the first read transistor and the second read transistor by the isolation region; forming a first wiring level above the substrate, the first wiring level comprising a write bit line, a read bit line, and a plurality of interconnect lines, wherein the write bit line is coupled to a first source / drain region of the write transistor, and the read bit line is coupled to a first drain / source region of the second read transistor; forming a second wiring level above the first wiring level, the second wiring level including a storage node, wherein the storage node is coupled to a second source / drain region of the write transistor and a gate terminal of the first read transistor; and forming a capacitor over the second wiring level, the capacitor having a lower electrode coupled to the storage node, a high-k dielectric layer overlying the lower electrode, and an upper electrode over the high-k dielectric layer; and A thermal anneal is performed after forming the capacitor, the thermal anneal causing the material of the high-k dielectric layer to transform into a highly symmetric crystalline phase.

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