Optical proximity effect correction method, semiconductor structure and preparation method

Abstract

The invention discloses an optical proximity effect correction method, a semiconductor structure and a preparation method, and the method comprises the steps: segmenting the edge of an initial mask pattern into a plurality of segments, and obtaining an initial cutting line corresponding to each segment; determining an initial edge placement error corresponding to the current position of the initial cutting line; adjusting the position of each segment according to the first initial edge placement error to obtain an intermediate mask pattern; and under the condition that a second edge placement error exists at the line end of the middle mask pattern, adjusting the position of the initial cutting line on the segment based on the cutting line movement ratio until the simulation wafer pattern is matched with the reference mask pattern, and obtaining a target mask pattern. According to the method, the cutting line is moved according to the cutting line movement ratio so as to gradually adjust the line end of the intermediate mask pattern, the edge placement error of the line end is reduced, the curvature and the inclusion degree of the line end are also improved, and the accuracy and the quality of the corrected target mask pattern are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an optical proximity effect correction method, a semiconductor structure and a preparation method. Background Art

[0002] During the exposure process, the interference and diffraction effects of ultraviolet light cause the wafer surface pattern to be distorted. This phenomenon is called the optical proximity effect (OPE). The main manifestations of pattern distortion are line width feature size deviation, line end shrinkage, bridging, corner rounding and other features. In order to compensate for the pattern distortion caused by OPE, the mask pattern needs to be corrected so that the final pattern on the wafer is consistent with the designed pattern. This correction process is called optical proximity correction (OPC).

[0003] In the existing OPC rules, the multi mode is used in 1D graphics, that is, the edge placement error (EPE) of multiple cutting line positions is calculated; the single mode is used in 2D graphics, that is, the edge placement error of a single cutting line position is calculated. When correcting the line endpoints (referred to as line ends), it is simpler and more convenient than the multi mode, and it is easy to control the final OPC correction result; however, the existing OPC rules still have problems such as large line end EPE, poor line end inclusion and low line end curvature, which makes it difficult for the target mask pattern corrected by the final OPC to meet the requirements and the pattern quality on the wafer is poor. Summary of the invention

[0004] In order to solve the problems of the prior art, the present application provides an optical proximity effect correction method, a semiconductor structure and a preparation method. The technical solution is as follows:

[0005] In one aspect, the present application provides a method for correcting an optical proximity effect, comprising:

[0006] Segmenting the edge of the initial mask pattern into a plurality of segments, and obtaining initial cutting lines corresponding to each segment, wherein the initial cutting lines are orthogonal to the segments;

[0007] Determine an initial edge placement error corresponding to the current position of the initial cutting line; the initial edge placement error includes a first initial edge placement error in the line width direction of the mask pattern and a second initial edge placement error at the line end position;

[0008] The positions of the segments are adjusted according to the first initial edge placement error, so that the line widths of the simulated wafer pattern and the reference mask pattern corresponding to the initial mask pattern match, thereby obtaining an intermediate mask pattern; the simulated wafer pattern is a lithography pattern obtained by performing lithography simulation based on the adjusted initial mask pattern, and the reference mask pattern is a target lithography pattern obtained when there is no optical proximity effect corresponding to the initial mask pattern;

[0009] In the case where the second initial edge placement error exists at the line end of the intermediate mask pattern, the position of the initial cutting line on the segment is adjusted based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern to obtain a target mask pattern; the cutting line movement ratio is determined based on the line end length and process node of the initial mask pattern.

[0010] Furthermore, at least one initial cutting line is provided on each geometric edge of the initial mask pattern, and at least one initial dividing line is provided on each segment.

[0011] Furthermore, the difference between the line end length and the process node is positively correlated with the cutting line movement ratio, and the cutting line movement ratio is negatively correlated with the process node.

[0012] Furthermore, the line end length and 0.5 power of the difference between the process nodes are proportional to the cutting line movement ratio, and the cutting line movement ratio is inversely proportional to the process node.

[0013] Furthermore, the ratio of the line end length to the process node is less than or equal to a preset ratio, and the preset ratio is 1-2.

[0014] Further, the adjusting the position of each of the segments according to the first initial edge placement error until the line width of the simulated wafer pattern and the reference mask pattern corresponding to the initial mask pattern match to obtain the intermediate mask pattern includes:

[0015] For each of the segments, determining a line width expansion value of the initial cutting line corresponding to the segment according to the first initial edge placement error;

[0016] Adjusting the initial mask pattern based on the line width expansion values ​​corresponding to the respective segments to obtain an updated mask pattern;

[0017] Determining an updated first edge placement error corresponding to each of the initial cutting lines in the updated mask pattern according to an edge placement error algorithm;

[0018] If the updated first edge placement error indicates that the line widths of the simulated wafer pattern corresponding to the updated mask pattern and the reference mask pattern match, the updated mask pattern is determined as the intermediate mask pattern.

[0019] Further, after determining the updated first edge placement error corresponding to the initial cutting line in the updated mask pattern according to the edge placement error algorithm, the method further comprises:

[0020] If the line widths of the simulated wafer pattern and the reference mask pattern do not match, the steps of determining the line width expansion value of the initial cutting line, adjusting the mask pattern based on the line width expansion value, and updating the first edge placement error are repeated until the updated first edge placement error indicates that the line widths of the simulated wafer pattern and the reference mask pattern match, and the updated mask pattern obtained when the line width match is satisfied is determined as the intermediate mask pattern.

[0021] Furthermore, the line width expansion value is determined by the following steps:

[0022] Obtaining a preset feedback value, where the preset feedback value is a correction coefficient for calculating a mask pattern outward expansion step length based on the first edge placement error;

[0023] The step length is calculated according to the preset feedback value and the first initial edge placement error to obtain the line width expansion value.

[0024] Further, in the case where there is a second edge placement error at the line end of the intermediate mask pattern, adjusting the position of the initial cutting line on the segment based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern, and obtaining the target mask pattern includes:

[0025] When the line end of the intermediate mask pattern has the second edge placement error, adjusting the position of the initial cutting line on the segment corresponding to the line end based on the cutting line movement ratio to obtain an updated cutting line;

[0026] determining an updated second edge placement error corresponding to the updated current position of the cutting line according to an edge placement error algorithm;

[0027] adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a line-end updated mask pattern;

[0028] If the simulated wafer pattern corresponding to the updated line-end mask pattern matches the reference mask pattern, the updated mask pattern at the line-end is determined to be the target mask pattern.

[0029] Further, after adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a mask pattern with updated line ends, the method further includes:

[0030] If the simulated wafer pattern corresponding to the updated line-end mask pattern does not match the reference mask pattern, the steps of moving the cutting line, updating the second edge placement error and updating the line end of the mask pattern are repeated until the simulated wafer pattern corresponding to the line-end updated mask pattern matches the reference mask pattern, and the line-end updated mask pattern obtained when the line-end matching is satisfied is determined as the target mask pattern.

[0031] Further, the process node includes at least one of 180nm, 150nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm and 28nm.

[0032] On the other hand, the present application also provides a method for preparing a semiconductor structure, which is prepared based on a target mask pattern corrected by the optical proximity effect correction method as described in any of the above items.

[0033] On the other hand, the present application also provides a semiconductor structure, which is manufactured based on the semiconductor structure manufacturing method as described above.

[0034] Implementing this application has the following beneficial effects:

[0035] 1. After correcting the line width of the initial mask pattern to obtain the intermediate mask pattern, the present application moves the cutting line according to the cutting line movement ratio to optimize the edge placement error algorithm, and can especially adjust and correct the line end, and gradually reduce the edge placement error (EPE) of the line end of the intermediate mask pattern, so that the lithography pattern simulated by the target mask pattern corrected by the optical proximity effect correction method is consistent with the target lithography pattern obtained when the initial mask pattern is not affected by the optical proximity effect, which greatly reduces the overall EPE of the target mask pattern, and also improves the curvature and inclusiveness of the line end, thereby improving the accuracy and quality of the corrected target mask pattern; in addition, the optical proximity effect correction method is suitable for mature process nodes and has good universality.

[0036] 2. In the present application, the 0.5 power of the difference between the line end length and the process nodes is proportional to the cutting line movement ratio, and the cutting line movement ratio is inversely proportional to the process node. When the cutting line movement ratio is met, the lithography pattern on the wafer surface obtained based on the corrected target mask pattern is almost consistent with the target lithography pattern on the wafer surface to be obtained in advance, which can effectively reduce the mask deviation, avoid the mask from violating the mask rule (MRC) after exposure, and reduce the overall edge placement error of the target mask pattern. At the same time, it also shortens the optical proximity effect correction time and the research and development time of the entire optical proximity effect correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A flowchart of an optical proximity effect correction method provided in an embodiment of the present application;

[0039] Figure 2 A comparison diagram of the matching status between the simulated wafer pattern and the target mask pattern provided in the embodiment of the present application after the cutting line is moved and before it is moved;

[0040] Figure 3 A schematic diagram of simulating wafer patterns under different cutting line movement ratio conditions at a 55nm process node provided by an embodiment of the present application;

[0041] Figure 4 A comparison diagram of the correction structures of the optical proximity effect correction method at the 153nm process node provided in the embodiments of the present application.

[0042] Wherein, the accompanying drawings are marked as follows:

[0043] 1-initial mask pattern, 2-reference mask pattern, 3-segment, 4-initial cut line, 41-updated cut line, 5-simulated wafer pattern, 6-intermediate mask pattern, 7-target mask pattern. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0045] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe specific objects or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that the depth direction of an element or layer is the direction perpendicular to the surface of the element or layer, and the direction of the cross section of an element or layer is the direction parallel to the surface of the element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0047] When correcting the optical proximity effect based on the existing OPC rules, there are still problems such as large edge placement error of the line end, poor line end inclusion and low line end curvature, which result in the inability to form high-quality graphics on the wafer surface.

[0048] In view of the above technical problems, the embodiments of the present application provide an optical proximity effect correction method, a semiconductor structure and a preparation method, firstly, the edge of the initial mask pattern is divided into multiple segments, and the initial cutting lines corresponding to each segment are obtained, and the initial cutting lines are orthogonal to the segments; then, the initial edge placement errors corresponding to the current positions of the initial cutting lines are determined, wherein the initial edge placement errors include the first initial edge placement errors in the line width direction of the mask pattern and the second initial edge placement errors at the line end positions; then, the positions of the corresponding segments are adjusted according to the first initial edge placement errors until the simulated wafer pattern and the reference mask pattern are aligned. The line width of the simulated wafer is matched to obtain an intermediate mask pattern, wherein the simulated wafer pattern is a lithography pattern on the wafer surface obtained by performing lithography simulation based on the adjusted initial mask pattern, and the reference mask pattern is a target lithography pattern obtained on the wafer surface when the initial mask pattern is not affected by the optical proximity effect; then, in the case where there is a second edge placement error at the line end of the intermediate mask pattern, the position of the initial cutting line on the segment is adjusted based on the cutting line movement ratio until the simulated wafer pattern and the reference mask pattern match to obtain a target mask pattern, wherein the cutting line movement ratio is determined based on the line end length of the initial mask pattern and the process node of the lithography process.

[0049] Through the optical proximity effect correction method, the line width of the initial mask pattern at the position of each segment can be adjusted based on the first initial edge prevention error, so that the line width of the lithography pattern on the real wafer obtained by lithography based on the intermediate mask pattern can match the line width of the expected reference mask pattern; and, when there is a second edge placement error at the line end of the intermediate mask pattern, the position of the initial cutting line on the segment can continue to be adjusted based on the cutting line movement ratio to adjust the line end of the intermediate mask pattern to obtain the target mask pattern, so that the line end of the lithography pattern on the real wafer obtained by lithography based on the target mask pattern can also be consistent with the line width of the expected reference mask pattern. The method calculates the edge placement error of the line end and reduces the edge placement error by moving the cutting line, greatly improving the correction accuracy of the optical proximity effect correction method, greatly reducing the overall edge placement error of the target mask pattern, and improving the line end curvature, so that high-quality lithography patterns can be obtained on the wafer surface after real lithography. It is convenient and fast, which is conducive to shortening the research and development time of optical proximity effect correction, and can be applicable to various process nodes and has a wide range of applications.

[0050] In addition, the line end coverage problem refers to the requirement in the design process of semiconductor devices that the metal material can cover the via below to form a good electrical connection. If the line end of the metal material shrinks significantly on the wafer, there is a risk that the metal material cannot effectively cover the via. The target mask pattern corrected by the optical proximity effect correction method is used for photolithography, which can greatly improve the morphological accuracy of the pattern on the wafer and match it with the expected reference mask pattern, effectively reducing the risk of line end coverage problems, which is beneficial to improving the subsequent preparation yield of semiconductor structures, as well as the morphological accuracy and performance of semiconductor structures.

[0051] Combine the following Figure 1-4 The optical proximity effect correction method of the embodiment of the present application is introduced in detail.

[0052] First, see Figure 1 , the edge of the initial mask pattern is divided into multiple segments, and the initial cutting lines corresponding to each segment are obtained.

[0053] In this step, the initial mask pattern 1 is the initial design pattern. If there is no optical proximity effect, the desired target lithography pattern can be obtained on the wafer surface by exposing based on the initial mask pattern 1.

[0054] Double or multiple photolithography technology requires the design of two or more masks according to the process flow, and the initial mask pattern 1 is mostly complex, and the initial mask pattern 1 needs to be split into simple patterns to meet the requirements of the multiple exposure process; further, the initial mask pattern 1 is mostly a 2D layout. In the 2D layout, the edge of the initial mask pattern 1 is divided into multiple fragments 3, and the fragments 3 are located at the edges of each line in the initial mask pattern 1. Each fragment 3 can move freely, and each fragment 3 can be corrected fragment by fragment 3 subsequently, thereby improving the overall correction precision of the initial mask pattern 1 and maximizing the accuracy of the photolithography pattern on the actual wafer after exposure and development.

[0055] Among them, each initial cutting line 4 is orthogonal to its corresponding segment 3; the cutting line is used for positioning, and is a positioning line that permanently determines the calculated position of the edge placement error in the subsequent steps, that is, the calculated edge placement error is corresponding to the cutting line; if the cutting line moves, the edge placement error corresponding to the moved cutting line will also change; the initial cutting line 4 is a positioning line used to determine the calculated position of the initial edge placement error in the subsequent steps, so as to facilitate the subsequent determination of the graphic deviation on each segment 3 according to the edge placement error of each initial cutting line 4 position, and then correct the initial mask graphic 1.

[0056] Specifically, in some exemplary embodiments, at least one initial cutting line 4 is provided on each geometric edge of the initial mask pattern 1; exemplarily, one initial cutting line 4 is provided on each geometric edge of the initial mask pattern 1, which is simple and convenient, and it is easier to control the final correction result; and again exemplarily, multiple initial cutting lines 4 are provided on each geometric edge of the initial mask pattern 1, which is conducive to improving the correction precision.

[0057] Specifically, each fragment 3 is provided with at least one initial dividing line, and the initial dividing line can be located at any point on the fragment 3, for example, the initial dividing line can be located at the end of the fragment 3, or at the middle of the fragment 3; in some exemplary embodiments, each fragment 3 is provided with an initial dividing line, and correction is efficient and convenient, and the correction effect is well controllable; in other exemplary embodiments, each fragment 3 is provided with multiple initial dividing lines, which improves the correction fineness of the optical proximity effect correction method.

[0058] Then, if Figure 1 As shown, the initial edge placement error corresponding to the current position of the initial cutting line is determined.

[0059] Edge Placement Error (EPE) is the deviation between the actual position and the designed position of the edge of the pattern photolithographed on the wafer surface. It is used to quantify the fidelity of the pattern manufactured during various exposure technologies. The initial edge placement error is the deviation between the actual position and the designed position of the edge of the pattern photolithographed on the wafer surface at the current position of the initial cutting line 4.

[0060] The lines in the initial mask pattern 1 have a certain line width. The initial mask pattern 1 has a first direction and a second direction that are orthogonal to each other. The first direction is the extension direction of the lines, and the second direction is the line width direction of the lines. Figure 1 The directions shown in are taken as references, that is, the first direction is the horizontal direction and the second direction is the vertical direction.

[0061] The initial edge placement error includes a first initial edge placement error in the line width direction of the mask pattern, which is used to indicate the line width difference between the initial simulated wafer pattern corresponding to the initial mask pattern 1 and the reference mask pattern 2. The longitudinal spacing between the edges of the two patterns at the initial cutting line 4 position is the first initial edge placement error; the initial edge placement error also includes a second initial edge placement error in the line end position of the mask pattern, which is used to indicate the line end difference between the initial simulated wafer pattern corresponding to the initial mask pattern 1 and the reference mask pattern 2. The spacing between the intersection point of the line end of the initial simulated wafer pattern and the initial cutting line 4 position and the intersection point of the reference mask pattern 2 and the initial cutting line 4 position is the second initial edge placement error.

[0062] The edge placement error is determined based on an edge placement error algorithm. In some exemplary embodiments, the edge placement error algorithm obtains the initial simulated wafer pattern and the reference mask pattern corresponding to the initial mask pattern, and calculates the distance difference between the edge points of the initial simulated wafer pattern and the edge points of the reference mask pattern at each initial cutting line position, thereby realizing the calculation of the initial edge placement error corresponding to the current position of each initial cutting line; in addition, in the process of calculating the edge placement error using the edge placement error algorithm in subsequent steps, the obtained simulated wafer patterns are all simulated by the current adjusted initial mask pattern (or the intermediate mask pattern updated at the line end), and are continuously iterated to gradually reduce the edge placement error at each cutting line position and improve the correction accuracy and correction stability.

[0063] Then in some exemplary embodiments, before performing the step of determining the initial edge placement error, the optical proximity effect correction method further includes:

[0064] The initial mask pattern is simulated to obtain an initial simulated wafer pattern.

[0065] In this step, the initial simulated wafer pattern is simulated based on the initial mask pattern 1, so as to determine the initial edge placement error; and in the subsequent adjustment step, after correction, the initial mask pattern changes, then the subsequent simulated wafer pattern 5 is a lithography pattern obtained by lithography simulation based on the current adjusted initial mask pattern in each adjustment stage, so as to update the edge placement error in real time to gradually correct the mask pattern and improve the correction effect.

[0066] In some other exemplary embodiments, before performing the step of determining the initial edge placement error, the optical proximity effect correction method further includes:

[0067] The initial mask pattern is smoothed to obtain a reference mask pattern.

[0068] The target photolithography pattern on the actual wafer surface is a smooth curve at the corner position, especially at the line end position, with a certain curvature; the smoothing process is calculated by defining the distance from the corner to simulate the most perfect actual photolithography pattern when there is no optical proximity effect. The reference mask pattern 2 is the target photolithography pattern obtained when there is no optical proximity effect corresponding to the initial mask pattern 1, and is the actual pattern morphology expected to be lithographically formed on the wafer surface, so as to facilitate comparison with the initial simulated wafer pattern and determine the initial edge placement error in subsequent steps; in addition, there is no restriction on the order of this step and the above-mentioned simulation step, as long as it is before the step of determining the initial edge placement error, which has good flexibility.

[0069] Then, if Figure 1As shown, the positions of each segment are adjusted according to the first initial edge placement error until the line widths of the reference mask pattern corresponding to the simulated wafer pattern and the initial mask pattern match, thereby obtaining an intermediate mask pattern.

[0070] The simulated wafer pattern is a lithography pattern obtained by lithography simulation based on the adjusted initial mask pattern. During the adjustment process, it corresponds to the mask pattern after each adjustment. After multiple adjustments, the initial mask pattern 1 gradually deforms into the shape of the intermediate mask pattern.

[0071] This step is used to adjust the line width of the initial mask pattern 1, determine the line width expansion distance that the corresponding segment needs to move according to the first initial edge placement error on each initial cutting line 4, and move the edge of the corresponding segment 3 in the initial mask pattern 1 based on the line width expansion distance, so that the simulated wafer pattern 5 simulated based on the adjusted intermediate mask pattern 6 has a line width consistent with the reference mask pattern, thereby improving the line width consistency and solving the edge placement error problem in the line width direction.

[0072] Specifically, the adjusting the position of each of the segments according to the first initial edge placement error until the line width of the simulated wafer pattern and the reference mask pattern corresponding to the initial mask pattern match to obtain the intermediate mask pattern includes:

[0073] For each of the segments, determining a line width expansion value of the initial cutting line corresponding to the segment according to the first initial edge placement error;

[0074] Adjusting the initial mask pattern based on the line width expansion values ​​corresponding to the respective segments to obtain an updated mask pattern;

[0075] Determining an updated first edge placement error corresponding to each of the initial cutting lines in the updated mask pattern according to an edge placement error algorithm;

[0076] If the updated first edge placement error indicates that the line widths of the simulated wafer pattern corresponding to the updated mask pattern and the reference mask pattern match, the updated mask pattern is determined as the intermediate mask pattern.

[0077] Among them, the line width expansion value is the distance that the edge of the segment 3 where the initial cutting line 4 is located moves toward the edge of the reference mask pattern 2. Each segment 3 can be moved based on its own line width expansion value, so that the initial mask pattern can be adjusted in shape through expansion to obtain an updated mask pattern; at this time, the updated first edge placement error corresponding to each initial cutting line 4 in the updated mask pattern can be determined again according to the edge placement error algorithm to determine whether the simulated wafer pattern 5 obtained by simulation based on the updated mask pattern in the current state is consistent with the line width of the reference mask pattern 2; if the updated first edge placement error is zero, or the updated first edge placement error indicates that the simulated wafer pattern 5 corresponding to the updated mask pattern matches the line width of the reference mask pattern 2, then the updated mask pattern in the current state is determined as the intermediate mask pattern 6. At this time, at each initial cutting line 4 position, the edge of the simulated wafer pattern 5 obtained by simulation based on the intermediate mask pattern 6 in the line width direction can overlap with the edge of the reference mask pattern 2 in the line width direction, which greatly improves the correction effect in the line width direction and reduces the edge placement error problem in the line width direction.

[0078] Specifically, the line width expansion value is determined by the following steps:

[0079] Obtaining a preset feedback value, where the preset feedback value is a correction coefficient for calculating a mask pattern outward expansion step length based on the first edge placement error;

[0080] The step length is calculated according to the preset feedback value and the first initial edge placement error to obtain the line width expansion value.

[0081] Among them, the preset feedback value is a pre-set coefficient, which can be obtained through experience. Then, the distance that the initial mask pattern moves in the line width direction can be determined by the first initial edge placement error and the preset feedback value; for example, assuming that the first initial edge placement error corresponding to the current initial cutting line 4 is -10nm, and the preset feedback value is -0.5, the line width expansion value is 5nm, indicating that the edge of the corresponding segment 3 needs to be moved outward by 5nm to obtain an updated mask pattern; then, the first edge placement error corresponding to the initial cutting line 4 is repeatedly calculated according to the updated mask pattern to determine whether the current first edge placement error is zero, that is, to determine whether the currently updated mask pattern can simulate the simulated wafer pattern 5 that matches the line width of the reference mask pattern 2. If the judgment result is yes, the currently updated mask pattern is used as the intermediate mask pattern 6; the method for determining the line width expansion value is simple and fast, and is not prone to over-correction, and has good correction stability and correction reliability.

[0082] Specifically, after determining the updated first edge placement error corresponding to the initial cutting line in the updated mask pattern according to the edge placement error algorithm, the method further includes:

[0083] If the line widths of the simulated wafer pattern and the reference mask pattern do not match, the steps of determining the line width expansion value of the initial cutting line, adjusting the mask pattern based on the line width expansion value, and updating the first edge placement error are repeated until the updated first edge placement error indicates that the line widths of the simulated wafer pattern and the reference mask pattern match, and the updated mask pattern obtained when the line width match is satisfied is determined as the intermediate mask pattern.

[0084] In this case, it means that the segment 3 cannot meet the correction requirement after moving once, so the above steps are repeated for 8 to 10 iterations, so that the segments 3 corresponding to each initial cutting line 4 can be gradually moved in the line width direction until the simulated wafer pattern 5 obtained by simulating the updated mask pattern matches the reference mask pattern 2 in the line width direction, that is, the edges of the simulated wafer pattern 5 and the reference mask pattern 2 in the line width direction coincide. At this time, the updated first edge placement error is zero, and accordingly, the line width expansion value is also zero. The segment 3 no longer moves, and the updated mask pattern that meets the line width matching requirement at this time can be determined as the intermediate mask pattern, thereby greatly improving the fineness, accuracy, stability and reliability of the optical proximity effect correction in the line width direction.

[0085] Then, if Figure 1 As shown, when there is a second initial edge placement error at the line end of the intermediate mask pattern, the position of the initial cutting line on the segment is adjusted based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern to obtain the target mask pattern.

[0086] In some exemplary embodiments, before the line end correction step, the second edge placement error of the fragment 3 at the line end position of the intermediate mask pattern 6 at the corresponding initial cutting line 4 can also be determined according to the edge placement error algorithm. If the second edge placement error indicates that there is a large deviation between the line end of the simulated wafer pattern 5 corresponding to the intermediate mask pattern 6 and the line end of the reference mask pattern 2, the step of adjusting the position of the initial cutting line 4 on the fragment 3 based on the cutting line movement ratio can be continued until the simulated wafer pattern 5 and the reference mask pattern 2 match to obtain the target mask pattern 7.

[0087] Among them, the cutting line movement ratio refers to the movement angle of the cutting line on the corresponding segment 3 at the line end of the initial mask pattern or the intermediate mask pattern 6; after the above-mentioned line width adjustment step, there may still be a large edge error at the line end position, then on the segment 3 at the line end, the second edge placement error corresponding to the initial cutting line 4 may have approached zero, but after the initial cutting line 4 moves, there may be a large second edge placement error corresponding to the moved cutting line. At this time, it is necessary to continue to expand the segment 3 so that the simulated wafer pattern 5 corresponding to the adjusted intermediate mask pattern 6 matches the reference mask pattern 2, reduce the edge placement error of the line end of the target mask pattern 7, solve the line end inclusion problem, and improve the line end curvature, so that high-quality lithography patterns can be obtained on the wafer based on the target mask pattern 7.

[0088] In an embodiment of the present application, the cutting line movement ratio is determined based on the line end length and process node of the initial mask pattern 1, which can improve the accuracy of the cutting line movement ratio, and thus in the process of adjusting the intermediate mask pattern 6 by moving the initial cutting line 4 based on the cutting line movement ratio, improve the adjustment effect, adjustment convenience and adjustment stability; the line end length refers to the length of the line end in the extension direction perpendicular to the line in the initial mask pattern 1, that is, the length of the line end in the second direction; the process node refers to the minimum feature size used in the manufacturing process of the semiconductor structure, which can measure the preparation accuracy and performance of the semiconductor structure.

[0089] Specifically, in the case where there is a second edge placement error at the line end of the intermediate mask pattern, adjusting the position of the initial cutting line on the segment based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern, and obtaining the target mask pattern includes:

[0090] When the line end of the intermediate mask pattern has the second edge placement error, adjusting the position of the initial cutting line on the segment corresponding to the line end based on the cutting line movement ratio to obtain an updated cutting line;

[0091] determining an updated second edge placement error corresponding to the updated current position of the cutting line according to an edge placement error algorithm;

[0092] adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a line-end updated mask pattern;

[0093] If the simulated wafer pattern corresponding to the updated line-end mask pattern matches the reference mask pattern, the updated mask pattern at the line-end is determined to be the target mask pattern.

[0094] Among them, at the position of the initial cutting line 4, the edge placement error of the line width of the intermediate mask pattern 6 is already extremely small, which is basically consistent with the line width of the reference mask pattern 2, but the line end still deviates from the line end of the reference mask pattern 2. At this time, the position of the initial cutting line 4 on the segment 3 corresponding to the line end is adjusted based on the cutting line movement ratio, and the initial cutting line 4 on the line end segment 3 is rotated by a certain angle to obtain an updated cutting line 41; then, at the updated cutting line 41 position, the updated second edge placement error corresponding to the current position of the updated cutting line 41 is determined again according to the edge placement error algorithm. It can be found that the updated second edge placement error is relatively large at this time, indicating that the line end of the intermediate mask pattern 6 still needs to be corrected.

[0095] Then, the intermediate mask pattern 6 is adjusted according to the updated second edge placement error to obtain the mask pattern updated at the line end. The adjustment process can also be implemented by gradually expanding outward in the direction of the updated cutting line 41 to increase the curvature of the line end and improve the edge placement error of the line end. At this time, the mask pattern updated at the line end can be simulated to obtain a simulated wafer pattern 5 corresponding to the mask pattern updated at the line end, and compared with the reference mask pattern 2 to determine whether the two match. It is also possible to determine the adjusted second edge placement error corresponding to the updated cutting line 41 position in the mask pattern updated at the current line end according to the edge placement error algorithm based on the mask pattern updated at the line end, so as to obtain a simulated wafer pattern 5 corresponding to the updated cutting line 41 position in the mask pattern updated at the current line end based on the adjusted second edge placement error. The edge placement error determines whether the simulated wafer graphic 5 corresponding to the updated line end mask graphic and the reference mask graphic 2 match; if the adjusted second edge placement error is zero, or indicates that the simulated wafer graphic 5 corresponding to the updated line end mask graphic and the reference mask graphic 2 match, it means that the line end adjustment can be completed by moving the initial cutting line 4 once to obtain the target mask graphic. At this time, the simulated wafer graphic 5 obtained by simulation based on the target mask graphic 7 can overlap with the reference mask graphic 2 in the edge of the line width direction and the line end position, which greatly improves the correction effect of the line end and the mask graphic as a whole, reduces the overall edge placement error problem of the target mask graphic 7, improves the line end curvature, and solves the line end inclusion problem.

[0096] Specifically, after adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a mask pattern with updated line ends, the method further includes:

[0097] If the simulated wafer pattern corresponding to the updated line-end mask pattern does not match the reference mask pattern, the steps of moving the cutting line, updating the second edge placement error and updating the line end of the mask pattern are repeated until the simulated wafer pattern corresponding to the line-end updated mask pattern matches the reference mask pattern, and the line-end updated mask pattern obtained when the line-end matching is satisfied is determined as the target mask pattern.

[0098] In this case, it means that the initial cutting line 4 moves once and only reduces the edge placement error of the line end to a certain extent, but has not yet met the correction requirement of the line end, and there is still a certain edge placement error at the line end, then the above-mentioned cutting line movement, second edge placement error update and line end update steps of the mask pattern are repeated, and the cycle is iterated multiple times, so that the cutting line moves gradually and gradually expands outward in each cutting line direction, so that the second edge placement error on the cutting line 41 updated on the final line end segment 3 approaches zero, that is, the simulated wafer pattern 5 obtained by simulating the line end updated mask pattern matches the reference mask pattern 2 everywhere, that is, the edges of the simulated wafer pattern 5 and the reference mask pattern 2 completely overlap, then the line end updated mask pattern that meets the line end matching requirement at this time can be determined as the second mask pattern, which greatly improves the fineness, accuracy, stability and reliability of the optical proximity effect correction of the line end position and the target mask pattern 7 as a whole.

[0099] For example, Figure 2 As shown, taking the 55nm process node as an example, Figure 2 a) is the target mask pattern when the cutting line does not move. Figure 2 b) is the target mask pattern 7 (Y=9%, calculated according to the preferred formula) after the cutting line movement correction of the embodiment of the present application. It can be seen that the simulated wafer pattern 5 after correction is consistent with the reference mask pattern 2. At this time, the target mask pattern 7 obtained will be updated on the photomask, and the pattern photolithographically formed on the real wafer surface after exposure and development will also be very matched with the simulated wafer pattern 5, thereby achieving the purpose of optical proximity effect correction.

[0100] Specifically, in some exemplary embodiments, the difference between the line end length and the process node is positively correlated with the cutting line movement ratio, and the cutting line movement ratio is negatively correlated with the process node, which can effectively improve the adjustment effect, adjustment convenience and adjustment stability of the step of adjusting the intermediate mask pattern 6 based on the cutting line movement ratio, effectively reduce the edge placement error of the mask pattern line end, and improve the line end curvature and line end inclusion.

[0101] Specifically, in some preferred embodiments, the line end length and the 0.5 power of the difference between the process nodes are proportional to the cutting line movement ratio, and the cutting line movement ratio is inversely proportional to the process node; further, the cutting line movement ratio satisfies the following formula:

[0102]

[0103] Where Y is the cutting line movement ratio;

[0104] X is the line end length;

[0105] Node is a process node.

[0106] When the cutting line movement ratio satisfies the formula, adjustment can be made to maximize the adjustment efficiency while preventing over-adjustment. The adjustment effect, adjustment efficiency, adjustment stability and adjustment reliability can all be effectively improved, and the placement error of the 7 line ends of the target mask pattern and the overall edge can be minimized, the line end curvature can be improved, and the line end inclusion problem can be solved.

[0107] like Figure 3 As shown in the figure, when the cutting line movement ratio satisfies different formulas, the correction effect is also different; taking the 55nm process node as an example, Figure 3 a) The cutting line movement ratio meets Correction result of optical proximity effect when Y is 45%; Figure 3 b) The cutting line movement ratio meets The optical proximity effect correction result is 9% at this time; Figure 3 c) The cutting line movement ratio meets The optical proximity effect correction result is , at this time Y is 5%; by comparison, we can see that Figure 3 b) The correction result shown has a smaller edge placement error, a larger curvature, and a better correction effect.

[0108] Specifically, in some exemplary embodiments, the ratio between the line end length and the process node is less than or equal to a preset ratio, and the preset ratio is 1 to 2; it can be understood that the preset ratio can be any point value between 1 and 2; illustratively, the preset ratio can be 1, 1.2, 1.5, 1.6, 1.7, 1.75, 1.8, 2, etc.; this is beneficial to improving the morphological accuracy of the target lithography pattern formed on the wafer surface during the lithography process based on the target mask pattern 7, and is also beneficial to improving the performance of the prepared semiconductor structure while reducing power consumption; for example, in some embodiments, the preset ratio can be 1.5, that is, the ratio between the line end length and the process node is less than or equal to 1.5.

[0109] Specifically, the process nodes include at least one of 180nm, 150nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm and 28nm, and have a wide range of applications; for example, the optical proximity effect correction method can be applicable to the 28nm process node, and the morphology of the lithography pattern formed on the wafer has high accuracy, and more transistors and electronic components can be integrated on the same semiconductor structure and the same area, thereby improving the performance of the semiconductor structure and semiconductor devices and reducing power consumption.

[0110] like Figure 4 As shown, taking the 153nm process node as an example, Figure 4 a) is the simulated wafer pattern without correction. Figure 4b) is a simulated wafer pattern corrected by the optical proximity effect correction method of the present application, wherein It can be seen that the simulated wafer pattern after correction is almost consistent with the reference mask pattern.

[0111] The present application also provides a method for preparing a semiconductor structure, which is prepared based on a target mask pattern corrected by the optical proximity effect correction method as described in any of the above items, and can greatly improve the accuracy of the surface pattern of the semiconductor structure, and improve the preparation efficiency and preparation yield.

[0112] The present application also provides a semiconductor structure, which is manufactured based on the semiconductor structure manufacturing method as described above, and the semiconductor structure has high morphology accuracy and excellent performance.

[0113] An embodiment of the present application also provides a semiconductor device, comprising any semiconductor structure described in the embodiment of the present application.

[0114] An embodiment of the present application also provides an electronic device, which includes any semiconductor structure described in the embodiment of the present application, or includes any semiconductor device described in the embodiment of the present application. The electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a car terminal, a VCD, a DVD, a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PSP, etc., and can also be an intermediate product having the semiconductor device, for example: a device motherboard having the semiconductor device, etc.; the electronic device adopts the semiconductor device, which correspondingly improves the working performance of the electronic device.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for correcting an optical proximity effect, characterized in that: include: Segmenting the edge of the initial mask pattern into a plurality of segments, and obtaining initial cutting lines corresponding to each segment, wherein the initial cutting lines are orthogonal to the segments; Determine an initial edge placement error corresponding to the current position of the initial cutting line; the initial edge placement error includes a first initial edge placement error in the line width direction of the mask pattern and a second initial edge placement error at the line end position; The positions of the segments are adjusted according to the first initial edge placement error, so that the line widths of the simulated wafer pattern and the reference mask pattern corresponding to the initial mask pattern match, thereby obtaining an intermediate mask pattern; the simulated wafer pattern is a lithography pattern obtained by performing lithography simulation based on the adjusted initial mask pattern, and the reference mask pattern is a target lithography pattern obtained when there is no optical proximity effect corresponding to the initial mask pattern; In the case where the second initial edge placement error exists at the line end of the intermediate mask pattern, adjusting the position of the initial cutting line on the segment based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern to obtain a target mask pattern; The cutting line moving ratio is determined based on the line end length and process node of the initial mask pattern.

2. The optical proximity effect correction method according to claim 1, characterized in that: At least one initial cutting line is arranged on each geometric edge of the initial mask pattern, and at least one initial dividing line is arranged on each segment.

3. The optical proximity effect correction method according to claim 1, characterized in that: The difference between the line end length and the process node is positively correlated with the cutting line movement ratio, and the cutting line movement ratio is negatively correlated with the process node.

4. The method for correcting the optical proximity effect according to claim 1, characterized in that: The line end length and 0.5 power of the difference between the process nodes are proportional to the cutting line movement ratio, and the cutting line movement ratio is inversely proportional to the process node.

5. The optical proximity effect correction method according to claim 4, characterized in that: The ratio between the line end length and the process node is less than or equal to a preset ratio, and the preset ratio is 1-2.

6. The method for correcting the optical proximity effect according to claim 1, characterized in that: The step of adjusting the position of each of the segments according to the first initial edge placement error until the line width of the simulated wafer pattern matches the reference mask pattern corresponding to the initial mask pattern to obtain the intermediate mask pattern comprises: For each of the segments, determining a line width expansion value of the initial cutting line corresponding to the segment according to the first initial edge placement error; Adjusting the initial mask pattern based on the line width expansion values ​​corresponding to the respective segments to obtain an updated mask pattern; Determining an updated first edge placement error corresponding to each of the initial cutting lines in the updated mask pattern according to an edge placement error algorithm; If the updated first edge placement error indicates that the line widths of the simulated wafer pattern corresponding to the updated mask pattern and the reference mask pattern match, the updated mask pattern is determined as the intermediate mask pattern.

7. The method for correcting the optical proximity effect according to claim 6, characterized in that: After determining the updated first edge placement error corresponding to the initial cutting line in the updated mask pattern according to the edge placement error algorithm, the method further includes: If the line widths of the simulated wafer pattern and the reference mask pattern do not match, the steps of determining the line width expansion value of the initial cutting line, adjusting the mask pattern based on the line width expansion value, and updating the first edge placement error are repeated until the updated first edge placement error indicates that the line widths of the simulated wafer pattern and the reference mask pattern match, and the updated mask pattern obtained when the line width match is satisfied is determined as the intermediate mask pattern.

8. The method for correcting the optical proximity effect according to claim 6, wherein: The line width expansion value is determined by the following steps: Obtaining a preset feedback value, where the preset feedback value is a correction coefficient for calculating a mask pattern outward expansion step length based on the first edge placement error; The step length is calculated according to the preset feedback value and the first initial edge placement error to obtain the line width expansion value.

9. The method for correcting the optical proximity effect according to claim 1, characterized in that: In the case where there is a second edge placement error at the line end of the intermediate mask pattern, adjusting the position of the initial cutting line on the segment based on the cutting line movement ratio until the simulated wafer pattern matches the reference mask pattern, and obtaining the target mask pattern includes: When the line end of the intermediate mask pattern has the second edge placement error, adjusting the position of the initial cutting line on the segment corresponding to the line end based on the cutting line movement ratio to obtain an updated cutting line; determining an updated second edge placement error corresponding to the updated current position of the cutting line according to an edge placement error algorithm; adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a line-end updated mask pattern; If the simulated wafer pattern corresponding to the updated line-end mask pattern matches the reference mask pattern, the updated mask pattern at the line-end is determined to be the target mask pattern.

10. The method for correcting the optical proximity effect according to claim 9, characterized in that: After adjusting the intermediate mask pattern according to the updated second edge placement error to obtain a mask pattern with updated line ends, the method further includes: If the simulated wafer pattern corresponding to the updated line-end mask pattern does not match the reference mask pattern, the steps of moving the cutting line, updating the second edge placement error and updating the line end of the mask pattern are repeated until the simulated wafer pattern corresponding to the line-end updated mask pattern matches the reference mask pattern, and the line-end updated mask pattern obtained when the line-end matching is satisfied is determined as the target mask pattern.

11. The method for correcting the optical proximity effect according to any one of claims 1 to 10, characterized in that: The process nodes include at least one of 180nm, 150nm, 130nm, 110nm, 90nm, 65nm, 55nm, 40nm and 28nm.

12. A method for preparing a semiconductor structure, characterized in that: The target mask pattern is prepared based on the correction method for optical proximity effect as described in any one of claims 1 to 11.

13. A semiconductor structure, characterized in that: It is manufactured based on the method for manufacturing a semiconductor structure as claimed in claim 12.

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