Control signal monitoring system for FPGA camera

Abstract

The invention discloses a control signal monitoring system for an FPGA camera, and the system comprises a signal sampling module which is used for obtaining a plurality of control signals in the camera; the clock frequency division module is used for dividing the frequency of a system clock into a signal sampling clock; the control module is used for sampling the control signal according to a preset condition; the bus module is used for transmitting data; wherein the signal sampling module is electrically connected to the control module, the clock frequency division module is electrically connected to the clock frequency division module, and the signal sampling module, the clock frequency division module and the control module are respectively connected to the bus module. The control signal monitoring system for the FPGA camera has the beneficial effects that the accuracy of debugging parameters is improved by directly acquiring a real control signal in the camera.

Description

Technical Field

[0001] The present application relates to the field of camera technology, and in particular to a control signal monitoring system for a FPGA camera. Background Art

[0002] With the development of semiconductor technology and sensor technology, industrial cameras are increasingly used in various fields. Since industrial applications vary greatly and performance and reliability requirements are very high, industrial cameras often use FPGA as the main control chip.

[0003] In industrial applications, multiple cameras are often required for image acquisition, and external triggering is an effective way to achieve precise synchronization between cameras. A unified trigger signal can ensure that all cameras capture images at exactly the same time, which is essential for applications such as 3D reconstruction and motion capture. In different fields, external trigger signals are also different. In the field of automated manufacturing, complex encoder signals are often used as external trigger signals, and photoelectric switch signals are used as trigger enable signals. All these types of signals are collectively referred to as control signals.

[0004] Since the control signal is crucial to the operation of the FPGA camera, interference with the control signal will seriously affect the operation of the camera. During on-site deployment, additional equipment is required to test the on-site signal, debug the signal connection, and set debugging parameters, which is time-consuming and labor-intensive.

[0005] For common FPGA cameras, the on-site deployment process is complicated and requires additional equipment to debug the signal. In addition, the equipment still tests external signals, which are still different from the actual control signals received internally, resulting in the debugged parameters being inaccurate. Summary of the invention

[0006] The content of this application is used to introduce concepts in a brief form, which will be described in detail in the detailed implementation section below. The content of this application is not intended to identify the key features or essential features of the technical solution claimed for protection, nor is it intended to limit the scope of the technical solution claimed for protection.

[0007] Some embodiments of the present application propose a control signal monitoring system for an FPGA camera to solve the technical problems mentioned in the above background technology section.

[0008] As a first aspect of the present application, some embodiments of the present application provide a control signal monitoring system for an FPGA camera, comprising: A signal sampling module is used to obtain several control signals inside the camera; A clock frequency division module, used to divide the system clock into a signal sampling clock; A control module, used for sampling a control signal according to preset conditions; Bus module, used for transmitting data; The signal sampling module is electrically connected to the control module, the clock frequency division module is electrically connected to the clock frequency division module, and the signal sampling module, the clock frequency division module and the control module are respectively connected to the bus module.

[0009] Optionally, the clock frequency division module includes a counter structure designed based on LUT6.

[0010] Optionally, the signal sampling module includes an anti-shake sampling structure designed based on LUT6 and D flip-flop.

[0011] Optionally, the control module includes a state machine structure designed based on LUT6 and D flip-flop.

[0012] Optionally, the control signal includes one or more of an encoder signal, a trigger signal and a trigger enable signal.

[0013] Optionally, the preset condition includes one or more of a preset level change of a control signal, a preset level value of a control signal, and a preset level combination of at least two control signals.

[0014] Optionally, the control signal monitoring system for the FPGA camera includes: A data delay module, used for delaying the control signal acquired by the signal sampling module by a preset clock; Wherein, the data delay module is electrically connected to the signal sampling module.

[0015] Optionally, the data delay module includes a LUTRAM-based shift register.

[0016] Optionally, the control signal monitoring system for the FPGA camera includes: FIFO module, used to store the data of all control signals sampled at one time; Wherein, the FIFO module is electrically connected to the data delay module, the control module and the bus module respectively.

[0017] Optionally, the FIFO module includes 1 BRAM.

[0018] The beneficial effect of the present application is that it provides a control signal monitoring system for an FPGA camera which improves the accuracy of debugging parameters by directly acquiring the real control signal inside the camera.

[0019] More specifically, the present application also includes the following specific beneficial effects: The data cache only needs one BRAM, and the control and clock division and sampling modules only need a few LUT resources. Since all data is cached before transmission, it does not need to pass through DDR, but can be transmitted only through the register ordinary bus, and does not need to use the high-speed bus, which saves a lot of logic resources of the high-speed bus arbitration module and saves the computing resources of the DMA module processing.

[0020] The sampling accuracy can be adjusted from 10ns to 1ms, which can save FPGA resources and meet various IO debugging needs.

[0021] For specific IO debugging needs, specific preset conditions can be configured to control the time to start acquisition, so as to capture the specific waveforms required and improve IO debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The illustrative embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application.

[0023] In addition, throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the components and elements are not necessarily drawn to scale.

[0024] In the attached picture: Figure 1 It is a principle block diagram of a control signal monitoring system for an FPGA camera according to an embodiment of the present application.

[0025] Reference numerals: 100. Monitoring system; 110, signal sampling module; 120, clock frequency division module; 130, control module; 140, bus module; 150. Data delay module; 160. FIFO module; DETAILED DESCRIPTION

[0026] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0027] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0028] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0029] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0030] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0031] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0032] like Figure 1 As shown, the present application provides a control signal monitoring system 100 for an FPGA camera, including: a signal sampling module 110 , a clock frequency division module 120 , a control module 130 and a bus module 140 .

[0033] Specifically, the signal sampling module 110 is used to obtain several control signals inside the camera; the clock division module 120 is used to divide the system clock into a signal sampling clock; the control module 130 is used to sample the control signal (IO signal) according to preset conditions; the bus module 140 is used to transmit data; wherein, the signal sampling module 110 is electrically connected to the control module 130, the clock division module 120 is electrically connected to the clock division module 120, and the signal sampling module 110, the clock division module 120 and the control module 130 are respectively connected to the bus module 140.

[0034] By adopting the above technical solution, the real control signal inside the camera is directly obtained, thereby improving the accuracy of the debugging parameters. At the same time, the system clock (100M) is divided into a signal sampling clock through the clock division module 120, thereby realizing the adjustment function within the range of 10ns to 1ms of acquisition accuracy.

[0035] As a specific solution, the signal sampling module 110 is connected to the trigger control unit of the camera to obtain one or more of the encoder A phase signal, encoder B phase signal, external trigger control signal, time trigger signal, encoder control signal, internal trigger signal, internal control signal, etc.

[0036] In some embodiments, the clock division module 120 includes a counter structure designed based on LUT6 to implement the clock division function.

[0037] In some embodiments, the signal sampling module 110 includes an anti-shake sampling structure designed based on LUT6 and D flip-flop to realize the sampling function.

[0038] In some embodiments, the control module 130 includes a state machine structure based on LUT6 and D flip-flop design.

[0039] In some embodiments, the control signal includes one or more of an encoder signal, a trigger signal, and a trigger enable signal.

[0040] In some embodiments, the preset condition includes one or more of a preset level change of a control signal, a preset level value of a control signal, and a preset level combination of at least two control signals.

[0041] It can be understood that when at least one of the above conditions is met, the control signal is sampled once.

[0042] Exemplarily, the preset level change of the control signal may be that the level of the control signal changes from 0 to 1, or from 1 to 0.

[0043] The preset level value of the control signal may be that the level of the control signal is 1, or that the level of the control signal is 0.

[0044] The preset level combination of the two control signals may be that the level of one of the control signals is 1, and the level of the other control signal is 0.

[0045] By adopting the above solution, for specific IO debugging requirements, specific preset conditions can be configured to control the time of starting acquisition, so as to capture the specific waveform required and improve IO debugging efficiency.

[0046] In some embodiments, the control signal monitoring system 100 for an FPGA camera includes: a data delay module 150 .

[0047] The data delay module 150 is electrically connected to the signal sampling module 110 and is used to delay the control signal acquired by the signal sampling module 110 by a preset clock.

[0048] Exemplarily, the data of the signal sampling is delayed by 32 clocks.

[0049] In some embodiments, the data delay module 150 includes a LUTRAM-based shift register to implement a 32-clock delay function.

[0050] In some embodiments, the control signal monitoring system 100 for an FPGA camera includes: a FIFO module 160 .

[0051] The FIFO module 160 is electrically connected to the data delay module 150 , the control module 130 , and the bus module 140 , respectively, and is used to store data of all control signals sampled at one time.

[0052] In some embodiments, the FIFO module 160 includes 1 BRAM (Block RAM). The data cache of the present application only requires one BRAM, and the control and clock frequency division and sampling modules only require a small number of LUT resources. Since all data are cached before transmission, they do not need to pass through DDR, but can be transmitted only through the register ordinary bus, and do not need to use a high-speed bus, which saves a lot of logic resources of the high-speed bus arbitration module and saves computing resources for DMA module processing.

[0053] As a specific solution, the bus module 140 uses a common register read / write interface to read and send the data buffered in the FIFO without going through the DDR.

[0054] The above descriptions are only some preferred embodiments of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A control signal monitoring system for an FPGA camera, characterized in that: include: A signal sampling module is used to obtain several control signals inside the camera; A clock frequency division module, used to divide the system clock into a signal sampling clock; A control module, used for sampling a control signal according to preset conditions; Bus module, used for transmitting data; The signal sampling module is electrically connected to the control module, the clock frequency division module is electrically connected to the clock frequency division module, and the signal sampling module, the clock frequency division module and the control module are respectively connected to the bus module.

2. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The clock frequency division module includes a counter structure designed based on LUT6.

3. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The signal sampling module includes an anti-shake sampling structure designed based on LUT6 and D trigger.

4. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The control module includes a state machine structure designed based on LUT6 and D flip-flop.

5. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The control signal includes one or more of an encoder signal, a trigger signal and a trigger enable signal.

6. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The preset condition includes one or more of a preset level change of a control signal, a preset level value of a control signal, and a preset level combination of at least two control signals.

7. The control signal monitoring system for FPGA camera according to claim 1, characterized in that: The control signal monitoring system for FPGA camera includes: A data delay module, used for delaying the control signal acquired by the signal sampling module by a preset clock; Wherein, the data delay module is electrically connected to the signal sampling module.

8. The control signal monitoring system for FPGA camera according to claim 7, characterized in that: The data delay module includes a LUTRAM-based shift register.

9. The control signal monitoring system for FPGA camera according to claim 7, characterized in that: The control signal monitoring system for FPGA camera includes: FIFO module, used to store the data of all control signals sampled at one time; Wherein, the FIFO module is electrically connected to the data delay module, the control module and the bus module respectively.

10. The control signal monitoring system for FPGA camera according to claim 9, characterized in that: The FIFO module includes 1 BRAM.

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