Method for calculating pulse width modulation frequency and duty cycle and fan control system

Abstract

The application discloses a pulse width modulation frequency and working period calculation method and a fan control system. The calculation method comprises the following steps: receiving a rotating speed information; converting the rotating speed information into a first two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of M to generate a second two-digit rotating speed information; dividing the first two-digit rotating speed information by 2 raised to the power of P to generate a third two-digit rotating speed information; adding the second two-digit rotating speed information and the third two-digit rotating speed information to generate a fourth two-digit rotating speed information; and generating a rotating speed count signal according to a first system clock frequency and a working period intermediate value by using a counter.

Description

Technical Field

[0001] This invention relates to a method for calculating pulse width modulation frequency and duty cycle, and a fan control system, and particularly to a low-cost method for calculating pulse width modulation frequency and duty cycle, and a fan control system. Background Technology

[0002] Traditionally, in a fan control system, the fan module drives the fan to rotate after receiving a pulse-width modulation (PWM) duty cycle input by the controller. In more complete applications, the fan module simultaneously drives the fan and reports the actual fan speed via a tachometer signal, allowing the controller to assess whether the input duty cycle provides sufficient airflow for cooling. However, obtaining frequency information from fan speed information requires a divider, because fan speed is a variable value. Directly implementing division of a variable value using a divider is not only time-consuming but also consumes significant logic resources, greatly increasing overall costs.

[0003] Therefore, providing a low-cost method for calculating the pulse width modulation frequency and duty cycle, as well as a fan control system, to overcome the aforementioned shortcomings has become an important issue that this project aims to address. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for calculating pulse width modulation frequency and duty cycle, addressing the shortcomings of existing technologies. The method comprises: receiving rotational speed information; converting the rotational speed information into a first two-bit rotational speed information; dividing the first two-bit rotational speed information by 2 to the power of M to generate a second two-bit rotational speed information, where M is an integer; dividing the first two-bit rotational speed information by 2 to the power of P to generate a third two-bit rotational speed information, where P is an integer; adding the second two-bit rotational speed information to the third two-bit rotational speed information to generate a fourth two-bit rotational speed information; obtaining a calculation frequency information based on the fourth two-bit rotational speed information; providing a first system clock frequency, and generating a duty cycle count based on the first system clock frequency and the calculation frequency information; dividing the duty cycle count by 2 to the power of 1 to obtain a duty cycle intermediate value; and using a counter to generate a tachometer signal based on the first system clock frequency and the duty cycle intermediate value.

[0005] Preferably, M equals 5 and P equals 9.

[0006] Preferably, the counter detects multiple rising edges in the first system clock frequency signal as the counting trigger condition.

[0007] Preferably, when the counter calculates a value that triggers the rising edge that is greater than the midpoint of the working cycle, the tachometer signal is a high-level signal; when the counter calculates a value that triggers the rising edge that is less than the midpoint of the working cycle, the tachometer signal is a low-level signal.

[0008] Preferably, the first system clock frequency is provided by a controller, which provides a speed adjustment signal based on the tachometer signal.

[0009] Preferably, the rotational speed information is provided by a fan speed sensor of a fan, and the fan is connected to the controller.

[0010] This invention also discloses a fan control system, characterized in that it includes: a controller; and a fan, including a fan speed sensor, wherein the fan and the fan sensor are electrically connected to the controller; wherein the fan speed sensor provides speed information to the controller, and the controller converts the speed information into a first two-bit speed information; wherein the controller divides the first two-bit speed information by 2 to the power of M to generate a second two-bit speed information, where M is an integer; wherein the controller divides the first two-bit speed information by 2 to the power of P to generate a third two-bit speed information, where P... It is an integer; wherein, the controller adds the second two-bit rotational speed information to the third two-bit rotational speed information to generate a fourth two-bit rotational speed information; the controller obtains a calculation frequency information based on the fourth two-bit rotational speed information; wherein, the controller provides a first system clock frequency and generates a number of working cycles based on the first system clock frequency and the calculation frequency information; the number of working cycles is divided by 2 to obtain a working cycle intermediate value; and wherein, the controller uses a counter to generate a tachometer signal based on the first system clock frequency and the working cycle intermediate value.

[0011] Preferably, M equals 5 and P equals 9.

[0012] Preferably, the counter detects multiple rising edges or multiple falling edges in the first system clock frequency signal as the counting trigger condition.

[0013] Preferably, when the counter calculates a value that triggers the rising edge or the falling edge that is greater than the midpoint of the working cycle, the tachometer signal is a high-level signal; when the counter calculates a value that triggers the rising edge or the falling edge that is less than the midpoint of the working cycle, the tachometer signal is a low-level signal.

[0014] One of the beneficial effects of the present invention is that the method for calculating the pulse width modulation frequency and working cycle provided by the present invention replaces the division operation with the addition operation, which can greatly reduce the logic resources for converting fan speed into frequency, thereby not only reducing costs but also improving efficiency.

[0015] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the fan control system according to the first embodiment of the present invention.

[0017] Figure 2 This is a flowchart of the calculation method for pulse width modulation frequency and duty cycle according to the first embodiment of the present invention.

[0018] Figure 3 yes Figure 1 A schematic diagram of the working cycle of the fan speed information.

[0019] Figure 4 This is a diagram showing the fan speed and frequency corresponding to the fan's working cycle.

[0020] Figure 5 This is a schematic diagram of a tachometer signal with a frequency of 519Hz. Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the "Calculation Method for Pulse Width Modulation Frequency and Duty Cycle and Fan Control System" disclosed in this invention. Those skilled in the art can understand the advantages and effects of this invention from the content disclosed in this specification. This invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this invention. Furthermore, the accompanying drawings of this invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of this invention in detail, but the disclosed content is not intended to limit the scope of protection of this invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0022] [First Embodiment]

[0023] See Figure 1 as well as Figure 2 , Figure 1 This is a schematic diagram of the fan control system according to the first embodiment of the present invention. Figure 2 This is a flowchart of the calculation method for pulse width modulation frequency and duty cycle according to the first embodiment of the present invention.

[0024] This embodiment provides a method for calculating the pulse width modulation frequency and duty cycle. This method is applicable to a fan control system SYS1. The fan control system SYS1 includes a controller 11 and a fan 12.

[0025] The calculation method for pulse width modulation frequency and duty cycle includes the following steps: Receive a rotation speed information (step S110); Convert the rotation speed information into a first two-bit rotation speed information (step S120). Divide the first two-bit rotational speed information by 2 to the power of M to generate a second two-bit rotational speed information (step S130). Divide the first two-bit rotation speed information by 2 to the power of P to generate a third two-bit rotation speed information (step S140). Add the second two-bit rotation speed information to the third two-bit rotation speed information to generate a fourth two-bit rotation speed information (step S150). A calculated frequency information is obtained based on the fourth two-bit rotational speed information (step S160). A first system clock frequency is provided, and a number of working cycles is generated based on the first system clock frequency and the calculated frequency information (step S170). Divide the number of work cycles by 2 to the power of 1 to obtain the intermediate value of one work cycle (step S180); and A tachometer signal is generated using a counter based on the first system clock frequency and the intermediate value of the working cycle (step S190).

[0026] In steps S110 and S120, the controller 11 is connected to a fan 12. The fan 12 is equipped with a fan speed sensor 121. The controller 11 is connected to the fan speed sensor 121 to receive the fan speed information of the fan 12.

[0027] The speed information is the rotational speed (RPM) of fan 12. It can be represented by N. That is, the speed information N indicates that fan 12 rotates N times in one minute (60 seconds).

[0028] like Figure 3 As shown, if the time for fan 12 to complete one revolution is expressed as the single-revolution time T', then the single-revolution time T' is 60 / N (seconds). As shown in Formula 1 below: – Formula 1 A fan completes two operating cycles in one revolution time T', which includes two high-level time regions and two low-level time regions. One operating cycle consists of the high-level time region plus one low-level time region. Therefore, half a revolution time T' constitutes one operating cycle T.

[0029] The working cycle T is shown in the following formula: – Formula 2 The controller 11 receives the fan speed information N from the fan 12 and converts the speed information N into a first two-bit speed information.

[0030] In steps S130, S140, and S150, using powers of 2 as the divisor in the binary information calculation can significantly reduce the computational load. Previously, the formula for calculating the working period T involved dividing 30 by the rotational speed N. Since the frequency (F) is the reciprocal of the period (T), we get frequency (F) = N / 30. While the value 30 is not an integer power of 2, it is close to 2 to the power of 5, or 32. Therefore, the calculation of the value 30 can be completed using two or more two-dimensional calculation processes.

[0031] In step S130, the first two-bit rotational speed information is divided by 2 to the power of M to generate a second two-bit rotational speed information, where M is an integer. In this embodiment, M equals 5. The second two-bit rotational speed information is N / 32. That is, the second two-bit rotational speed information is obtained by right-shifting the first two-bit rotational speed information by 5 bits.

[0032] In step S140, the first two-bit rotational speed information is divided by 2 raised to the power of P to generate a third two-bit rotational speed information, where P is an integer. In this embodiment, P equals 9. The third two-bit rotational speed information is N / 512. That is, the third two-bit rotational speed information is obtained by right-shifting the first two-bit rotational speed information by 9 bits. In other embodiments, M and P can be chosen as different numbers to perform approximate value calculations.

[0033] In step S150, the second two-bit rotational speed information is added to the third two-bit rotational speed information to generate the fourth two-bit rotational speed information, which can then obtain the value of the frequency (N / 30) corresponding to the approximate working period T.

[0034] The error rate calculated using the above method can be obtained from the following formula: (N / 30- (N / 32+N / 512)) / (N / 30)=30(1 / 30-17 / 512)=0.39% If users want to further reduce the error rate, they can add 2 to the power of 10 or 2 to the power of 11 calculations to reduce the error rate.

[0035] In this embodiment, for example Figure 4 as well as Figure 5 As shown, the maximum speed information (N) of fan 12 is approximately 30,000 revolutions per minute. If calculated using the formula frequency (F) = N / 30, when the maximum speed information (N) is 30,000 revolutions per minute, the maximum clock frequency (F) of the output tachometer signal must be below 1 kHz. In other embodiments, calculations can be performed based on other speed information (N) and related parameters; this is not limited in this invention.

[0036] In step S160, the fourth two-bit rotation speed information is converted into calculated frequency information, which is a frequency estimate of a fan.

[0037] In step S170, the first system clock frequency is 32KHz. When the calculated frequency information is 519Hz, the number of working cycles can be obtained as 32KHz / 519Hz=61 (times).

[0038] In step S180, the number of work cycles needs to be divided by 2 to obtain the intermediate value of the work cycle, which is the midpoint between the high-level region and the low-level region of the work cycle. Alternatively, the two-bit information of the number of work cycles can be shifted right by one bit to obtain the intermediate value of the work cycle.

[0039] Dividing the number of working cycles of S170 by 2 gives 61 / 2 = 30 (cycles).

[0040] In step S190, a counter is used to generate a tach signal based on the first system clock frequency (32KHz) and the intermediate value of the working cycle.

[0041] First, a counter (not shown) is used with multiple rising edges of the first system clock frequency (32kHz) as the counting trigger condition. That is, each time a rising edge is encountered when the first system clock frequency transitions from the low level region to the high level region, the counter (not shown) counts once. The counting will restart when the counter (not shown) counts equal to the number of working cycles.

[0042] If the counter (not shown) counts a value greater than the midpoint of the working cycle, the output tachometer signal is a high-level signal. If the counter (not shown) counts a value less than the midpoint of the working cycle, the output tachometer signal is a low-level signal.

[0043] For example, taking a calculated frequency of 519Hz as an example, when the counter with an initial value of 1 counts from 1 to 30 times, the output tachometer signal is a low-level signal. When the counter counts from 31 to 61 times, the output tachometer signal is a high-level signal. Since the first system clock frequency is 32kHz, its corresponding period is 1 / 32000 = 321250ns. The period of the tachometer signal is 1 / 32000. 61 = 1906250ns. The tachometer signal consists of one low-level signal and one high-level signal. The number 61 represents the number of working cycles mentioned earlier, calculated as 32kHz / 519Hz = 61 (cycles). Further, the period corresponding to the calculated frequency information of 519Hz is 1 / 519 = 1926782ns. Therefore, the error rate is approximately 1%, calculated by subtracting the tachometer signal period from the period of the calculated frequency information of 519Hz, then dividing by the calculated frequency information of 519Hz to obtain the percentage error rate. The calculation process is equal to (1926782 - 1906250) / 1926782 = 1%.

[0044] In this embodiment, the first system clock frequency is provided by the controller 11. The controller provides a speed adjustment signal based on the tachometer signal.

[0045] In addition, the counter (not shown) can also use multiple falling edges of the first system clock frequency (32kHz) as counting trigger conditions. That is, each time a falling edge is encountered when the first system clock frequency transitions from the high level region to the low level region, the counter (not shown) will count once. It will start counting again when the count value of the counter (not shown) equals the number of working cycles.

[0046] Furthermore, the counter (not shown) can count forward or backward. Counting forward means starting from 1. Counting backward means starting from a larger number (e.g., 1000) and counting backward.

[0047] The controller 11 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a microprocessor (MCU), a complex programmable logic device (CPLD), or a field-programmable gate array (FPGA).

[0048] The fan speed sensor 121 can be a Hall sensor.

[0049] [Second Embodiment]

[0050] Please see Figures 1 to 5 The fan control system SYS1 includes a controller 11 and a fan 12. The controller 11 is connected to the fan 12. The fan also includes a fan speed sensor 121. The controller 11 is connected to the fan speed sensor 121 to receive fan speed information.

[0051] The speed information is the rotational speed (RPM) of fan 12. It can be represented by N. That is, the speed information N indicates that fan 12 rotates N times in one minute (60 seconds).

[0052] If the time it takes for fan 12 to complete one revolution is expressed as the single-revolution time T', then the single-revolution time T' is 60 / N (seconds), as shown in Formula 1 above.

[0053] like Figure 3 As shown, a fan experiences two operating cycles in one revolution time T', which means it experiences two high-level time regions and two low-level time regions. One high-level time region plus one low-level time region constitutes one operating cycle. Therefore, half a revolution time T' equals one operating cycle T. The operating cycle T is shown in Formula 2 above.

[0054] That is, the controller 11 receives the speed information N of the fan 12 and converts the speed information N into a first two-bit speed information.

[0055] In binary information calculations, using powers of 2 as divisors can significantly reduce the computational load. In the previous formula for calculating the working period T, 30 was divided by the rotational speed N. Since frequency (F) is the reciprocal of period (T), we get frequency (F) = N / 30. The value 30 is not an integer power of 2, but it is close to 2 to the power of 5, or 32. Therefore, the calculation of the value 30 can be completed using two or more two-dimensional calculations.

[0056] First, the controller 11 divides the first two-bit rotational speed information by 2 to the power of M to generate a second two-bit rotational speed information, where M is an integer. In this embodiment, M equals 5. The second two-bit rotational speed information is N / 32. That is, the second two-bit rotational speed information is obtained by right-shifting the first two-bit rotational speed information by 5 bits.

[0057] Furthermore, controller 11 divides the first two-bit rotational speed information by 2 raised to the power of P to generate a third two-bit rotational speed information, where P is an integer. In this embodiment, P equals 9. The third two-bit rotational speed information is N / 512. That is, the third two-bit rotational speed information is obtained by right-shifting the first two-bit rotational speed information by 9 bits. In other embodiments, M and P can be chosen as different numbers to perform approximate value calculations.

[0058] The two binary division operations above can be easily and quickly completed by right-shifting the two bits by a few bits.

[0059] Next, the controller 11 will add the second two-bit rotational speed information to the third two-bit rotational speed information to generate the fourth two-bit rotational speed information, so as to obtain the value of the frequency (N / 30) corresponding to the approximate working period T.

[0060] The error rate calculated using the above method can be obtained from the following formula: (N / 30-(N / 32+N / 512)) / (N / 30)=30(1 / 30-17 / 512)=0.39% If users want to further reduce the error rate, they can add a division process of 2 to the power of 10 or 2 to the power of 11 to reduce the error rate.

[0061] The maximum speed information (N) of fan 12 is approximately 30,000 revolutions per minute. If calculated using the formula (F) = N / 30, when the maximum speed information (N) is 30,000 revolutions per minute, the maximum clock frequency (F) of the output tach signal must be below 1 kHz.

[0062] Next, the controller 11 can convert the fourth two-bit rotation speed information into a calculated frequency information, which is a frequency estimate of the fan 12.

[0063] Here, taking the frequency information 519Hz as an example, the first system clock frequency is 32KHz. When the calculated frequency information is 519Hz, the number of working cycles can be obtained as 32KHz / 519Hz=61 (times).

[0064] Next, controller 12 divides the number of work cycles by 2 to obtain the intermediate value of the work cycle, which is the midpoint between the high-level region and the low-level region of the work cycle. Alternatively, controller 12 can right-shift the two-bit information of the number of work cycles by one bit to obtain the intermediate value of the work cycle.

[0065] When the number of work cycles is divided by 2, we get 61 / 2 = 30 (times).

[0066] Furthermore, the controller 11 uses a counter to generate a tachometer signal based on the first system clock frequency (32KHz) and the intermediate value of the working cycle.

[0067] First, the controller 11 needs to use a counter (not shown) with multiple rising edges of the first system clock frequency (32kHz) as counting trigger conditions. That is, each time a rising edge is encountered when the first system clock frequency transitions from a low level region to a high level region, the counter (not shown) counts once. The counting resumes when the counter (not shown) reaches the number of operating cycles. In this embodiment, the counter (not shown) can be implemented using software, hardware, or firmware.

[0068] If the counter (not shown) counts a value greater than the midpoint of the working cycle, the output tachometer signal is a high-level signal. If the counter (not shown) counts a value less than the midpoint of the working cycle, the output tachometer signal is a low-level signal.

[0069] In this embodiment, the first system clock frequency is provided by the controller 11. The controller 11 provides a speed adjustment signal based on the tachometer signal.

[0070] In addition, the counter (not shown) can also use multiple falling edges of the first system clock frequency (32kHz) as counting trigger conditions. That is, each time a falling edge is encountered when the first system clock frequency transitions from the high level region to the low level region, the counter (not shown) will count once. It will start counting again when the count value of the counter (not shown) equals the number of working cycles.

[0071] For example, taking a calculated frequency of 519Hz as an example, when the counter with an initial value of 1 counts from 1 to 30 times, the output tachometer signal is a low-level signal. When the counter counts from 31 to 61 times, the output tachometer signal is a high-level signal. Since the first system clock frequency is 32kHz, its corresponding period is 1 / 32000 = 321250ns. The period of the tachometer signal is 1 / 32000. 61 = 1906250ns. The tachometer signal consists of one low-level signal and one high-level signal. The number 61 represents the number of working cycles mentioned earlier, calculated as 32kHz / 519Hz = 61 (times). Further, the period corresponding to the calculated frequency information of 519Hz is 1 / 519 = 1926782ns. Therefore, the error rate is approximately 1%, calculated by subtracting the period of the tachometer signal from the period of the calculated frequency information of 519Hz, then dividing by the period of the calculated frequency information of 519Hz to obtain the percentage error rate. The calculation process is equal to (1926782 - 1906250) / 1926782 = 1%.

[0072] Furthermore, the counter (not shown) can count forward or backward. Counting forward means starting from 1. Counting backward means starting from a larger number (e.g., 1000) and counting backward.

[0073] The controller 11 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a microprocessor (MCU), a complex programmable logic device (CPLD), or a field-programmable gate array (FPGA).

[0074] The fan speed sensor 121 can be a Hall sensor.

[0075] [Beneficial Effects of the Examples]

[0076] One of the beneficial effects of the present invention is that the method for calculating the pulse width modulation frequency and working cycle provided by the present invention replaces the division operation with the addition operation, which can greatly reduce the logic resources for converting fan speed into frequency, thereby not only reducing costs but also improving efficiency.

[0077] The above-disclosed content is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included within the scope of the claims of the present invention.

Claims

1. A method for calculating pulse width modulation frequency and duty cycle, characterized in that, include: Receive rotational speed information; The rotation speed information is converted into a first binary rotation speed information; Divide the first binary rotation speed information by 2 to the power of M to generate a second binary rotation speed information, where M is an integer. Divide the first binary rotation speed information by 2 to the power of P to generate a third binary rotation speed information, where P is an integer. The second binary speed information is added to the third binary speed information to generate a fourth binary speed information; A calculated frequency information is obtained based on the fourth binary rotation speed information; A first system clock frequency is provided, and a number of duty cycles is generated based on the first system clock frequency and the calculated frequency information; Divide the number of work cycles by 2 to the power of 1 to obtain the intermediate value of a work cycle; as well as A counter is used to generate a tachometer signal based on the first system clock frequency and the intermediate value of the working cycle, wherein M and P are not equal, and M and P are adjusted according to an error rate between the calculated frequency information and the fourth binary speed information to reduce the error rate.

2. The method for calculating the pulse width modulation frequency and duty cycle as described in claim 1, characterized in that, M equals 5, and P equals 9.

3. The method for calculating the pulse width modulation frequency and duty cycle as described in claim 1, characterized in that, The counter detects multiple rising edges in the first system clock frequency signal as counting trigger conditions.

4. The method for calculating the pulse width modulation frequency and duty cycle as described in claim 3, characterized in that, When the counter calculates a value that triggers the rising edge that is greater than the midpoint of the working cycle, the tachometer signal is a high-level signal; when the counter calculates a value that triggers the rising edge that is less than the midpoint of the working cycle, the tachometer signal is a low-level signal.

5. The method for calculating the pulse width modulation frequency and duty cycle as described in claim 4, characterized in that, The first system clock frequency is provided by a controller, which provides a speed adjustment signal based on the tachometer signal.

6. The method for calculating the pulse width modulation frequency and duty cycle as described in claim 5, characterized in that, The rotational speed information is provided by a fan speed sensor of a fan connected to the controller.

7. A fan control system, characterized in that, include: One controller; as well as A fan, including a fan speed sensor, wherein the fan and the fan sensor are electrically connected to the controller; The fan speed sensor provides speed information to the controller, which converts the speed information into a first binary speed information. The controller divides the first binary speed information by 2 to the power of M to generate a second binary speed information, where M is an integer. The controller divides the first binary speed information by 2 to the power of P to generate a third binary speed information, where P is an integer. The controller adds the second binary speed information to the third binary speed information to generate a fourth binary speed information. The controller obtains a calculated frequency information based on the fourth binary speed information; The controller provides a first system clock frequency and generates a number of working cycles based on the first system clock frequency and the calculation frequency information. Divide the number of work cycles by 2 to the power of 1 to obtain the median value of a work cycle; and The controller uses a counter to generate a tachometer signal based on the first system clock frequency and the intermediate value of the working cycle. M and P are not equal, and M and P are adjusted according to an error rate between the calculated frequency information and the fourth binary speed information to reduce the error rate.

8. The fan control system as described in claim 7, characterized in that, M equals 5, and P equals 9.

9. The fan control system as described in claim 7, characterized in that, The counter detects multiple rising edges or multiple falling edges in the first system clock frequency signal as counting trigger conditions.

10. The fan control system as described in claim 9, characterized in that, When the counter calculates a value that triggers the rising edge or the falling edge that is greater than the midpoint of the working cycle, the tachometer signal is a high-level signal; when the counter calculates a value that triggers the rising edge or the falling edge that is less than the midpoint of the working cycle, the tachometer signal is a low-level signal.

Images