A request management apparatus and method, DPU, storage medium, program product

Abstract

The application relates to a request management device and method, a DPU, a storage medium, and a program product. The device comprises a management unit, which comprises a memory, a row bitmap register, a row scheduler, a data bitmap register, and a control module. The plurality of bits of the memory correspond to virtual queues one by one and are arranged in rows and columns. The value of each bit is used to indicate whether a to-be-scheduled request is cached. The row bitmap register is used to indicate whether each row has a to-be-scheduled request. The row scheduler is used to select a target row from the rows having to-be-scheduled requests. The data bitmap register is used to cache all bit data of the target row. The column scheduler is used to select a target column from the data bitmap register. The control module is used to receive a to-be-scheduled request, set the corresponding position in the memory to 1 according to the virtual queue number in the to-be-scheduled request, calculate a target virtual queue according to the target row selected by the row scheduler and the target column selected by the column scheduler, and output a target to-be-scheduled request. The application can reduce resource consumption and automatically merge repeated requests.

Description

Technical Field

[0001] This application relates to the field of virtio technology, specifically to a request management device and method, a data processing unit (DPU), a computer-readable storage medium, and a computer program product. Background Technology

[0002] VirtIO is an I / O paravirtualization framework whose system architecture consists of two parts: front-end drivers and back-end devices. In traditional implementations, back-end devices are simulated by software on the host (such as QEMU or vhost). In hardware offloading architecture, back-end devices are offloaded to hardware devices such as data processing units and smart network cards. That is, the host runs the virtIO front-end driver, and the functions of the back-end devices are implemented by the hardware devices. The host and the hardware devices communicate through the PCIe bus.

[0003] Data is transferred between the host and hardware devices via shared virtual queues. To achieve high concurrency and throughput, a large number of virtual queues are required. Each virtual queue may generate multiple consecutive interrupt requests (MSI-X interrupts) or doorbell requests within a short period. Doorbell requests are sent from the host to the hardware device to notify it that a new request is pending in the virtual queue, while interrupt requests are sent from the hardware device to the host to notify it that a request has been completed. Functionally, multiple consecutive requests from the same virtual queue only require one valid notification, because after the host or hardware device processes the first notification, subsequent duplicate requests arriving within a short period are redundant.

[0004] Currently, linked lists are commonly used to cache and manage large numbers of requests. This approach requires allocating a node for each request and managing nodes through head pointers, tail pointers, and free chains. However, when the number of requests is enormous, linked lists need to maintain complex free chain management logic, which is difficult to implement and consumes a lot of hardware resources. In addition, linked lists cannot automatically merge duplicate requests; multiple interrupted requests in the same queue will generate multiple linked list nodes, resulting in wasted PCIe bandwidth and decreased host CPU performance. Summary of the Invention

[0005] This application provides a request management apparatus and method, a DPU, a computer-readable storage medium, and a computer program product for reducing resource consumption and automatically merging duplicate requests when managing a large number of requests.

[0006] According to a first aspect, embodiments of this application provide a request management device, including at least one management unit, the management unit comprising:

[0007] The memory includes multiple bits arranged in an m-row-n-column configuration. Each bit uniquely corresponds to a virtual queue. The value of each bit is used to indicate whether the management unit has received a scheduling request for the corresponding virtual queue, where m and n are positive integers. A row bitmap register, comprising n bits, wherein the value of each bit of the row bitmap register is used to indicate whether the corresponding row of the memory is cached with a scheduling request; A row scheduler, in response to a first scheduling enable signal, determines a target row based on the values ​​of multiple bits in the row bitmap register; A data bitmap register, comprising m bits, is used to store the values ​​of the m bits of the target row; A column scheduler, in response to a second scheduling enable signal, determines a target column based on the value in the data bitmap register; The control module is configured to generate a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register, and in response to the target row determined by the row scheduler, write the values ​​of m bits of the target row in the memory into the data bitmap register; and generate a second scheduling enable signal based on the values ​​in the data bitmap register, and in response to the target column confirmed by the column scheduler, obtain a target scheduling request based on the row number of the target row and the column number of the target column, and output it to the next-level module.

[0008] In one specific implementation, the control module is specifically used for: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

[0009] In one specific implementation, the control module is specifically used for: A scheduling request is received. The corresponding first target bit in the memory is determined according to the virtual queue number carried in the scheduling request. If the value of the first target bit is 0, the value of the first target bit is set to 1. If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, the value of the second target bit is set to 1. Otherwise, the value of the second target bit is not updated.

[0010] In one specific implementation, the control module is further configured to, after writing the values ​​of m bits of the target row in the memory into the data bitmap register, clear the target row in the memory and clear the bits in the row bitmap register corresponding to the target row; and, after outputting the target scheduling request to the next level module, clear the bits in the data bitmap register corresponding to the target column.

[0011] In one specific implementation, the request management device includes at least two management units and an output scheduler, with each management unit corresponding to a host; The output scheduler is connected to the at least two management units and is used to select one of the scheduling requests output by the at least two management units for output.

[0012] In one specific implementation, each of the management units further includes: A mask bitmap register, wherein multiple bits of the mask bitmap register correspond one-to-one with multiple input channels, and the value of each bit of the mask bitmap register is used to indicate whether the scheduling request input on the corresponding input channel should be received by this management unit. The control module is further configured to acquire a request vector to be scheduled, and perform a bitwise AND operation between the request vector to be scheduled and the values ​​of multiple bits in the mask bitmap register to determine the request to be scheduled to be received; wherein, the request vector to be scheduled is a multi-bit vector, and the value of each bit of the request vector to be scheduled is used to indicate whether a request to be scheduled has been received on the corresponding input channel.

[0013] In one specific implementation, the request management device supports receiving multiple scheduled requests in parallel within one clock cycle. The multiple scheduled requests belong to different management units, or the multiple scheduled requests belong to the same management unit and the virtual queue numbers carried by the multiple scheduled requests correspond to the same row of the memory.

[0014] In one specific implementation, a request distribution module is also included. The request distribution module is used to determine the target management unit based on the management unit number carried by the scheduling request input through the input channel, and send the scheduling request to the target management unit.

[0015] In one specific implementation, the control module is used for: In response to receiving a priority processing instruction, the corresponding third target bit in the memory is determined according to the virtual queue number carried by the priority processing instruction. If the third target bit is 1, a scheduling request is generated according to the virtual queue number carried by the priority processing instruction, the scheduling request is output, and the third target bit is cleared to zero.

[0016] According to a second aspect, embodiments of this application provide a request management method, including: Receive a scheduling request and determine the virtual queue number carried in the scheduling request; The values ​​of the corresponding bits in the memory and row bitmap register are updated according to the virtual queue number carried in the scheduling request; wherein, the memory includes multiple bits, which are arranged in an m-row n-column manner, each bit uniquely corresponds to a virtual queue, and the value of each bit is used to indicate whether the management unit has received the scheduling request of the corresponding virtual queue, where m and n are positive integers; the row bitmap register includes n bits, and the value of each bit of the row bitmap register is used to indicate whether the corresponding row of the memory has cached the scheduling request; A first scheduling enable signal is generated based on the values ​​of the data bitmap register and the row bitmap register. The first scheduling enable signal is used to control the row scheduler to determine a target row based on the values ​​of multiple bits in the row bitmap register. In response to the target row determined by the row scheduler, the m bits of the target row in the memory are written into the data bitmap register; A second scheduling enable signal is generated based on the value in the data bitmap register. The second scheduling enable signal is used to control the column scheduler to determine the target scheduling request based on the value in the data bitmap register. The data bitmap register includes m bits for storing the values ​​of the m bits of the target row. In response to the target column confirmed by the column scheduler, a target scheduling request is obtained based on the row number of the target row and the column number of the target column, and then output to the next level module.

[0017] In one specific implementation, generating the first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register includes: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated based on the value in the data bitmap register: The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

[0018] In one specific implementation, updating the values ​​of the corresponding bits in the memory and row bitmap register according to the virtual queue number carried by the scheduling request specifically includes: The first target bit in the memory is determined based on the virtual queue number carried in the scheduling request; If the value of the first target bit is 0, then set the value of the first target bit to 1; If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, then the value of the second target bit is set to 1.

[0019] In one specific implementation, the method specifically includes: After writing the m bits of the target row in the memory into the data bitmap register, the target row in the memory is cleared to zero, and the bits in the row bitmap register corresponding to the target row are cleared to zero. After outputting the target scheduling request to the next level module, the bit corresponding to the target column in the data bitmap register is cleared to zero.

[0020] According to a third aspect, embodiments of this application provide a data processing unit (DPU) including the request management device as described in the first aspect.

[0021] According to a fourth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in the second aspect.

[0022] According to a fifth aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in the second aspect.

[0023] The request management apparatus and method, data processing unit (DPU), computer-readable storage medium, and computer program product according to embodiments of this application have the following beneficial effects: This approach can be applied to electronic devices that need to cache and schedule multiple requests. By allocating a fixed bit (1 bit) in memory (e.g., RAM) for each virtual queue, the value of which (0 / 1) indicates whether there is a request to be scheduled in the corresponding virtual queue. This eliminates the need to maintain an idle chain and head and tail pointers, greatly simplifying hardware design and saving logic resources. At the same time, when multiple requests to be scheduled for the same virtual queue are received, since the corresponding bit in the memory for that virtual queue has already been set to 1 when the first request is received, subsequent requests will not change the value of the corresponding bit in the memory. This automatically merges multiple requests to be scheduled for the same virtual queue into one processing step, avoiding the waste of system bandwidth caused by duplicate requests. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of a management unit in one embodiment of this application.

[0026] Figure 2 This is a schematic diagram of the structure of a management unit in one embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the structure of a management unit in one embodiment of this application.

[0028] Figure 4 This is a schematic diagram of the structure of a management unit in one embodiment of this application.

[0029] Figure 5 This is a flowchart illustrating a request management method in one embodiment of this application.

[0030] Marked in the image: 1-Memory, 2-Row bitmap register, 3-Row scheduler, 4-Data bitmap register, 5-Column scheduler, 6-Control module, 7-Mask bitmap register, 10-Management unit, 20-Output scheduler, 30-Request dispatch module. Detailed Implementation

[0031] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0032] This application provides a request management device that can be integrated into electronic devices that need to cache and schedule multiple requests, such as data processing units (DPUs), smart network cards, server chips, or other hardware acceleration devices. It can be used to solve the problem of large-scale caching and efficient scheduling of doorbell requests and interrupt requests in virtio multi-queue scenarios, reduce hardware resource consumption, automatically merge duplicate requests in the same virtual queue, and avoid PCIe bandwidth waste and host CPU performance degradation.

[0033] Please see Figure 1The request management device in this embodiment includes at least one management unit. The management unit includes a memory, a row bitmap register, a row scheduler, a data bitmap register, a column scheduler, and a control module. The memory is, for example, random access memory (RAM). The row scheduler is connected to the row bitmap register, the column scheduler is connected to the data bitmap register, and the control module is connected to the memory, the row bitmap register, the data bitmap register, the row scheduler, and the column scheduler, respectively.

[0034] The memory includes multiple bits arranged in m rows and n columns. Each bit uniquely corresponds to a virtual queue. The value of each bit is used to indicate whether the management unit has received a scheduling request for the corresponding virtual queue, where m and n are positive integers. Specifically, each bit in the memory occupies only 1 bit, with a value of 1 indicating that there is a request to be processed in the corresponding virtual queue, and a value of 0 indicating that there is no request. Multiple bits are arranged in a row and column manner, for example, arranged in 256 rows × 64 columns. In a specific embodiment, the virtual queue number is represented by a set of binary bits. The high-order bits of the binary number are used to locate the row address in the memory, and the low-order bits are used to locate the column address, thereby realizing a fixed mapping relationship between each virtual queue and a unique bit in RAM. Since each virtual queue occupies only one bit, compared with the traditional linked list scheme (each request requires multiple bytes of node storage), only 16K bits of RAM are needed for 16K virtual queues, which greatly saves storage resources. At the same time, there is no need to maintain free chains and head and tail pointers, simplifying hardware design.

[0035] The row bitmap register includes n bits, and the value of each bit in the row bitmap register is used to indicate whether the corresponding row of the memory is cached with a scheduling request; Specifically, the n bits of the row bitmap register correspond one-to-one with the n rows of the memory. If there is at least one bit with a value of 1 in a certain row of the memory, the corresponding bit in the row bitmap register is 1; otherwise, it is 0. The bit width (n) of the row bitmap register is equal to the number of rows (n) of the memory. Through the row bitmap register, it is possible to quickly determine which rows have requests to be processed without traversing the entire RAM, thereby improving the initial efficiency of scheduling and reducing unnecessary RAM accesses.

[0036] The row scheduler is used to determine a target row based on the values ​​of multiple bits in the row bitmap register in response to a first scheduling enable signal. Specifically, the row scheduler reads the values ​​of multiple bits in the row bitmap register, selects one bit from the bits with a value of 1 using a preset scheduling algorithm, and determines the row corresponding to the selected bit as the target row; the preset scheduling algorithm is, for example, a round-robin algorithm, which ensures that requests for each row can be scheduled fairly and avoids a row not being scheduled for a long time.

[0037] The data bitmap register includes m bits for storing the values ​​of the m bits of the target row; Specifically, the data bitmap register is used to temporarily store the values ​​of all bits of the target row read from memory. The bit width of the data bitmap register is equal to the number of columns in the memory (e.g., 64 bits). The m bits of the data bitmap register correspond one-to-one with the m columns of the target row. The data stored in the data bitmap register serves as a copy of the currently scheduled row, enabling column scheduling to be performed quickly and directly based on the data bitmap register without repeatedly accessing RAM. This significantly improves the efficiency of column scheduling while reducing RAM read / write power consumption.

[0038] A column scheduler, in response to a second scheduling enable signal, determines a target column based on the value in the data bitmap register; Specifically, the column scheduler reads the values ​​of multiple bits in the data bitmap register, selects one bit from the bits with a value of 1 using a preset scheduling algorithm, and determines the column corresponding to the selected bit as the target column.

[0039] The control module is configured to generate a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register, and in response to the target row determined by the row scheduler, write the values ​​of m bits of the target row in the memory into the data bitmap register; and generate a second scheduling enable signal based on the values ​​in the data bitmap register, and in response to the target column confirmed by the column scheduler, obtain a target scheduling request based on the row number of the target row and the column number of the target column, and output it to the next-level module.

[0040] Specifically, the control module generates a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register, and sends the first scheduling enable signal to the row scheduler to drive the row scheduler to perform row scheduling operations. It also generates a second scheduling enable signal based on the value in the data bitmap register and sends the second scheduling enable signal to the column scheduler to drive the column scheduler to perform column scheduling operations. The control module obtains the row number of the target row output by the row scheduler and the column number of the target column output by the column scheduler. Based on the row number of the target row and the column number of the target column, it determines the corresponding target bit in the memory, obtains the target virtual queue number of the target virtual queue corresponding to the target bit, generates a scheduling request for the target virtual queue based on the target virtual queue number, and outputs it to the next-level module.

[0041] It should be noted that the values ​​of the row bitmap register, row scheduler, data bitmap register, and column scheduler are updated in real time based on the reception and scheduling of the requests to be scheduled. For example, when a new request is enqueued, the corresponding bit in the row bitmap register may change from 0 to 1; when a row of data is retrieved from RAM, the corresponding bit in the row bitmap register changes from 1 to 0; the data bitmap register is updated when each row is read and cleared sequentially after each column request is output; the row scheduler and column scheduler dynamically select the next target row or target column based on the real-time changing bitmap values.

[0042] As can be seen from the above embodiments, the device of this embodiment can be applied to electronic devices that need to cache and schedule multiple pending requests. By allocating a fixed bit (1 bit) in memory (e.g., RAM) for each virtual queue, the value of which (0 / 1) is used to indicate whether there is a pending request in the corresponding virtual queue. There is no need to maintain an idle chain and head and tail pointers, which greatly simplifies the hardware design and saves logic resources. At the same time, when multiple pending requests for the same virtual queue are received, since the corresponding bit in the memory of the virtual queue has been set to 1 when the first pending request is received, subsequent pending requests will not change the value of the corresponding bit in the memory. Thus, multiple pending requests for the same virtual queue are automatically merged into one processing, avoiding the waste of system bandwidth caused by duplicate requests.

[0043] In one embodiment, the control module is specifically used for: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

[0044] Specifically, when all values ​​in the data bitmap register are 0, it indicates that all scheduled requests for the current target row have been scheduled. When not all values ​​in the row bitmap register are 0, it indicates that there are still unscheduled requests in the memory. Therefore, it is necessary to continue scheduling the scheduled requests for the next row in the memory, generating the first scheduling enable signal and sending it to the row scheduler. When at least one value in the data bitmap register is non-zero, it indicates that there are still unscheduled requests for the current target row. In this case, it is necessary to continue scheduling the scheduled requests for the current target row, generating the second scheduling enable signal and sending it to the column scheduler.

[0045] In some embodiments, the control module is specifically used for: A scheduling request is received. The corresponding first target bit in the memory is determined according to the virtual queue number carried in the scheduling request. If the value of the first target bit is 0, the value of the first target bit is set to 1. If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, the value of the second target bit is set to 1. Otherwise, the value of the second target bit is not updated.

[0046] Specifically, the management unit receives a scheduling request at its input. The control module first calculates the row and column addresses of the memory based on the virtual queue number carried in the scheduling request, thereby determining the corresponding first target bit in the memory. It then reads the current value of the first target bit. If the current value of the first target bit is 0, it is written as 1; if the current value of the first target bit is already 1, its value remains unchanged. Next, based on the row address (row number) of the first target bit, the corresponding second target bit in the row bitmap register is read. If the current value of the second target bit is 0, it is written as 1; if the current value of the second target bit is already 1, its value remains unchanged. Thus, when the first scheduling request for a row arrives, the corresponding bit in the row bitmap register for that row is set to 1, and subsequent scheduling requests for that row will not repeatedly set the corresponding bit in the row bitmap. Simultaneously, since multiple scheduling requests for the same virtual queue only change the first target bit from 0 to 1 once, subsequent scheduling requests will not change the value of the first target bit, thereby automatically merging duplicate requests.

[0047] In some embodiments, the control module is further configured to, after writing the value of m bits of the target row in the memory into the data bitmap register, clear the target row in the memory and clear the bit in the row bitmap register corresponding to the target row; and, after outputting the target scheduling request to the next level module, clear the bit in the data bitmap register corresponding to the target column.

[0048] Specifically, the control module needs to perform state clearing during the request scheduling process. First, after copying the value of m bits of the selected target row from memory to the data bitmap register, the control module immediately clears the m bits of the target row in memory and clears the corresponding row bits in the row bitmap register to prevent the target row request from being repeatedly loaded and scheduled by the row scheduler. Subsequently, after the column scheduler selects a specific request to be scheduled in the target row and successfully outputs it to the next level module, the control module clears the bit corresponding to the target column in the data bitmap register to mark that the specific request to be scheduled has been processed and to prevent the specific request to be scheduled from being repeatedly scheduled by the column scheduler.

[0049] In some embodiments, see Figure 2 The request management device includes at least two management units and an output scheduler, with each management unit corresponding to a host; The output scheduler is connected to the at least two management units and is used to select one of the scheduling requests output by the at least two management units for output.

[0050] Specifically, the output scheduler is connected to all management units and uses a preset scheduling algorithm to select one of the pending requests output by each management unit as the final output. The preset scheduling algorithm can be a round-robin algorithm, in which requests from different hosts can be processed in parallel within their respective management units, while the output stage is arbitrated by the output scheduler to ensure fairness.

[0051] In some embodiments, see Figure 3 Each of the management units further includes: A mask bitmap register, wherein multiple bits of the mask bitmap register correspond one-to-one with multiple input channels, and the value of each bit of the mask bitmap register is used to indicate whether the scheduling request input on the corresponding input channel should be received by this management unit. Specifically, the bit width of the mask bitmap register is equal to the number of parallel input channels of the request management device (e.g., 64 bits), and each bit corresponds one-to-one with an input channel. A 1 in the i-th bit of the mask bitmap register indicates that the scheduled request on input channel i should be received by this management unit, while a 0 indicates that the scheduled request on input channel i should not be received. The mask bitmap register configurations of different management units do not overlap, and the union of the mask bitmap registers of all management units covers all input channels. By statically configuring the mask bitmap, the input channels are assigned to different management units, realizing hardware-level routing of requests without software intervention and reducing processing latency.

[0052] The control module is further configured to acquire a request vector to be scheduled, and perform a bitwise AND operation between the request vector to be scheduled and the values ​​of multiple bits in the mask bitmap register to determine the request to be scheduled to be received; wherein, the request vector to be scheduled is a multi-bit vector, and the value of each bit of the request vector to be scheduled is used to indicate whether a request to be scheduled has been received on the corresponding input channel.

[0053] Specifically, the control module obtains a request vector to be scheduled. This request vector is a multi-bit vector (including multiple bits), with a bit width equal to the number of input channels. The value of each bit indicates whether a request to be scheduled has been received on the corresponding input channel (e.g., 1 indicates a request, 0 indicates no request). The control module performs a bitwise AND operation on the request vector and the values ​​of multiple bits in the mask bitmap register. The request on the input channel corresponding to the bit with a result of 1 is the request that this management unit should receive. Through the bitwise AND operation, all requests belonging to this management unit can be filtered out at once without checking each channel individually. For the request management device, the attribution determination of all input channels can be completed within a single cycle, greatly improving the request distribution efficiency.

[0054] In some embodiments, the request management device supports receiving multiple scheduled requests in parallel within one clock cycle. The multiple scheduled requests belong to different management units, or the multiple scheduled requests belong to the same management unit and the virtual queue numbers carried by the multiple scheduled requests correspond to the same row of the memory.

[0055] Specifically, when multiple requests to be scheduled are received in parallel, if the requests belong to different management units, the mask bitmap registers of each management unit work in parallel without interfering with each other and can be received simultaneously. If the requests belong to the same management unit, the virtual queue numbers carried by these requests must correspond to the same row of memory (i.e., the high-order address of the virtual queue numbers is the same). This is because within the same clock cycle, the memory of a management unit can only perform one write operation and can only write to multiple columns of the same row. When this condition is met, multiple requests can be written to different columns of the same row simultaneously, achieving high-throughput queuing.

[0056] In some embodiments, see Figure 4 It also includes a request distribution module, which is used to determine the target management unit based on the management unit number carried by the scheduling request input through the input channel, and send the scheduling request to the target management unit.

[0057] Specifically, the request distribution module receives a scheduling request, which carries a management unit number. The request distribution module determines the target management unit based on the management unit number and then sends the scheduling request to the corresponding target management unit. Other management units will not receive the scheduling request, which is different from the implementation scheme that includes a mask bitmap register. The explicit routing method eliminates the mask bitmap register and broadcast overhead, and is suitable for scenarios with a small number of management units or where the request itself contains target information, providing design flexibility.

[0058] In some embodiments, the control module is used to: In response to receiving a priority processing instruction, the corresponding third target bit in the memory is determined according to the virtual queue number carried by the priority processing instruction. If the third target bit is 1, a scheduling request is generated according to the virtual queue number carried by the priority processing instruction, the scheduling request is output, and the third target bit is cleared to zero.

[0059] Specifically, the control module receives a priority processing instruction from an external source, which carries a virtual queue number. Based on this virtual queue number, the control module directly calculates the corresponding row and column addresses in memory, locating the third target bit. The control module reads the current value of the third target bit. If the current value is 1, it immediately generates a scheduling request based on the virtual queue number and outputs it to the output scheduler, then clears the third target bit. If the current value is 0, no operation is performed or an error is returned. This process does not involve polling by the row and column schedulers.

[0060] It should be noted that priority processing instructions are applicable to emergency scenarios that require breaking the normal polling scheduling order and processing specific virtual queue requests with minimal latency. This provides a low-latency channel for emergency requests, meeting the real-time requirements of virtio control plane commands without interfering with the fairness of normal scheduling, and avoiding protocol timeouts or device failures caused by scheduling delays. In virtio scenarios, priority processing instructions are applicable in the following situations: For example, when a host sends a doorbell request to a hardware device, if the configuration operation of a virtio-net control queue (such as VQ control) is blocked for a long time due to too many doorbells in the data queue, it may lead to delays in device status updates or network function abnormalities. In this case, the driver can issue a priority processing instruction, specifying the virtual queue number of the control queue, requesting the management device to immediately locate and output the corresponding pending request to the downstream module, which will then process the corresponding doorbell request, thereby ensuring that control commands are executed with priority and avoiding device function failures.

[0061] In some embodiments, the request management device of this embodiment only needs to be based on the virtual queue number when recording / caching the request to be scheduled. Therefore, the request to be scheduled can be the virtual queue number. The request management device of this embodiment is integrated into a hardware device such as a DPU. The hardware device is connected to the host through a bus. The hardware device also includes a request processing module and an interrupt module. The request management device of this embodiment is suitable for managing doorbell requests and interrupt requests. The request processing module receives the doorbell request sent by the host to the hardware device or the interrupt request generated by the interrupt module that needs to be sent to the host. The request processing module processes the doorbell request or interrupt request to obtain the virtual queue number and sends the virtual queue number as the request to be scheduled to the request management device of this embodiment. Specifically, doorbell requests are sent from the host to hardware devices (such as the DPU) to notify the hardware devices that there is new data or a new buffer descriptor to be processed in the virtual queue. Doorbell requests actually include not only the virtual queue number but also other information. Therefore, the request processing module can process the doorbell request, extract the virtual queue number from the doorbell request, and input it into the request management device of this embodiment. Interrupt requests are sent from the hardware device to the host to notify the host that the request has been completed or the data is ready. Similarly, interrupt requests actually include not only the virtual queue number but also other information. Therefore, the request processing module can process the interrupt request, extract the virtual queue number from the interrupt request, and input it into the request management device of this embodiment. The request management device of this application is applicable to the management of doorbell requests and interrupt requests, and achieves resource saving and duplicate request merging through the same caching and scheduling mechanism.

[0062] See Figure 5 Another embodiment of this application provides a request management method, including: Step S100: Receive a scheduling request and determine the virtual queue number carried in the scheduling request; Step S200: Update the values ​​of the corresponding bits in the random access memory and the row bitmap register according to the virtual queue number carried in the scheduling request; wherein, the random access memory includes multiple bits, which are arranged in an m-row-n-column manner, each bit uniquely corresponds to a virtual queue, and the value of each bit is used to indicate whether the management unit has received the scheduling request of the corresponding virtual queue, where m and n are positive integers; the row bitmap register includes n bits, and the value of each bit in the row bitmap register is used to indicate whether the corresponding row of the memory has cached the scheduling request; Step S300: Generate a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register. The first scheduling enable signal is used to control the row scheduler to determine a target row based on the values ​​of multiple bits in the row bitmap register. Step S400: In response to the target row determined by the row scheduler, write the m bits of the target row from the memory into the data bitmap register; Step S500: Generate a second scheduling enable signal based on the value in the data bitmap register. The second scheduling enable signal is used to control the column scheduler to determine the target scheduling request based on the value in the data bitmap register. The data bitmap register includes m bits for storing the values ​​of the m bits of the target row. In step S600, in response to the target column confirmed by the column scheduler, a target scheduling request is obtained based on the row number of the target row and the column number of the target column, and then output to the next level module.

[0063] In some embodiments, step S200 generates a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register, including: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated based on the value in the data bitmap register: The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

[0064] In some embodiments, step S200 updates the values ​​of the corresponding bits in the random access memory and the row bitmap register according to the virtual queue number carried by the scheduling request, specifically including: The first target bit in the memory is determined based on the virtual queue number carried in the scheduling request; If the value of the first target bit is 0, then set the value of the first target bit to 1; If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, then the value of the second target bit is set to 1.

[0065] In some embodiments, step S400 specifically includes: After writing the m bits of the target row in the memory into the data bitmap register, the target row in the memory is cleared to zero, and the bits in the row bitmap register corresponding to the target row are cleared to zero. Step S600 specifically includes: After outputting the target scheduling request to the next level module, the bit corresponding to the target column in the data bitmap register is cleared to zero.

[0066] In some embodiments, the method further includes: Step S700: In response to receiving a priority processing instruction, determine the corresponding third target bit in the memory according to the virtual queue number carried by the priority processing instruction, query whether the third target bit is 1, if so, generate a target scheduling request according to the virtual queue number carried by the priority processing instruction, output the target scheduling request, and clear the third target bit to zero.

[0067] It should be noted that the specific operations of the request management method in this embodiment correspond one-to-one with the structure and function of the management unit of the request management device described in the above embodiments. The step features of the method in this embodiment have been described in detail in the corresponding device embodiments. Those skilled in the art can directly implement the corresponding method steps based on the device description, so they will not be repeated here.

[0068] Another embodiment of this application provides a data processing unit (DPU) including the request management device as described in the above embodiments.

[0069] Specifically, a DPU is a data processing chip typically used for networking, storage, or security offloading. By integrating a request management device, the DPU can efficiently handle a massive number of doorbell requests from the host and interrupt requests sent to the host, reducing PCIe bandwidth consumption and host CPU load. This request management device can be integrated into the DPU as a hardware module or implemented as a configurable logic circuit.

[0070] Another embodiment of this application provides a computer-readable storage medium storing a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in the above embodiments.

[0071] Specifically, the computer-readable storage medium can be any non-transitory medium that contains or stores program instructions, such as read-only memory (ROM), random access memory (RAM), disk, optical disk, solid-state drive (SSD), or USB flash drive; the processor can be an embedded processor in the DPU, a host CPU, or other hardware unit that can execute instructions; when the computer program is executed by the processor, the processor controls the control module, row scheduler, column scheduler, and other components in the request management device according to the steps in the aforementioned method embodiments to complete operations such as enqueuing and caching of the requests to be scheduled, row / column scheduling, request output, and bit clearing. Since the specific process of program execution is completely consistent with the aforementioned method embodiments, it will not be repeated here.

[0072] Another embodiment of this application provides a computer program product, including a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in the above embodiments.

[0073] Specifically, the computer program product can be provided in the form of a software installation package, firmware image, dynamic link library (DLL), executable file (.exe), or driver. When the computer program product is loaded into a computing device and executed by a processor (such as an embedded processor in a DPU or a host CPU), the processor controls the control module, row scheduler, column scheduler, and other components of the request management device according to the steps in the aforementioned method embodiment to complete operations such as queuing and caching of requests to be scheduled, row / column scheduling, request output, and bit clearing. The computer program product can be stored in temporary or non-temporary media or obtained by downloading from a network. Since the specific process of program execution is completely consistent with the method embodiment, it will not be described again here.

[0074] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A request management device, characterized in that, It includes at least one management unit, the management unit comprising: The memory includes multiple bits arranged in an m-row-n-column configuration. Each bit uniquely corresponds to a virtual queue. The value of each bit is used to indicate whether the management unit has received a scheduling request for the corresponding virtual queue, where m and n are positive integers. A row bitmap register, comprising n bits, wherein the value of each bit of the row bitmap register is used to indicate whether the corresponding row of the memory is cached with a scheduling request; A row scheduler, in response to a first scheduling enable signal, determines a target row based on the values ​​of multiple bits in the row bitmap register; A data bitmap register, comprising m bits, is used to store the values ​​of the m bits of the target row; A column scheduler, in response to a second scheduling enable signal, determines a target column based on the value in the data bitmap register; The control module is configured to generate a first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register, and in response to the target row determined by the row scheduler, write the values ​​of m bits of the target row in the memory into the data bitmap register; and generate a second scheduling enable signal based on the values ​​in the data bitmap register, and in response to the target column confirmed by the column scheduler, obtain a target scheduling request based on the row number of the target row and the column number of the target column, and output it to the next-level module.

2. The apparatus according to claim 1, characterized in that, The control module is specifically used for: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

3. The request management device according to claim 1, characterized in that, The control module is specifically used for: A scheduling request is received. The corresponding first target bit in the memory is determined according to the virtual queue number carried in the scheduling request. If the value of the first target bit is 0, the value of the first target bit is set to 1. If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, the value of the second target bit is set to 1. Otherwise, the value of the second target bit is not updated.

4. The request management device according to claim 1, characterized in that, The control module is further configured to, after writing the value of m bits of the target row in the memory into the data bitmap register, clear the target row in the memory and clear the bit in the row bitmap register corresponding to the target row; and, after outputting the target scheduling request to the next level module, clear the bit in the data bitmap register corresponding to the target column.

5. The request management device according to claim 1, characterized in that, The request management device includes at least two management units and an output scheduler, with each management unit corresponding to a host. The output scheduler is connected to the at least two management units and is used to select one of the scheduling requests output by the at least two management units for output.

6. The request management device according to claim 5, characterized in that, Each of the management units further includes: A mask bitmap register, wherein multiple bits of the mask bitmap register correspond one-to-one with multiple input channels, and the value of each bit of the mask bitmap register is used to indicate whether the scheduling request input on the corresponding input channel should be received by this management unit. The control module is further configured to acquire a request vector to be scheduled, and perform a bitwise AND operation between the request vector to be scheduled and the values ​​of multiple bits in the mask bitmap register to determine the request to be scheduled to be received; wherein, the request vector to be scheduled is a multi-bit vector, and the value of each bit of the request vector to be scheduled is used to indicate whether a request to be scheduled has been received on the corresponding input channel.

7. The request management device according to claim 6, characterized in that, The request management device supports receiving multiple scheduled requests in parallel within one clock cycle. The multiple scheduled requests belong to different management units, or the multiple scheduled requests belong to the same management unit and the virtual queue numbers carried by the multiple scheduled requests correspond to the same row of the memory.

8. The request management device according to claim 5, characterized in that, It also includes a request distribution module, which is used to determine the target management unit based on the management unit number carried by the scheduling request input through the input channel, and send the scheduling request to the target management unit.

9. The request management device according to claim 1, characterized in that, The control module is used for: In response to receiving a priority processing instruction, the corresponding third target bit in the memory is determined according to the virtual queue number carried by the priority processing instruction. If the third target bit is 1, a target scheduling request is generated according to the virtual queue number carried by the priority processing instruction, the target scheduling request is output, and the third target bit is cleared to zero.

10. A request management method, characterized in that, include: Receive a scheduling request and determine the virtual queue number carried in the scheduling request; The values ​​of the corresponding bits in the memory and row bitmap register are updated according to the virtual queue number carried in the scheduling request; wherein, the memory includes multiple bits, which are arranged in an m-row n-column manner, each bit uniquely corresponds to a virtual queue, and the value of each bit is used to indicate whether the management unit has received the scheduling request of the corresponding virtual queue, where m and n are positive integers; the row bitmap register includes n bits, and the value of each bit of the row bitmap register is used to indicate whether the corresponding row of the memory has cached the scheduling request; A first scheduling enable signal is generated based on the values ​​of the data bitmap register and the row bitmap register. The first scheduling enable signal is used to control the row scheduler to determine a target row based on the values ​​of multiple bits in the row bitmap register. In response to the target row determined by the row scheduler, the m bits of the target row in the memory are written into the data bitmap register; A second scheduling enable signal is generated based on the value in the data bitmap register. The second scheduling enable signal is used to control the column scheduler to determine the target scheduling request based on the value in the data bitmap register. The data bitmap register includes m bits for storing the values ​​of the m bits of the target row. In response to the target column confirmed by the column scheduler, a target scheduling request is obtained based on the row number of the target row and the column number of the target column, and then output to the next level module.

11. The request management method according to claim 10, characterized in that, The step of generating the first scheduling enable signal based on the values ​​of the data bitmap register and the row bitmap register includes: When all values ​​in the data bitmap register are 0 and the values ​​in the row bitmap register are not all 0, the first scheduling enable signal is generated. The second scheduling enable signal is generated based on the value in the data bitmap register: The second scheduling enable signal is generated when at least one of the values ​​in the data bitmap register is non-zero.

12. The request management method according to claim 10, characterized in that, The step of updating the corresponding bit values ​​in the memory and row bitmap register according to the virtual queue number carried in the scheduling request specifically includes: The first target bit in the memory is determined based on the virtual queue number carried in the scheduling request; If the value of the first target bit is 0, then set the value of the first target bit to 1; If the value of the second target bit in the row bitmap register corresponding to the row where the first target bit is located is 0, then the value of the second target bit is set to 1.

13. The request management method according to claim 10, characterized in that, The method specifically includes: After writing the m bits of the target row in the memory into the data bitmap register, the target row in the memory is cleared to zero, and the bits in the row bitmap register corresponding to the target row are cleared to zero. After outputting the target scheduling request to the next level module, the bit corresponding to the target column in the data bitmap register is cleared to zero.

14. A data processing unit, characterized in that, Includes the request management device as described in any one of claims 1 to 9.

15. A computer-readable storage medium, characterized in that, The system stores a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in any one of claims 10 to 13.

16. A computer program product, characterized in that, The system includes a computer program that, when executed by at least one processor, causes the at least one processor to perform the request management method as described in any one of claims 10 to 13.

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