Trench p-type gallium oxide junction barrier Schottky diode and preparation method thereof

Abstract

The invention discloses a trench p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, and mainly solves the problems that an existing gallium oxide Schottky diode is high in on resistance and reverse leakage current and poor in voltage endurance capability and surge resistance capability. The device comprises a cathode ohmic metal layer (1), an n-type heavily-doped gallium oxide substrate (2), an n-type lightly-doped gallium oxide drift layer (3) and an anode Schottky metal layer (4) from bottom to top, and the upper surface of the n-type lightly-doped gallium oxide drift layer is downwards provided with a plurality of grooves (5) so as to change the surface electric field of the device; a p-type gallium oxide region (6) is injected below each groove, and the p-type gallium oxide region (6) and the n-type lightly doped gallium oxide drift layer form a gallium oxide homogeneous pn junction; and a high-k dielectric layer (7) is deposited in each groove. According to the invention, the leakage current is reduced, the reverse breakdown voltage of the device is improved, the on resistance is reduced, the anti-surge capability is improved, and the device can be used for power electronic equipment.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a trench p-type gallium oxide junction barrier Schottky diode, which can be used for power electronic equipment. Background Art

[0002] In the field of wide bandgap semiconductors, Ga2O3 is significantly superior to GaN and SiC due to its 4.8eV bandgap, 8MV / cm breakdown electric field strength limit, and BFOM up to 3400. These characteristics make Ga2O3 extremely important in research value and broad market application potential in modern power electronics applications that pursue higher power density and lower energy consumption.

[0003] In order to reduce the reverse leakage current of Ga2O3 Schottky diodes, a current strategy is to adopt a fin-type structure design, using the field plate effect to disperse the electric field of the Schottky contact interface and ensure that the electric field is evenly distributed along the field plate. In the forward conduction state, the current is first conducted through the fin-shaped epitaxial structure, then flows into the inside of the device, and finally reaches the cathode. Although this structure can achieve withstand voltage and forward conduction performance to a certain extent, it is also accompanied by some significant defects. First, the quality and thickness of the insulating medium used in the field plate must be strictly controlled, because poor quality or improper thickness may cause the electric field to be excessively concentrated in a certain place, thereby affecting the reliability and life of the device. Second, during the forward conduction process, due to the limited width of the fin-shaped structure, the current cannot effectively expand its conduction path when passing through the fin-shaped epitaxy, which increases the on-resistance of the device. Third, due to the lack of conductivity modulation capability of Ga2O3 Schottky diodes, the device is easily damaged when facing high surge currents, thus limiting its wide application in power circuits. Therefore, in order to overcome these challenges, it is necessary to continue to develop Ga2O3 Schottky diodes with lower on-resistance, higher voltage resistance and stronger surge resistance.

[0004] Patent document with application number CN202310938602.0 discloses a "Schottky diode based on p-type Ga2O3 and preparation method", which first grows GaN on the gallium oxide groove, and then oxidizes the GaN at high temperature to prepare a p-type gallium oxide layer to form a homogeneous pn junction to improve the device's withstand voltage and increase the device's power figure of merit. The quality of the crystals grown by this process, doping uniformity, and interface flatness are difficult to guarantee, new defects and impurities will be introduced during the preparation process, and the process steps are complicated, and the performance of the pn junction is highly uncertain.

[0005] Patent document with application number WOJP18035645 discloses a "Schottky barrier diode" that reduces the probability of dielectric breakdown by selectively enlarging the trench width, thereby increasing the bottom curvature radius of the trench. Although the device prepared by this method has improved breakdown performance, it will lead to an increase in forward on-resistance and reverse leakage current. At the same time, the wide trench structure will increase the thermal resistance of the device, affecting the reliability and service life in high temperature environments. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and to provide a trench p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, so as to improve the performance of the homogeneous pn junction of the gallium oxide Schottky diode and reduce the on-resistance and reverse leakage current of the device.

[0007] To achieve the above object, the technical solution of the present invention includes the following:

[0008] 1. A trench p-type gallium oxide junction barrier Schottky diode, comprising a cathode ohmic metal layer, an n-type heavily doped gallium oxide substrate, an n-type lightly doped gallium oxide drift layer and an anode Schottky metal layer, characterized in that:

[0009] The n-type lightly doped gallium oxide drift layer has a plurality of grooves in its upper portion to change the surface electric field of the device and increase the reverse breakdown voltage;

[0010] A p-type gallium oxide region is injected under each trench, which forms a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer;

[0011] A high-k dielectric layer is deposited in each trench to improve the device's voltage resistance, reduce leakage current, and increase switching speed.

[0012] Furthermore, the groove has a depth of 1 μm to 1.5 μm, a width of 5 μm to 6 μm, and a groove spacing of 2 μm to 3 μm.

[0013] Furthermore, the p-type gallium oxide region is composed of P 3+ or Ni 3+ The doping concentration is 2×10 18 cm -3 ~2×10 20 cm -3 .

[0014] Furthermore, the high-k dielectric layer is made of Al2O3 or HfO2 and has a thickness of 20nm to 40nm.

[0015] Furthermore, the cathode ohmic metal layer is made of Ti / Au, and the thickness of the first layer of Ti is 20nm-40nm, and the thickness of the second layer of Au metal is 100nm-200nm; the thickness of the n-type heavily doped gallium oxide substrate is 600μm-700μm, and the doping concentration is about 5×10 18 cm -3 ~1×10 19 cm -3 .

[0016] Furthermore, the n-type lightly doped gallium oxide drift layer has a thickness of 10 μm to 20 μm and a doping concentration of 1×10 12 cm -3 ~5×10 12 cm -3 The anode Schottky metal layer covers the n-type lightly doped gallium oxide drift layer, and its material is a Ni / Au metal layer. The thickness of the first layer Ni is 40nm to 60nm, and the thickness of the second layer Au is 100nm to 200nm.

[0017] 2. A method for preparing a trench p-type gallium oxide junction barrier Schottky diode, characterized in that it comprises the following steps:

[0018] 1) placing an n-type heavily doped gallium oxide substrate (2) in acetone, isopropanol, and piranha solution for cleaning in sequence;

[0019] 2) using HVPE technology to grow an n-type lightly doped gallium oxide drift layer (3) on the processed n-type heavily doped gallium oxide substrate (2);

[0020] 3) etching a plurality of grooves (5) on the n-type lightly doped gallium oxide drift layer (3) using ICP etching technology;

[0021] 4) performing ion implantation below the trench (5), and then forming a p-type gallium oxide region (6) by rapid thermal annealing;

[0022] 5) depositing a cathode ohmic metal layer (1) on the bottom surface of the n-type heavily doped gallium oxide substrate (2), and performing high temperature annealing to form an ohmic contact;

[0023] 6) Depositing a high-k dielectric layer (7) on the surface of the sample after completing step 5) using atomic layer deposition technology;

[0024] 7) using RIE etching technology to remove the high-k dielectric layer (7) on the top of the fin, exposing the Schottky contact area on the n-type lightly doped gallium oxide drift layer (3) below;

[0025] 8) After completing step 7), an anode Schottky metal layer (4) is grown on the surface of the sample, and the anode Schottky metal layer (4) forms a Schottky contact with the Schottky contact region on the n-type lightly doped gallium oxide drift layer (3), thereby completing the device preparation.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] Firstly, the present invention uses ion implantation technology to prepare a p-type gallium oxide region in an n-type lightly doped gallium oxide drift layer, and can accurately control the amount and depth of doped ions, thereby forming a p-type gallium oxide region with a specific hole concentration in the n-type lightly doped gallium oxide drift layer to meet the requirements of different device performances; at the same time, the complexity and difficulty of the process are significantly simplified, and the potential impact of the preparation process on the device performance is greatly reduced;

[0028] Secondly, since the present invention has grooves on the surface of the n-type lightly doped gallium oxide drift layer, the surface electric field of the device can be changed to increase the reverse breakdown voltage;

[0029] Thirdly, since the p-type gallium oxide region is injected below the groove below the groove of the trench-type gallium oxide Schottky diode, it can form a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer, and has better depletion characteristics, that is, it can not only effectively suppress reverse leakage and improve the withstand voltage of the device, but also adjust the conductivity of the drift region to reduce the on-state voltage drop, form an additional current channel, and significantly improve the surge resistance.

[0030] Fourthly, since the present invention deposits a high-k dielectric layer in the groove, the longitudinal electric field distribution of the device can be optimized, the reverse breakdown voltage can be further improved, and the leakage current can be reduced, and the thermal stability of the device can be improved, thereby meeting the needs of higher performance and higher reliability of gallium oxide devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic structural diagram of the junction barrier Schottky diode of the present invention.

[0032] Figure 2 The figure is a schematic diagram of the process of manufacturing a junction barrier Schottky diode according to the present invention. DETAILED DESCRIPTION

[0033] The specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. The experimental methods described in the following embodiments are conventional methods unless otherwise specified; the reagents and materials described are commercially available unless otherwise specified.

[0034] Reference Figure 1The junction barrier Schottky diode of this example includes: a cathode ohmic metal layer 1, an n-type heavily doped gallium oxide substrate 2, an n-type lightly doped gallium oxide drift layer 3, an anode Schottky metal layer 4, a trench 5, a p-type gallium oxide region 6, and a high-k dielectric layer 7, wherein:

[0035] The n-type heavily doped gallium oxide substrate 2 has a thickness of 600 μm to 700 μm and a doping concentration of about 5×10 18 cm -3 ~1×10 19 cm -3 .

[0036] The cathode ohmic metal layer 1 is located at the bottom of the n-type heavily doped gallium oxide substrate 2 and is made of Ti / Au material, with the thickness of the first layer of Ti being 20nm-30nm and the thickness of the second layer of Au metal being 150nm-200nm.

[0037] The n-type lightly doped gallium oxide drift layer 3 is located above the n-type heavily doped gallium oxide substrate 2 and has a thickness of 10 μm to 20 μm and a doping concentration of 1×10 12 cm -3 ~5×10 12 cm -3 .

[0038] The groove 5 has a width of 5 μm to 6 μm, a groove spacing of 2 μm to 3 μm, and a depth of 1 μm to 1.5 μm from the upper surface of the n-type lightly doped gallium oxide drift layer 3 , and is used to change the device surface electric field and increase the reverse breakdown voltage.

[0039] The p-type gallium oxide region 6 is composed of P 3+ or Ni 3+ The doping concentration is 2×10 18 cm -3 ~2×10 20 cm -3 , which is located inside the n-type lightly doped gallium oxide drift layer 3 below the trench 5 , and forms a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer 3 .

[0040] The high-k dielectric layer 7 is deposited on the inner wall and bottom of the groove 5 and is made of Al2O3 or HfO2 with a thickness of 20nm to 40nm. It is used to improve the withstand voltage of the device, reduce leakage current, and increase switching speed.

[0041] The anode Schottky metal layer 4 covers the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the high-k dielectric layer 7 in the groove. Its material is a Ni / Au metal layer, and the thickness of the first layer Ni is 40nm-60nm, and the thickness of the second layer Au is 150nm-200nm.

[0042] Reference Figure 2 The present invention provides three embodiments for manufacturing junction barrier Schottky diodes.

[0043] In Example 1, a plurality of trenches 5 with a depth of 1 μm, a width of 6 μm, and a trench spacing of 3 μm are prepared above an n-type lightly doped gallium oxide drift layer 3 on an n-type heavily doped gallium oxide substrate 2, a HfO2 dielectric layer is grown at the bottom and sidewalls of the trenches 5, and P is implanted into the n-type lightly doped gallium oxide drift layer 3 below the trenches 5. 3+ Junction barrier Schottky diode in the ionic gallium oxide region.

[0044] Step 1: Clean the n-type heavily doped gallium oxide substrate. Figure 2 (a).

[0045] 1.1) Select a thickness of 600 μm and a doping concentration of about 5×10 18 cm -3 The n-type heavily doped gallium oxide substrate 2 is ultrasonically cleaned in acetone, isopropanol and piranha solution for 15 minutes in sequence;

[0046] 1.2) Use nitrogen to blow dry and set aside.

[0047] Step 2, growing an n-type lightly doped gallium oxide drift layer on the substrate, such as Figure 2 (b).

[0048] Using the HVPE process, under the process conditions of GaCl and O2 as precursors, SiCl4 as dopant, and growth temperature of 850℃, a 10μm thick and 1×10 12 cm -3 An n-type lightly doped gallium oxide drift layer 3.

[0049] Step 3, etching the groove, such as Figure 2 (d).

[0050] 4.1) Spin-coating photoresist on the n-type lightly doped gallium oxide drift layer 3;

[0051] 4.2) using a corresponding mask to expose the n-type lightly doped gallium oxide drift layer 3 after spin coating of photoresist to form a pattern;

[0052] 4.3) Use a degumming machine at 200W to degumming the exposed sample for 5 minutes to remove the residual glue on the pattern;

[0053] 4.4) Using a mixed gas of BCl 3 and Ar as an etching medium, a plasma etching method is used to etch downwards on the n-type lightly doped gallium oxide drift layer 3 to form a plurality of grooves 5 with a depth of 1 μm, a width of 6 μm, and a groove spacing of 3 μm.

[0054] Step 4, ion implantation to form a p-type gallium oxide region, such as Figure 2 (e).

[0055] 5.1) Inject P into the n-type lightly doped gallium oxide drift layer 3 below each trench 5 3+ Cation, the implantation dose is 2×10 15 ions / cm -2 , the injection energy is 100keV;

[0056] 5.2) The sample after ion implantation was placed in a nitrogen gas environment and annealed at 1000°C for 1 min to form a p-type gallium oxide region 6 with a doping concentration of about 2×10 20 cm -3 .

[0057] Step 5, forming an ohmic contact, such as Figure 2 (c).

[0058] 3.1) using electron beam evaporation to grow a Ti / Au cathode ohmic metal layer 1 below the n-type heavily doped gallium oxide substrate 2, the thickness of the first Ti layer is 20 nm, and the thickness of the second Au layer is 100 nm;

[0059] 3.2) The sample with the Ti / Au cathode ohmic metal layer was placed in a nitrogen gas environment and annealed at 550° C. for 1 min to form an ohmic contact between the n-type heavily doped gallium oxide substrate and the Ti / Au cathode ohmic metal layer.

[0060] Step 6, growing a high-k dielectric layer, such as Figure 2 (f).

[0061] Using atomic layer deposition, with hafnium tetradiethylamide and water as precursors, hafnium tetradiethylamide flow rate of 50 sccm, reaction gas pressure of 50 Pa, reaction temperature of 250° C., a 20 nm HfO2 dielectric layer 7 is grown on the surface of the sample after completing step 5.

[0062] Step 7, etching the dielectric layer, such as Figure 2 (g).

[0063] RIE etching technology is used to etch the HfO2 dielectric layer on the top of the fin between each groove at 300W RF power and 20mTorr pressure in a BCl3 and Ar environment, so that the HfO2 dielectric layer is opened to expose the Schottky contact area on the underlying n-type lightly doped gallium oxide drift layer 3.

[0064] Step 8, forming a Schottky contact, such as Figure 2 (h).

[0065] Electron beam evaporation is used to grow a Ni / Au anode Schottky metal layer 4 on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the HfO2 dielectric layer 7 in the groove. The thickness of the first layer of Ni is 40nm, and the thickness of the second layer of Au is 150nm. Then, the layers are stripped and cleaned to form a Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni / Au anode Schottky metal layer 4, and the device preparation is completed.

[0066] In Example 2, a plurality of trenches 5 with a depth of 1.2 μm, a width of 5 μm, and a trench spacing of 2 μm are prepared above the n-type lightly doped gallium oxide drift layer 3 on the n-type heavily doped gallium oxide substrate 2, and a HfO2 dielectric layer is grown on the bottom and sidewalls of the trenches 5. Ni is implanted into the n-type lightly doped gallium oxide drift layer 3 below the trenches 5. 3+ Junction barrier Schottky diode in the ionic gallium oxide region.

[0067] Step 1: Cleaning the n-type heavily doped gallium oxide substrate.

[0068] The thickness is 700 μm and the doping concentration is about 1×10 19 cm -3 The n-type heavily doped gallium oxide substrate 2 was placed in acetone, isopropanol and piranha solution for ultrasonic cleaning for 15 minutes, and dried with nitrogen for later use.

[0069] Step 2: growing an n-type lightly doped gallium oxide drift layer on the substrate, such as Figure 2 (b)

[0070] The process conditions were set to use GaCl and O2 as precursors, SiCl4 as dopant, and the growth temperature was 1000℃. The HVPE process was used to grow a 15μm thick and 2×10 12 cm -3 An n-type lightly doped gallium oxide drift layer 3.

[0071] Step three, etching the grooves.

[0072] First, a photoresist is spin-coated on the n-type lightly doped gallium oxide drift layer 3, and then a corresponding mask is used to expose the n-type lightly doped gallium oxide drift layer 3 after the photoresist is spin-coated to form a pattern;

[0073] Next, the exposed sample was stripped for 4 minutes using a stripper at a power of 250 W to remove the residual glue above the pattern; then, a mixed gas of BCl3 and Ar was used as an etching medium, and a plasma etching method was used to etch downward above the n-type lightly doped gallium oxide drift layer 3 to form a plurality of grooves 5 with a depth of 1.2 μm, a width of 5 μm, and a groove spacing of 2 μm.

[0074] Step 4: ion implantation to form a p-type gallium oxide region.

[0075] Ni is implanted into the n-type lightly doped gallium oxide drift layer 3 below each trench 5. 3+ Cation, the implantation dose is 2×10 15 ions / cm -2 The implantation energy is 500 keV. The sample after ion implantation is then placed in a nitrogen gas environment and annealed at 1200°C for 1 min to form a p-type gallium oxide region 6 with a doping concentration of approximately 2×10 18 cm -3 . .

[0076] Step 5: Forming Ohmic Contact

[0077] A Ti / Au cathode ohmic metal layer 1 with a thickness of 40nm / 200nm is grown under the n-type heavily doped gallium oxide substrate 2 by electron beam evaporation; and the sample is placed in a nitrogen gas environment and annealed at a high temperature of 550°C for 1 minute to form an ohmic contact between the n-type heavily doped gallium oxide substrate 2 and the Ti / Au cathode ohmic metal layer 1.

[0078] Step six, growing a high-k dielectric layer.

[0079] Set the process conditions of using trimethylaluminum and water as precursors, a trimethylaluminum flow rate of 50 sccm, a reaction gas pressure of 100 Pa, and a reaction temperature of 250° C. to grow a 40 nm HfO2 dielectric layer on the surface of the sample after completing step 5 using atomic layer deposition.

[0080] Step seven, etching the dielectric layer.

[0081] The RF power is set to 350W, the pressure is set to 25mTorr, and the gas environment is set to BCl3 and Ar. The dielectric layer on the top of the fin between each groove is etched using RIE etching technology to open the HfO2 dielectric layer to expose the Schottky contact area on the underlying n-type lightly doped gallium oxide drift layer 3.

[0082] Step eight, forming a Schottky contact.

[0083] Electron beam evaporation is used to grow a 50nm / 150nm Ni / Au anode Schottky metal layer 4 on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the HfO2 dielectric layer 7 in the groove, and then stripping and cleaning are performed to form a Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni / Au anode Schottky metal layer 4 to complete the device preparation.

[0084] In Example 3, a plurality of trenches 5 with a depth of 1.2 μm, a width of 5 μm, and a trench spacing of 2 μm are prepared above the n-type lightly doped gallium oxide drift layer 3 on the n-type heavily doped gallium oxide substrate 2, an Al2O3 dielectric layer is grown on the bottom and sidewalls of the trenches 5, and P is implanted into the n-type lightly doped gallium oxide drift layer 3 below the trenches 5. 3+ Junction barrier Schottky diode in the ionic gallium oxide region.

[0085] Step A: cleaning the n-type heavily doped gallium oxide substrate.

[0086] A1) The thickness is 650 μm and the doping concentration is about 6.5×10 18 cm -3 The n-type heavily doped gallium oxide substrate 2 is placed in acetone, isopropanol and piranha solution for ultrasonic cleaning for 15 minutes in sequence;

[0087] A2) Blow dry with nitrogen gas for later use.

[0088] Step B, growing an n-type lightly doped gallium oxide drift layer on the substrate, such as Figure 2 (b)

[0089] Using the HVPE process, a 20 μm thick and 5×10 12 cm -3 An n-type lightly doped gallium oxide drift layer 3.

[0090] The growth process conditions are: GaCl and O2 as precursors, SiCl4 as dopant, and growth temperature of 1100°C.

[0091] Step C, etching the grooves.

[0092] D1) spin-coating a photoresist on the n-type lightly doped gallium oxide drift layer 3, and using a corresponding mask to expose the n-type lightly doped gallium oxide drift layer 3 after the spin-coating of the photoresist to form a pattern;

[0093] D2) Use a degumming machine at 300W to degumming the exposed sample for 3 minutes to remove the residual glue on the pattern;

[0094] D3) placing the debonded sample in a mixed gas of BCl3 and Ar, and using plasma etching to etch downwards on the n-type lightly doped gallium oxide drift layer 3 to form a plurality of grooves 5 with a depth of 1.5 μm, a width of 6 μm, and a groove spacing of 2 μm.

[0095] Step D: ion implantation to form a p-type gallium oxide region.

[0096] E1) implanting P into the n-type lightly doped gallium oxide drift layer 3 below each trench 5 3+ Cation, the implantation dose is 2.5×10 13 ions / cm -2 , the injection energy is 40keV;

[0097] E2) The sample after ion implantation is placed in a nitrogen gas environment and annealed at 1000°C for 1 min to form a p-type gallium oxide region 6 with a doping concentration of about 2×10 19 cm -3 . .

[0098] Step E: Forming Ohmic Contact

[0099] C1) growing a Ti / Au cathode ohmic metal layer 1 below an n-type heavily doped gallium oxide substrate 2 using electron beam evaporation, wherein the thickness of the first Ti layer is 30 nm and the thickness of the second Au layer is 150 nm;

[0100] C2) placing the sample with the Ti / Au cathode ohmic metal layer in a nitrogen gas environment and annealing at 550° C. for 1 min to form an ohmic contact between the n-type heavily doped gallium oxide substrate 2 and the Ti / Au cathode ohmic metal layer 1 .

[0101] Step F, growing a high-k dielectric layer.

[0102] Using atomic layer deposition, a 30 nm Al2O3 dielectric layer is grown on the surface of the sample after completing step 5.

[0103] The process conditions of the atomic layer deposition are: trimethylaluminum and water are used as precursors, the trimethylaluminum flow rate is 80 sccm, the reaction gas pressure is 120 Pa, and the reaction temperature is 300°C.

[0104] Step G, etching the dielectric layer.

[0105] RIE etching technology is used to etch the dielectric layer on the top of the fin between each groove at 400W RF power and 30mTorr pressure in a BCl3 and Ar environment, so that the Al2O3 dielectric layer exposes the Schottky contact area on the underlying n-type lightly doped gallium oxide drift layer 3.

[0106] Step H, forming a Schottky contact.

[0107] H1) Using electron beam evaporation, a Ni / Au anode Schottky metal layer 4 is grown on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the Al2O3 dielectric layer 7 in the groove, wherein the thickness of the first layer of Ni is 60nm, and the thickness of the second layer of Au is 200nm, followed by stripping and cleaning, forming a Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni / Au anode Schottky metal layer 4, and completing device preparation.

[0108] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention. For example, in addition to the P used in the specific embodiment, 3+ Cation, Ni 3+ Cations may also be implanted using other cations; the process condition parameters for ion implantation may use any parameters within the range in addition to those used in the specific embodiments; other high-k dielectrics may be deposited as dielectric layers in addition to HfO2 and Al2O3 used in the specific embodiments; the process parameters for depositing the dielectric layer may use any parameters within the range in addition to those used in the specific embodiments; the size of the groove may be changed according to actual needs in addition to the etching parameters in the specific embodiments, but these modifications based on the ideas of the present invention all fall within the scope of protection of the present invention.

Claims

1. A trench p-type gallium oxide junction barrier Schottky diode, comprising a cathode ohmic metal layer (1), an n-type heavily doped gallium oxide substrate (2), an n-type lightly doped gallium oxide drift layer (3) and an anode Schottky metal layer (4), characterized in that: The n-type lightly doped gallium oxide drift layer (3) has a plurality of grooves (5) arranged in its upper portion to change the surface electric field of the device and increase the reverse breakdown voltage; A p-type gallium oxide region (6) is injected below each trench (5), and forms a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer (3); A high-k dielectric layer (7) is deposited in each groove (5) to improve the voltage resistance of the device, reduce leakage current, and increase switching speed.

2. The diode according to claim 1, characterized in that The groove (5) has a depth of 1 μm to 1.5 μm, a width of 5 μm to 6 μm, and a groove spacing of 2 μm to 3 μm.

3. The diode according to claim 1, characterized in that The p-type gallium oxide region (6) is composed of P 3+ or Ni 3+ The doping concentration is 2×10 18 cm -3 ~2×10 20 cm -3 .

4. The diode according to claim 1, characterized in that The high-k dielectric layer (7) is made of Al2O3 or HfO2 and has a thickness of 20nm to 40nm.

5. The diode according to claim 1, characterized in that: The cathode ohmic metal layer (1) is made of Ti / Au, and the thickness of the first layer of Ti is 20nm to 40nm, and the thickness of the second layer of Au metal is 100nm to 200nm; The n-type heavily doped gallium oxide substrate (2) has a thickness of 600 μm to 700 μm and a doping concentration of about 5×10 18 cm -3 ~1×10 19 cm -3 .

6. The diode according to claim 1, characterized in that: The n-type lightly doped gallium oxide drift layer (3) has a thickness of 10 μm to 20 μm and a doping concentration of 1×10 12 cm -3 ~5×10 12 cm -3 ; The anode Schottky metal layer (4) covers the n-type lightly doped gallium oxide drift layer (3), and its material is a Ni / Au metal layer, the thickness of the first Ni layer is 40nm-60nm, and the thickness of the second Au layer is 100nm-200nm.

7. A method for preparing a trench p-type gallium oxide junction barrier Schottky diode, characterized in that: The steps include: 1) placing an n-type heavily doped gallium oxide substrate (2) in acetone, isopropanol, and piranha solution for cleaning in sequence; 2) using HVPE technology to grow an n-type lightly doped gallium oxide drift layer (3) on the processed n-type heavily doped gallium oxide substrate (2); 3) etching a plurality of grooves (5) on the n-type lightly doped gallium oxide drift layer (3) using ICP etching technology; 4) performing ion implantation below the trench (5), and then forming a p-type gallium oxide region (6) by rapid thermal annealing; 5) depositing a cathode ohmic metal layer (1) on the bottom surface of the n-type heavily doped gallium oxide substrate (2), and performing high temperature annealing to form an ohmic contact; 6) Depositing a high-k dielectric layer (7) on the surface of the sample after completing step 5) using atomic layer deposition technology; 7) using RIE etching technology to remove the high-k dielectric layer (7) on the top of the fin, exposing the Schottky contact area on the n-type lightly doped gallium oxide drift layer (3) below; 8) After completing step 7), an anode Schottky metal layer (4) is grown on the surface of the sample, and the anode Schottky metal layer (4) forms a Schottky contact with the Schottky contact region on the n-type lightly doped gallium oxide drift layer (3), thereby completing the device preparation.

8. The method according to claim 7, characterized in that: In step 2), the HVPE technology is used to grow the n-type lightly doped gallium oxide drift layer, and the process conditions are as follows: The materials are GaCl and O2, the dopant is SiCl4, and the doping concentration is 1×10 12 cm -3 ~5×10 12 cm -3 , the growth temperature is 850℃~1100℃; In step 6), an atomic layer deposition technique is used to deposit a high-k dielectric layer (7) on the surface of the sample. The deposition material is HfO2 or Al2O3. The process conditions are as follows: When depositing HfO2, tetrakis diethylamino hafnium and water are used as precursors, the flow rate of the tetrakis diethylamino hafnium is 50 sccm to 100 sccm, the reaction gas pressure is 50 Pa to 100 Pa, and the reaction temperature is 250° C. to 300° C.; When depositing Al2O3, trimethylaluminum and water are used as precursors, the trimethylaluminum flow rate is 50sccm~100sccm, the reaction gas pressure is 100Pa~200Pa, and the reaction temperature is 250℃~350℃.

9. The method according to claim 7, characterized in that: In the step 3), a plurality of grooves are etched on the n-type lightly doped gallium oxide drift layer using ICP etching technology, which comprises firstly spin-coating a photoresist on the n-type lightly doped gallium oxide drift layer, then using a corresponding mask to form a pattern after exposure, and then using a stripper to remove the residual glue above the pattern at a power of 200W to 300W for 3min to 5min; and then using an ICP etcher to etch at a depth of 1μm to 1.5μm in an environment of BCl3 and Ar to form a plurality of grooves; In step 4), ion implantation is performed below the trench (5) using P 3+ or Ni 3+ An ion implantation is performed, wherein: Conduct P 3+ During the injection, the injection dose was 2×10 13 ~2×10 15 ions / cm -2 , the implantation energy is 40keV~100keV, the temperature of rapid thermal annealing in nitrogen environment is 1000℃, and the time is 1min; Conduct Ni 3+ During injection, the injection dose was 5×10 14 ~2×10 15 ions / cm -2 The implantation energy is 500keV~600keV, and the rapid thermal annealing temperature is 1200℃ in a nitrogen environment for 1min.

10. The method according to claim 7, characterized in that: In the step 7), the high-k dielectric layer (7) on the top of the fin is removed by RIE etching technology, which is performed in an environment of BCl3 and Ar with a radio frequency power of 300W to 400W and a pressure of 20mTorr to 30mTorr; In the step 8), the anode Schottky metal layer is grown on the surface of the sample by first using electron beam evaporation to grow a Ni / Au metal layer with a first layer of Ni having a thickness of 40nm to 60nm and a second layer of Au having a thickness of 100nm to 200nm, and then peeling and cleaning.

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