Shift register, gate drive circuit and display panel

Abstract

The embodiment of the invention discloses a shift register, a gate drive circuit and a display panel, and is characterized in that a node voltage control module controls the voltage of a first node and a second node according to an input signal, and a first output module outputs a first gate drive signal according to the voltage of the first node and the second node; and the second output module outputs a second gate driving signal according to the voltage of the first node and / or the second node, and the first gate driving signal is different from the second gate driving signal. Thus, two different gate driving signals can be output through the same shift register, the driving requirement for a pixel circuit can be met, the frame of the display panel can be reduced, and the user experience can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] In some existing display panels, the pixel circuit includes both P-type transistors and N-type transistors, and two gate driving signals are required to drive the pixel circuit. If two sets of gate driving circuits are provided, the border area will be increased, affecting the user experience. Summary of the invention

[0003] The present invention provides a shift register, a gate driving circuit and a display panel, so as to output two gate driving signals through the gate driving circuit, reduce the border area of ​​the display panel and improve the user experience.

[0004] According to one aspect of the present invention, there is provided a shift register, comprising a node voltage control module, a first output module and a second output module, wherein the node voltage control module is connected to a first node and a second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node;

[0005] The node voltage control module is used to control the voltage of the first node and the second node according to the input signal; the first output module is used to output a first gate drive signal through the first output terminal according to the voltage of the first node and the second node, and the second output module is used to output a second gate drive signal through the second output terminal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different.

[0006] Optionally, the first gate driving signal and the second gate driving signal have different pulse widths, pulse amplitudes, and positive and negative polarities of the pulse amplitudes;

[0007] and / or, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types;

[0008] Optionally, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor;

[0009] The second gate driving signal includes a first level signal and a second level signal, the voltage of the first level signal is lower than the voltage of the second level signal; the second output module includes a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor;

[0010] Optionally, the P-type transistor included in the second output module is a polysilicon transistor; optionally, the first gate drive signal includes a first level signal and a second level signal; optionally, the pulse of the first gate drive signal overlaps with the pulse of the second gate drive signal; optionally, the duration of the first level signal of the pulse of the first gate drive signal is within the duration of the second level signal of the pulse of the second gate drive signal; optionally, the pulse width of the first gate drive signal is smaller than the pulse width of the second gate drive signal; optionally, the input signal includes a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal; optionally, the input The signal includes a first clock signal and a second clock signal, wherein the pulse of the first clock signal overlaps with the pulse of the start signal, and the pulse of the second clock signal overlaps with the pulse of the first gate drive signal; optionally, the transition edge of the pulse of the first gate drive signal is aligned with the transition edge of the pulse of the second clock signal; optionally, the transition edge of the pulse of the second gate drive signal is aligned with the transition edge of the pulse of the first clock signal; optionally, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the second clock signal; the rising edge of the pulse of the first gate drive signal is aligned with the rising edge of the pulse of the second clock signal; optionally, the rising edge and falling edge of the pulse of the second gate drive signal are respectively aligned with the falling edges of two adjacent pulses of the first clock signal. Optionally, the first clock signal and the second clock signal have the same frequency and different phases.

[0011] Optionally, the second output module includes a first output unit and a second output unit.

[0012] The first output unit is connected to the second node, and is used to be turned on or off according to the potential of the second node, and outputs the second level signal to the second output terminal when turned on; or the first output unit is connected to the first node, and is used to be turned on or off according to the potential of the first node, and outputs the second level signal to the second output terminal when turned on;

[0013] The second output unit is connected to the first node and / or the second node, and is used to be turned on or off according to the potential of the first node and / or the second node, and output a first level signal to the second output terminal when turned on;

[0014] Optionally, the first output unit includes a first transistor, a gate potential of the first transistor is positively correlated with a potential of the second node, or a gate potential of the first transistor is negatively correlated with a potential of the first node, or a gate of the first transistor is connected to the second node; a first electrode of the first transistor is connected to a second power line or is connected to a second level signal, and a second electrode of the first transistor is connected to a second output terminal;

[0015] And / or, the second output unit includes a second transistor, the gate potential of the second transistor is positively correlated with the potential of the first node, or the gate potential of the first transistor is negatively correlated with the potential of the second node; the first electrode of the second transistor is connected to the first power line or connected to the first level signal, and the second electrode of the second transistor is connected to the second output terminal;

[0016] Optionally, the second transistor is a P-type transistor; Optionally, the first transistor is a P-type transistor;

[0017] Optionally, the second output unit also includes a first capacitor, a first end of the first capacitor is connected to the gate of the second transistor, and a second end of the first capacitor is connected to the second output end; optionally, the node voltage control module is used to control the potential of the first node to jump from a low potential to a high potential, and the potential of the second node to jump from a high potential to a low potential, and when the potential of the first node jumps from a high potential to a low potential, the potential of the second node jumps from a low potential to a high potential; optionally, the node voltage control module is used to control the potentials of the first node and the second node to remain opposite.

[0018] Optionally, the second output unit also includes an output control subunit, the output control subunit is connected to the first node and the second node respectively, the output control subunit and the gate of the second transistor are connected to the third node, the output control subunit is used to control the potential of the third node according to the potentials of the first node and the second node, so that the potential of the third node is positively correlated with the potential of the first node, the potential of the third node includes a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; the potential of the second node When the potential jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; optionally, the potentials of the second node and the third node remain opposite; optionally, the potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or, the potentials of the first node and the third node jump from a high potential to a low potential at the same time; optionally, the potential of the third node also includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal; optionally, the absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor.

[0019] Optionally, the output control subunit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; the gate of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second power line or connected to the second level signal, the second electrode of the third transistor is connected to the first electrode of the fifth transistor, and the second electrode of the fifth transistor is connected to the third power line or connected to the third level signal; the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the second power line or connected to the second level signal, the second electrode of the fourth transistor is connected to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is connected to the third power line or connected to the third level signal; the gate of the fifth transistor is connected to the second electrode of the fourth transistor, and the gate of the sixth transistor is connected to the second electrode of the third transistor; optionally, the voltage of the third power line is lower than the voltage of the first power line; optionally, the third transistor and the fourth transistor are P-type transistors, and the fifth transistor and the sixth transistor are N-type transistors.

[0020] Optionally, the second output unit further includes an output control subunit, the output control subunit includes a first inverter, the input end of the first inverter is connected to the second node, the output end of the first inverter and the gate of the second transistor are connected to a third node; the first end of the first inverter is connected to the second power line or connected to the second level signal, and the output control subunit is used to control the potential of the third node according to the potential of the second node; the second end of the first inverter is connected to the third power line or connected to the third level signal;

[0021] Alternatively, the output control subunit includes M first inverters;

[0022] M is an odd number greater than 1, the input end of the 1st first inverter is connected to the second node, the output end of the i-th first inverter is connected to the input end of the i+1-th first inverter, and the output end of the M-th first inverter and the gate of the second transistor are connected to the third node; i is an integer greater than or equal to 1 and less than or equal to M; the output control subunit is used to control the potential of the third node according to the potential of the second node;

[0023] Alternatively, M is an even number greater than or equal to 2; the input end of the 1st first inverter is connected to the first node, the output end of the ith first inverter is connected to the input end of the (i+1)th first inverter, and the output end of the Mth first inverter and the gate of the second transistor are connected to the third node; the output control subunit is used to control the potential of the third node according to the potential of the first node;

[0024] The first end of the first inverter is connected to the second power line or connected to the second level signal, and the second end of the Mth first inverter is connected to the third power line or connected to the third level signal;

[0025] Optionally, the second end of at least one first inverter is connected to the first power line or connected to the first level signal; or, the second ends of all first inverters are connected to the third power line or connected to the third level signal; optionally, the voltage of the third power line is lower than the voltage of the first power line; optionally, the potential of the third node includes a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; optionally, the potentials of the second node and the third node remain opposite; optionally, the potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or, the potentials of the first node and the third node jump from a high potential to a low potential at the same time; optionally, the potential of the third node also includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal; optionally, the absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor;

[0026] Optionally, the first inverter includes a fifteenth transistor and a sixteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor are connected to the input terminal of the first inverter, the first electrode of the fifteenth transistor is connected to the first end of the first inverter, the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor are connected to the output terminal of the first inverter, and the second electrode of the sixteenth transistor is connected to the second end of the first inverter. Optionally, the fifteenth transistor is an N-type transistor and the sixteenth transistor is a P-type transistor.

[0027] Optionally, the first output module includes a third output unit and a fourth output unit, the third output unit is connected to the first node, and is used to be turned on or off according to the potential of the first node, and output the second level signal to the first output terminal when turned on; the fourth output unit is connected to the second node, and is used to be turned on or off according to the potential of the second node, and output the first level signal to the first output terminal during at least a part of the time period when it is turned on;

[0028] Optionally, the effective levels of the first gate driving signal and the second gate driving signal overlap; optionally, the effective level of the first gate driving signal is a first level signal, and the effective level of the second gate driving signal is a second level signal; optionally, the invalid levels of the first gate driving signal and the second gate driving signal overlap;

[0029] Optionally, the third output unit includes a seventh transistor, the gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the seventh transistor is connected to the first output terminal; optionally, the fourth output unit includes an eighth transistor, the gate of the eighth transistor is connected to the second node; the first electrode of the eighth transistor is connected to the second clock signal, and the second electrode of the eighth transistor is connected to the first output terminal; optionally, the fourth output unit also includes a second capacitor, the first end of the second capacitor is connected to the second node, and the second end of the second capacitor is connected to the first output terminal.

[0030] Optionally, the input signal includes a first clock signal, a second clock signal and a start signal; the node voltage control module includes an input unit and a first control unit, the input unit is used to turn on or off according to the first clock signal, and transmit the start signal to the second node when turned on; the first control unit is used to transmit a first level signal or a second level signal to the first node according to the potential of the second node; optionally, the node voltage control module also includes a second control unit, the second control unit is used to transmit a second level signal to the second node according to the potential of the first node and the second clock signal; optionally, the first control unit includes a second inverter; optionally, the first clock signal, the second clock signal, and the start signal respectively include alternately set first level pulses and second level pulses, the first level pulse of the start signal overlaps with the first level pulse of the first clock signal, and does not overlap with the first level pulse of the second clock signal; optionally, the first level pulse of the start signal is one or more, and the first level pulses of the first clock signal and the second clock signal are multiple respectively;

[0031] The first output module includes a third output unit and a fourth output unit, the third output unit includes a seventh transistor, the gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the seventh transistor is connected to the first output terminal; the fourth output unit includes an eighth transistor, the gate of the eighth transistor is connected to the second node; the first electrode of the eighth transistor is connected to the second clock signal, and the second electrode of the eighth transistor is connected to the first output terminal; optionally, the input unit includes a ninth transistor, the gate of the ninth transistor is connected to the first clock signal, the first electrode of the ninth transistor is connected to the start signal, and the second electrode of the ninth transistor is connected to the second node; optionally, the shift register also includes a tenth transistor, the second electrode of the ninth transistor is connected to the second node through the tenth transistor; the gate of the tenth transistor is connected to the first power line or connected to the first level signal; optionally, the first control unit includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second electrode of the ninth transistor Or connected to the second node, the first electrode of the eleventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the eleventh transistor is connected to the first node; the gate of the twelfth transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the twelfth transistor is connected to the first power line or connected to the first level signal, and the second electrode of the twelfth transistor is connected to the first node; the second control unit includes a thirteenth transistor and a fourteenth transistor, the first electrode of the thirteenth transistor is connected to the second power line or connected to the second level signal, the second electrode of the thirteenth transistor is connected to the first electrode of the fourteenth transistor, the second electrode of the fourteenth transistor is connected to the second electrode or the second node of the ninth transistor, one of the gate of the thirteenth transistor and the gate of the fourteenth transistor is connected to the first node, and the other is connected to the second clock signal; optionally, the gate of the thirteenth transistor is connected to the first node, and the gate of the fourteenth transistor is connected to the second clock signal; optionally, the eleventh transistor is a P-type transistor and the twelfth transistor is an N-type transistor.

[0032] According to another aspect of the present invention, a gate drive circuit is provided, comprising a plurality of shift registers of any embodiment of the present invention, wherein the plurality of shift registers are cascaded; the start signal input terminal of the n+1th stage shift register is connected to the first output terminal of the nth stage shift register, wherein n is a positive integer greater than or equal to 1.

[0033] According to another aspect of the present invention, a display panel is provided, which includes a pixel circuit and a gate driving circuit of any embodiment of the present invention, the pixel circuit includes multiple transistors, and the first output terminal and the second output terminal of the shift register are connected to transistors of different channel types in the pixel circuit.

[0034] Optionally, the pixel circuit includes a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is connected between the data line and the first electrode of the driving transistor, and the compensation transistor is connected between the second electrode and the gate of the driving transistor; the gate of the data writing transistor is connected to the first output terminal, and the gate of the compensation transistor is connected to the second output terminal; optionally, the channel type of the data writing transistor is a P channel, and the channel type of the compensation transistor is an N channel; optionally, the pixel circuit also includes a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor is connected between the fourth power line and the first electrode of the driving transistor; the second light-emitting control transistor is connected between the second electrode and the driving transistor The first electrode of the light-emitting device and the second electrode of the light-emitting device are connected to the fifth power line; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to the light-emitting control signal line; optionally, the pixel circuit also includes a first initialization transistor, the gate of the first initialization transistor is connected to the first scanning line, the first electrode of the first initialization transistor is connected to the first initialization signal line, and the second electrode of the first initialization transistor is connected to the gate or the second electrode of the driving transistor; optionally, the pixel circuit also includes a second initialization transistor, the gate of the second initialization transistor is connected to the second scanning line, the first electrode of the second initialization transistor is connected to the second initialization signal line, and the second electrode of the second initialization transistor is connected to the first electrode of the light-emitting device.

[0035] The shift register, gate drive circuit and display panel of the embodiment of the present invention control the voltage of the first node and the second node according to the input signal by setting a node voltage control module, the first output module outputs a first gate drive signal according to the voltage of the first node and the second node, and the second output module outputs a second gate drive signal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different. In this way, two different gate drive signals can be output through the same shift register, which can meet the driving requirements of the pixel circuit, and can reduce the border of the display panel, thereby improving the user experience.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1is a schematic diagram of the structure of a shift register provided by an embodiment of the present invention;

[0039] Figure 2 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0040] Figure 3 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0042] Figure 5 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0043] Figure 6 It is a structural schematic diagram of a pixel circuit in the related art;

[0044] Figure 7 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0045] Figure 8 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0046] Fig. 9 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0047] Fig.10 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0048] Fig.11 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0049] Fig.12 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0050] Fig.13 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0051] Fig.14 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention,

[0052] Fig.15 is a working timing diagram of a shift register provided by an embodiment of the present invention;

[0053] Fig.16 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0054] Fig.17 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The connection may include a direct connection or an indirect connection. The connection may include an electrical connection.

[0057] Figure 1 is a schematic diagram of a structure of a shift register provided by an embodiment of the present invention, with reference to Figure 1 The shift register includes a node voltage control module 110, a first output module 120 and a second output module 130, wherein the node voltage control module 110 is connected to the first node N1 and the second node N2, the first output module 120 is connected to the first node N1 and the second node N2, and the second output module 130 is connected to the first node N1 and / or the second node N2. Figure 1 The example shows a case where the second output module 130 is connected to the first node N1 and the second node N2); the node voltage control module 110 is used to control the voltage of the first node N1 and the second node N2 according to the input signal; the first output module 120 is used to output a first gate drive signal through the first output terminal OUT1 according to the voltage of the first node N1 and the second node N2, and the second output module 130 is used to output a second gate drive signal through the second output terminal OUT2 according to the voltage of the first node N1 and / or the second node N2, and the first gate drive signal and the second gate drive signal are different.

[0058] The number of input signals connected to the node voltage control module 110 may be multiple, and the input signals include, but are not limited to, a start signal and one or at least two clock signals. The node voltage control module 110 transmits corresponding voltages to the first node N1 and the second node N2 respectively in different working periods of the shift register according to the input signal. The first node N1 and the second node N2 have different potentials in at least part of the time period, for example, opposite potentials, or opposite highs and lows, or opposite positive and negative polarities, etc.

[0059] The first output module 120 is connected to the first node N1 and the second node N2 respectively. The first output module 120 can output a first gate drive signal to the first output terminal OUT1 of the shift register according to the potentials of the first node N1 and the second node N2, wherein the first gate drive signal includes a first level signal and a second level signal. Specifically, in a part of the working period, the first gate drive signal is a first level signal; in another part of the working period, the first gate drive signal is a second level signal. The first gate drive signal is used to drive a transistor of the first channel type.

[0060] The second output module 130 is connected to the first node N1 and / or the second node N2. The second output module 130 can output a second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1 and / or the second node N2, wherein the second gate drive signal includes a first level signal and a second level signal. Specifically, in a part of the working period, the second gate drive signal is a first level signal; in another part of the working period, the second gate drive signal is a second level signal. The second gate drive signal is used to drive a transistor of a second channel type. The first channel type is a P channel, and the second channel type is an N channel, or the first channel type is an N channel, and the second channel type is a P channel.

[0061] The shift register of this embodiment controls the voltage of the first node and the second node according to the input signal by setting a node voltage control module, the first output module outputs a first gate drive signal according to the voltage of the first node and the second node, and the second output module outputs a second gate drive signal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different. In this way, two different gate drive signals can be output through the same shift register, which can meet the driving requirements of the pixel circuit, and can reduce the border of the display panel and improve the user experience.

[0062] Optionally, one or more of the pulse width, pulse amplitude, and positive and negative polarity of the pulse amplitude of the first gate drive signal and the second gate drive signal are different; and / or the first gate drive signal and the second gate drive signal are used to drive transistors of different channel types. In this way, the first gate drive signal and the second gate drive signal can drive different transistors, for example, drive transistors that are turned on in different working stages in the pixel circuit of the display panel, and / or drive transistors of different channel types, so as to meet the driving requirements of the pixel circuit and reduce the border of the display panel.

[0063] As described in the above embodiments, the first gate drive signal includes a first level signal and a second level signal; the second gate drive signal includes a first level signal and a second level signal. In some optional embodiments of the present invention, the first gate drive signal is used to drive a P-type transistor, and the second gate drive signal is used to drive an N-type transistor; the voltage of the first level signal is lower than the voltage of the second level signal; the second output module 130 includes a P-type transistor, and the second output module 130 is used to output the first level signal through the P-type transistor.

[0064] Specifically, in the related art, the first level signal in the second gate drive signal is output through an N-type oxide transistor. Since the mobility of the oxide transistor is low, when the transistor characteristics fluctuate under stress, the output waveform stability of the second gate drive signal is poor, thereby reducing the reliability of the gate drive circuit. In this embodiment, the second output module 130 is provided to include a P-type transistor, and the first level signal is output through the P-type transistor, wherein the P-type transistor may be a polysilicon transistor, such as a low-temperature polysilicon transistor. Compared with the N-type oxide transistor, the P-type transistor has a higher mobility, which can improve the output stability of the second gate drive signal and enhance the reliability of the gate drive circuit.

[0065] Figure 2 is a schematic diagram of the structure of another gate drive circuit provided by an embodiment of the present invention, referring to Figure 2 Optionally, in the gate driving circuit, the second output module 130 includes a first output unit 131 and a second output unit 132 .

[0066] The first output unit 131 is connected to the second node N2, and the first output unit 131 is used to control the potential of the second output terminal OUT2 according to the potential of the second node N2. For example, the first output unit 131 is used to be turned on or off according to the potential of the second node N2, and outputs the second level signal VGH to the second output terminal OUT2 when turned on; or, the first output unit 131 is connected to the first node N1, and the first output unit 131 is used to control the potential of the second output terminal OUT2 according to the potential of the first node N1. For example, the first output unit 131 is used to be turned on or off according to the potential of the first node N1, and outputs the second level signal VGH to the second output terminal OUT2 when turned on.

[0067] The second output unit 132 is connected to the first node N1 and / or the second node N2, and is used to control the potential of the second output terminal OUT2 according to the potential of the first node N1 and / or the second node N2. For example, the second output unit 132 is used to be turned on or off at least according to the potential of the first node N1, and output the first level signal VGL to the second output terminal OUT2 when turned on.

[0068] Specifically, in the second output module 130, the first output unit 131 can control whether the voltage of the second power line and / or the second level signal VGH are output to the second output terminal OUT2, and the second output unit 132 can control whether the voltage of the first power line and / or the first level signal VGL are output to the second output terminal OUT2. For example, the conduction period of the first output unit 131 and the conduction period of the second output unit 132 are at least partially different. For example, the first output unit 131 and the second output unit 132 are turned on in time division. Optionally, the node voltage control module 110 is used to control the potentials of the first node N1 and the second node N2 to remain opposite, that is, when the first node N1 is at a high potential, the second node N2 is at a low potential; when the first node N1 is at a low potential, the second node N2 is at a high potential. Specifically, the node voltage control module 110 is used to control the potential of the second node N2 to jump from a high potential to a low potential when the potential of the first node N1 jumps from a low potential to a high potential, and when the potential of the first node N1 jumps from a high potential to a low potential, the potential of the second node N2 jumps from a low potential to a high potential. The first output unit 131 and the second output unit 132 each include at least one switch element, which may be a transistor. The first output unit 131 is connected to the second node N2, and the node voltage control module 110 controls the conduction state of the first output unit 131 by controlling the potential of the second node N2, thereby controlling whether the second level signal VGH is output to the second output terminal OUT2. The first output unit 131 can be used to control the potential of the second output terminal OUT2 according to the potential of the second node N2.

[0069] Optionally, the first output unit 131 includes a first transistor T1, and the gate potential of the first transistor T1 is positively correlated with the potential of the second node N2. That is, the gate potential of the first transistor T1 and the potential of the second node N2 are both high potentials and low potentials. And / or, that is, the gate potential of the first transistor T1 and the potential of the second node N2 jump from a low potential to a high potential at the same time, and jump from a high potential to a low potential at the same time. For example, the gate of the first transistor T1 is connected to the second node N2. The first electrode of the first transistor T1 is connected to the second power line and / or connected to the second level signal VGH, and the second electrode of the first transistor T1 is connected to the second output terminal OUT2.

[0070] The second output unit 132 is connected to the first node N1 and / or the second node N2, and the second output unit 132 is used to turn on or off according to the potential of the first node N1 and / or the second node N2. When it is turned on, the first level signal VGL is transmitted to the second output terminal OUT2. For example, the second output unit 132 is connected to the first node N1, and the second output unit 132 is used to turn on or off according to the potential of the first node N1. When it is turned on, the first level signal VGL is transmitted to the second output terminal OUT2. For example, the second output unit 132 is connected to the second node N2, and the second output unit 132 is used to turn on or off according to the potential of the second node N2. When it is turned on, the first level signal VGL is transmitted to the second output terminal OUT2. The second output unit 132 is connected to the first node N1 and the second node N2, and the second output unit 132 is used to turn on or off according to the potential of the first node N1 and the second node N2. When it is turned on, the first level signal VGL is transmitted to the second output terminal OUT2. The second output unit 132 is connected to at least the first node N1. In some embodiments, the second output unit 132 is connected to the first node N1 and is turned on or off according to the potential of the first node N1; in other embodiments, the second output unit 132 is connected to the first node N1 and the second node N2, respectively, and is turned on or off according to the potentials of the first node N1 and the second node N2. When the second output unit 132 is turned on, it transmits the first level signal VGL to the second output terminal OUT2. The second output unit 132 can be used to control the potential of the second output terminal OUT2 according to the potentials of the first node N1 and the second node N2.

[0071] Figure 2exemplarily shows the case where the second output unit 132 is connected to the first node N1 but not to the second node N2. Optionally, the second output unit 132 includes a second transistor T2, and the gate potential of the second transistor T2 is positively correlated with the potential of the first node N1. That is, the gate potential of the second transistor T2 and the potential of the first node N1 are both high potential and low potential at the same time. And / or, that is, the gate potential of the second transistor T2 and the potential of the first node N1 are both changed from low potential to high potential and from high potential to low potential at the same time.

[0072] In some other embodiments, optionally, the gate potential of the second transistor T2 is inversely correlated with the potential of the second node N2, for example, the potentials remain opposite. That is, one of the gate potential of the second transistor T2 and the potential of the second node N2 is a high potential, and the other is a low potential. And / or, that is, when the gate potential of the second transistor T2 jumps from a low potential to a high potential, the potential of the second node N2 jumps from a high potential to a low potential. When the gate potential of the second transistor T2 jumps from a high potential to a low potential, the potential of the second node N21 jumps from a low potential to a high potential. The jump from a low potential to a high potential can be a rising edge. The jump from a high potential to a low potential can be a falling edge.

[0073] The first electrode of the second transistor T2 is connected to the first power line and / or receives the first level signal VGL, and the second electrode of the second transistor T2 is connected to the second output terminal OUT2. Figure 2 As shown, in some embodiments, the gate of the second transistor T2 is connected to the first node N1. Optionally, the second transistor T2 is a P-type transistor, so that the second output module 130 outputs the first level signal VGL through the P-type transistor, and the stability of the first level signal VGL in the second gate drive signal output by the shift register is ensured, which is conducive to improving the display effect.

[0074] In some optional embodiments of the present invention, the first transistor T1 is a P-type transistor, so that the second output module 130 outputs the second level signal VGH through the P-type transistor, ensuring the stability of the second level signal VGH in the second gate drive signal output by the shift register, which is beneficial to improving the display effect.

[0075] Optionally, the second output unit 132 further includes a first capacitor C1 , a first end of the first capacitor C1 is connected to the gate of the second transistor T2 , and a second end of the first capacitor C1 is connected to the second output end OUT2 .

[0076] Figure 3 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 3In some embodiments, the second output unit 132 further includes an output control subunit 133, the output control subunit 133 is connected to the first node N1 and the second node N2 respectively, the output control subunit 133 and the gate of the second transistor T2 are connected to the third node N3, and are used to control the potential of the third node N3 according to the potentials of the first node N1 and the second node N2, so that the potential of the third node N3 is positively correlated with the potential of the first node N1, and when the potential of the first node N1 is the first level signal VGL, the potential of the third node N3 is the third level signal VGL2, and the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL. The potential of the third node N3 is positively correlated with the potential of the first node N1, that is, the potential of the third node N3 and the potential of the first node N1 are both high potential and low potential at the same time, and / or, the potential of the third node N3 and the potential of the first node N1 are both changed from low potential to high potential and from high potential to low potential at the same time.

[0077] Optionally, when the potential of the second node N2 jumps from a low potential to a high potential, the potential of the third node N3 jumps from a high potential to a low potential; when the potential of the second node N2 jumps from a high potential to a low potential, the potential of the third node N3 jumps from a low potential to a high potential. Optionally, the potentials of the second node N2 and the third node N3 remain opposite.

[0078] In this embodiment, the gate of the second transistor T2 is not directly connected to the first node N1, but connected to the first node N1 and the second node N2 through the output control subunit 133. The output control subunit 133 controls the potential of the third node N3 according to the potentials of the first node N1 and the second node N2. Optionally, when the first node N1 is a first level signal VGL and the second node N2 is a second level signal VGH, the output control subunit 133 outputs a third level signal VGL2 to the third node N3 according to the first level signal VGL of the first node N1 and the second level signal VGH of the second node N2; when the first node N1 is a second level signal VGH and the second node N2 is a first level signal VGL, the output control subunit 133 outputs a second level signal VGH to the third node N3 according to the second level signal VGH of the first node N1 and the first level signal VGL of the second node N2. Since the voltage of the third level signal VGL2 is lower than the voltage of the first level signal VGL, when the third node N3 is the third level signal VGL2, the absolute value of the voltage difference between the gate and the first electrode of the second transistor T2 is large, so that the on state of the second transistor T2 is better, ensuring that the first level signal VGL connected to the first electrode of the second transistor T2 can be transmitted to the second output terminal OUT2 with equal amplitude, thereby ensuring that the on or off state of the transistor driven by the second gate drive signal is better, which is conducive to improving the display effect. Exemplarily, when the transistor driven by the second gate drive signal is an N-type transistor, the first level signal VGL is a low level signal, and the second level signal VGH is a high level signal, the N-type transistor driven by the second gate drive signal can be completely turned off under the action of the first level signal VGL in the second gate drive signal.

[0079] Optionally, the potential of the third node N3 further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal.

[0080] In some optional embodiments of the present invention, the absolute value of the voltage difference between the third level signal VGL2 and the first level signal VGL is greater than or equal to the absolute value of the threshold voltage of the second transistor T2. In this way, it can be ensured that when the potential of the third node N3 is the third level signal VGL2, the second transistor T2 can be fully turned on, and it can be further ensured that when the second transistor T2 is turned on, the first level signal VGL can be transmitted to the second output terminal OUT2 with equal amplitude, thereby improving the display effect.

[0081] For example, the absolute value of the difference between the third level signal VGL2 and the voltage of the first power line (eg, capable of transmitting the first level signal VGL) is greater than or equal to the absolute value of the threshold voltage of the second transistor T2.

[0082] Continue to refer Figure 3Optionally, the output control subunit 133 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; the gate of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second power line and / or connected to the second level signal VGH, the second electrode of the third transistor T3 is connected to the first electrode of the fifth transistor T5, and the second electrode of the fifth transistor T5 is connected to the third power line and / or connected to the third level signal VGL2; the gate of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second power line and / or connected to the second level signal VGH, the second electrode of the fourth transistor T4 is connected to the first electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is connected to the third power line and / or connected to the third level signal VGL2; the gate of the fifth transistor T5 is connected to the second electrode of the fourth transistor T4, and the gate of the sixth transistor T6 is connected to the second electrode of the third transistor T3. In this connection mode, when the fifth transistor T5 is turned off, the gate of the fifth transistor can be transmitted with the third level signal VGL2 by the sixth transistor T6, and the source of the fifth transistor T5 is also the third level signal VGL2. The potentials of the gate and source of the fifth transistor T5 are equal, so the leakage current is small when the fifth transistor T5 is turned off, which reduces the power consumption of the gate drive circuit. The same is true for the sixth transistor T6 in the output control subunit 133. When the output control subunit 133 is set to an inverter structure, when the N-type transistor in the inverter is turned off, the gate is the first level signal VGL1, and the source is the third level signal VGL3. The leakage current of the N-type transistor is large, and the power consumption is also large. That is, the structure of the output control subunit 133 in this embodiment can reduce the leakage current of the N-type transistor and reduce the power consumption of the gate drive circuit relative to the structure of the inverter.

[0083] Optionally, the voltage of the third power line is lower than the voltage of the first power line.

[0084] Optionally, the third transistor T3 is a P-type transistor, and / or the fourth transistor T4 is a P-type transistor, and / or the fifth transistor T5 is an N-type transistor, and / or the sixth transistor T6 is an N-type transistor.

[0085] Take the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example. When the first node N1 is the first level signal VGL and the second node N2 is the second level signal VGH, the third transistor T3 is turned on, the fourth transistor T4 is turned off, the second level signal VGH is transmitted to the gate of the sixth transistor T6 through the third transistor T3, so that the sixth transistor T6 is turned on, and the third level signal VGL2 is transmitted to the third node N3, and the fifth transistor T5 is turned off according to the third level signal VGL2. When the first node N1 is the second level signal VGH and the second node N2 is the first level signal VGL, the third transistor T3 is turned off, the fourth transistor T4 is turned on, the second level signal VGH is transmitted to the gate of the fifth transistor T5 and the third node N3 through the fourth transistor T4, the fifth transistor T5 is turned on according to the second level signal VGH at the gate, the third level signal VGL2 is transmitted to the gate of the sixth transistor T6 through the fifth transistor T5, and the sixth transistor T6 is turned off. In this way, the potential of the third node N3 is positively correlated with the potential of the first node N1 , and when the potential of the first node N1 is the first level signal VGL, the potential of the third node N3 is the third level signal VGL2 .

[0086] Figure 4 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 4 Optionally, the second electrode of the sixth transistor T6 is connected to the third power line and / or is connected to the third level signal VGL2; the second electrode of the fifth transistor T5 is connected to the first power line and / or is connected to the first level signal VGL.

[0087] Compared with the second electrode of the fifth transistor T5 being connected to the first power line and / or being connected to the first level signal VGL (the gate-source voltage difference when the sixth transistor T6 is turned off is the difference between the first level signal VGL and the third level signal VGL2, that is, greater than 0), the second electrode of the fifth transistor T5 is connected to the third power line and / or is connected to the third level signal VGL2 (the gate-source voltage difference when the sixth transistor T6 is turned off is the difference between the third level signal VGL2 and the third level signal VGL2, that is, 0), which can reduce the leakage current when the sixth transistor T6 is turned off.

[0088] Figure 5 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 5Optionally, the first output module 120 includes a third output unit 121 and a fourth output unit 122, the third output unit 121 is connected to the first node N1, and the third output unit 121 is used to control the potential of the first output terminal OUT1 according to the potential of the first node N1, for example, the third output unit 121 is used to turn on or off according to the potential of the first node N1, and output the second level signal VGH to the first output terminal OUT1 when turned on; the fourth output unit 122 is connected to the second node N2, and the fourth output unit 122 is used to control the potential of the first output terminal OUT1 according to the potential of the second node N2, for example, the fourth output unit 122 is used to turn on or off according to the potential of the second node N2, and output the first level signal VGL to the first output terminal OUT1 during at least part of the turn-on period.

[0089] The third output unit 121 and the fourth output unit 122 respectively include at least one switch device, which may be a transistor. By setting the first output module 120 to include the third output unit 121 and the fourth output unit 122, the third output unit 121 and the fourth output unit 122 can be turned on in time division. When the third output unit 121 is turned on, the third output unit 121 outputs the second level signal VGH to the first output terminal OUT1; during at least a portion of the time period when the fourth output unit 122 is turned on, the fourth output unit 122 outputs the first level signal to the first output terminal OUT1.

[0090] Optionally, the third output unit 121 includes a seventh transistor T7, a gate of the seventh transistor T7 is connected to the first node N1, a first electrode of the seventh transistor T7 is connected to the second power line and / or connected to the second level signal VGH, and a second electrode of the seventh transistor T7 is connected to the first output terminal OUT1.

[0091] In some embodiments, the fourth output unit 122 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the second node N2, the first electrode of the eighth transistor T8 is connected to the signal including the first level signal VGL, and in some embodiments, the first electrode of the eighth transistor T8 is connected to the periodic clock signal including the first level signal VGL and the second level signal VGH ( Figure 4 FIG. 5 schematically shows that a first electrode of the eighth transistor T8 is connected to the second clock signal CK2 , and a second electrode of the eighth transistor T8 is connected to the first output terminal OUT1 .

[0092] Optionally, the fourth output unit 122 further includes a second capacitor C2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first output end OUT1.

[0093] Optionally, effective levels of the first gate driving signal and the second gate driving signal overlap.

[0094] The effective level of the first gate drive signal is a level that can turn on the driven transistor, and the invalid level of the first gate drive signal is a level that can turn off the driven transistor. The effective level of the second gate drive signal is a level that can turn on the driven transistor, and the invalid level of the second gate drive signal is a level that can turn off the driven transistor.

[0095] Optionally, the effective level of the first gate driving signal is a first level signal, and the effective level of the second gate driving signal is a second level signal. In some optional embodiments, the ineffective levels of the first gate driving signal and the second gate driving signal overlap.

[0096] Among them, one of the first level signal VGL and the second level signal VGH is a high level signal, and the other is a low level signal. When the first gate drive signal is used to drive a P-type transistor and the second gate drive signal is used to drive an N-type transistor, the first level signal VGL is a low level signal and the second level signal VGH is a high level signal; when the first gate drive signal is used to drive an N-type transistor and the second gate drive signal is used to drive a P-type transistor, the first level signal VGL is a high level signal and the second level signal VGH is a low level signal.

[0097] The first gate driving signal and the second gate driving signal output by the shift register can be used to drive different transistors in the pixel circuit. Figure 6 This is a schematic diagram of a pixel circuit structure in the related art, refer to Figure 6 The pixel circuit includes a driving transistor DT, a data writing transistor M1 and a compensation transistor M2. The data writing transistor M1 is connected between the data line Data and the first electrode of the driving transistor DT, and the compensation transistor M2 is connected between the second electrode and the gate of the driving transistor DT. The first output terminal OUT1 of the shift register can be connected to the data writing transistor M1 in the pixel circuit, and the second output terminal OUT2 can be connected to the compensation transistor M2 in the pixel circuit. The effective level of the first gate driving signal Scan1 is the level that turns on the data writing transistor M1, and the second gate driving signal Scan2 is the level that turns on the compensation transistor M2. By setting the effective level of the first gate driving signal output by the shift register to overlap with the effective level of the second gate driving signal, the data writing transistor M1 and the compensation transistor M2 can be turned on at the same time during the overlapping period of the first gate driving signal and the effective level and the effective level of the second gate driving signal, thereby completing the writing of the data voltage on the data line to the gate of the driving transistor DT.

[0098] In some embodiments, the data write transistor M1 is a P-type transistor, and the compensation transistor M2 is an N-type transistor. That is, the channel type of the data write transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel. Optionally, the P-type transistor in the pixel circuit is a polysilicon transistor, such as a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. Accordingly, the display panel is a display panel of a low-temperature polycrystalline oxide (LTPO) process. In some embodiments, the P-type transistor in the shift register is a polysilicon transistor, such as a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. That is, the shift register of this embodiment can be used to drive a display panel of an LTPO process, which is conducive to ensuring higher smoothness and lower power consumption of the display panel.

[0099] Optionally, the pixel circuit also includes a first light-emitting control transistor M3 and a second light-emitting control transistor M4, the first light-emitting control transistor M3 is connected between the fourth power line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, and the second electrode of the light-emitting device D1 is connected to the fifth power line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM.

[0100] Optionally, the pixel circuit further includes a first initialization transistor M5, a gate of the first initialization transistor M5 connected to the first scan line Sn1, a first electrode of the first initialization transistor M5 connected to the first initialization signal line Vref1, and a second electrode of the first initialization transistor M5 connected to the gate or second electrode of the driving transistor DT.

[0101] Optionally, the pixel circuit further includes a second initialization transistor M6, a gate of the second initialization transistor M6 is connected to the second scan line Sn2, a first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and a second electrode of the second initialization transistor M6 is connected to the first electrode of the light emitting device D1.

[0102] Optionally, the pixel circuit further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and a second end of the storage capacitor Cst is connected to a fourth power line VDD.

[0103] Figure 7 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 7Optionally, the input signal includes a first clock signal CK1, a second clock signal CK2 and a start signal SIN; the node voltage control module 110 includes an input unit 111, a first control unit 112 and part or all of a second control unit 113, the input unit 111 is used to control the transmission of the start signal SIN to the second node N2 according to the first clock signal CK1, for example, the input unit 111 is used to turn on or off according to the first clock signal CK1, and transmit the start signal SIN to the second node N2 when turned on; the first control unit 112 is used to invert the potential of the second node N2 and output it to the first node, for example, the first control unit 112 is used to transmit the first level signal VGL or the second level signal VGH to the first node N1 according to the potential of the second node N2; the second control unit 113 is used to transmit the second level signal VGH to the second node N2 according to the potential of the first node N1 and the second clock signal CK2.

[0104] Among them, the first clock signal CK1, the second clock signal CK2, and the start signal SIN respectively include first level pulses and second level pulses alternately set, the first clock signal CK1 and the second clock signal CK2 are both periodic signals, the periods of the first clock signal CK1 and the second clock signal CK2 are equal, and the first clock signal CK1 and the second clock signal CK2 include multiple first level pulses and second electrical pulses, the first level pulse of the first clock signal CK1 overlaps with the second level pulse of the second clock signal CK2, and the second level pulse of the first clock signal CK1 overlaps with the first level pulse of the second clock signal CK2.

[0105] The gate drive circuit in the display panel includes a plurality of shift registers, and the plurality of shift registers are cascaded. For the first-stage shift register, the start signal SIN is provided by an external circuit structure. For the second to last-stage shift registers, the start signal SIN may be the first gate drive signal output by the previous-stage shift register, that is, in two adjacent stages of registers, the latter-stage shift register is connected to the first output terminal OUT1 of the former-stage shift register. Optionally, the first level pulse of the start signal SIN is one or more, and the first level pulse of the start signal SIN overlaps with the first level pulse of the first clock signal CK1, and does not overlap with the first level pulse of the second clock signal CK2.

[0106] Specifically, when the first clock signal CK1 is the first level signal VGL, the input unit 111 is turned on. When the second node N2 is the first level signal VGL, the first control unit 112 transmits the second level signal VGH to the first node N1; when the second node N2 is the second level signal VGH, the first control unit 112 transmits the first level signal VGL to the first node N1. When the first node N1 is the first level signal VGL and the second clock signal CK2 is the first level signal VGL, the second control unit 113 transmits the second level signal VGH to the second node N2.

[0107] In some embodiments, the first output module 120 includes a third output unit 121 and a fourth output unit 122, the third output unit 121 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the first node N1, the first electrode of the seventh transistor T7 is connected to the second power line and / or connected to the second level signal VGH, and the second electrode of the seventh transistor T7 is connected to the first output terminal OUT1; the fourth output unit 122 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the second node N2; the first electrode of the eighth transistor T8 is connected to the second clock signal CK2, and the second electrode of the eighth transistor T8 is connected to the first output terminal OUT1.

[0108] Figure 8 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 8 Optionally, the input unit 111 includes a ninth transistor T9, a gate of the ninth transistor T9 is connected to the first clock signal CK1, a first electrode of the ninth transistor T9 is connected to the start signal SIN, and a second electrode of the ninth transistor T9 is connected to the second node N2.

[0109] In some embodiments, the shift register further includes a tenth transistor T10, and the second electrode of the ninth transistor T9 is connected to the second node N2 through the tenth transistor T10, or the second electrode of the ninth transistor T9 is connected to the gate of the eighth transistor T8 through the tenth transistor T10; the gate of the tenth transistor T10 is connected to the first power line and / or connected to the first level signal VGL. Taking the tenth transistor T10 as a P-type transistor as an example, the setting of the tenth transistor T10 can make the level of the second node N2 coupled to the extremely low level be blocked by the tenth transistor T10 and will not be transmitted to the common end of the tenth transistor T10 and the ninth transistor T9 (that is, the fourth node N4), thereby protecting the ninth transistor T9 and the transistor connected to the tenth transistor T10 in the second control unit 113 from being damaged due to excessive voltage difference, thereby improving the reliability of the shift register.

[0110] Fig. 9 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig. 9 Optionally, the first control unit 112 includes a second inverter. In some embodiments, the first control unit 112 includes an eleventh transistor T11 and a twelfth transistor T12. The gate of the eleventh transistor T11 is connected to the second electrode or the second node N2 of the ninth transistor T9, the first electrode of the eleventh transistor T11 is connected to the second power line and / or connected to the second level signal VGH, and the second electrode of the eleventh transistor T11 is connected to the first node N1; the gate of the twelfth transistor T12 is connected to the second electrode or the second node N2 of the ninth transistor T9, the first electrode of the twelfth transistor T12 is connected to the first power line and / or connected to the first level signal VGL, and the second electrode of the twelfth transistor T12 is connected to the first node N1. Optionally, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor. By setting the shift register to include both a P-type transistor and an N-type transistor, the number of transistor devices included in the shift register can be reduced, which is conducive to reducing the frame and improving the user experience. Optionally, the P-type transistor is a polysilicon transistor, and the N-type transistor is an oxide transistor. For example, the second inverter includes an eleventh transistor T11 and a twelfth transistor T12.

[0111] Specifically, when the ninth transistor T9 is directly connected to the second output unit 132 at the second node N2, the gate of the eleventh transistor T11 is directly connected to the second node N2. When the ninth transistor T9 is connected to the second output unit 132 through the tenth transistor T10, the gate of the eleventh transistor T11 is connected to the second electrode (fourth node N4) of the ninth transistor T9. The same is true for the twelfth transistor T12, which will not be described here. The eleventh transistor T11 is turned on when the second node N2 is the first level signal VGL or the second electrode (fourth node N4) of the ninth transistor T9 is the first level signal VGL, and transmits the second level signal VGH to the first node N1. The twelfth transistor T12 is turned on when the second node N2 is the second level signal VGH or the second electrode (fourth node N4) of the ninth transistor T9 is the second level signal VGH, and transmits the first level signal VGL to the first node N1.

[0112] Continue to refer Fig. 9 In some embodiments, the second control unit 113 includes a thirteenth transistor T13 and a fourteenth transistor T14, the first electrode of the thirteenth transistor T13 is connected to the second level signal VGH, the second electrode of the thirteenth transistor T13 is connected to the first electrode of the fourteenth transistor T14, the second electrode of the fourteenth transistor T14 is connected to the second electrode (the fourth node N4) or the second node N2 of the ninth transistor T9, one of the gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 is connected to the first node N1, and the other is connected to the second clock signal CK2.

[0113] Optionally, the gate of the thirteenth transistor T13 is connected to the first node N1, and the gate of the fourteenth transistor T14 is connected to the second clock signal CK2.

[0114] Specifically, when the first node N1 is the first level signal VGL, the thirteenth transistor T13 is turned on, and the second level signal VGH is transmitted from the first electrode of the thirteenth transistor T13 to the first electrode of the fourteenth transistor T14. When the second clock signal CK2 is the first level signal VGL, the fourteenth transistor T14 is turned on, and the signal of the first electrode of the fourteenth transistor T14 is transmitted to the second electrode (fourth node N4) or the second node N2 of the ninth transistor T9. When the first node N1 is the first level signal VGL, and the second clock signal CK2 of the gate of the fourteenth transistor T14 is the first level signal VGL, the second level signal VGH is transmitted to the second electrode (fourth node N4) or the second node N2 of the ninth transistor T9 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0115] Fig.10 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.10 Optionally, the connection node between the tenth transistor T10 and the ninth transistor T9 (ie, the fourth node N4) can be used as the second node N2, which is equivalent to the fourth output unit 122 including the tenth transistor T10. The gate of the fourth transistor can be connected to the fourth node N4. The fourth node N4 and the second node are the same node.

[0116] Fig.11 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.11, optionally, the gate potential of the first transistor T1 is inversely correlated with the potential of the first node N1, and the potentials remain opposite. That is, one of the gate potential of the first transistor T1 and the potential of the first node N1 is a high potential, and the other is a low potential. And / or, that is, when the gate potential of the first transistor T1 jumps from a low potential to a high potential, the potential of the first node N1 jumps from a high potential to a low potential. When the gate potential of the first transistor T1 jumps from a high potential to a low potential, the potential of the first node N1 jumps from a low potential to a high potential. For example, the first node N1 is connected to the gate of the first transistor T1 through the third inverter 1311. Optionally, the first output unit 131 also includes a third inverter 1311, the input end of the third inverter 1311 is connected to the first node N1, and the output end of the third inverter 1311 is connected to the gate of the first transistor T1. Among them, the third inverter 1311 can invert the potential of the first node N1 and output it to the gate of the first transistor T1. The gate of the second transistor T2 is used as the third node N3, and the third node N3 is connected to the first node N1, or the third node N3 and the first node N1 are the same node. In this case, the second output module 130 can output the second gate driving signal through the second output terminal OUT2 according to the voltage of the first node N1. The structure of the third inverter 1311 is the same or similar to that of the first inverter 1331 or the second inverter, and will not be repeated here.

[0117] For example Fig.10 The first node N1 in is connected to the gate of the first transistor T1 through the third inverter 1311, instead of the gate of the first transistor T1 being directly connected to the second node. The working principle is the same or similar to that of FIG.

[0118] Fig.12 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.12 Optionally, the second output unit 132 also includes an output control subunit 133, the output control subunit 133 includes a first inverter 1331, the input end of the first inverter 1331 is connected to the second node N2, the output end of the first inverter 1331 and the gate of the second transistor T2 are connected to the third node N3; the first end of the first inverter 1331 is connected to the second power line or connected to the second level signal VGH, the output control subunit 133 is used to control the potential of the third node N3 according to the potential of the second node N2; the second end of the first inverter 1331 is connected to the third power line or connected to the third level signal VGL2.

[0119] Specifically, the first inverter 1331 can invert the potential of the second node N2, so that when the potential of the second node N2 is the first level signal VGL, the potential of the third node N3 is the second level signal VGH; when the potential of the second node N2 is the second level signal VGH, the potential of the third node N3 is the third level signal VGL2 or the voltage on the third power line.

[0120] In some optional embodiments, the output control subunit 133 includes M first inverters 1331; optionally, M is an odd number greater than 1, the input end of the 1st first inverter 1331 is connected to the second node N2, the output end of the i-th first inverter 1331 is connected to the input end of the i+1-th first inverter 1331, and the output end of the M-th first inverter 1331 is connected to the gate of the second transistor T2 at the third node N3; i is an integer greater than or equal to 1 and less than or equal to M; the output control subunit 133 is used to control the potential of the third node N3 according to the potential of the second node N2.

[0121] Fig.13 It is a structural diagram of another shift register provided by an embodiment of the present invention. In other optional embodiments, M is an even number greater than or equal to 2; the input end of the 1st first inverter 1331 is connected to the first node, the output end of the i-th first inverter 1331 is connected to the input end of the i+1-th first inverter 1331, and the output end of the M-th first inverter 1331 is connected to the gate of the second transistor T2 at the third node N3; the output control subunit 133 is used to control the potential of the third node N3 according to the potential of the first node; the first end of the first inverter 1331 is connected to the second power line or connected to the second level signal VGH, and the second end of the M-th first inverter 1331 is connected to the third power line or connected to the third level signal VGL2.

[0122] Optionally, when the potential of the second node N2 jumps from a low potential to a high potential, the potential of the third node N3 jumps from a high potential to a low potential; when the potential of the second node N2 jumps from a high potential to a low potential, the potential of the third node N3 jumps from a low potential to a high potential. Optionally, the potentials of the second node N2 and the third node N3 remain opposite. Optionally, the potentials of the first node N1 and the third node N3 jump from a low potential to a high potential at the same time, and / or, the potentials of the first node N1 and the third node N3 jump from a high potential to a low potential at the same time.

[0123] Optionally, the first inverter 1331 includes a fifteenth transistor T15 and a sixteenth transistor T16, the gate of the fifteenth transistor T15 and the gate of the sixteenth transistor T16 are connected to the input end of the first inverter 1331, the first electrode of the fifteenth transistor T15 is connected to the first end of the first inverter 1331, the second electrode of the fifteenth transistor T15 and the first electrode of the sixteenth transistor T16 are connected to the output end of the first inverter 1331, and the second electrode of the sixteenth transistor T16 is connected to the second end of the first inverter 1331; optionally, the fifteenth transistor T15 is an N-type transistor and the sixteenth transistor T16 is a P-type transistor.

[0124] refer to Fig.12 When M is an odd number, when the potential of the second node N2 is at a low level, the fifteenth transistor T15 is turned on to transmit the second level signal VGH to the third node N3. When the potential of the second node N2 is at a high level, the sixteenth transistor T16 is turned on to transmit the third level signal VGL2 to the third node N3.

[0125] refer to Fig.13 , when M is an even number, when the potential of the first node N1 is at a low level, in the first inverter 1331 at the odd number position, the fifteenth transistor T15 is turned on, and the second level signal VGH is transmitted to the input terminal of the first inverter 1331 at the even number position, so that the sixteenth transistor T16 in the first inverter 1331 at the even number position is turned on, and the third level signal VGL2 is transmitted backward, and finally the potential of the third node is the third level signal VGL2. When the potential of the first node N1 is at a high level, in the first inverter 1331 at the odd number position, the sixteenth transistor T16 is turned on, and the third level signal VGL2 is transmitted to the input terminal of the first inverter 1331 at the even number position, so that the fifteenth transistor T15 in the first inverter 1331 at the even number position is turned on, and the second level signal VGH is transmitted backward, and finally the potential of the third node is the second level signal VGH.

[0126] Fig.14 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.14 Optionally, the second end of at least one first inverter 1331 is connected to the first power line or is connected to the first level signal; or, with reference to Fig.12 and Fig.13 The second ends of all the first inverters 1331 are connected to the third power line or connected to the third level signal VGL2.

[0127] Optionally, the potential of the third node N3 includes a third level signal VGL2, and the voltage of the third level signal VGL2 is lower than the voltage of the first power line; optionally, the voltage of the third power line is lower than the voltage of the first power line.

[0128] Optionally, the potential of the third node N3 further includes the second level signal VGH, and the voltage of the third level signal VGL2 is lower than the voltage of the second level signal VGH.

[0129] Optionally, an absolute value of a voltage difference between the third level signal VGL2 and the voltage of the first power line is greater than or equal to an absolute value of a threshold voltage of the second transistor T2.

[0130] Fig.15 is a working timing diagram of a shift register provided by an embodiment of the present invention, refer to Fig. 9 and Fig.15 , taking the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13 and the fourteenth transistor T14 as P-type transistors, and the fifth transistor T5, the sixth transistor T6 and the twelfth transistor T12 as N-type transistors as an example, taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example, the working timing of the shift register includes the following stages.

[0131] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the fourth node N4, and the first level signal VGL (low level signal) is transmitted to the first node N1, the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The third transistor T3 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is transmitted to the gate of the sixth transistor T6, and the sixth transistor T6 is turned on, and the third level signal VGL2 is transmitted to the third node N3, so that the second transistor T2 is turned on, and the first level signal VGL is transmitted to the second output terminal OUT2. Furthermore, the voltage of the third level signal VGL2 is lower than that of the first level signal VGL, so that the second transistor T2 is in a good conduction state, reducing the influence of the threshold voltage of the second transistor T2 on the output of the first level signal VGL. The first transistor T1 is turned off according to the high level signal of the second node N2.

[0132] In the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off in response to the first clock signal CK1, and no signal is transmitted to the fourth node N4. The fourth node N4 maintains the high level of the previous stage. Correspondingly, the second node N2 maintains the high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 remains on, and correspondingly, the seventh transistor T7 remains on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, in the second stage t2, the second transistor T2 is turned on, the first transistor T1 is turned off, and the first level signal VGL is transmitted to the second output terminal OUT2 through the second transistor T2. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the second level signal VGH is transmitted to the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0133] In the third stage t3, the start signal SIN is a low level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, and the low level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned on according to the low level signal of the second node N2, and the high level second clock signal CK2 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on according to the low level signal of the fourth node N4, and the second level signal VGH (high level signal) is transmitted to the first node N1, and the seventh transistor T7 is turned off according to the high level signal of the first node N1. The first transistor T1 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the second output terminal OUT2. The fourth transistor T4 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the gate of the fifth transistor T5 and the third node N3, so that the fifth transistor T5 is turned on, and the third level signal VGL2 is transmitted to the gate of the sixth transistor T6, so that the sixth transistor T6 is turned off. The second transistor T2 is turned off according to the high level of the third node N3.

[0134] In the fourth stage t4, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a low level signal, the ninth transistor T9 is turned off in response to the first clock signal CK1, no signal is transmitted to the fourth node N4, the fourth node N4 maintains the low level of the previous stage, and accordingly, the second node N2 maintains the low level of the previous stage, the eighth transistor T8 is turned on, and the low level second clock signal CK2 is transmitted to the first output terminal OUT1. The eleventh transistor T11 remains turned on, the first node N1 is a high level signal, and accordingly, the seventh transistor T7 remains turned off. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, therefore, in the second stage t2, the first transistor T1 is turned on, the second transistor T2 is turned off, and the second level signal VGH is transmitted to the second output terminal OUT2 through the first transistor T1.

[0135] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 is turned on in response to the first clock signal CK1, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the fourth node N4, and the first level signal VGL (low level signal) is transmitted to the first node N1, the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The third transistor T3 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is transmitted to the gate of the sixth transistor T6, and the sixth transistor T6 is turned on, and the third level signal VGL2 is transmitted to the third node N3, so that the second transistor T2 is turned on, and the first level signal VGL is transmitted to the second output terminal OUT2. Furthermore, the voltage of the third level signal VGL2 is lower than that of the first level signal VGL, so that the second transistor T2 is in a good conduction state, reducing the influence of the threshold voltage of the second transistor T2 on the output of the first level signal VGL. The first transistor T1 is turned off according to the high level signal of the second node N2.

[0136] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned off in response to the first clock signal CK1, and no signal is transmitted to the fourth node N4. The fourth node N4 maintains the high level of the previous stage. Correspondingly, the second node N2 maintains the high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 remains on, and correspondingly, the seventh transistor T7 remains on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Because the potentials of the first node N1 and the second node N2 are the same as the state of the first stage t1, therefore, in the sixth stage t6, the second transistor T2 is turned on, the first transistor T1 is turned off, and the first level signal VGL is transmitted to the second output terminal OUT2 through the second transistor T2. The thirteenth transistor T13 and the fourteenth transistor T14 are turned on, and the second level signal VGH is transmitted to the second node N2 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0137] In the subsequent process, the fifth stage t5 and the sixth stage t6 are repeated alternately with the same timing.

[0138] The intermediate state stages are respectively included between the first stage t1 and the second stage t2, between the second stage t2 and the third stage t3, between the third stage t3 and the fourth stage t4, between the fourth stage t4 and the fifth stage t5, and between the fifth stage t5 and the sixth stage t6. In each intermediate state stage, the potentials of the first node N1, the second node N2, the third node N3 and the fourth node N4 in the shift register are respectively the same as the potentials of the first node N1, the second node N2, the third node N3 and the fourth node N4 in the previous stage corresponding to the intermediate state stage.

[0139] Exemplarily, in the first intermediate state between the first stage t1 and the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the first stage t1, so that the twelfth transistor T12 remains turned on, and the first node N1 is still at a low level. Because the potential state of the first node N1 and the second node N2 is the same as that of the first stage t1, the potential state of the third node N3 is determined by the potential of the first node N1 and the second node N2, and therefore the potential state of the third node N3 is also the same as that of the first stage t1, therefore, in the first intermediate state, the first output terminal OUT1 is still the second level signal VGH output by the seventh transistor T7, and the second output terminal OUT2 is still the first level signal VGL output by the second transistor T2.

[0140] In the second intermediate state between the second stage t2 and the third stage t3, the start signal SIN is a high level signal for a period of time and a low level signal for a period of time, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the second stage t2, so that the twelfth transistor T12 remains turned on, and the first node N1 is still at a low level. Since the potential state of the first node N1 and the second node N2 is the same as that of the second stage t2, the potential state of the third node N3 is determined by the potential of the first node N1 and the second node N2, so the potential state of the third node N3 is also the same as that of the second stage t2, and accordingly, the third node N3 is a low level signal. Therefore, in the second intermediate state, the first output terminal OUT1 is still the second level signal VGH output by the seventh transistor T7, and the second output terminal OUT2 is still the first level signal VGL output by the second transistor T2.

[0141] In the third intermediate state between the third stage t3 and the fourth stage t4, the start signal SIN is a low level signal for a period of time and a high level signal for a period of time, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the low level of the third stage t3, the eighth transistor T8 is turned on according to the low level of the second node N2, and the high level second clock signal CK2 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on according to the low level of the fourth node N4, and the second level signal VGH (high level signal) is transmitted to the first node N1, so that the seventh transistor T7 is turned off. Since the potential state of the first node N1 and the second node N2 is the same as that in the third stage t3, and the potential state of the third node N3 is determined by the potentials of the first node N1 and the second node N2, the potential state of the third node N3 is also the same as that in the third stage t3. Correspondingly, the third node N3 is a high-level signal. Therefore, in the third intermediate state stage, the first output terminal OUT1 is still the high-level second clock signal CK2 output by the eighth transistor T8, and the second output terminal OUT2 is still the second-level signal VGH output by the first transistor T1.

[0142] In the fourth intermediate state between the fourth stage t4 and the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, and the fourth node N4 and the second node N2 maintain the low level of the fourth stage t4, so that the eleventh transistor T11 remains turned on, and the first node N1 is still at a high level. The eighth transistor T8 is still turned on, and the high-level second clock signal CK2 is transmitted to the first output terminal OUT1. Because the potential state of the first node N1 and the second node N2 is the same as the first stage t1, the potential state of the third node N3 is determined by the potential of the first node N1 and the second node N2, so the potential state of the third node N3 is also the same as the fourth stage t4. Therefore, in the fourth intermediate state, the first output terminal OUT1 is the high-level second clock signal CK2 output by the eighth transistor T8, and the second output terminal OUT2 is still the second level signal VGH output by the first transistor T1.

[0143] In the fifth intermediate state between the fifth stage t5 and the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the fourth node N4 and the second node N2 maintain the high level of the fifth stage t5, so that the twelfth transistor T12 remains turned on, and the first node N1 is still at a low level. Since the potential state of the first node N1 and the second node N2 is the same as that of the first stage t1, the potential state of the third node N3 is determined by the potential of the first node N1 and the second node N2, and therefore the potential state of the third node N3 is also the same as that of the fifth stage t5, therefore, in the fifth intermediate state, the first output terminal OUT1 is still the second level signal VGH output by the seventh transistor T7, and the second output terminal OUT2 is still the first level signal VGL output by the second transistor T2.

[0144] refer to Fig.15 , Optionally, a pulse of the first gate driving signal overlaps with a pulse of the second gate driving signal.

[0145] Wherein, the pulse of the first gate driving signal includes a first level pulse (i.e., a pulse of the first level signal) and a second level pulse (i.e., a pulse of the second level signal), and the pulse of the second gate driving signal includes a first level pulse and a second level pulse. Optionally, the first level pulse of the first gate driving signal overlaps with the first level pulse of the second gate driving signal, and / or the second level pulse of the first gate driving signal overlaps with the second level pulse of the second gate driving signal.

[0146] In some embodiments, a duration of a first level signal of a pulse of the first gate driving signal is within a duration of a second level signal of a pulse of the second gate driving signal.

[0147] Optionally, a pulse width of the first gate driving signal is smaller than a pulse width of the second gate driving signal.

[0148] Optionally, the input signal includes a clock signal and a start signal SIN, a pulse width of the first gate drive signal is equal to a pulse width of the clock signal, and a pulse width of the second gate drive signal is equal to a clock period of the clock signal;

[0149] Optionally, the input signal includes a first clock signal CK1 and a second clock signal CK2, a pulse of the first clock signal CK1 overlaps with a pulse of the start signal SIN, and a pulse of the second clock signal CK2 overlaps with a pulse of the first gate drive signal;

[0150] Optionally, a transition edge of a pulse of the first gate driving signal is aligned with a transition edge of a pulse of the second clock signal CK2.

[0151] Optionally, a transition edge of a pulse of the second gate driving signal is aligned with a transition edge of a pulse of the first clock signal CK1.

[0152] Optionally, the falling edge of the pulse of the first gate driving signal is aligned with the falling edge of the pulse of the second clock signal CK2; the rising edge of the pulse of the first gate driving signal is aligned with the rising edge of the pulse of the second clock signal CK2.

[0153] Optionally, a rising edge and a falling edge of a pulse of the second gate driving signal are respectively aligned with falling edges of two adjacent pulses of the first clock signal CK1 .

[0154] Optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency and different phases, for example, opposite phases. The effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 do not overlap, for example, there is a time interval. The effective potential of the effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 is a first level signal, for example, a low potential.

[0155] The embodiment of the present invention further provides a gate driving circuit. Fig.16 is a schematic diagram of a gate drive circuit provided by an embodiment of the present invention, with reference to Fig.16The gate drive circuit includes a plurality of shift registers 10, wherein the shift register 10 is the shift register 10 of any of the above embodiments of the present invention, and the plurality of shift registers 10 are cascaded, and optionally, the start signal input terminal (which can be connected to the start signal SIN) of the n+1th stage shift register is connected to the first output terminal OUT1 of the nth stage shift register, wherein n is a positive integer greater than or equal to 1, that is, the first gate drive signal output by the first output terminal OUT1 of the nth stage shift register is used as the start signal of the n+1th stage register. The start signal of the first stage shift register is input from the outside.

[0156] The gate driving circuit of this embodiment includes the shift register of any of the above embodiments of the present invention, and has the beneficial effects of the shift register of any of the above embodiments of the present invention, which will not be described in detail here.

[0157] The gate driving circuit can be connected to a first clock line and a second clock line. The first clock line can be used to provide a first clock signal to an odd-numbered shift register, and the second clock line can be used to provide a second clock signal to an odd-numbered shift register. The first clock line can be used to provide a second clock signal to an even-numbered shift register, and the second clock line can be used to provide a first clock signal to an even-numbered shift register.

[0158] An embodiment of the present invention further provides a display panel, Fig.17 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 6 and Fig.17 The display panel includes a pixel circuit 2 and a gate driving circuit 1 of any embodiment of the present invention, the pixel circuit 2 includes multiple transistors, and the first output terminal and the second output terminal of the shift register 10 are connected to transistors of different channel types in the pixel circuit 2.

[0159] Optionally, the pixel circuit 2 includes a driving transistor DT, a data writing transistor M1 and a compensation transistor M2, the data writing transistor M1 is respectively connected to the data line Data and the first electrode of the driving transistor DT, and the compensation transistor M2 is connected between the second electrode and the gate of the driving transistor DT; the gate of the data writing transistor M1 is connected to the first output terminal OUT1, the gate of the data writing transistor M1 is connected to the first gate driving signal Scan1, the gate of the compensation transistor M2 is connected to the second output terminal OUT2, and the gate of the compensation transistor M2 is connected to the second gate driving signal Scan2.

[0160] Optionally, the channel type of the data writing transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel.

[0161] Optionally, the pixel circuit 2 also includes a first light-emitting control transistor M3 and a second light-emitting control transistor M4, the first light-emitting control transistor M3 is connected between the fourth power line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, and the second electrode of the light-emitting device D1 is connected to the fifth power line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM.

[0162] Optionally, the pixel circuit further includes a first initialization transistor M5, a gate of the first initialization transistor M5 connected to the first scan line Sn1, a first electrode of the first initialization transistor M5 connected to the first initialization signal line Vref1, and a second electrode of the first initialization transistor M5 connected to the gate or second electrode of the driving transistor DT.

[0163] Optionally, the pixel circuit further includes a second initialization transistor M6, a gate of the second initialization transistor M6 is connected to the second scan line Sn2, a first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and a second electrode of the second initialization transistor M6 is connected to the first electrode of the light emitting device D1.

[0164] Optionally, the pixel circuit further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and a second end of the storage capacitor Cst is connected to a fourth power line VDD.

[0165] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0166] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shift register, characterized in that: It includes a node voltage control module, a first output module and a second output module, wherein the node voltage control module is connected to a first node and a second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node; The node voltage control module is used to control the voltage of the first node and the second node according to an input signal; The first output module is used to output a first gate drive signal through a first output terminal according to the voltages of the first node and the second node, and the second output module is used to output a second gate drive signal through a second output terminal according to the voltages of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different.

2. The shift register according to claim 1, characterized in that: The first gate driving signal and the second gate driving signal have different pulse widths, pulse amplitudes, and positive and negative polarities of the pulse amplitudes; And / or, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types; Preferably, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor; The second gate driving signal includes a first level signal and a second level signal, the voltage of the first level signal is lower than the voltage of the second level signal; the second output module includes a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor; Preferably, the P-type transistor included in the second output module is a polysilicon transistor; Preferably, the first gate driving signal includes the first level signal and the second level signal; Preferably, a pulse of the first gate driving signal overlaps with a pulse of the second gate driving signal; Preferably, the duration of the first level signal of the pulse of the first gate driving signal is within the duration of the second level signal of the pulse of the second gate driving signal; Preferably, the pulse width of the first gate driving signal is smaller than the pulse width of the second gate driving signal; Preferably, the input signal includes a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal; Preferably, the input signal includes a first clock signal and a second clock signal, a pulse of the first clock signal overlaps with a pulse of the start signal, and a pulse of the second clock signal overlaps with a pulse of the first gate drive signal; Preferably, a transition edge of a pulse of the first gate drive signal is aligned with a transition edge of a pulse of the second clock signal; Preferably, a transition edge of a pulse of the second gate drive signal is aligned with a transition edge of a pulse of the first clock signal; Preferably, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the second clock signal; A rising edge of a pulse of the first gate drive signal is aligned with a rising edge of a pulse of the second clock signal; Preferably, the rising edge and the falling edge of the pulse of the second gate driving signal are respectively aligned with the falling edges of two adjacent pulses of the first clock signal; Preferably, the first clock signal and the second clock signal have the same frequency and different phases.

3. The shift register according to claim 1 or 2, characterized in that: The second output module includes a first output unit and a second output unit. The first output unit is connected to the second node, and is used to be turned on or off according to the potential of the second node, and output a second level signal to the second output terminal when turned on; Alternatively, the first output unit is connected to the first node, and is used to be turned on or off according to the potential of the first node, and output a second level signal to the second output terminal when turned on; The second output unit is connected to the first node and / or the second node, and is used to be turned on or off according to the potential of the first node and / or the second node, and output a first level signal to the second output terminal when turned on; Preferably, the first output unit comprises a first transistor, a gate potential of the first transistor is positively correlated with a potential of the second node, or a gate potential of the first transistor is negatively correlated with a potential of the first node, or a gate of the first transistor is connected to the second node; a first electrode of the first transistor is connected to a second power line or connected to the second level signal, and a second electrode of the first transistor is connected to the second output terminal; And / or, the second output unit includes a second transistor, a gate potential of the second transistor is positively correlated with the potential of the first node, or a gate potential of the second transistor is anti-correlated with the potential of the second node; A first electrode of the second transistor is connected to a first power line or connected to the first level signal, and a second electrode of the second transistor is connected to the second output terminal; Preferably, the second transistor is a P-type transistor; Preferably, the first transistor is a P-type transistor; Preferably, the second output unit further includes a first capacitor, a first end of the first capacitor is connected to the gate of the second transistor, and a second end of the first capacitor is connected to the second output end; Preferably, the node voltage control module is used to control the potential of the second node to jump from a high potential to a low potential when the potential of the first node jumps from a low potential to a high potential, and the potential of the second node to jump from a low potential to a high potential when the potential of the first node jumps from a high potential to a low potential; Preferably, the node voltage control module is used to control the potentials of the first node and the second node to remain opposite.

4. The shift register according to claim 3, characterized in that: The second output unit further includes an output control subunit, the output control subunit is connected to the first node and the second node respectively, the output control subunit and the gate of the second transistor are connected to a third node, the output control subunit is used to control the potential of the third node according to the potentials of the first node and the second node, so that the potential of the third node is positively correlated with the potential of the first node, the potential of the third node includes a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; Preferably, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; Preferably, the potentials of the second node and the third node are maintained at opposite high and low potentials; Preferably, the potentials of the first node and the third node simultaneously jump from a low potential to a high potential, and / or the potentials of the first node and the third node simultaneously jump from a high potential to a low potential; Preferably, the potential of the third node further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal; Preferably, the absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the second transistor; Optionally, the output control subunit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; The gate of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second power line or connected to the second level signal, the second electrode of the third transistor is connected to the first electrode of the fifth transistor, and the second electrode of the fifth transistor is connected to the third power line or connected to the third level signal; the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the second power line or connected to the second level signal, the second electrode of the fourth transistor is connected to the first electrode of the sixth transistor, and the second electrode of the sixth transistor is connected to the third power line or connected to the third level signal; the gate of the fifth transistor is connected to the second electrode of the fourth transistor, and the gate of the sixth transistor is connected to the second electrode of the third transistor; Preferably, the voltage of the third power line is lower than the voltage of the first power line; Preferably, the third transistor and the fourth transistor are P-type transistors, and the fifth transistor and the sixth transistor are N-type transistors.

5. The shift register according to claim 3, characterized in that: The second output unit also includes an output control subunit, The output control subunit includes a first inverter, an input end of the first inverter is connected to the second node, and an output end of the first inverter and a gate of the second transistor are connected to a third node; a first end of the first inverter is connected to a second power line or connected to the second level signal, and the output control subunit is used to control the potential of the third node according to the potential of the second node; a second end of the first inverter is connected to a third power line or connected to the third level signal; Alternatively, the output control subunit includes M first inverters; M is an odd number greater than 1, the input terminal of the first inverter is connected to the second node, the output terminal of the i-th inverter is connected to the input terminal of the i+1-th inverter, and the output terminal of the M-th inverter is connected to the gate of the second transistor at a third node; i is an integer greater than or equal to 1 and less than or equal to M; The output control subunit is used to control the potential of the third node according to the potential of the second node; Alternatively, M is an even number greater than or equal to 2; the input end of the first inverter is connected to the first node, the output end of the i-th inverter is connected to the input end of the i+1-th inverter, and the output end of the M-th inverter is connected to the gate of the second transistor at a third node; the output control subunit is used to control the potential of the third node according to the potential of the first node; The first end of the first inverter is connected to the second power line or connected to the second level signal, and the second end of the Mth first inverter is connected to the third power line or connected to the third level signal; Preferably, a second end of at least one of the first inverters is connected to a first power line or is connected to the first level signal; Alternatively, the second ends of all the first inverters are connected to a third power line or connected to the third level signal; Preferably, the voltage of the third power line is lower than the voltage of the first power line; Preferably, the potential of the third node includes a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; Preferably, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; Preferably, the potentials of the second node and the third node are maintained at opposite high and low potentials; Preferably, the potentials of the first node and the third node simultaneously jump from a low potential to a high potential, and / or the potentials of the first node and the third node simultaneously jump from a high potential to a low potential; Preferably, the potential of the third node further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the first level signal; Preferably, an absolute value of a voltage difference between the third level signal and the voltage of the first power line is greater than or equal to an absolute value of a threshold voltage of the second transistor; Preferably, the first inverter comprises a fifteenth transistor and a sixteenth transistor, the gate of the fifteenth transistor and the gate of the sixteenth transistor are connected to the input terminal of the first inverter, the first electrode of the fifteenth transistor is connected to the first terminal of the first inverter, the second electrode of the fifteenth transistor and the first electrode of the sixteenth transistor are connected to the output terminal of the first inverter, and the second electrode of the sixteenth transistor is connected to the second terminal of the first inverter. Preferably, the fifteenth transistor is an N-type transistor, and the sixteenth transistor is a P-type transistor.

6. The shift register according to claim 1, characterized in that: The first output module includes a third output unit and a fourth output unit, the third output unit is connected to the first node, and is used to be turned on or off according to the potential of the first node, and output a second level signal to the first output terminal when turned on; The fourth output unit is connected to the second node, and is used to be turned on or off according to the potential of the second node, and output a first level signal to the first output terminal during at least a part of the time period when it is turned on; Preferably, effective levels of the first gate driving signal and the second gate driving signal overlap; Preferably, the effective level of the first gate driving signal is a first level signal, and the effective level of the second gate driving signal is a second level signal; Preferably, the invalid levels of the first gate driving signal and the second gate driving signal overlap; Preferably, the third output unit comprises a seventh transistor, a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to a second power line or is connected to a second level signal, and a second electrode of the seventh transistor is connected to the first output terminal; Preferably, the fourth output unit comprises an eighth transistor, the gate of the eighth transistor is connected to the second node; the first electrode of the eighth transistor is connected to the second clock signal, and the second electrode of the eighth transistor is connected to the first output terminal; Preferably, the fourth output unit further includes a second capacitor, a first end of the second capacitor is connected to the second node, and a second end of the second capacitor is connected to the first output end.

7. The shift register according to claim 1, characterized in that: The input signal includes a first clock signal, a second clock signal and a start signal; the node voltage control module includes an input unit and a first control unit, the input unit is used to turn on or off according to the first clock signal, and transmit the start signal to the second node when turned on; The first control unit is used for transmitting a first level signal or a second level signal to the first node according to the potential of the second node; Preferably, the node voltage control module further includes a second control unit, and the second control unit is used to transmit the second level signal to the second node according to the potential of the first node and the second clock signal; Preferably, the first control unit includes a second inverter; Preferably, the first clock signal, the second clock signal and the start signal respectively include first level pulses and second level pulses that are alternately arranged, and the first level pulse of the start signal overlaps with the first level pulse of the first clock signal, and does not overlap with the first level pulse of the second clock signal; Preferably, the number of first level pulses of the start signal is one or more, and the number of first level pulses of the first clock signal and the second clock signal are respectively multiple; The first output module includes a third output unit and a fourth output unit, the third output unit includes a seventh transistor, the gate of the seventh transistor is connected to the first node, the first electrode of the seventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the seventh transistor is connected to the first output terminal; the fourth output unit includes an eighth transistor, the gate of the eighth transistor is connected to the second node; the first electrode of the eighth transistor is connected to the second clock signal, and the second electrode of the eighth transistor is connected to the first output terminal; Preferably, the input unit comprises a ninth transistor, a gate of the ninth transistor is connected to the first clock signal, a first electrode of the ninth transistor is connected to the start signal, and a second electrode of the ninth transistor is connected to the second node; Preferably, the shift register further includes a tenth transistor, the second electrode of the ninth transistor is connected to the second node through the tenth transistor; the gate of the tenth transistor is connected to the first power line or connected to the first level signal; Preferably, the first control unit includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the eleventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the eleventh transistor is connected to the first node; the gate of the twelfth transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the twelfth transistor is connected to the first power line or connected to the first level signal, and the second electrode of the twelfth transistor is connected to the first node; The second control unit includes a thirteenth transistor and a fourteenth transistor, a first electrode of the thirteenth transistor is connected to the second power line or connected to the second level signal, a second electrode of the thirteenth transistor is connected to the first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected to the second electrode or the second node of the ninth transistor, one of the gate of the thirteenth transistor and the gate of the fourteenth transistor is connected to the first node, and the other is connected to the second clock signal; Preferably, the gate of the thirteenth transistor is connected to the first node, and the gate of the fourteenth transistor is connected to the second clock signal; Preferably, the eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

8. A gate drive circuit, characterized in that: Comprising a plurality of shift registers according to any one of claims 1 to 7, wherein the plurality of shift registers are cascaded; The start signal input terminal of the n+1th stage shift register is connected to the first output terminal of the nth stage shift register, wherein n is a positive integer greater than or equal to 1.

9. A display panel, characterized in that: comprising a pixel circuit and the gate driving circuit according to claim 8, The pixel circuit includes a plurality of transistors, and the first output terminal and the second output terminal of the shift register are connected to transistors of different channel types in the pixel circuit.

10. The display panel according to claim 9, characterized in that: The pixel circuit includes a driving transistor, a data writing transistor and a compensation transistor, wherein the data writing transistor is connected between a data line and a first electrode of the driving transistor, and the compensation transistor is connected between a second electrode and a gate of the driving transistor; the gate of the data writing transistor is connected to the first output terminal, and the gate of the compensation transistor is connected to the second output terminal; Preferably, the channel type of the data writing transistor is P-channel, and the channel type of the compensation transistor is N-channel; Preferably, the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, wherein the first light-emitting control transistor is connected between a fourth power line and a first electrode of the driving transistor; the second light-emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to a fifth power line; The gate of the first light emission control transistor and the gate of the second light emission control transistor are connected to a light emission control signal line; Preferably, the pixel circuit further comprises a first initialization transistor, a gate of the first initialization transistor is connected to a first scan line, a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor is connected to a gate or a second electrode of the driving transistor; Preferably, the pixel circuit further includes a second initialization transistor, a gate of the second initialization transistor is connected to a second scan line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor is connected to a first electrode of the light-emitting device.

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