Shift register, gate drive circuit and display panel

Abstract

The embodiment of the invention discloses a shift register, a gate drive circuit and a display panel, and is characterized in that a node voltage control module is arranged to control the voltage of a first node and a second node, and a first output module is arranged to output a first gate drive signal according to the voltage of the first node and the second node; and the second output module outputs a second gate driving signal according to the voltage of the first node and / or the second node, and the first gate driving signal is different from the second gate driving signal. Therefore, two different gate driving signals can be output through the same shift register, so that the frame of the display panel is reduced, and the user experience is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a shift register, a gate drive circuit and a display panel. Background Art

[0002] In some existing display panels, the pixel circuit includes both P-type transistors and N-type transistors, and two gate driving signals are required to drive the pixel circuit. If two sets of gate driving circuits are provided, the border area will be increased, affecting the user experience. Summary of the invention

[0003] The present invention provides a shift register, a gate driving circuit and a display panel, so as to output two different gate driving signals through the same gate driving circuit, reduce the border area of ​​the display panel and improve the user experience.

[0004] According to one aspect of the present invention, there is provided a shift register, comprising a node voltage control module, a first output module and a second output module, wherein the node voltage control module is connected to a first node and a second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node;

[0005] The node voltage control module is used to control the potential of the first node and the second node; the first output module is used to output a first gate drive signal through the first output terminal according to the potential of the first node and the second node; the second output module is used to output a second gate drive signal through the second output terminal according to the potential of the first node and / or the second node; the first gate drive signal and the second gate drive signal are different.

[0006] Optionally, the first gate driving signal and the second gate driving signal have different pulse widths, pulse amplitudes, and positive and negative polarities of the pulse amplitudes;

[0007] Optionally, the second gate driving signal includes a first level signal and a second level signal respectively;

[0008] Optionally, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types;

[0009] Optionally, the first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor;

[0010] The voltage of the first level signal is lower than the voltage of the second level signal; the second output module includes a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor;

[0011] Optionally, the P-type transistor included in the second output module is a polysilicon transistor;

[0012] Optionally, the first gate driving signal includes a first level signal and a second level signal;

[0013] Optionally, a pulse of the first gate driving signal overlaps with a pulse of the second gate driving signal;

[0014] Optionally, a duration of a first level signal of a pulse of the first gate driving signal is within a duration of a second level signal of a pulse of the second gate driving signal;

[0015] Optionally, the pulse width of the first gate driving signal is smaller than the pulse width of the second gate driving signal;

[0016] Optionally, the node voltage control module is connected to a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal;

[0017] Optionally, the clock signal connected to the node voltage control module includes a first clock signal and a second clock signal.

[0018] The pulse of the second clock signal overlaps with the pulse of the start signal, and the pulse of the first clock signal overlaps with the pulse of the first gate drive signal;

[0019] Optionally, a transition edge of a pulse of the first gate drive signal is aligned with a transition edge of a pulse of the first clock signal;

[0020] Optionally, a transition edge of a pulse of the second gate drive signal is aligned with a transition edge of a pulse of the second clock signal;

[0021] Optionally, a falling edge of a pulse of the first gate drive signal is aligned with a falling edge of a pulse of the first clock signal; a rising edge of a pulse of the first gate drive signal is aligned with a rising edge of a pulse of the first clock signal;

[0022] Optionally, a rising edge and a falling edge of a pulse of the second gate driving signal are respectively aligned with falling edges of two adjacent pulses of the second clock signal;

[0023] Optionally, the first clock signal and the second clock signal have the same frequency but different phases.

[0024] Optionally, the second output module includes a first output submodule and a second output submodule, the first output submodule is electrically connected to the second node, and is used to be turned on or off according to the potential of the second node, and transmits a second level signal to the second output terminal when turned on; or, the first output submodule is electrically connected to the first node, and is used to be turned on or off according to the potential of the first node, and transmits a second level signal to the second output terminal when turned on;

[0025] The second output submodule is connected to the first node and is used to transmit the first level signal to the second output terminal according to the potential of the first node; or the second output submodule is connected to the second node and is used to transmit the first level signal to the second output terminal according to the potential of the second node;

[0026] Optionally, effective levels of the first gate driving signal and the second gate driving signal overlap;

[0027] Optionally, the effective level of the first gate driving signal is a first level signal, and the effective level of the second gate driving signal is a second level signal;

[0028] Optionally, the invalid levels of the first gate driving signal and the second gate driving signal overlap;

[0029] Optionally, the node voltage control module is used to control the potential of the second node to jump from a high potential to a low potential when the potential of the first node jumps from a low potential to a high potential, and the potential of the second node to jump from a low potential to a high potential when the potential of the first node jumps from a high potential to a low potential;

[0030] Optionally, the node voltage control module is used to control the potentials of the first node and the second node to remain opposite.

[0031] Optionally, the second output submodule is connected to the first node;

[0032] Optionally, the first output submodule includes a first transistor, a gate of the first transistor is connected to the second node, a first electrode of the first transistor is connected to a second power line or is connected to a second level signal, and a second electrode of the first transistor is connected to a second output terminal;

[0033] The second output submodule includes a second transistor, a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to the first power line or connected to the first level signal, and a second electrode of the second transistor is connected to the second output terminal;

[0034] Optionally, the second transistor is a P-type transistor;

[0035] Optionally, the first transistor is a P-type transistor;

[0036] Optionally, the second output submodule further includes a first capacitor, a first end of the first capacitor is connected to the gate of the second transistor, and a second end of the first capacitor is connected to the second output end.

[0037] Optionally, the second output submodule includes an output control unit and an output unit, the output control unit is connected to the second node, the output control unit is connected to the third node, and the output unit is connected to the third node;

[0038] The output control unit is also connected to a preset clock signal, and is used to control the potential of the third node according to the potential of the second node and the preset clock signal, so that the potential of the third node is positively correlated with the potential of the first node;

[0039] Optionally, the node voltage control module is connected to the first clock signal and / or the second clock signal, and the preset clock signal includes the first clock signal or the second clock signal;

[0040] Optionally, the first output submodule includes a first transistor, the gate of the first transistor is connected to the second node, the first electrode of the first transistor is connected to the second power line or connected to the second level signal, and the second electrode of the first transistor is connected to the second output terminal; the output unit includes a third transistor, the gate of the third transistor is connected to the third node, the first electrode of the third transistor is connected to the first power line or connected to the first level signal, and the second electrode of the third transistor is connected to the second output terminal;

[0041] Optionally, the potential of the third node includes a third level signal, and a voltage of the third level signal is lower than a voltage of the first power line;

[0042] Optionally, an absolute value of a voltage difference between the third level signal and the first level signal is greater than or equal to an absolute value of a threshold voltage of the third transistor;

[0043] Optionally, the third transistor is a P-type transistor;

[0044] Optionally, the first transistor is a P-type transistor;

[0045] Optionally, the second output submodule further includes a first capacitor, a first end of the first capacitor is connected to the gate of the third transistor, and a second end of the first capacitor is connected to the second output end;

[0046] Optionally, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential;

[0047] Optionally, the potentials of the second node and the third node are kept opposite to each other;

[0048] Optionally, the potentials of the first node and the third node jump from a low potential to a high potential at the same time, and / or, the potentials of the first node and the third node jump from a high potential to a low potential at the same time;

[0049] Optionally, the potential of the third node further includes a second level signal, and a voltage of the third level signal is lower than a voltage of the second level signal;

[0050] Optionally, an absolute value of a voltage difference between the third level signal and the voltage of the first power line is greater than or equal to an absolute value of a threshold voltage of the second transistor.

[0051] Optionally, the output control unit includes a charge and discharge control subunit, a coupling subunit and a unidirectional conduction subunit;

[0052] The charge and discharge control subunit is connected to the second node, the first end of the coupling subunit, and the second end of the coupling subunit respectively, the second end of the coupling subunit is connected to the first end of the unidirectional conduction subunit, and the second end of the unidirectional conduction subunit is connected to the third node;

[0053] The charge and discharge control subunit is used to charge and / or discharge the coupling subunit according to the potential of the second node and the preset clock signal; the coupling subunit is used to couple the potential change of its first end to the second end; the unidirectional conduction subunit is used to conduct when the potential of the first end of the unidirectional conduction subunit is lower than the potential of the third node;

[0054] Optionally, the charge and discharge control subunit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the second power line or connected to the second level signal, and the second electrode of the fourth transistor is connected to the first end of the coupling subunit; the gate of the fifth transistor is connected to the second end of the coupling subunit, the first electrode of the fifth transistor is connected to the preset clock signal, and the second electrode of the fifth transistor is connected to the first end of the coupling subunit;

[0055] Optionally, the coupling subunit includes a second capacitor, a first electrode plate of the second capacitor serves as a first end of the coupling subunit, and a second electrode plate of the second capacitor serves as a second end of the coupling subunit;

[0056] Optionally, the second capacitance is greater than the first capacitance;

[0057] Optionally, the unidirectional conducting sub-unit includes a sixth transistor, the gate of the sixth transistor is connected to the first electrode of the sixth transistor, the gate of the sixth transistor is connected to the second end of the coupling sub-unit, and the second electrode of the sixth transistor is connected to the third node;

[0058] Optionally, the sixth transistor is a P-type transistor.

[0059] Optionally, the first output module includes a third output submodule and a fourth output submodule, the third output submodule is connected to the first node, and is used to be turned on or off according to the potential of the first node, and output the second level signal to the first output terminal when turned on; the fourth output submodule is connected to the second node, and is used to be turned on or off according to the potential of the second node, and output the first clock signal to the first output terminal when turned on;

[0060] Optionally, the third output submodule includes a seventh transistor, a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the second power line or connected to the second level signal, and a second electrode of the seventh transistor is connected to the first output terminal;

[0061] Optionally, the fourth output submodule includes an eighth transistor, a gate of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first clock signal, and a second electrode of the eighth transistor is connected to the first output terminal;

[0062] Optionally, the seventh transistor is a P-type transistor, and the eighth transistor is a P-type transistor;

[0063] Optionally, the fourth output submodule further includes a third capacitor, a first end of the third capacitor is connected to the second node, and a second end of the third capacitor is connected to the first output end.

[0064] Optionally, the node voltage control module includes an input unit and a first control unit, the input unit is used to be turned on or off according to the second clock signal, and transmit a start signal to the second node when turned on;

[0065] The first control unit is used for transmitting a first level signal or a second level signal to the first node according to the potential of the second node;

[0066] Optionally, the node voltage control module further includes a second control unit, the second control unit being configured to transmit a second level signal to the second node according to the potential of the first node and the first clock signal;

[0067] Optionally, the first clock signal, the second clock signal, and the start signal respectively include first level pulses and second level pulses that are alternately arranged, and the first level pulse of the start signal overlaps with the first level pulse of the second clock signal, and does not overlap with the first level pulse of the first clock signal;

[0068] Optionally, the number of first level pulses of the start signal is one or more, and the number of first level pulses of the first clock signal and the second clock signal are respectively multiple;

[0069] Optionally, the input unit includes a ninth transistor, a gate of the ninth transistor is connected to the first clock signal, a first electrode of the ninth transistor is connected to the start signal, and a second electrode of the ninth transistor is connected to the second node;

[0070] Optionally, the shift register further includes a tenth transistor, the second electrode of the ninth transistor is connected to the second node through the tenth transistor; the gate of the tenth transistor is connected to the first power line or connected to the first level signal;

[0071] Optionally, the first control unit includes an inverter;

[0072] Optionally, the first control unit includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the eleventh transistor is connected to the second power line or is connected to the second level signal, and the second electrode of the eleventh transistor is connected to the first node; the gate of the twelfth transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the twelfth transistor is connected to the first power line or is connected to the first level signal, and the second electrode of the twelfth transistor is connected to the first node;

[0073] The second control unit includes a thirteenth transistor and a fourteenth transistor, a first electrode of the thirteenth transistor is connected to the second power line or the second level signal, a second electrode of the thirteenth transistor is connected to the first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected to the second electrode or the second node of the ninth transistor, one of the gate of the thirteenth transistor and the gate of the fourteenth transistor is connected to the first node, and the other is connected to the first clock signal;

[0074] Optionally, the gate of the thirteenth transistor is connected to the first node; the gate of the fourteenth transistor is connected to the first clock signal;

[0075] Optionally, the eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

[0076] In the second aspect, an embodiment of the present invention further provides a gate drive circuit, which includes multiple shift registers of any embodiment of the present invention, and the multiple shift registers are cascaded; the start signal input terminal of the n+1th stage shift register is connected to the first output terminal of the nth stage shift register, where n is a positive integer greater than or equal to 1.

[0077] In a third aspect, an embodiment of the present invention further provides a display panel, the display panel comprising a pixel circuit and a gate driving circuit of any embodiment of the present invention,

[0078] The pixel circuit includes a plurality of transistors, and the first output terminal and the second output terminal of the shift register are connected to transistors of different channel types in the pixel circuit.

[0079] Optionally, the pixel circuit includes a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is connected between the data line and the first electrode of the driving transistor, and the compensation transistor is connected between the second electrode and the gate of the driving transistor; the gate of the data writing transistor is connected to the first output terminal, and the gate of the compensation transistor is connected to the second output terminal;

[0080] Optionally, the channel type of the data writing transistor is a P channel, and the channel type of the compensation transistor is an N channel;

[0081] Optionally, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor is connected between the fourth power line and the first electrode of the driving transistor; the second light-emitting control transistor is connected between the second electrode of the driving transistor and the first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to the fifth power line; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to the light-emitting control signal line;

[0082] Optionally, the pixel circuit further includes a first initialization transistor, a gate of the first initialization transistor is connected to the first scan line, a first electrode of the first initialization transistor is connected to the first initialization signal line, and a second electrode of the first initialization transistor is connected to the gate or the second electrode of the driving transistor;

[0083] Optionally, the pixel circuit further includes a second initialization transistor, a gate of the second initialization transistor is connected to the second scan line, a first electrode of the second initialization transistor is connected to the second initialization signal line, and a second electrode of the second initialization transistor is connected to the first electrode of the light-emitting device.

[0084] The shift register, gate drive circuit and display panel of the embodiment of the present invention are provided with a node voltage control module to control the voltage of the first node and the second node, the first output module outputs the first gate drive signal according to the voltage of the first node and the second node, and the second output module outputs the second gate drive signal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different. In this way, two different gate drive signals can be output through the same shift register, for example, the driving requirements of the pixel circuit including both P-type transistors and N-type transistors can be met, and the border of the display panel can be reduced to improve the user experience.

[0085] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0087] Figure 1 is a structural schematic diagram of a shift register provided by an embodiment of the present invention;

[0088] Figure 2is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0089] Figure 3 It is a structural schematic diagram of a pixel circuit in the related art;

[0090] Figure 4 is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0091] Figure 5 is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0092] Figure 6 When the potential at the second node is a second level signal Figure 5 Equivalent circuit diagram of the output control unit;

[0093] Figure 7 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0094] Figure 8 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0095] Fig. 9 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0096] Fig.10 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0097] Fig.11 is a schematic structural diagram of another shift register provided by an embodiment of the present invention;

[0098] Fig.12 is a working timing diagram of a shift register provided by an embodiment of the present invention;

[0099] Fig.13 is a working timing diagram of another shift register provided by an embodiment of the present invention;

[0100] Fig.14 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0101] Fig.15 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0102] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0103] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The connection may include a direct connection or an indirect connection. The connection may include an electrical connection.

[0104] An embodiment of the present invention provides a shift register, Figure 1 is a schematic diagram of a structure of a shift register provided by an embodiment of the present invention, with reference to Figure 1 The shift register includes a node voltage control module 110, a first output module 120 and a second output module 130, the node voltage control module 110 is connected to the first node N1 and the second node N2, the first output module 120 is connected to the first node N1 and the second node N2, and the second output module 130 is connected to the first node N1 and / or the second node N2; the node voltage control module 110 is used to control the potential of the first node N1 and the second node N2; the first output module 120 is used to output a first gate driving signal through the first output terminal OUT1 according to the potential of the first node N1 and the second node N2; the second output module 130 is used to output a second gate driving signal through the second output terminal OUT2 according to the potential of the first node N1 and / or the second node N2; the first gate driving signal and the second gate driving signal are different.

[0105] The node voltage control module 110 may be connected to an input signal, and the number of input signals may be multiple. For example, the input signal includes but is not limited to a start signal and one or at least two clock signals. The node voltage control module 110 transmits corresponding voltages to the first node N1 and the second node N2 respectively in different working periods of the shift register according to the input signal. The first node N1 and the second node N2 have different potentials in at least part of the time period, for example, opposite potentials, or opposite highs and lows, or opposite positive and negative polarities, etc.

[0106] The first output module 120 is connected to the first node N1 and the second node N2 respectively. The first output module 120 can output a first gate drive signal to the first output terminal OUT1 of the shift register according to the potentials of the first node N1 and the second node N2, wherein the first gate drive signal includes a first level signal and a second level signal. Specifically, in a part of the working period, the first gate drive signal is a first level signal; in another part of the working period, the first gate drive signal is a second level signal. The first gate drive signal is used to drive a transistor of the first channel type.

[0107] The second output module 130 is connected to the first node N1 and / or the second node N2, and the second output module 130 can output a second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1 and / or the second node N2, wherein the second gate drive signal includes a first level signal and a second level signal. In some embodiments, the second output module 130 is connected to the first node N1, and the second output module 130 outputs the second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1. In other embodiments, the second output module 130 is connected to the second node N2 ( Figure 1 ), the second output module 130 outputs the second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the second node N2. In other embodiments, the second output module 130 is connected to the first node N1 and the second node N2, respectively, and the second output module 130 outputs the second gate drive signal to the second output terminal OUT2 of the shift register according to the potential of the first node N1 and the second node N2. Specifically, in a part of the working period, the second gate drive signal is a first level signal; in another part of the working period, the second gate drive signal is a second level signal. Among them, the second gate drive signal is used to drive a transistor of the second channel type. The first channel type is P channel, and the second channel type is N channel, or the first channel type is N channel, and the second channel type is P channel. The gate drive signals of two channel type transistors can be driven simultaneously through the same shift register output, and there is no need to set different gate drive circuits for each channel type transistor, which can reduce the border of the display panel.

[0108] The shift register of this embodiment is provided with a node voltage control module to control the voltage of the first node and the second node, the first output module outputs the first gate drive signal according to the voltage of the first node and the second node, and the second output module outputs the second gate drive signal according to the voltage of the first node and / or the second node, and the first gate drive signal and the second gate drive signal are different. In this way, two different gate drive signals can be output through the same shift register, for example, the driving requirements of the pixel circuit including both P-type transistors and N-type transistors can be met, and the border of the display panel can be reduced to improve the user experience.

[0109] Optionally, one or more of the pulse width, pulse amplitude, and positive and negative polarity of the pulse amplitude of the first gate drive signal and the second gate drive signal are different; and / or the first gate drive signal and the second gate drive signal are used to drive transistors of different channel types. In this way, the first gate drive signal and the second gate drive signal can drive different transistors, for example, drive transistors that are turned on in different working stages in the pixel circuit of the display panel, and / or drive transistors of different channel types, so as to meet the driving requirements of the pixel circuit and reduce the border of the display panel.

[0110] As described in the above embodiments, the first gate drive signal includes a first level signal and a second level signal; the second gate drive signal includes a first level signal and a second level signal. In some optional embodiments of the present invention, the first gate drive signal is used to drive a P-type transistor, and the second gate drive signal is used to drive an N-type transistor; the voltage of the first level signal is lower than the voltage of the second level signal; the second output module 130 includes a P-type transistor, and the second output module 130 is used to output the first level signal through the P-type transistor.

[0111] Specifically, in the related art, the first level signal in the second gate drive signal is output through an N-type oxide transistor. Since the mobility of the oxide transistor is low, when the transistor characteristics fluctuate under stress, the output waveform stability of the second gate drive signal is poor, which reduces the reliability of the gate drive circuit. In this embodiment, the second output module 130 is provided to include a P-type transistor, and the first level signal is output through the P-type transistor, wherein the P-type transistor included in the second output module 130 may be a polysilicon transistor, such as a low-temperature polysilicon transistor. Compared with the N-type oxide transistor, the P-type transistor has a higher mobility, which can improve the output stability of the second gate drive signal and improve the reliability of the gate drive circuit.

[0112] Figure 2 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 2Optionally, the second output module 130 includes a first output submodule 131 and a second output submodule 132, the first output submodule 131 is electrically connected to the second node N2, and the first output submodule 131 is used to control the potential of the second output terminal OUT2 according to the potential of the second node N2, for example, the first output submodule 131 is used to turn on or off according to the potential of the second node N2, and transmit the second level signal VGH to the second output terminal OUT2 when turned on; or, the first output submodule 131 is electrically connected to the first node N1, and is used to turn on or off according to the potential of the first node N1, and transmit the second level signal VGL to the second output terminal OUT2 when turned on. The second output submodule 132 is connected to the first node N1, and the second output submodule 132 is used to control the potential of the second output terminal OUT2 according to the potential of the first node N1, for example, the second output submodule 132 is used to transmit the first level signal VGL to the second output terminal OUT2 according to the potential of the first node N1; the second output submodule 131 is connected to the second node N2, and the second output submodule 132 is used to control the potential of the second output terminal OUT2 according to the potential of the second node N2, for example, the second output submodule 132 is used to transmit the first level signal VGL to the second output terminal OUT2 according to the potential of the second node N2.

[0113] Specifically, in the second output module 130, the first output submodule 131 can control whether the voltage of the second power line and / or the second level signal VGH are output to the second output terminal OUT2, and the second output submodule 132 can control whether the voltage of the first power line and / or the first level signal VGL are output to the second output terminal OUT2. For example, the conduction period of the first output submodule 131 and the conduction period of the second output submodule 132 are at least partially different. For example, the first output submodule 131 and the second output submodule 132 are turned on in time division. Optionally, at least in part of the time period (for example, in the stable working state of the shift register, for example, after the t1 stage), the node voltage control module 110 is used to control the potentials of the first node N1 and the second node N2 to remain opposite, that is, when the first node N1 is at a high potential, the second node N2 is at a low potential; when the first node N1 is at a low potential, the second node N2 is at a high potential. Specifically, at least in part of the time period (for example, in the stable working state of the shift register, for example, after the t1 stage), the node voltage control module 110 is used to control the potential of the second node N2 to jump from a high potential to a low potential when the potential of the first node N1 jumps from a low potential to a high potential, and the potential of the second node N2 to jump from a low potential to a high potential when the potential of the first node N1 jumps from a high potential to a low potential. The first output submodule 131 and the second output submodule 132 each include at least one switching element, which can be a transistor. The first output submodule 131 is connected to the second node N2, and the node voltage control module 110 controls the conduction state of the first output submodule 131 by controlling the potential of the second node N2, thereby controlling whether the second level signal VGH is output to the second output terminal OUT2. The first output submodule 131 can be used to control the potential of the second output terminal OUT2 according to the potential of the second node N2. Optionally, the first output submodule 131 includes a first transistor T1, a gate of the first transistor T1 is connected to the second node N2, a first electrode of the first transistor T1 is connected to the second power line or connected to the second level signal VGH, and a second electrode of the first transistor T1 is connected to the second output terminal OUT2. The low potential jumps to the high potential can be a rising edge, and the high potential jumps to the low potential can be a falling edge.

[0114] In some embodiments, the second output submodule 132 is connected to the first node N1, and controls the transmission of the first level signal VGL to the second output terminal OUT2 according to the potential of the first node N1, and the second output submodule 132 can be used to control the potential of the second output terminal OUT2 according to the potential of the first node N1; in other embodiments, the second output submodule 132 is connected to the second node N2, and controls the transmission of the first level signal VGL to the second output terminal OUT2 according to the potential of the second node N2, and the second output submodule 132 can be used to control the potential of the second output terminal OUT2 according to the potential of the second node N2. In the case where the second output submodule 132 is connected to the first node N1, the second output submodule 132 includes a second transistor T2, the gate of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power line or the first level signal VGL, and the second electrode of the second transistor T2 is connected to the second output terminal OUT2.

[0115] Optionally, the second transistor T2 is a P-type transistor, so that the second output module 130 outputs the first level signal VGL through the P-type transistor, ensuring the stability of the first level signal VGL in the second gate drive signal output by the shift register, which is beneficial to improving the display effect.

[0116] For example, the switching states of the second transistor T2 and the first transistor T1 are opposite. For example, when the second transistor T2 changes from on to off, the first transistor T1 changes from off to on. For example, when the second transistor T2 changes from off to on, the first transistor T1 changes from on to off.

[0117] In some optional embodiments of the present invention, the first transistor T1 is a P-type transistor, so that the second output module 130 outputs the second level signal VGH through the P-type transistor, ensuring the stability of the second level signal VGH in the second gate drive signal output by the shift register, which is beneficial to improving the display effect.

[0118] Optionally, the second output submodule 132 further includes a first capacitor C1 , a first end of the first capacitor C1 is connected to the gate of the second transistor T2 , and a second end of the first capacitor C1 is connected to the second output end OUT2 .

[0119] In some embodiments, effective levels of the first gate driving signal and the second gate driving signal overlap.

[0120] The effective level of the first gate drive signal is a level that can turn on the driven transistor, and the invalid level of the first gate drive signal is a level that can turn off the driven transistor. The effective level of the second gate drive signal is a level that can turn on the driven transistor, and the invalid level of the second gate drive signal is a level that can turn off the driven transistor.

[0121] Optionally, the effective level of the first gate driving signal is a first level signal VGL, and the effective level of the second gate driving signal is a second level signal VGH. In some optional embodiments, the ineffective levels of the first gate driving signal and the second gate driving signal overlap.

[0122] When the first gate drive signal is used to drive a P-type transistor and the second gate drive signal is used to drive an N-type transistor, the first level signal VGL is a low level signal and the second level signal VGH is a high level signal; when the first gate drive signal is used to drive an N-type transistor and the second gate drive signal is used to drive a P-type transistor, the first level signal VGL is a high level signal and the second level signal VGH is a low level signal.

[0123] The first gate driving signal and the second gate driving signal output by the shift register can be used to drive different transistors in the pixel circuit. Figure 3 This is a schematic diagram of a pixel circuit structure in the related art, refer to Figure 3 The pixel circuit includes a driving transistor DT, a data writing transistor M1 and a compensation transistor M2. The data writing transistor M1 is connected between the data line Data and the first electrode of the driving transistor DT, and the compensation transistor M2 is connected between the second electrode and the gate of the driving transistor DT. The first output terminal OUT1 of the shift register can be connected to the data writing transistor M1 in the pixel circuit, and the second output terminal OUT2 can be connected to the compensation transistor M2 in the pixel circuit. The effective level of the first gate driving signal Scan1 is the level that turns on the data writing transistor M1, and the second gate driving signal Scan2 is the level that turns on the compensation transistor M2. By setting the effective level of the first gate driving signal output by the shift register to overlap with the effective level of the second gate driving signal, the data writing transistor M1 and the compensation transistor M2 can be turned on at the same time during the overlapping period of the first gate driving signal and the effective level and the effective level of the second gate driving signal, thereby completing the writing of the data voltage on the data line to the gate of the driving transistor DT.

[0124] In some embodiments, the data write transistor M1 is a P-type transistor, and the compensation transistor M2 is an N-type transistor. That is, the channel type of the data write transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel. Optionally, the P-type transistor in the pixel circuit is a polysilicon transistor, such as a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. Accordingly, the display panel is a display panel of a low-temperature polycrystalline oxide (LTPO) process. In some embodiments, the P-type transistor in the shift register is a polysilicon transistor, a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. That is, the shift register of this embodiment can be used to drive a display panel of an LTPO process, which is conducive to ensuring higher smoothness and lower power consumption of the display panel.

[0125] Optionally, the pixel circuit further includes a first light-emitting control transistor M3 and a second light-emitting control transistor M4, wherein the first light-emitting control transistor M3 is connected between the fourth power line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, and the second electrode of the light-emitting device D1 is connected to the fifth power line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM;

[0126] Optionally, the pixel circuit further includes a first initialization transistor M5, a gate of the first initialization transistor M5 is connected to the first scan line Sn1, a first electrode of the first initialization transistor M5 is connected to the first initialization signal line Vref1, and a second electrode of the first initialization transistor M5 is connected to the gate of the driving transistor DT;

[0127] Optionally, the pixel circuit further includes a second initialization transistor M6, a gate of the second initialization transistor M6 is connected to the second scan line Sn2, a first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and a second electrode of the second initialization transistor M6 is connected to the first electrode of the light emitting device D1.

[0128] Optionally, the pixel circuit further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and a second end of the storage capacitor Cst is connected to a fourth power line VDD.

[0129] Figure 2The shift register shown shows that the second output module 130 is connected to the first node N1 and the second node N2 respectively. In some other optional embodiments of the present invention, the second output module 130 can be connected to the first node N1 but not to the second node N2. In other optional embodiments of the present invention, the second output module 130 can be connected to the second node N2 but not to the first node N1.

[0130] Figure 4 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 4 , the shift register may correspond to the case where the second output submodule 132 is connected to the second node N2. Optionally, the second output submodule 132 includes an output control unit 1321 and an output unit 1322, the output control unit 1321 is connected to the second node N2, the output control unit 1321 is connected to the third node N3, and the output unit 1322 is connected to the third node N3; the output control unit 1321 is also connected to a preset clock signal, and the output control unit 1321 is used to control the potential of the third node N3 according to the potential of the second node N2 and the preset clock signal, so that at least in part of the time period (for example, in the stable working state of the shift register, such as after the t1 stage), the potential of the third node N3 is positively correlated with the potential of the first node N1, and / or the potential of the third node N3 is anti-correlated with the potential of the second node N2.

[0131] For example, the node voltage control module 110 receives the first clock signal and / or the second clock signal. The preset clock signal includes the first clock signal CK1 ( Figure 4 ) or a second clock signal.

[0132] Optionally, the potential of the third node N3 includes a third level signal, and a voltage of the third level signal is lower than a voltage of the first power line.

[0133] In which, at least in a partial period (for example, in a stable working state of the shift register, for example, after stage t1), the potential of the third node N3 is positively correlated with the potential of the first node N1, that is, the potential of the third node N3 and the potential of the first node N1 are both high potential and low potential at the same time. The potentials of the first node N1 and the third node N3 jump from a low potential to a high potential at the same time, and / or the potentials of the first node N1 and the third node N3 jump from a high potential to a low potential at the same time.

[0134] Optionally, at least in a partial period (e.g., when the shift register is in a stable working state, such as after stage t1), the potential of the third node N3 is inversely correlated with the potential of the second node N2, that is, when the potential of the second node N2 jumps from a low potential to a high potential, the potential of the third node N3 jumps from a high potential to a low potential; when the potential of the second node N2 jumps from a high potential to a low potential, the potential of the second node N2 jumps from a low potential to a high potential. Optionally, the potentials of the second node N2 and the third node N3 remain opposite.

[0135] Specifically, the output control unit 1321 controls the potential of the third node N3 to be positively correlated with the potential of the first node N1 according to the potential of the second node N2 and the preset clock signal CK1. Since the node voltage control module 110 can control the potential of the first node N1 to be opposite to the potential of the second node N2, accordingly, through the control of the output control module, the potential of the third node N3 can be opposite to the potential of the second node N2. In this way, it is convenient to control the time-sharing conduction of the first output sub-module 131 and the output unit 1322, so as to realize that when the first output sub-module 131 is turned on, the output unit 1322 is turned off, and the second level signal VGH is transmitted to the second output terminal OUT2; when the output unit 1322 is turned on, the first output sub-module 131 is turned off, and the first level signal VGL is transmitted to the second output terminal OUT2.

[0136] Optionally, the first output submodule 131 includes a first transistor T1, the gate of the first transistor T1 is connected to the second node N2, and / or the gate potential of the first transistor T1 is positively correlated with the potential of the second node N2, and / or the gate potential of the first transistor T1 is negatively correlated with the potential of the first node N1, the first electrode of the first transistor T1 is connected to the second power line or connected to the second level signal VGH, and the second electrode of the first transistor T1 is connected to the second output terminal OUT2; the output unit 1322 includes a third transistor T3, the gate of the third transistor T3 is connected to the third node N3, and / or the gate potential of the third transistor T3 is negatively correlated with the potential of the second node N2, and / or the gate potential of the third transistor T3 is positively correlated with the potential of the first node N1, the first electrode of the third transistor T3 is connected to the first power line or the first level signal VGL, and the second electrode of the third transistor T3 is connected to the second output terminal OUT2.

[0137] Optionally, the output control unit 1321 is used to control the potential of the third node N3 to be a third level signal according to the potential of the second node N2 and a preset clock signal when the potential of the first node N1 is the first level signal VGL, and the voltage of the third level signal is lower than the voltage of the first level signal VGL.

[0138] Specifically, under the control of the node voltage control module 110, the potential of the first node N1 is opposite to the potential of the second node N2. When the potential of the first node N1 is the first level signal VGL, the potential of the second node N2 is the second level signal VGH. When the potential of the second node N2 is the second level signal VGH, the output control unit 1321 controls the potential of the third node N3 to be a third level signal lower than the first level signal VGL according to the first clock signal CK1, so that the gate of the third transistor T3 is the third level signal, and the first pole of the third transistor T3 is the first level signal VGL. The absolute value of the voltage difference between the gate and the first pole of the third transistor T3 is large, so that the turn-on state of the third transistor T3 is better, ensuring that the first level signal VGL connected to the first pole of the third transistor T3 can be transmitted to the second output terminal OUT2 with equal amplitude, improving the stability of the output of the third transistor T3, ensuring that the turn-on or turn-off state of the transistor driven by the second gate drive signal is better, which is conducive to improving the display effect. Exemplarily, when the transistor driven by the second gate drive signal is an N-type transistor, and the first level signal VGL is a low level signal and the second level signal VGH is a high level signal, the N-type transistor driven by the second gate drive signal can be completely turned off under the action of the first level signal VGL in the second gate drive signal.

[0139] Optionally, the potential of the third node N3 further includes a second level signal, the voltage of the third level signal is lower than the voltage of the second level signal, and / or the voltage of the third level signal is lower than the voltage of the first power line.

[0140] In some optional embodiments of the present invention, the absolute value of the voltage difference between the third level signal and the voltage of the first power line is greater than or equal to the absolute value of the threshold voltage of the third transistor T3. In this way, it can be ensured that when the potential of the third node N3 is the third level signal, the third transistor T3 can be fully turned on, and further ensured that when the third transistor T3 is turned on, the first level signal VGL can be transmitted to the second output terminal OUT2 with equal amplitude, thereby improving the display effect.

[0141] Optionally, the third transistor T3 is a P-type transistor, so that the second output module 130 outputs the first level signal VGL through the P-type transistor, ensuring the stability of the first level signal VGL in the second gate driving signal output by the shift register, which is beneficial to improving the display effect.

[0142] Optionally, the first transistor T1 is a P-type transistor, so that the second output module 130 outputs the second level signal VGH through the P-type transistor, ensuring the stability of the second level signal VGH in the second gate driving signal output by the shift register, which is beneficial to improving the display effect.

[0143] Optionally, the second output submodule 132 further includes a first capacitor C1 , a first end of the first capacitor C1 is connected to the gate of the third transistor T3 , and a second end of the first capacitor C1 is connected to the second output end OUT2 .

[0144] Figure 5 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 5 Optionally, the output control unit 1321 includes a charge and discharge control subunit 1322, a coupling subunit 1323 and a unidirectional conduction subunit 1324; the charge and discharge control subunit 1322 is respectively connected to the second node N2, the first end of the coupling subunit 1323, and the second end of the coupling subunit 1323, the second end of the coupling subunit 1323 is connected to the first end of the unidirectional conduction subunit 1324, and the second end of the unidirectional conduction subunit 1324 is connected to the third node N3; the charge and discharge control subunit 1322 is used to charge and / or discharge the coupling subunit 1323 according to the potential of the second node N2 and a preset clock signal; the coupling subunit 1323 is used to couple the potential change of its first end to the second end; the unidirectional conduction subunit 1324 is used to be turned on when the potential of the first end of the unidirectional conduction subunit 1324 is lower than the potential of the third node N3.

[0145] The preset clock signal is a periodic signal, and the preset clock signal includes a first level signal VGL pulse and a second level signal VGH pulse that are alternately set. Specifically, when the potential of the second node N2 is the first level signal VGL, the charge and discharge control subunit 1322 transmits the second level signal VGH to the first end of the coupling subunit 1323, so that the potential of the first end of the coupling subunit 1323 rises. Due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 is pulled up, and the unidirectional conduction subunit 1324 is turned off. When the potential of the second node N2 is the second level signal VGH, the charge and discharge control subunit 1322 alternately charges and discharges the coupling subunit 1323 according to the high and low potential jumps of the preset clock signal. Exemplarily, when the potential of the second node N2 is the second level signal VGH and the preset clock signal jumps from a high level to a low level, the coupling subunit 1323 discharges, and the potential of the first end of the coupling subunit 1323 decreases. Due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 is pulled down, the unidirectional conductive subunit 1324 is turned on, and the potential of the third node N3 is pulled down, so that the potential of the third node N3 is lower than the first level signal VGL, and the output unit 1322 is turned on to transmit the first level signal VGL to the second output terminal OUT2 with equal amplitude. When the potential of the second node N2 is the second level signal VGH and the preset clock signal jumps from a low level to a high level, the coupling subunit 1323 is charged, and the potential of the first end of the coupling subunit 1323 increases. Due to the coupling effect of the coupling subunit 1323 itself, the potential of the second end of the coupling subunit 1323 increases, and the unidirectional conductive subunit 1324 is turned off. The third node N3 still maintains a low potential, so that the potential of the third node N3 is lower than the first level signal VGL, and the output unit 1322 is turned on, and the first level signal VGL is transmitted to the second output terminal OUT2 with equal amplitude.

[0146] Continue to refer Figure 5 Optionally, the charge and discharge control subunit 1322 includes a fourth transistor T4 and a fifth transistor T5, the gate of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second power line or connected to the second level signal VGH, and the second electrode of the fourth transistor T4 is connected to the first end of the coupling subunit 1323; the gate of the fifth transistor T5 is connected to the second end of the coupling subunit 1323, the first electrode of the fifth transistor T5 is connected to the preset clock signal, and the second electrode of the fifth transistor T5 is connected to the first end of the coupling subunit 1323.

[0147] The channel types of the fourth transistor T4 and the fifth transistor T5 may be the same. The fourth transistor T4 may include a P-type transistor. The fifth transistor T5 may include a P-type transistor.

[0148] Optionally, the coupling subunit 1323 includes a second capacitor C2 , a first electrode plate of the second capacitor C2 serves as a first end of the coupling subunit 1323 , and a second electrode plate of the second capacitor C2 serves as a second end of the coupling subunit 1323 .

[0149] Optionally, the second capacitor C2 is larger than the first capacitor C1. In this way, the coupling effect of the first capacitor C1 can be reduced, thereby avoiding the gate drive signal waveform output from the second output terminal OUT2 from having a long transition time and tilting due to the first capacitor C1 being too large, thereby improving the output signal reliability.

[0150] Optionally, the unidirectional conducting subunit 1324 includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to a first electrode of the sixth transistor T6, a gate of the sixth transistor T6 is connected to a second end of the coupling subunit 1323, and a second electrode of the sixth transistor T6 is connected to a third node N3.

[0151] The sixth transistor T6 may include a P-type transistor. The channel type of the sixth transistor T6 and the fifth transistor T5 may be the same. The channel type of the sixth transistor T6 and the fourth transistor T4 may be the same.

[0152] Figure 6 When the potential at the second node is a second level signal Figure 5 The equivalent circuit diagram of the output control unit in Figure 5 and Figure 6, when the potential of the second node N2 is the first level signal VGL, the fourth transistor T4 is turned on, and the second level signal VGH is transmitted to the second electrode of the fourth transistor T4 and the first end of the coupling subunit 1323, wherein the connection point between the second electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5 and the first end of the coupling subunit 1323 is recorded as the fourth node N4, so when the second node N2 is the first level signal VGL, the fourth node N4 is the second level signal VGH. The potential of the first end of the second capacitor C2 is pulled up, and due to the coupling effect of the second capacitor C2, the potential of the second end of the second capacitor C2 (recorded as the fifth node N5) is also pulled up, so that the sixth transistor T6 is turned off. When the potential of the second node N2 is the second level signal VGH, the fourth transistor T4 is turned off. When the preset clock signal is the first clock signal CK1, when the first clock signal CK1 jumps from a high level to a low level, the fifth transistor T5 is turned on, and the low-level first clock signal CK1 is transmitted to the fourth node N4, and the second capacitor C2 is discharged. Due to the coupling effect of the second capacitor C2, the potential of the second end of the first capacitor C1 (the fifth node N5) is pulled down, so that the potential of the second end of the first capacitor C1 is lower than the potential of the third node N3, the sixth transistor T6 is turned on, and the potential of the third node N3 is lower than the first level signal VGL, and the output unit 1322 is turned on, and the first level signal VGL is transmitted to the second output terminal OUT2 with equal amplitude. When the first clock signal CK1 jumps from a low level to a high level, the fifth transistor T5 is turned on, and the high-level first clock signal CK1 is transmitted to the fourth node N4 to charge the second capacitor C2. Due to the coupling effect of the second capacitor C2, the potential of the second end (fifth node N5) of the second capacitor C2 increases, the unidirectional conducting sub-unit 1324 is turned off, and the third node N3 still maintains a low potential, so that the potential of the third node N3 is still lower than the first level signal VGL, and the output unit 1322 is turned on, and the first level signal VGL is transmitted to the second output terminal OUT2 with equal amplitude.

[0153] Optionally, the unidirectional conducting subunit 1324 includes a diode, a cathode of the diode is connected to the second end of the coupling subunit 1323, and an anode of the diode is connected to the third node N3;

[0154] Figure 7 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 7Optionally, the first output module 120 includes a third output submodule 121 and a fourth output submodule 122, the third output submodule 121 is connected to the first node N1, and the third output submodule 121 is used to control the potential of the first output terminal OUT1 according to the potential of the first node N1, for example, the third output submodule 121 is used to turn on or off according to the potential of the first node N1, and output the second level signal VGH to the first output terminal OUT1 when turned on; the fourth output submodule 122 is connected to the second node N2, and the fourth output submodule 122 is used to control the potential of the first output terminal OUT1 according to the potential of the second node N2, for example, the fourth output submodule 122 is used to turn on or off according to the potential of the second node N2, and output the first clock signal CK1 to the first output terminal OUT1 when turned on.

[0155] The third output submodule 121 and the fourth output submodule 122 respectively include at least one switch device, which may be a transistor. By setting the first output module 120 to include the third output submodule 121 and the fourth output submodule 122, the third output submodule 121 and the fourth output submodule 122 can be turned on in time division. When the third output submodule 121 is turned on, the third output submodule 121 outputs the second level signal VGH to the first output terminal OUT1; when the fourth output submodule 122 is turned on, the fourth output submodule 122 outputs the first clock signal CK1 to the first output terminal OUT1.

[0156] Optionally, the third output submodule 121 includes a seventh transistor T7, the gate of the seventh transistor T7 is connected to the first node N1, the first electrode of the seventh transistor T7 is connected to the second power line or connected to the second level signal VGH, and the second electrode of the seventh transistor T7 is connected to the first output terminal OUT1; optionally, the seventh transistor is a P-type transistor. In this way, the first output module 120 outputs the second level signal VGH through the P-type transistor, which is conducive to improving output stability.

[0157] Optionally, the fourth output submodule 122 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the second node N2, the first electrode of the eighth transistor T8 is connected to the first clock signal CK1, and the second electrode of the eighth transistor T8 is connected to the first output terminal OUT1. Optionally, the eighth transistor T8 is a P-type transistor. In this way, the first output module 120 outputs the first level signal VGL through the P-type transistor, which is conducive to improving output stability.

[0158] Optionally, the fourth output submodule 122 further includes a third capacitor C3, a first end of the third capacitor C3 is connected to the second node N2, and a second end of the third capacitor C3 is connected to the first output end OUT1.

[0159] Figure 8is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Figure 8 Optionally, the node voltage control module 110 includes an input unit 111 and a first control unit 112, the input unit 111 is used to control the transmission of the start signal SIN to the second node N2 according to the first clock signal CK1, for example, to be turned on or off according to the second clock signal CK2, and to transmit the start signal SIN to the second node N2 when turned on; optionally, the first control unit 112 includes an inverter, the first control unit 112 is used to invert the potential of the second node N2 and output it to the first node, for example, to transmit the first level signal VGL or the second level signal VGH to the first node N1 according to the potential of the second node N2; optionally, the node voltage control module 110 also includes a second control unit 113, the second control unit 113 is used to transmit the second level signal VGH to the second node N2 according to the potential of the first node N1 and the first clock signal CK1.

[0160] Among them, the first clock signal CK1, the second clock signal CK2, and the start signal SIN respectively include first level pulses and second level pulses that are alternately set, the first clock signal CK1 and the second clock signal CK2 are both periodic signals, the periods of the first clock signal CK1 and the second clock signal CK2 are equal, and the first clock signal CK1 and the second clock signal CK2 include multiple first level pulses and second electric pulses, the first level pulse of the first clock signal CK1 overlaps with the second level pulse of the second clock signal CK2, and the second level pulse of the first clock signal CK1 overlaps with the first level pulse of the second clock signal CK2. The gate drive circuit in the display panel includes multiple shift registers, and the multiple shift registers are cascaded. For the first-stage shift register, the start signal SIN is provided by an external circuit structure. For the second to last-stage shift registers, the start signal SIN can be the first gate drive signal output by the previous-stage shift register, that is, in two adjacent stages of registers, the latter-stage shift register is connected to the first output terminal OUT1 of the former-stage shift register. Optionally, the first level pulse of the start signal SIN is one or more, and the first level pulse of the start signal SIN overlaps with the first level pulse of the second clock signal CK2 and does not overlap with the first level pulse of the first clock signal CK1.

[0161] Specifically, when the second clock signal CK2 is the first level signal VGL, the input unit 111 is turned on. When the second node N2 is the first level signal VGL, the first control unit 112 transmits the second level signal VGH to the first node N1; when the second node N2 is the second level signal VGH, the first control unit 112 transmits the first level signal VGL to the first node N1. When the first node N1 is the first level signal VGL and the first clock signal CK1 is the first level signal VGL, the second control unit 113 transmits the second level signal VGH to the second node N2.

[0162] Fig. 9 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig. 9 Optionally, the input unit 111 includes a ninth transistor T9, a gate of the ninth transistor T9 is connected to the first clock signal CK1, a first electrode of the ninth transistor T9 is connected to the start signal SIN, and a second electrode of the ninth transistor T9 is connected to the second node N2.

[0163] Optionally, the shift register further includes a tenth transistor T10, the second electrode of the ninth transistor T9 is connected to the second node N2 through the tenth transistor T10, or the second electrode of the ninth transistor T9 is connected to the gate of the eighth transistor T8 through the tenth transistor T10; the gate of the tenth transistor T10 is connected to the first power line or connected to the first level signal VGL. Taking the tenth transistor T10 as a P-type transistor as an example, the setting of the tenth transistor T10 can make the level of the second node N2 coupled to the extremely low level be isolated by the tenth transistor T10, and will not be transmitted to the common end of the tenth transistor T10 and the ninth transistor T9 (that is, the sixth node N6), thereby protecting the ninth transistor T9 and the transistor connected to the tenth transistor T10 in the second control unit 113 from being damaged due to excessive voltage difference, thereby improving the reliability of the shift register.

[0164] Fig.10 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.10Optionally, the first control unit 112 includes an eleventh transistor T11 and a twelfth transistor T12, the gate of the eleventh transistor T11 is connected to the second electrode or the second node N2 of the ninth transistor T9, the first electrode of the eleventh transistor T11 is connected to the second power line or connected to the second level signal VGH, and the second electrode of the eleventh transistor T11 is connected to the first node N1; the gate of the twelfth transistor T12 is connected to the second electrode or the second node N2 of the ninth transistor T9, the first electrode of the twelfth transistor T12 is connected to the first power line or connected to the first level signal VGL, and the second electrode of the twelfth transistor T12 is connected to the first node N1; optionally, the eleventh transistor T11 is a P-type transistor, and the twelfth transistor T12 is an N-type transistor. By setting the shift register to include both P-type transistors and N-type transistors, the number of transistor devices included in the shift register can be reduced, which is conducive to reducing the frame and improving the user experience. Optionally, the P-type transistor is a polysilicon transistor, such as a low-temperature polysilicon transistor, and the N-type transistor is an oxide transistor. The inverter in the first control unit 112 includes an eleventh transistor T11 and a twelfth transistor T12 .

[0165] Specifically, when the ninth transistor T9 is directly connected to the fourth output submodule (including the eighth transistor T8) at the second node N2, the gate of the eleventh transistor T11 is directly connected to the second node N2. When the ninth transistor T9 is connected to the fourth output submodule 122 through the tenth transistor T10, the gate of the eleventh transistor T11 is connected to the second pole (sixth node N6) of the ninth transistor T9. The same is true for the twelfth transistor T12, which will not be repeated here. The eleventh transistor T11 is turned on when the second node N2 is the first level signal VGL or the second pole (sixth node N6) of the ninth transistor T9 is the first level signal VGL, and the second level signal VGH is transmitted to the first node N1. The twelfth transistor T12 is turned on when the second node N2 is the second level signal VGH or the second pole (sixth node N6) of the ninth transistor T9 is the second level signal VGH, and the first level signal VGL is transmitted to the first node N1.

[0166] Optionally, the second control unit 113 includes a thirteenth transistor T13 and a fourteenth transistor T14, the first electrode of the thirteenth transistor T13 is connected to the second power line and / or connected to the second level signal VGH, the second electrode of the thirteenth transistor T13 is connected to the first electrode of the fourteenth transistor T14, one of the gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 is connected to the first node N1, and the other is connected to the first clock signal CK1; the second electrode of the fourteenth transistor T14 is connected to the second electrode or the second node N2 of the ninth transistor T9, and the gate of the fourteenth transistor T14 is connected to the first clock signal CK1.

[0167] Optionally, the gate of the thirteenth transistor T13 is connected to the first node N1; the gate of the fourteenth transistor T14 is connected to the first clock signal CK1.

[0168] Optionally, the gate of the thirteenth transistor T13 is connected to the first clock signal CK1; the gate of the fourteenth transistor T14 is connected to the first node N1.

[0169] Specifically, when the first node N1 is the first level signal VGL, the thirteenth transistor T13 is turned on, and the second level signal VGH is transmitted from the first electrode of the thirteenth transistor T13 to the first electrode of the fourteenth transistor T14. When the first clock signal CK1 is the first level signal VGL, the fourteenth transistor T14 is turned on, and the signal of the first electrode of the fourteenth transistor T14 is transmitted to the second electrode (fifth node N5) or the second node N2 of the ninth transistor T9. When the first node N1 is the first level signal VGL, and the first clock signal CK1 of the gate of the fourteenth transistor T14 is the first level signal VGL, the second level signal VGH is transmitted to the second electrode (sixth node N6) or the second node N2 of the ninth transistor T9 through the thirteenth transistor T13 and the fourteenth transistor T14.

[0170] In other optional embodiments of the present invention, the connection node between the tenth transistor T10 and the ninth transistor T9 (ie, the sixth node N6 ) may serve as the second node N2 , which is equivalent to the fourth output submodule including the tenth transistor T10 .

[0171] Figure 4-Figure 10 The example shows the case where the preset clock signal is the first clock signal CK1. Fig.11 is a schematic diagram of the structure of another shift register provided by an embodiment of the present invention, referring to Fig.11 In the shift register, the preset clock signal is the second clock signal CK2. Figure 4-Figure 11In some other embodiments of the present invention, the second output module 130 is connected to the first node N2, but not to the first node N1. In this case, an inverter can be provided, the input end of the inverter is connected to the first node N1, and the output end of the inverter is respectively connected to the first output submodule 131 and the second output submodule 132, for example, the output end of the inverter is connected to the gate of the first transistor T1, and the gate of the fourth transistor T4 in the output control unit 1321. For example, the output control unit 1321 also includes a second inverter, the first node N1 is connected to the input end of the second inverter, the output end of the second inverter is connected to the charge and discharge control subunit 1322, the charge and discharge control subunit 1322 is respectively connected to the first end of the coupling subunit 1323 and the second end of the coupling subunit 1323, and the charge and discharge control subunit 1322 is used to charge and / or discharge the coupling subunit 1323 according to the potential of the output end of the second inverter and the preset clock signal. The structure of the second inverter is the same or similar to that of the inverter in the first control unit 112 and will not be described in detail herein.

[0172] Fig.12 is a working timing diagram of a shift register provided by an embodiment of the present invention, and the working timing corresponds to Fig.10 The shift register shown in Figure 1 is referenced Fig.10 and Fig.12 , taking the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13 and the fourteenth transistor T14 as P-type transistors, and the twelfth transistor T12 as an N-type transistor as an example, taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example, the working timing of the shift register includes the following stages.

[0173] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned on in response to the second clock signal CK2, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the sixth node N6, and the first level signal VGL (low level signal) is transmitted to the first node N1, the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2, and the fifth transistor T5 is turned on according to the initial potential of the fifth node N5, wherein the fifth node N5 has no signal input in the initial state, so the fifth node N5 can be considered as a low level signal (e.g., equal to the ground level) in the initial state, so the fifth transistor T5 is turned on, and the high level first clock signal CK1 is transmitted to the fourth node N4, so that the potential of the fourth node N4 is increased, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also raised. In the initial state, no signal is input to the third node N3, so the initial potential of the third node N3 can be considered as a low level signal, so the potential of the fifth node N5 is higher than the potential of the third node N3, the sixth transistor T6 is turned off, and the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0174] In the first intermediate state stage t12, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, the sixth node N6 and the second node N2 maintain the high level of the first stage t1, so that the twelfth transistor T12 remains turned on, and the first node N1 is still at a low level. Because the potential state of the second node N2 is the same as that of the first stage t1, and the first clock signal CK1 is the same as that of the first stage t1, the potential state of the third node N3 is the same as that of the first stage t1, and the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0175] In the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. The ninth transistor T9 is turned off in response to the second clock signal CK2, and no signal is transmitted to the sixth node N6. The sixth node N6 maintains the high level of the previous stage. Correspondingly, the second node N2 maintains the high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 remains on, and correspondingly, the seventh transistor T7 remains on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Since the first clock signal CK1 jumps from a high level to a low level, the potential of the fourth node N4 is reduced. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is reduced. When the potential of the fifth node N5 is reduced to a potential lower than that of the third node N3, the sixth transistor T6 is turned on, and the lower potential is transmitted to the third node N3, so that the conduction state of the third transistor T3 is good, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0176] In the second intermediate state stage t23, the start signal SIN is a high level signal for a period of time and a low level signal for a period of time, the first clock signal CK1 jumps to a high level signal, the second clock signal CK2 remains a high level signal, the ninth transistor T9 in the shift register is turned off according to the first clock signal CK1, the sixth node N6 and the second node N2 maintain the high level of the second stage t2, so that the twelfth transistor T12 remains turned on, the first node N1 is still at a low level, the seventh transistor T7 remains turned on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. Since the first clock signal CK1 jumps from a low level to a high level, the potential of the fourth node N4 increases, due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 increases, the sixth transistor T6 is turned off, and the third node N3 can maintain the potential of the second stage t2, so that the third transistor T3 maintains a good conduction state, and transmits the first level signal VGL (low level signal) to the second output terminal OUT2.

[0177] In the third stage t3, the start signal SIN is a low level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned on in response to the second clock signal CK1, and the low level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned on according to the low level signal of the second node N2, and the high level first clock signal CK1 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on according to the low level signal of the sixth node N6, and the second level signal VGH (high level signal) is transmitted to the first node N1, and the seventh transistor T7 is turned off according to the high level signal of the first node N1. The first transistor T1 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the second output terminal OUT2. The fourth transistor T4 is turned on according to the low level signal of the second node N2, and the second level signal VGH (high level signal) is transmitted to the fourth node N4. That is, the potential state of the fourth node N4 is the same as the potential state of the second intermediate state stage t23, the potential of the fifth node N5 remains high, the fifth transistor T5 is turned off, the potential of the fifth node N5 is higher than the potential of the third node N3, and the sixth transistor T6 is turned off.

[0178] In the third intermediate state stage t34, the start signal SIN is a low level signal for a period of time and a high level signal for a period of time, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, the sixth node N6 and the second node N2 maintain the low level of the third stage t3, the eighth transistor T8 is turned on according to the low level of the second node N2, and the high level second clock signal CK2 is transmitted to the first output terminal OUT1. The eleventh transistor T11 is turned on according to the low level of the sixth node N6, and the second level signal VGH (high level signal) is transmitted to the first node N1, so that the seventh transistor T7 is turned off. Because the potential state of the second node N2 is the same as the third stage t3, and the first clock signal CK1 is the same as the third stage t3, the potential states of the fourth node N4, the fifth node N4 and the third node N3 are the same as the third stage t3, and the third transistor T3 is turned off. The first transistor T1 is turned on, and the second level signal VGH (high level signal) is transmitted to the second output terminal OUT2.

[0179] In the fourth stage t4, the start signal SIN is a high-level signal, the first clock signal CK1 jumps to a low-level signal, the second clock signal CK2 is a high-level signal, the ninth transistor T9 is turned off in response to the second clock signal CK2, no signal is transmitted to the sixth node N6, the sixth node N6 maintains the low level of the previous stage, and accordingly, the second node N2 maintains the low level of the previous stage, the eighth transistor T8 is turned on, and the low-level first clock signal CK1 is transmitted to the first output terminal OUT1. The eleventh transistor T11 remains turned on, the first node N1 is a high-level signal, and accordingly, the seventh transistor T7 remains turned off. Because the potential state of the second node N2 is the same as that of the third stage t3, the first transistor T1 is turned on, and the second-level signal VGH (high-level signal) is transmitted to the second output terminal OUT2. The states of the third node N3, the fourth node N4 and the fifth node N5 are the same as those of the third intermediate state stage t34.

[0180] In the fourth intermediate state stage t45, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the first clock signal CK2 is a high level signal. The ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, and the sixth node N6 and the second node N2 maintain the low level of the fourth stage t4, so that the eleventh transistor T11 remains turned on, and the first node N1 is still at a high level. The eighth transistor T8 remains turned on and transmits the high level second clock signal CK2 to the first output terminal OUT1. Because the potential state of the second node N2 is the same as that of the fourth stage t4, the first transistor T1 is turned on and the second level signal VGH (high level signal) is transmitted to the second output terminal OUT2. The states of the third node N3, the fourth node N4 and the fifth node N5 are the same as those of the fourth stage t4.

[0181] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. The ninth transistor T9 is turned on in response to the second clock signal CK2, and the high level signal of the start signal SIN is transmitted to the second node N2 through the ninth transistor T9 and the tenth transistor T10, and the eighth transistor T8 is turned off. The twelfth transistor T12 is turned on according to the high level signal of the sixth node N6, and the first level signal VGL (low level signal) is transmitted to the first node N1, the seventh transistor T7 is turned on according to the low level signal of the first node N1, and the second level signal VGH (high level signal) is output to the first output terminal OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2, the first transistor T1 is turned off according to the high level of the second node N2, the second level signal VGH is no longer output to the second output terminal OUT2, the potential of the second output terminal OUT2 gradually decreases, and due to the coupling effect of the first capacitor C1, the potential of the third node N3 is gradually pulled down, the fourth node N4 and the fifth node N5 maintain a high level, so that the sixth transistor T6 is turned off, the third transistor T3 is turned on, and the first level signal VGL is output to the second output terminal OUT2.

[0182] In the fifth intermediate state stage t56, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, the second clock signal CK2 is a high level signal, the ninth transistor T9 in the shift register is turned off according to the second clock signal CK2, the sixth node N6 and the second node N2 maintain the high level of the first stage t1, so that the twelfth transistor T12 remains turned on, and the first node N1 is still at a low level. Because the potential state of the second node N2 is the same as that of the first stage t1, and the first clock signal CK1 is the same as that of the first stage t1, the potential state of the third node N3 is the same as that of the first stage t1, and the third transistor T3 is turned on, transmitting the first level signal VGL (low level signal) to the second output terminal OUT2.

[0183] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. The ninth transistor T9 is turned off in response to the second clock signal CK2, and no signal is transmitted to the sixth node N6. The sixth node N6 maintains the high level of the previous stage. Correspondingly, the second node N2 maintains the high level of the previous stage, and the eighth transistor T8 is turned off. The twelfth transistor T12 remains on, and correspondingly, the seventh transistor T7 remains on, and the second level signal VGH is transmitted to the first output terminal OUT1 through the seventh transistor T7. The fourth transistor T4 is turned off according to the high level signal of the second node N2. The fifth transistor T5 is turned on. Since the first clock signal CK1 jumps from a high level to a low level, the potential of the fourth node N4 decreases. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 decreases. When the potential of the fifth node N5 decreases to be lower than the potential of the third node N3, the sixth transistor T6 is turned on and the lower potential is transmitted to the third node N3, so that the conduction state of the third transistor T3 is good, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0184] In the subsequent process, the fifth stage t5 and the sixth stage t6 are repeated in the same timing sequence, until the start signal SIN becomes a pulse again and enters the t3 stage again.

[0185] Fig.13 is another working timing diagram of a shift register provided by an embodiment of the present invention, and the working timing corresponds to Fig.11 The shift register shown in Figure 1 is referenced Fig.11 and Fig.13 , still taking the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13 and the fourteenth transistor T14 as P-type transistors, and the twelfth transistor T12 as an N-type transistor as an example, taking the first level signal VGL as a low level signal and the second level signal VGH as a high level signal as an example for explanation, the working timing of the shift register includes the following stages.

[0186] In the first stage t1, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. Fig.10The difference of the shift register shown in the first stage t1 is that after the fifth transistor T5 is turned on according to the initial potential of the fifth node N5, the low-level second clock signal CK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 is reduced. Due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 is also reduced, and since the fifth node N5 can be considered as a ground potential in the initial situation, the potential of the fifth node N5 will become lower after being coupled and reduced. In the initial situation, no signal is input to the third node N3, so the initial potential of the third node N3 can be considered as a low-level signal (for example, a ground level), so the potential of the fifth node N5 is lower than the potential of the third node N3, the sixth transistor T6 is turned on, the third transistor T3 is turned on, and the first-level signal VGL (low-level signal) is transmitted to the second output terminal OUT2.

[0187] In the first intermediate state stage t12, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 jumps to a high level signal. Fig.10 The shift register shown is different in the first intermediate state stage t12 in that, since the fifth node N5 is at a low level in the first stage t1, the fifth transistor T5 is turned on at the initial moment of the first intermediate state stage t12, and the high-level second clock signal CK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 increases, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 increases accordingly, so that the potential of the fifth node N5 is higher than the potential of the third node N3, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0188] In the second stage t2, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 is a high level signal. Fig.10 The shift register shown is different in the second stage t2 in that, since the potential state of the second node N2 is the same as that in the first intermediate stage t12, the potential state of the second clock signal CK2 is the same as that in the first intermediate stage t12, therefore, the fourth transistor T4 and the fifth transistor T5 are both turned off, the potential states of the fourth node N4 and the fifth node N5 are the same as those in the first intermediate stage t12, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0189] In the second intermediate state stage t23, the start signal SIN is a high level signal for a period of time and a low level signal for a period of time, the first clock signal CK1 jumps to a high level signal, and the second clock signal CK2 remains a high level signal. Fig.10 The shift register shown is different in the second intermediate state stage in that, since the potential state of the second node N2 is the same as that in the second stage t2, the potential state of the second clock signal CK2 is the same as that in the second stage t2, therefore, the fourth transistor T4 and the fifth transistor T5 are both turned off, the potential state of the fourth node N4 and the fifth node N5 are the same as the potential state of the first intermediate stage t12, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0190] In the third stage t3 , the start signal SIN is a low level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 jumps to a low level signal. Fig.11 The working process of the shift register in the third stage t3 is similar to Fig.10 The working process of the shift register in the third stage t3 is basically the same. It should be noted that due to Fig.11 The first electrode of the fifth transistor T5 is connected to the second clock signal CK2. Therefore, during a period of time at the beginning of the third stage t3, the jump of the second clock signal CK2 from high to low will have a certain impact on the fourth node N4 and the fifth node N5, so that the potential state of the fourth node N4 and the fifth node N5 is pulled down at the beginning of the third stage t3, a spike appears, and then quickly returns to a high level due to the conduction of the fourth transistor T4.

[0191] In the third intermediate state stage t34 , the start signal SIN is a low level signal for a period of time and a high level signal for a period of time, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a high level signal. Fig.11 The working process of the shift register in the third intermediate state stage t34 is similar to Fig.10 The working process of the shift register shown in the third intermediate state stage t34 is basically the same.

[0192] In the fourth stage t4 , the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 is a high level signal. Fig.11 The working process of the shift register in the fourth stage t4 is similar to Fig.10 The working process of the shift register shown in the fourth stage t4 is basically the same.

[0193] In the fourth intermediate state stage t45 , the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the first clock signal CK2 is a high level signal. Fig.11 The working process of the shift register in the fourth intermediate state stage t45 is similar to Fig.10 The working process of the shift register shown in the fourth intermediate state stage t45 is basically the same.

[0194] In the fifth stage t5, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. Fig.10 The difference of the shift register shown in the fifth stage t5 is that the potential of the second output terminal OUT2 gradually decreases, and due to the coupling effect of the first capacitor C1, the potential of the third node N3 is gradually pulled down, and the third transistor T3 is turned on, and the first level signal VGL is output to the second output terminal OUT2. Since the second clock signal CK1 jumps from a high level to a low level, the potential of the fifth node N5 is pulled down, so that the fifth transistor T5 is turned on, and the low-level second clock signal CK2 is transmitted to the fourth node N4. The potential of the fourth node N4 decreases. When the turn-on condition of the sixth transistor T6 is met, the sixth transistor T6 is turned on, the third node N3 is at a low potential, and the third transistor T3 is turned on, and the first level signal VGL is output to the second output terminal OUT2.

[0195] In the fifth intermediate state stage t56, the start signal SIN is a high level signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 jumps to a high level signal. Fig.10 The shift register shown is different in the fifth intermediate state stage t56 in that, since the fifth node N5 is at a low level in the fifth stage t5, at the initial moment of the fifth intermediate state stage t56, the fifth transistor T5 is turned on, and the high-level second clock signal CK2 is transmitted to the fourth node N4, so that the potential of the fourth node N4 increases, and due to the coupling effect of the second capacitor C2, the potential of the fifth node N5 increases accordingly, so that the potential of the fifth node N5 is higher than the potential of the third node N3, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0196] In the sixth stage t6, the start signal SIN is a high level signal, the first clock signal CK1 jumps to a low level signal, and the second clock signal CK2 jumps to a high level signal. Fig.10The shift register shown is different in the sixth stage t6 in that, since the potential state of the second node N2 is the same as that of the fifth intermediate state stage t56, the potential state of the second clock signal CK2 is the same as that of the fifth intermediate state stage t56, therefore, the fourth transistor T4 and the fifth transistor T5 are both turned off, the potential states of the fourth node N4 and the fifth node N5 are the same as those of the fifth intermediate state stage t56, the sixth transistor T6 is turned off, and the third node N3 can still maintain a low level, so that the third transistor T3 is turned on, and the first level signal VGL (low level signal) is transmitted to the second output terminal OUT2.

[0197] In the subsequent process, the fifth stage t5 and the sixth stage t6 are repeated in the same timing sequence, until the start signal SIN becomes a pulse again and enters the t3 stage again.

[0198] Continue to refer Fig.12 and Fig.13 , Optionally, the first gate driving signal includes a first level signal and a second level signal;

[0199] Optionally, a pulse of the first gate driving signal overlaps with a pulse of the second gate driving signal;

[0200] Optionally, a duration of a first level signal of a pulse of the first gate driving signal is within a duration of a second level signal of a pulse of the second gate driving signal;

[0201] Optionally, the pulse width of the first gate driving signal is smaller than the pulse width of the second gate driving signal;

[0202] Optionally, the node voltage control module is connected to a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal;

[0203] Optionally, the clock signal connected to the node voltage control module includes a first clock signal CK1 and a second clock signal CK2.

[0204] The pulse of the second clock signal CK2 overlaps with the pulse of the start signal, and the pulse of the first clock signal CK1 overlaps with the pulse of the first gate drive signal;

[0205] Optionally, a transition edge of a pulse of the first gate driving signal is aligned with a transition edge of a pulse of the first clock signal CK1;

[0206] Optionally, a transition edge of a pulse of the second gate driving signal is aligned with a transition edge of a pulse of the second clock signal CK2;

[0207] Optionally, the falling edge of the pulse of the first gate driving signal is aligned with the falling edge of the pulse of the first clock signal CK1; the rising edge of the pulse of the first gate driving signal is aligned with the rising edge of the pulse of the first clock signal CK1;

[0208] Optionally, a rising edge and a falling edge of a pulse of the second gate driving signal are respectively aligned with falling edges of two adjacent pulses of the second clock signal CK2.

[0209] Optionally, the first clock signal CK1 and the second clock signal CK2 have the same frequency and different phases, for example, opposite phases. The effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 do not overlap, for example, there is a time interval. The effective potential of the effective potential pulse of the first clock signal CK1 and the effective potential pulse of the second clock signal CK2 is a first level signal, for example, a low potential.

[0210] In at least part of the time period, the rising edges and falling edges of the positively correlated multiple signals are synchronized, that is, the voltage synchronization jump directions of the positively correlated multiple signals are the same. In at least part of the time period, the rising edges and falling edges of the two anti-correlated signals are synchronized, that is, the voltage synchronization jump directions of the two anti-correlated signals are opposite.

[0211] The embodiment of the present invention further provides a gate driving circuit. Fig.14 is a schematic diagram of a gate drive circuit provided by an embodiment of the present invention, with reference to Fig.14 The gate drive circuit includes a plurality of shift registers 10, wherein the shift register 10 is the shift register 10 of any of the above embodiments of the present invention, and the plurality of shift registers 10 are cascaded, and optionally, the start signal input terminal (which can be connected to the start signal SIN) of the n+1th stage shift register is connected to the first output terminal OUT1 of the nth stage shift register, wherein n is a positive integer greater than or equal to 1, that is, the first gate drive signal output by the first output terminal OUT1 of the nth stage shift register is used as the start signal of the n+1th stage register. The start signal of the first stage shift register is input from the outside.

[0212] The gate driving circuit of this embodiment includes the shift register of any of the above embodiments of the present invention, and has the beneficial effects of the shift register of any of the above embodiments of the present invention, which will not be described in detail here.

[0213] The gate driving circuit can be connected to a first clock line and a second clock line. The first clock line can be used to provide a first clock signal to an odd-numbered shift register, and the second clock line can be used to provide a second clock signal to an odd-numbered shift register. The first clock line can be used to provide a second clock signal to an even-numbered shift register, and the second clock line can be used to provide a first clock signal to an even-numbered shift register.

[0214] An embodiment of the present invention further provides a display panel, Fig.15 is a schematic diagram of a display panel provided by an embodiment of the present invention, with reference to Figure 3 and Fig.15 The display panel includes a pixel circuit 2 and a gate driving circuit 1 according to any embodiment of the present invention, the pixel circuit 2 includes a plurality of transistors, and the first output terminal and the second output terminal of the shift register 10 are connected to different transistors in the pixel circuit 2. For example, the first output terminal and the second output terminal of the shift register 10 are connected to transistors of different channel types in the pixel circuit 2.

[0215] Optionally, the pixel circuit 2 includes a driving transistor DT, a data writing transistor M1 and a compensation transistor M2, the data writing transistor M1 is connected between the data line Data and the first electrode of the driving transistor DT, and the compensation transistor M2 is connected between the second electrode and the gate of the driving transistor DT; the gate of the data writing transistor M1 is connected to the first output terminal OUT1, the gate of the data writing transistor M1 is connected to the first gate driving signal Scan1, the gate of the compensation transistor M2 is connected to the second output terminal OUT2, and the gate of the compensation transistor M2 is connected to the second gate driving signal Scan2.

[0216] Optionally, the channel type of the data writing transistor M1 is a P-channel, and the channel type of the compensation transistor M2 is an N-channel.

[0217] Optionally, the pixel circuit 2 also includes a first light-emitting control transistor M3 and a second light-emitting control transistor M4, the first light-emitting control transistor M3 is connected between the fourth power line VDD and the first electrode of the driving transistor DT; the second light-emitting control transistor M4 is connected between the second electrode of the driving transistor DT and the first electrode of the light-emitting device D1, and the second electrode of the light-emitting device D1 is connected to the fifth power line VSS; the gate of the first light-emitting control transistor M3 and the gate of the second light-emitting control transistor M4 are connected to the light-emitting control signal line EM.

[0218] Optionally, the pixel circuit further includes a first initialization transistor M5, a gate of the first initialization transistor M5 connected to the first scan line Sn1, a first electrode of the first initialization transistor M5 connected to the first initialization signal line Vref1, and a second electrode of the first initialization transistor M5 connected to the gate or second electrode of the driving transistor DT.

[0219] Optionally, the pixel circuit further includes a second initialization transistor M6, a gate of the second initialization transistor M6 is connected to the second scan line Sn2, a first electrode of the second initialization transistor M6 is connected to the second initialization signal line Vref2, and a second electrode of the second initialization transistor M6 is connected to the first electrode of the light emitting device D1.

[0220] Optionally, the pixel circuit further includes a storage capacitor Cst, a first end of the storage capacitor Cst is connected to the gate of the driving transistor DT, and a second end of the storage capacitor Cst is connected to a fourth power line VDD.

[0221] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0222] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A shift register, characterized in that: It includes a node voltage control module, a first output module and a second output module, wherein the node voltage control module is connected to the first node and the second node, the first output module is connected to the first node and the second node, and the second output module is connected to the first node and / or the second node; The node voltage control module is used to control the potential of the first node and the second node; The first output module is used for outputting a first gate driving signal through a first output terminal according to the potentials of the first node and the second node; The second output module is used for outputting a second gate driving signal through a second output terminal according to the potential of the first node and / or the second node; the first gate driving signal and the second gate driving signal are different.

2. The shift register according to claim 1, characterized in that: The first gate driving signal and the second gate driving signal have different pulse widths, pulse amplitudes, and positive and negative polarities of the pulse amplitudes; Preferably, the second gate driving signal includes a first level signal and a second level signal respectively; Preferably, the first gate driving signal and the second gate driving signal are used to drive transistors of different channel types; The first gate driving signal is used to drive a P-type transistor, and the second gate driving signal is used to drive an N-type transistor; The voltage of the first level signal is lower than the voltage of the second level signal; the second output module includes a P-type transistor, and the second output module is used to output the first level signal through the P-type transistor; Preferably, the P-type transistor included in the second output module is a polysilicon transistor; Preferably, the first gate driving signal includes the first level signal and the second level signal; Preferably, a pulse of the first gate driving signal overlaps with a pulse of the second gate driving signal; Preferably, the duration of the first level signal of the pulse of the first gate driving signal is within the duration of the second level signal of the pulse of the second gate driving signal; Preferably, the pulse width of the first gate driving signal is smaller than the pulse width of the second gate driving signal; Preferably, the node voltage control module is connected to a clock signal and a start signal, the pulse width of the first gate drive signal is equal to the pulse width of the clock signal, and the pulse width of the second gate drive signal is equal to the clock period of the clock signal; Preferably, the clock signal connected to the node voltage control module includes a first clock signal and a second clock signal. A pulse of the second clock signal overlaps with a pulse of the start signal, and a pulse of the first clock signal overlaps with a pulse of the first gate drive signal; Preferably, a transition edge of a pulse of the first gate drive signal is aligned with a transition edge of a pulse of the first clock signal; Preferably, a transition edge of a pulse of the second gate drive signal is aligned with a transition edge of a pulse of the second clock signal; Preferably, the falling edge of the pulse of the first gate drive signal is aligned with the falling edge of the pulse of the first clock signal; A rising edge of a pulse of the first gate drive signal is aligned with a rising edge of a pulse of the first clock signal; Preferably, the rising edge and the falling edge of the pulse of the second gate driving signal are respectively aligned with the falling edges of two adjacent pulses of the second clock signal; Preferably, the first clock signal and the second clock signal have the same frequency and different phases.

3. The shift register according to claim 1 or 2, characterized in that: The second output module includes a first output submodule and a second output submodule. The first output submodule is electrically connected to the second node, and is used to be turned on or off according to the potential of the second node, and transmit the second level signal to the second output terminal when turned on; Alternatively, the first output submodule is electrically connected to the first node, and is used to be turned on or off according to the potential of the first node, and transmit the second level signal to the second output terminal when turned on; The second output submodule is connected to the first node, and is used to transmit the first level signal to the second output end according to the potential of the first node; Alternatively, the second output submodule is connected to the second node, and is used to transmit the first level signal to the second output end according to the potential of the second node; Preferably, effective levels of the first gate driving signal and the second gate driving signal overlap; Preferably, the effective level of the first gate driving signal is a first level signal, and the effective level of the second gate driving signal is a second level signal; Preferably, the invalid levels of the first gate driving signal and the second gate driving signal overlap; Preferably, the node voltage control module is used to control the potential of the second node to jump from a high potential to a low potential when the potential of the first node jumps from a low potential to a high potential, and the potential of the second node to jump from a low potential to a high potential when the potential of the first node jumps from a high potential to a low potential; Preferably, the node voltage control module is used to control the potentials of the first node and the second node to remain opposite.

4. The shift register according to claim 3, characterized in that: The second output submodule is connected to the first node; Preferably, the first output submodule comprises a first transistor, a gate of the first transistor is connected to the second node, a first electrode of the first transistor is connected to a second power line or connected to the second level signal, and a second electrode of the first transistor is connected to the second output terminal; The second output submodule includes a second transistor, a gate of the second transistor is connected to the first node, a first electrode of the second transistor is connected to a first power line or connected to the first level signal, and a second electrode of the second transistor is connected to the second output terminal; Preferably, the second transistor is a P-type transistor; Preferably, the first transistor is a P-type transistor; Preferably, the second output submodule further includes a first capacitor, a first end of the first capacitor is connected to the gate of the second transistor, and a second end of the first capacitor is connected to the second output end.

5. The shift register according to claim 3, characterized in that: The second output submodule includes an output control unit and an output unit, the output control unit is connected to the second node, the output control unit is connected to the third node, and the output unit is connected to the third node; The output control unit is further connected to a preset clock signal, and is used to control the potential of the third node according to the potential of the second node and the preset clock signal, so that the potential of the third node is positively correlated with the potential of the first node; Preferably, the node voltage control module is connected to the first clock signal and / or the second clock signal, and the preset clock signal includes the first clock signal or the second clock signal; Preferably, the first output submodule includes a first transistor, the gate of the first transistor is connected to the second node, the first electrode of the first transistor is connected to the second power line or connected to the second level signal, and the second electrode of the first transistor is connected to the second output terminal; the output unit includes a third transistor, the gate of the third transistor is connected to the third node, the first electrode of the third transistor is connected to the first power line or connected to the first level signal, and the second electrode of the third transistor is connected to the second output terminal; Preferably, the potential of the third node includes a third level signal, and the voltage of the third level signal is lower than the voltage of the first power line; Preferably, an absolute value of a voltage difference between the third level signal and the first level signal is greater than or equal to an absolute value of a threshold voltage of the third transistor; Preferably, the third transistor is a P-type transistor; Preferably, the first transistor is a P-type transistor; Preferably, the second output submodule further includes a first capacitor, a first end of the first capacitor is connected to the gate of the third transistor, and a second end of the first capacitor is connected to the second output end; Preferably, when the potential of the second node jumps from a low potential to a high potential, the potential of the third node jumps from a high potential to a low potential; when the potential of the second node jumps from a high potential to a low potential, the potential of the third node jumps from a low potential to a high potential; Preferably, the potentials of the second node and the third node are maintained at opposite high and low potentials; Preferably, the potentials of the first node and the third node simultaneously jump from a low potential to a high potential, and / or the potentials of the first node and the third node simultaneously jump from a high potential to a low potential; Preferably, the potential of the third node further includes a second level signal, and the voltage of the third level signal is lower than the voltage of the second level signal; Preferably, an absolute value of a voltage difference between the third level signal and the voltage of the first power line is greater than or equal to an absolute value of a threshold voltage of the third transistor.

6. The shift register according to claim 5, characterized in that: The output control unit includes a charge and discharge control subunit, a coupling subunit and a unidirectional conduction subunit; The charge and discharge control subunit is connected to the second node, the first end of the coupling subunit, and the second end of the coupling subunit respectively, the second end of the coupling subunit is connected to the first end of the one-way conducting subunit, and the second end of the one-way conducting subunit is connected to the third node; The charge and discharge control subunit is used to charge and / or discharge the coupling subunit according to the potential of the second node and the preset clock signal; The coupling subunit is used to couple the potential change of its first end to the second end; the unidirectional conducting subunit is used to conduct when the potential of the first end of the unidirectional conducting subunit is lower than the potential of the third node; Preferably, the charge and discharge control subunit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the second node, the first electrode of the fourth transistor is connected to the second power line or connected to the second level signal, and the second electrode of the fourth transistor is connected to the first end of the coupling subunit; the gate of the fifth transistor is connected to the second end of the coupling subunit, the first electrode of the fifth transistor is connected to the preset clock signal, and the second electrode of the fifth transistor is connected to the first end of the coupling subunit; Preferably, the coupling subunit includes a second capacitor, a first electrode plate of the second capacitor serves as a first end of the coupling subunit, and a second electrode plate of the second capacitor serves as a second end of the coupling subunit; Preferably, the second capacitance is greater than the first capacitance; Preferably, the unidirectional conducting subunit comprises a sixth transistor, the gate of the sixth transistor is connected to the first electrode of the sixth transistor, the gate of the sixth transistor is connected to the second end of the coupling subunit, and the second electrode of the sixth transistor is connected to the third node; Preferably, the sixth transistor is a P-type transistor.

7. The shift register according to claim 5, characterized in that: The first output module includes a third output submodule and a fourth output submodule, the third output submodule is connected to the first node, and is used to be turned on or off according to the potential of the first node, and output the second level signal to the first output terminal when turned on; The fourth output submodule is connected to the second node, and is used to be turned on or off according to the potential of the second node, and output the first clock signal to the first output terminal when turned on; Preferably, the third output submodule comprises a seventh transistor, a gate of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to a second power line or is connected to a second level signal, and a second electrode of the seventh transistor is connected to the first output terminal; Preferably, the fourth output submodule comprises an eighth transistor, a gate of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the first clock signal, and a second electrode of the eighth transistor is connected to the first output terminal; Preferably, the seventh transistor is a P-type transistor, and the eighth transistor is a P-type transistor; Preferably, the fourth output submodule further includes a third capacitor, a first end of the third capacitor is connected to the second node, and a second end of the third capacitor is connected to the first output end; Preferably, the node voltage control module comprises an input unit and a first control unit, wherein the input unit is used to be turned on or off according to the second clock signal and transmit a start signal to the second node when turned on; The first control unit is used for transmitting a first level signal or a second level signal to the first node according to the potential of the second node; Preferably, the node voltage control module further includes a second control unit, and the second control unit is used to transmit the second level signal to the second node according to the potential of the first node and the first clock signal; Preferably, the first clock signal, the second clock signal and the start signal respectively include first level pulses and second level pulses that are alternately arranged, and the first level pulse of the start signal overlaps with the first level pulse of the second clock signal, and does not overlap with the first level pulse of the first clock signal; Preferably, the number of first level pulses of the start signal is one or more, and the number of first level pulses of the first clock signal and the second clock signal are respectively multiple; Preferably, the input unit comprises a ninth transistor, a gate of the ninth transistor is connected to the first clock signal, a first electrode of the ninth transistor is connected to the start signal, and a second electrode of the ninth transistor is connected to the second node; Preferably, the shift register further includes a tenth transistor, the second electrode of the ninth transistor is connected to the second node through the tenth transistor; the gate of the tenth transistor is connected to the first power line or connected to the first level signal; Preferably, the first control unit comprises an inverter; Preferably, the first control unit includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the eleventh transistor is connected to the second power line or connected to the second level signal, and the second electrode of the eleventh transistor is connected to the first node; the gate of the twelfth transistor is connected to the second electrode or the second node of the ninth transistor, the first electrode of the twelfth transistor is connected to the first power line or connected to the first level signal, and the second electrode of the twelfth transistor is connected to the first node; The second control unit includes a thirteenth transistor and a fourteenth transistor, a first electrode of the thirteenth transistor is connected to a second power line or a second level signal, a second electrode of the thirteenth transistor is connected to a first electrode of the fourteenth transistor, a second electrode of the fourteenth transistor is connected to a second electrode or a second node of the ninth transistor, one of a gate of the thirteenth transistor and a gate of the fourteenth transistor is connected to the first node, and the other is connected to a first clock signal; Preferably, the gate of the thirteenth transistor is connected to the first node; the gate of the fourteenth transistor is connected to the first clock signal; Preferably, the eleventh transistor is a P-type transistor, and the twelfth transistor is an N-type transistor.

8. A gate drive circuit, characterized in that: It comprises a plurality of shift registers as described in any one of claims 1 to 7, wherein the plurality of shift registers are cascaded; the start signal input terminal of the n+1th stage shift register is connected to the first output terminal of the nth stage shift register, wherein n is a positive integer greater than or equal to 1.

9. A display panel, characterized in that: comprising a pixel circuit and the gate driving circuit according to claim 8, The pixel circuit includes a plurality of transistors, and the first output terminal and the second output terminal of the shift register are connected to transistors of different channel types in the pixel circuit.

10. The display panel according to claim 9, characterized in that: The pixel circuit includes a driving transistor, a data writing transistor and a compensation transistor, wherein the data writing transistor is connected between a data line and a first electrode of the driving transistor, and the compensation transistor is connected between a second electrode and a gate of the driving transistor; the gate of the data writing transistor is connected to the first output terminal, and the gate of the compensation transistor is connected to the second output terminal; Preferably, the channel type of the data writing transistor is P-channel, and the channel type of the compensation transistor is N-channel; Preferably, the pixel circuit further comprises a first light-emitting control transistor and a second light-emitting control transistor, wherein the first light-emitting control transistor is connected between a fourth power line and a first electrode of the driving transistor; the second light-emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light-emitting device, and the second electrode of the light-emitting device is connected to a fifth power line; The gate of the first light emission control transistor and the gate of the second light emission control transistor are connected to a light emission control signal line; Preferably, the pixel circuit further comprises a first initialization transistor, a gate of the first initialization transistor is connected to a first scan line, a first electrode of the first initialization transistor is connected to a first initialization signal line, and a second electrode of the first initialization transistor is connected to a gate or a second electrode of the driving transistor; Preferably, the pixel circuit further includes a second initialization transistor, a gate of the second initialization transistor is connected to a second scan line, a first electrode of the second initialization transistor is connected to a second initialization signal line, and a second electrode of the second initialization transistor is connected to a first electrode of the light-emitting device.

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