Transistor packaging method

Abstract

The invention provides a transistor packaging method, which comprises the following steps that the front surface of a chip comprises a collector end, an emitter end and a grounding end of a transistor, the back surface of the chip comprises a base end of the transistor, and the back surface of the chip is bonded with a carrier plate; a first metal layer is formed on the surface of the carrier plate through an RDL method, a second metal layer is formed on the front face of the chip, and the second metal layer is connected with the collector end, the emitter end and the grounding end; forming a first plastic layer, packaging the chip, the first metal layer and the second metal layer by the first plastic layer, and removing the carrier plate; grinding the first plastic layer; forming a third metal layer through the RDL method, wherein the third metal layer connects the first metal layer with the second metal layer; forming a second plastic layer, and packaging the third metal layer; cutting parts of the first plastic layer and the second plastic layer to expose the side surface of the first metal layer; and connecting the first metal layer and the base end to the surface of the lead frame.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit packaging, and in particular to a packaging method for a transistor. Background Art

[0002] In order to achieve stability and easy installation of transistors, transistors can be packaged.

[0003] The prior art transistor package uses a wire bonding process to connect the circuit, specifically including providing a lead frame 110, attaching a transistor chip 120 to the lead frame 110. The collector, emitter, base and ground terminal of the transistor chip 120 are bonded to four pins of the lead frame through wires 130. Then, the transistor chip 120 on the lead frame 110 is sealed by a plastic encapsulation layer 140.

[0004] However, due to the limitations of wire bonding, transistor packaging in the prior art has the following disadvantages: 1. A larger package size is required; 2. The parasitic inductance and capacitance of the leads are large, so overheating may occur when a large current flows through the leads; 3. The wiring may become loose or broken, resulting in poor electrical contact. Summary of the invention

[0005] The object of the present invention is to provide a transistor packaging method, which can reduce the packaging size, prevent overheating, and prevent poor electrical contact.

[0006] In order to achieve the above object, the present invention provides a transistor packaging method, comprising:

[0007] Providing a carrier and a chip, wherein the chip comprises a front side and a back side opposite to each other, the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of a transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the back side of the chip to the carrier;

[0008] Forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the front side of the chip by a method of forming a redistribution layer, wherein the second metal layer is connected to the collector terminal, the emitter terminal and the ground terminal respectively;

[0009] forming a first plastic layer, wherein the first plastic layer encapsulates the chip, the first metal layer and the second metal layer, and removing the carrier;

[0010] Grinding a portion of the thickness of the first plastic layer to expose surfaces of the first metal layer and the second metal layer;

[0011] forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer;

[0012] forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and covers the first plastic layer, the first metal layer and the second metal layer;

[0013] Cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer;

[0014] A lead frame is provided, and the first metal layer and the base terminal are both connected to a surface of the lead frame.

[0015] Optionally, in the transistor packaging method, the thickness of the first metal layer, the second metal layer and the third metal layer are all greater than 50 μm.

[0016] Optionally, in the transistor packaging method, the lead frame includes a plurality of pins.

[0017] Optionally, in the transistor packaging method, the surface of the lead frame has solder balls, and the first metal layer and the collector terminal are respectively connected to the surface of the lead frame through the solder balls.

[0018] Optionally, in the transistor packaging method, the back side of the chip is bonded to the carrier board via bonding glue.

[0019] The present invention also provides a transistor packaging method, comprising:

[0020] Providing a carrier and a chip, wherein the chip comprises a front side and a back side opposite to each other, the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of a transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the front side of the chip to the carrier;

[0021] Forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the back side of the chip by a method of forming a redistribution layer, wherein the second metal layer is connected to the base terminal;

[0022] forming a first plastic layer, wherein the first plastic layer encapsulates the chip, the first metal layer and the second metal layer, and removing the carrier;

[0023] Grinding a portion of the thickness of the first plastic layer to expose surfaces of the first metal layer and the second metal layer;

[0024] forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer;

[0025] Forming a fourth metal layer on the front side of the chip by forming a redistribution layer, wherein the fourth metal layer is connected to the collector terminal, the emitter terminal and the ground terminal respectively, and the fourth metal layer is also connected to the first metal layer;

[0026] forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and the fourth metal layer and covers the first plastic layer, the first metal layer and the second metal layer;

[0027] Cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer;

[0028] A lead frame is provided, and the first metal layer and the fourth metal layer are both connected to a surface of the lead frame.

[0029] Optionally, in the transistor packaging method, the thickness of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are all greater than 50 μm.

[0030] Optionally, in the transistor packaging method, the lead frame includes a plurality of pins.

[0031] Optionally, in the transistor packaging method, the surface of the lead frame has solder balls, and the first metal layer and the fourth metal layer are both connected to the surface of the lead frame through the solder balls.

[0032] Optionally, in the transistor packaging method, the back side of the chip is bonded to the carrier board via bonding glue.

[0033] In the transistor packaging method provided by the present invention, the first metal layer, the second metal layer and the third metal layer are formed by forming a redistribution layer, or the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are formed by forming a redistribution layer to guide the device of the chip to the lead frame. Compared with the prior art method of using wire bonding, the present invention reduces the packaging size, prevents overheating, and prevents poor electrical contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of a transistor packaging process in the prior art;

[0035] Figure 2 is a flow chart of a transistor packaging method according to a first embodiment of the present invention;

[0036] Figure 3 , Figure 4 , Figures 7 to 9 as well as Figure 11 to Figure 12 is a schematic longitudinal cross-sectional view of the packaging process of the first embodiment of the present invention;

[0037] Figure 5 , Figure 6 and Fig.10 is a top view of the packaging process of the first embodiment of the present invention;

[0038] Fig.13 is a flow chart of a transistor packaging method according to a second embodiment of the present invention;

[0039] Figures 14 to 19 is a schematic longitudinal cross-sectional view of a transistor during packaging according to a second embodiment of the present invention;

[0040] In the figure: 110-lead frame, 120-transistor chip, 130-lead, 140-plastic packaging layer, 210-carrier, 220-chip, 230-bonding glue, 240-first metal layer, 250-second metal layer, 260-first plastic layer, 270-third metal layer, 280-second plastic layer, 290-lead frame, 310-carrier, 320-chip, 330-bonding glue, 340-first metal layer, 350-second metal layer, 360-first plastic layer, 370-third metal layer, 380-fourth metal layer, 390-second plastic layer, 400-lead frame. DETAILED DESCRIPTION

[0041] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0043] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0044] Embodiment 1

[0045] Please refer to Figure 2 , an embodiment of the present invention provides a transistor packaging method, comprising:

[0046] S11: providing a carrier and a chip, wherein the chip comprises a front side and a back side, wherein the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of the transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the back side of the chip to the carrier;

[0047] S12: forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the front side of the chip by a method of forming a redistribution layer, the second metal layer being connected to the collector terminal, the emitter terminal and the ground terminal respectively;

[0048] S13: forming a first plastic layer, the first plastic layer encapsulating the chip, the first metal layer and the second metal layer, and removing the carrier;

[0049] S14: grinding a portion of the first plastic layer to expose surfaces of the first metal layer and the second metal layer;

[0050] S15: forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer;

[0051] S16: forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and covers the first plastic layer, the first metal layer and the second metal layer;

[0052] S17: cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer;

[0053] S18: Provide a lead frame, and connect the first metal layer and the base terminal to the surface of the lead frame.

[0054] Please refer to Figure 3 First, provide a carrier 210 and a chip 220. The chip 220 includes a front side and a back side relative to each other. The front side of the chip 220 includes a collector terminal, an emitter terminal and a ground terminal of the transistor, and the back side of the chip 220 includes a base terminal of the transistor. The back side of the chip 220 is bonded to the carrier 210 by bonding glue 230. The chip 220 covers a partial area of ​​the carrier 210.

[0055] Next, please refer to Figure 4 A first metal layer 240 is formed on the surface of the carrier 210 not covered by the chip 220 by forming a redistribution layer (RDL), and a second metal layer 250 is formed on the front surface of the chip 220 by forming a redistribution layer. The first metal layer 240 is at a certain distance from the chip 220. The wiring of the first metal layer 240 is as follows: Figure 5The second metal layer 250 is connected to the collector terminal, the emitter terminal and the ground terminal respectively. Figure 6 .

[0056] First, please refer to Figure 7 , forming a first plastic layer 260, the first plastic layer 260 encapsulates the chip 220, the first metal layer 240 and the second metal layer 250. Next, the carrier 210 and the bonding adhesive 230 are removed.

[0057] Next, please refer to Figure 8 , grinding a portion of the first plastic layer 260 , so that the first plastic layer 260 exposes the surfaces of the first metal layer 240 and the second metal layer 250 .

[0058] Next, please refer to Fig. 9 and Fig.10 , Fig.10 It is a top view, in which the third metal layer 270 is formed by forming a redistribution layer, the third metal layer 270 connects the first metal layer 240 and the second metal layer 250, and the thickness of the third metal layer 270, the first metal layer 240 and the second metal layer 250 are all greater than 50 μm.

[0059] Next, please refer to Fig.11 , forming a second plastic layer 280 , the second plastic layer 280 encapsulates the third metal layer 270 and covers the first plastic layer 260 , the first metal layer 240 and the second metal layer 250 .

[0060] Next, please refer to Fig.12 , cut part of the first plastic layer 260 and the second plastic layer 280 to expose the side of the first metal layer 240. Then, provide a lead frame 290, connect the first metal layer 240 and the base terminal on the back of the chip 220 to the surface of the lead frame 290. Specifically, the surface of the lead frame 290 has solder balls, and the first metal layer 240 and the collector terminal can be connected to the surface of the lead frame through the solder balls respectively. The lead frame 290 is connected to the devices on the front of the chip 220, such as the collector terminal, the emitter terminal and the ground terminal through the first metal layer 240, the third metal layer 270 and the second metal layer 250. The lead frame 290 is metal, and the lead frame 290 includes a plurality of pins. Therefore, the encapsulation of the chip 220 is realized, and the functional end of the transistor is also led out through the pins of the lead frame 290, which is convenient for connection with other circuits.

[0061] Embodiment 2

[0062] Please refer to Fig.13 , Embodiment 2 of the present invention provides a transistor packaging method, comprising:

[0063] S21: providing a carrier and a chip, wherein the chip comprises a front side and a back side opposite to each other, the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of the transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the front side of the chip to the carrier;

[0064] S22: forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the back side of the chip by a method of forming a redistribution layer, and the second metal layer is connected to the base terminal;

[0065] S23: forming a first plastic layer, the first plastic layer encapsulating the chip, the first metal layer and the second metal layer, and removing the carrier;

[0066] S24: grinding a portion of the first plastic layer to expose surfaces of the first metal layer and the second metal layer;

[0067] S25: forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer;

[0068] S26: forming a fourth metal layer on the front side of the chip by forming a redistribution layer, wherein the fourth metal layer is connected to the collector terminal, the emitter terminal and the ground terminal respectively, and the fourth metal layer is also connected to the first metal layer;

[0069] S27: forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and the fourth metal layer and covers the first plastic layer, the first metal layer and the second metal layer;

[0070] S28: cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer;

[0071] S29: providing a lead frame, and connecting the first metal layer and the fourth metal layer to a surface of the lead frame.

[0072] First, please refer to Fig.14 , provide a carrier 310 and a chip 320, the chip 320 includes a relative front and back side, the front side of the chip 320 includes a base terminal, an emitter terminal and a collector terminal of the transistor, the back side of the chip 320 includes a ground terminal of the transistor, the front side of the chip 320 is bonded to the carrier 310 by bonding glue 330, and the chip 320 covers a partial area of ​​the carrier 310.

[0073] Next, please refer to Fig.15 A first metal layer 340 is formed on the surface of the carrier 310 by forming a redistribution layer, and a second metal layer 350 is formed on the back side of the chip 320 by forming a redistribution layer. The second metal layer 350 is connected to the base terminal on the back side of the chip 320, and the first metal layer 340 has a certain distance from the chip 320.

[0074] Next, please refer to Fig.16 , forming a first plastic layer 360, the first plastic layer 360 encapsulates the chip 320, the carrier 310, the first metal layer 340 and the second metal layer 350. Next, the carrier 310 and the bonding adhesive 330 are removed.

[0075] Next, please refer to Fig.17 , grinding a portion of the first plastic layer 360, so that the first plastic layer 360 exposes the surface of the first metal layer 340 and the second metal layer 350. Then, forming the third metal layer 370 by forming a redistribution layer, the third metal layer 370 connects the first metal layer 340 and the second metal layer 350.

[0076] Next, please refer to Fig.18 , a fourth metal layer 380 is formed on the front side of the chip 320, and the fourth metal layer 380 is connected to the first metal layer 340. The thickness of the first metal layer 340, the second metal layer 350, the third metal layer 370 and the fourth metal layer 380 are all greater than 50 μm. Next, a second plastic layer 390 is formed, and the second plastic layer 390 encapsulates the third metal layer 370 and the fourth metal layer 380 and covers the first plastic layer 360, the first metal layer 340 and the second metal layer 350.

[0077] Next, please refer to Fig.19 , cutting part of the first plastic layer 360 and the second plastic layer 390 to expose the side of the first metal layer 340. Provide a lead frame 400, and connect the fourth metal layer 380 to the surface of the lead frame 400. Specifically, the surface of the lead frame 400 has solder balls, and the fourth metal layer 380 can be connected to the surface of the lead frame 400 through the solder balls. The lead frame 400 is connected to the devices on the front side of the chip 320, such as the collector terminal, the emitter terminal and the ground terminal through the fourth metal layer 380. The lead frame 400 is connected to the base terminal of the device on the back side of the chip 320 through the first metal layer 340, the third metal layer 370 and the second metal layer 350. The lead frame 400 is metal, and the lead frame 400 includes a plurality of pins. Therefore, the encapsulation of the chip 320 is realized, and the functional end of the transistor is also led out through the pins of the lead frame 400, which is convenient for connection with other circuits.

[0078] In summary, in the transistor packaging method provided by the embodiment of the present invention, the first metal layer, the second metal layer and the third metal layer are formed by forming a redistribution layer, or the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are formed by forming a redistribution layer to guide the device of the chip to the lead frame. Compared with the prior art method of using wire bonding, the present invention reduces the packaging size, prevents overheating, and prevents poor electrical contact.

[0079] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for packaging a transistor, characterized in that: include: Providing a carrier and a chip, wherein the chip comprises a front side and a back side opposite to each other, the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of a transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the back side of the chip to the carrier; Forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the front side of the chip by a method of forming a redistribution layer, wherein the second metal layer is connected to the collector terminal, the emitter terminal and the ground terminal respectively; forming a first plastic layer, wherein the first plastic layer encapsulates the chip, the first metal layer and the second metal layer, and removing the carrier; Grinding a portion of the thickness of the first plastic layer to expose surfaces of the first metal layer and the second metal layer; forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer; forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and covers the first plastic layer, the first metal layer and the second metal layer; Cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer; A lead frame is provided, and the first metal layer and the base terminal are both connected to a surface of the lead frame.

2. The transistor packaging method according to claim 1, characterized in that: The thickness of the first metal layer, the second metal layer and the third metal layer are all greater than 50 μm.

3. The transistor packaging method according to claim 1, characterized in that: The lead frame includes a plurality of leads.

4. The transistor packaging method according to claim 1, characterized in that: The surface of the lead frame is provided with solder balls, and the first metal layer and the collector terminal are respectively connected to the surface of the lead frame through the solder balls.

5. The transistor packaging method according to claim 1, characterized in that: The back side of the chip is bonded to the carrier board via bonding glue.

6. A method for packaging a transistor, characterized in that: include: Providing a carrier and a chip, wherein the chip comprises a front side and a back side opposite to each other, the front side of the chip comprises a collector terminal, an emitter terminal and a ground terminal of a transistor, and the back side of the chip comprises a base terminal of the transistor, and bonding the front side of the chip to the carrier; Forming a first metal layer on the surface of the carrier by a method of forming a redistribution layer, forming a second metal layer on the back side of the chip by a method of forming a redistribution layer, wherein the second metal layer is connected to the base terminal; forming a first plastic layer, wherein the first plastic layer encapsulates the chip, the first metal layer and the second metal layer, and removing the carrier; Grinding a portion of the thickness of the first plastic layer to expose surfaces of the first metal layer and the second metal layer; forming a third metal layer by forming a redistribution layer, wherein the third metal layer connects the first metal layer and the second metal layer; Forming a fourth metal layer on the front side of the chip by forming a redistribution layer, wherein the fourth metal layer is connected to the collector terminal, the emitter terminal and the ground terminal respectively, and the fourth metal layer is also connected to the first metal layer; forming a second plastic layer, wherein the second plastic layer encapsulates the third metal layer and the fourth metal layer and covers the first plastic layer, the first metal layer and the second metal layer; Cutting a portion of the first plastic layer and the second plastic layer to expose a side surface of the first metal layer; A lead frame is provided, and the first metal layer and the fourth metal layer are both connected to a surface of the lead frame.

7. The transistor packaging method according to claim 6, characterized in that: The thickness of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are all greater than 50 μm.

8. The transistor packaging method according to claim 6, characterized in that: The lead frame includes a plurality of leads.

9. The transistor packaging method according to claim 6, characterized in that: The surface of the lead frame is provided with solder balls, and the first metal layer and the fourth metal layer are both connected to the surface of the lead frame through the solder balls.

10. The transistor packaging method according to claim 6, characterized in that: The back side of the chip is bonded to the carrier board via bonding glue.

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