The structure is based on frame and package design to support inductance and master chip stacking

Abstract

The utility model discloses a kind of structure based on frame and encapsulation design support inductance and main control chip stacking, comprising: S1, design base material frame, main control chip is inverted on base material frame;Base material frame includes first support layer, second support layer and multiple installation layers;Every top of first support layer and second support layer is respectively provided with every electroplating place;S2, lower film is pasted in bottom, upper film is pasted in top, filling plastic encapsulation material;S3, remove upper film and lower film, inductance is welded at every electroplating place, complete preparation.The utility model is welded inductance by the welding connection of NiPdAu electroplating layer, reduces cost and improves yield by frame integration design and realizes the 3D stacking of inductance and main control chip, effectively reduces package size;Traditional copper column grinding step is also cancelled, and in combination with the height difference and slope via hole of concave, it is convenient to use and plastic encapsulation filling is uniform, so that overall product reliability is high, and long-term use is suitable.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, specifically to a structure based on framework and packaging design that supports the stacking of inductors and main control chips. Background Technology

[0002] In modern electronic packaging technology, stacking inductors with main control chips is a common design to achieve a more compact and efficient circuit layout. However, this design presents several technical and process challenges, particularly in ensuring high package yield and reliable electrical connections.

[0003] On inductor components, the stacking of the main control chip with copper pillars soldered to both ends of the frame pins involves a complex packaging process, resulting in low yield and an inability to lock the solder paste at the inductor solder joints. Furthermore, the yield of electroplated copper pillars on the frame pins is also low. For example... Figure 6 The diagram shown is a schematic of a conventional electroplated copper pillar packaging scheme. In the diagram, 100 is the electroplated copper pillar, 101 is the conventional frame, 102 is the conventional chip, 103 is the conventional molding compound, and 104 is the conventional inductor. Figure 6 The connection structure between the frame, electroplated copper pillars, and the main control chip was demonstrated. The copper pillars were thinned through grinding to expose the solder joints, and then filled with molding compound to secure them. However, the height of the exposed copper pillar solder joints was uncontrollable, the ground copper pillars lacked electroplating, and grinding required additional equipment, resulting in the inability to lock the solder and hindering further processing and use, thus increasing product costs.

[0004] In other words, conventional electroplated copper pillar encapsulation solutions contain at least the following two problems: 1) The packaging process is complex and the product yield is low; 2) Low yield and the need for additional grinding equipment have led to increased costs. Utility Model Content

[0005] To address the two issues mentioned above, the purpose of this invention is to propose a structure based on frame and packaging design that supports the stacking of inductors and main control chips. The integrated frame design enables 3D stacking of inductors and main control chips, reducing the need for traditional PCB interlayers and effectively reducing package size. Furthermore, it eliminates the traditional copper pillar grinding step, using NiPdAu electroplating for soldering, enabling rapid and efficient inductor connection, reducing costs and improving yield. Combined with recessed height difference design and beveled vias, it facilitates soldering and ensures uniform molding and filling, resulting in high overall product reliability and long-term usability.

[0006] This was achieved through the following technical solutions: A structure based on a frame and packaging design supporting the stacking of inductors and a main control chip includes a substrate frame, an upper film, a lower film, a main control chip, and molding compound. The substrate frame includes a first support layer, a second support layer, and multiple mounting layers. Each bottom end of the first and second support layers is parallel and serves as the bottom of the substrate frame. Each top end of the first and second support layers is parallel and serves as the top of the substrate frame. The multiple mounting layers are parallel to each bottom end. Each top end of the first and second support layers has an electroplating area, and each electroplating area is used to solder an inductor. The main control chip is flip-chip bonded to at least two mounting layers. Molding compound fills the gaps in the substrate frame. The lower film is attached to the bottom of the substrate frame using a removable bonding method. The upper film is also attached to the bottom of the substrate frame using a removable bonding method.

[0007] Preferably, each of the first support layer and the second support layer has a recessed area at its top end, and the positions other than the recessed areas at each top end are respectively marked as non-recessed areas. Each non-recessed area is used to set a corresponding electroplating area, and there is a height difference between each recessed area and each corresponding adjacent non-recessed area.

[0008] Preferably, the first support layer and the second support layer have the same structure, and each top end and each corresponding bottom end are connected by a corresponding slope, and each slope is also provided with a recessed through hole.

[0009] Preferably, each through hole is located at the center of each slope.

[0010] Preferably, the first support layer, the second support layer, and the multiple mounting layers are all made of copper.

[0011] Preferably, each electroplating area is a NiPdAu electroplating layer.

[0012] Preferably, the distance between the two bottom ends is greater than the distance between the two top ends, and the acute angle formed by each slope and the bottom is denoted as A, 45°. <A<60°。

[0013] Preferably, the molding compound is epoxy resin.

[0014] Preferably, both the upper and lower membranes are polyimide membranes.

[0015] Preferably, the thickness of both the upper and lower membranes ranges from 20 micrometers to 75 micrometers.

[0016] The advantages of this utility model compared with the prior art are: The technical solution of this utility model achieves 3D stacking of inductors and main control chips through an integrated frame design, reducing the traditional PCB interlayer and effectively reducing the package size; it also eliminates the traditional electroplated copper pillar grinding step, and performs welding through NiPdAu electroplating, which quickly and efficiently connects the inductors, reducing costs and improving yield; combined with the recessed height difference design and sloped through holes, it facilitates welding and uniform plastic filling, making the overall product highly reliable and easy to use for a long time. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a substrate frame structure; Figure 2 This is a schematic diagram of a structure after a substrate frame and a chip are flip-chip bonded together, and then encapsulated using an upper film and a lower film. Figure 3 This is a schematic diagram of a structure using an upper film and a lower film, and then encapsulated. Figure 4 This is a schematic diagram of the structure after removing the upper and lower membranes; Figure 5 This is a schematic diagram of a structure based on a framework and packaging design that supports the stacking of inductors and main control chips, and the inductors after soldering. Figure 6 This is a schematic diagram of a conventional electroplated copper pillar encapsulation scheme. Detailed Implementation

[0018] The following will be combined with the present invention. Figures 1 to 6 The technical solutions in the embodiments of this utility model will be described in detail below.

[0019] like Figure 5 The diagram shown illustrates a structure based on a framework and packaging design that supports the stacking of inductors and a main control chip, along with a schematic diagram of the inductor after soldering. In the diagram, 1 represents multiple mounting layers, 4 represents the molding compound, 5 represents the main control chip, 31 represents the bottom of the second support layer, 32 represents the through-hole of the second support layer, and 33 represents the top of the second support layer. Figure 5 As shown, by constructing a substrate frame with uniform stress distribution and easy welding, and designing a height difference between the recessed area and the non-recessed area used for NiPdAu electroplating, the filling molding compound is more uniform, the frame has stronger support capacity and is easier to weld. Furthermore, under the action of the upper film, the NiPdAu electroplating layer can effectively weld inductors and stably lock the solder without the need for grinding.

[0020] like Figure 1 The image shown is a schematic diagram of a base material frame structure. Figure 1 In the diagram, 331 is the recessed area of ​​the second support layer, and 332 is the non-recessed area of ​​the second support layer. (Combined...) Figure 1 and Figure 5As shown, the substrate frame includes a first support layer, a second support layer, and multiple mounting layers. The bottom ends of the first and second support layers are parallel and serve as the bottom of the substrate frame. The top ends of the first and second support layers are parallel and serve as the top of the substrate frame. The multiple mounting layers are parallel to each bottom end. Gaps are left between each mounting layer for subsequent filling with molding compound. The main control chip is soldered to at least two mounting layers by flip-chip bonding for fixation.

[0021] The substrate frame includes a first support layer, a second support layer, and multiple mounting layers. The bottom ends of each of the first and second support layers are parallel and serve as the bottom of the substrate frame. The top ends of each of the first and second support layers are parallel and serve as the top of the substrate frame. The multiple mounting layers are parallel to each bottom end. Each top end of the first and second support layers has a plating area, and each plating area is soldered with an inductor. Molding compound fills the gaps in the substrate frame.

[0022] like Figure 2 The diagram shows a structure after the substrate frame and chip are flip-chip bonded together, and then encapsulated with an upper and lower film. The main control chip is flip-chip bonded to at least two mounting layers. Flip-chip bonding, also known as flip-chip soldering, means that the front side of the main control chip is soldered towards the mounting layer.

[0023] In this embodiment, the first support layer, the second support layer, and multiple mounting layers are all made of copper. The non-recessed areas at the top of each of the first and second support layers are used as electroplating sites, employing NiPdAu electroplating. NiPdAu is a continuous electroplating of nickel, palladium, and gold. Nickel plating provides excellent mechanical support and corrosion resistance, as well as a stable substrate. The palladium layer, located above the nickel layer, prevents nickel from diffusing into the gold layer, and palladium itself is also an excellent welding material, improving the quality of the solder joint. Gold plating not only improves conductivity and solderability but also protects palladium and nickel from oxidation or contamination. Therefore, using NiPdAu electroplating balances mechanical support, corrosion resistance, solderability, and long-term use.

[0024] Each of the first and second support layers has a recessed area at its top. The area outside the recessed area at each top is designated as a non-recessed area. Each non-recessed area is used to set the corresponding electroplating area. There is a height difference between each recessed area and each adjacent non-recessed area, forming a stepped structure, which facilitates welding at the non-recessed areas and optimizes stress distribution.

[0025] The structures of the first support layer and the second support layer are the same. Each top end and each corresponding bottom end are connected by each corresponding ramp, and each ramp is respectively provided with each through hole that is recessed. Arranging the corresponding through holes in each ramp can make the stress distribution more balanced and also facilitate more uniform filling of the encapsulant during subsequent filling. Each through hole is arranged in the center of each ramp. The distance between the two bottom ends is greater than the distance between the two top ends. At the same time, the acute angle formed by each ramp and the bottom is denoted as A, and 45° < A < 60°; controlling the acute angle formed by the ramp and the bottom helps to ensure the mechanical strength of the support layer.

[0026] As Figure 3 shown, it is a schematic structural diagram of a structure after using an upper film and a lower film and encapsulation. 6 in the figure is the upper film, and 7 in the figure is the lower film; the lower film is attached to the bottom of the substrate frame by a detachable bonding method; the upper film layer is also attached to the bottom of the substrate frame by a detachable bonding method, and then the encapsulant is filled. Here, detachable means that it can be attached to the corresponding part and can also be removed, so as to facilitate use before and after filling the encapsulant. Both the upper film and the lower film are made of polyimide film. The polyimide film is heat-resistant and easy to remove. The upper film can effectively protect the electroplated part from being covered by the encapsulant, and the lower film can protect the back of the bottom of the substrate frame from being covered by the encapsulant. Before welding the inductor to the NiPdAu electroplated layer, the upper film or the lower film can be removed and then welded. The thickness range of both the upper film and the lower film is 20 microns - 75 microns. Strictly controlling the thickness range of the film material not only ensures the protection effect of the film but also facilitates loading and unloading at any time.

[0027] As Figure 4 shown, it is a schematic structural diagram after removing the upper film and the lower film. Since polyimide film is used, it can not only play a protective role but also be easily removed. After removing the film, welding can be carried out at the position where the NiPdAu electroplated layer is located through solder, completing the welding with the inductor and completing the laying of the overall 3D stacking structure.

[0028] In summary, the present utility model realizes the 3D stacking of the inductor and the main control chip through the integrated design of the frame, reduces the traditional PCB interposer layer, effectively reduces the packaging volume; also cancels the traditional electroplated copper column grinding step, and performs welding through the NiPdAu electroplated layer, quickly and efficiently connecting the inductor, reducing costs and improving the yield; combined with the concave height difference design and ramp through holes, etc., it is convenient for welding use and the encapsulation filling is uniform, making the overall product highly reliable and convenient for long-term use, with significant progressiveness.

[0029] The above embodiments are only for illustrating the technical concept of this utility model and should not be construed as limiting the scope of protection of this utility model. Any modifications made to the technical solution based on the technical concept proposed by this utility model shall fall within the scope of protection of this utility model.

Claims

1. A structure for supporting inductance and master chip stacking based on frame and package design, characterized in that, Includes substrate frame, upper film, lower film, main control chip, and molding compound: The substrate frame includes a first support layer, a second support layer, and multiple mounting layers. The bottom ends of the first and second support layers are parallel and serve as the bottom of the substrate frame. The top ends of the first and second support layers are parallel and serve as the top of the substrate frame. The multiple mounting layers are parallel to each bottom end. Each top end of the first and second support layers is provided with an electroplating point, and each electroplating point is soldered with an inductor. The main control chip is flip-chip soldered onto at least two mounting layers; molding compound fills the gaps in the substrate frame; The lower film is attached to the bottom of the substrate frame using a removable bonding method; the upper film layer is also attached to the bottom of the substrate frame using a removable bonding method.

2. The structure of claim 1, wherein the structure is designed to support the inductor and the main control chip stacked based on a frame and package design. Each of the first and second support layers has a recessed area at its top end. The positions outside the recessed areas at each top end are designated as non-recessed areas. Each non-recessed area is used to set the corresponding electroplating area. There is a height difference between each recessed area and each adjacent non-recessed area.

3. The structure of claim 1, wherein the structure is designed to support the inductor and the main control chip stacked based on a frame and package design. The first and second support layers have the same structure. Each top and corresponding bottom are connected by a corresponding ramp, and each ramp is provided with a recessed through hole.

4. The structure of claim 3, wherein the structure is characterized by, Each through-hole is located in the center of each slope.

5. The structure of claim 1, wherein the structure is designed to support the inductor and the main control chip stacked based on a frame and package design. The first support layer, the second support layer, and multiple mounting layers are all made of copper.

6. The structure of claim 1, wherein the structure is designed to support the inductor and the main chip stacked based on a frame and package design. Each electroplating area is a NiPdAu electroplated layer.

7. The structure of claim 3, wherein the structure is designed to support the inductor and the main control chip stacked based on a frame and package design. The distance between the two bottom ends is greater than the distance between the two top ends. Also, let A, 45°, be the acute angle formed by each slope and the bottom. <A<60°。 8. The structure of claim 1, wherein the structure is designed to support the inductor and the main chip stacked based on a frame and package design. The molding compound is epoxy resin.

9. The structure of claim 1, wherein the structure is designed to support the inductor and the main chip stacked based on a frame and package design. Both the upper and lower membranes are polyimide membranes.

10. The structure of claim 1, wherein the structure is designed to support the inductor and the main chip stacked based on a frame and package design. The thickness of both the upper and lower membranes ranges from 20 micrometers to 75 micrometers.

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