Quasi-super junction trench gate silicon carbide VDMOS and preparation method thereof

Abstract

The invention provides a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; a barrier layer is formed above the drift layer, etching and ion implantation are carried out, a plurality of N-type regions, a plurality of P-type masking regions, a P-type well region, an N-type source region and a P-type source region are formed, the barrier layer is formed again, etching and oxidation are carried out to form a gate dielectric layer, and a groove is formed in the gate dielectric layer; and forming a barrier layer again, etching, depositing metal, forming a gate metal layer and a source metal layer, and removing the barrier layer to complete preparation. An N-type region and a masking region are constructed in the device, so that a transverse and longitudinal combined quasi super junction voltage-withstanding structure is formed to improve the voltage-withstanding capability of the device, and meanwhile, the N-type region can reduce the on resistance of the device.

Description

Technical Field

[0001] The invention relates to a quasi-super junction trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] As an outstanding representative of silicon carbide power devices, silicon carbide vertical bipolar metal oxide semiconductor field effect transistor (VDMOS) plays a vital role in many fields such as electric vehicles, aerospace and power conversion. For silicon carbide power MOSFET, different application fields have different requirements for its performance, but in general, they all pursue the following characteristics: higher voltage resistance to cope with extreme voltage conditions; lower on-resistance to reduce energy loss; faster switching speed to improve efficiency; higher reliability, including gate stability, tolerance to drain voltage shocks and robustness under short-circuit conditions; and lower body diode conduction losses to optimize overall energy efficiency. The improvement of these comprehensive performance is the technical goal that silicon carbide power MOSFET is constantly pursuing. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a quasi-superjunction trench gate silicon carbide VDMOS and a preparation method thereof, wherein an N-type region and a masking region are constructed inside the device, thereby forming a quasi-superjunction voltage-withstand structure that combines horizontal and vertical elements to improve the voltage-withstand capability of the device. At the same time, the N-type region can reduce the on-resistance of the device.

[0004] In a first aspect, the present invention provides a method for preparing a quasi-superjunction trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer;

[0006] Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form a plurality of N-type regions;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form multiple P-type masking areas;

[0008] Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region. The ion implantation energy is 70-170kev.

[0009] Step 5, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form an N-type source region, with the ion implantation energy being 70-130kev;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form a P-type source region. The ion implantation energy is 70-130kev.

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to form a groove, and oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal into the groove to form a gate metal layer;

[0013] Step 9, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention provides a quasi-super junction trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a quasi-super junction trench gate silicon carbide VDMOS according to the first aspect.

[0015] The advantages of the present invention are:

[0016] 1. Optimization of voltage-resistant structure: By constructing N-type area and P-type masking area, the vertical pn junction voltage-resistant structure of traditional devices is transformed into a structure in which the vertical pn junction and the horizontal pn junction jointly bear the voltage-resistant structure. This design effectively improves the voltage-resistant capability of the device while keeping the silicon wafer thickness and lateral conditions unchanged, realizes the quasi-super junction structure, and thus enhances the electrical performance of the device.

[0017] 2. Reduction of on-resistance: The N-type region in the trench gate structure not only transforms the device's withstand voltage structure, but also successfully reduces the device's on-resistance by appropriately increasing the doping concentration of the N-type drift layer. This improvement helps to improve the device's energy efficiency and reduce energy loss.

[0018] 3. Enhanced gate reliability: While constructing a quasi-superjunction structure, the P-type masking area of ​​the device is specially designed with a part of the structure located at the gate corner at the bottom of the trench gate. This design effectively solves the gate reliability problem caused by electric field concentration, and consistently improves the electrical performance at the bottom of the trench gate, thereby enhancing the overall reliability of the device.

[0019] The trench gate device of the present invention achieves a dual improvement in voltage resistance and conduction performance while maintaining a compact structure, providing a more reliable solution for the application of high-voltage power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0021] Figure 1 The schematic diagram of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention.

[0022] Figure 2 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 1 .

[0023] Figure 3 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 2 .

[0024] Figure 4 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 3 .

[0025] Figure 5 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 4 .

[0026] Figure 6 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 5 .

[0027] Figure 7 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 6 .

[0028] Figure 8 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 7 .

[0029] Fig. 9 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 8 .

[0030] Fig.10 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 9 .

[0031] Fig.11 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 10 .

[0032] Fig.12 A cross-sectional view of the process of a quasi-superjunction trench gate silicon carbide VDMOS of the present invention Figure 10 one. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a quasi-superjunction trench gate silicon carbide VDMOS, comprising the following steps:

[0039] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 7; epitaxially growing on the upper side of the silicon carbide substrate 1 to form a drift layer 2;

[0040] Step 2, forming a barrier layer 8 on the drift layer 2, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of N-type regions 21;

[0041] Step 3, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form through holes, and performing ion implantation into the drift layer 2 to form a plurality of P-type masking regions 22;

[0042] Step 4, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, and perform ion implantation into the drift layer 2 to form a P-type well region 3, the ion implantation energy is 70-170kev;

[0043] Step 5, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, perform ion implantation into the P-type well region 3 to form an N-type source region 31, and the ion implantation energy is 70-130kev;

[0044] Step 6, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and performing ion implantation into the P-type well region 3 to form a P-type source region 32, the ion implantation energy is 70-130kev;

[0045] Step 7, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, etching the drift layer 2 to form a groove 23, and oxidizing to form a gate dielectric layer 4, wherein the gate dielectric layer 4 is provided with a groove 41;

[0046] Step 8, removing the original barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing metal into the groove 41, and forming a gate metal layer 5;

[0047] Step 9, remove the original barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, etch the drift layer 2 to the upper side of the P-type well region 3, deposit metal to form a source metal layer 6, remove the barrier layer 8, and complete the preparation.

[0048] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0049] Silicon carbide substrate 1,

[0050] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, and a plurality of N-type regions 21 are evenly spaced at the lower part of the drift layer 2; a plurality of P-type masking regions 22 are evenly spaced at the upper part of the drift layer 2, and the lower side of each of the N-type regions 21 is connected to the upper side of the silicon carbide substrate 1, and a groove 23 is provided on the drift layer 2;

[0051] A P-type well region 3, wherein the lower side of the P-type well region 3 is connected to the upper side of the drift layer 2 and the upper side of the P-type masking region 22, and an N-type source region 31 and a P-type source region 32 are provided in the P-type well region 3, and the P-type source region 32 is connected to the N-type source region 31;

[0052] A gate dielectric layer 4, wherein the lower portion of the gate dielectric layer 4 is disposed in the groove 23, the lower side of the gate dielectric layer 4 is respectively connected to the upper side of the drift layer 2 and the upper side of the P-type shielding region 22; the outer side of the gate dielectric layer 4 is respectively connected to the inner side of the P-type well region 3 and the inner side of the N-type source region 31; a groove 41 is disposed in the gate dielectric layer 4;

[0053] A gate metal layer 5, wherein the gate metal layer 5 is disposed in the groove 41;

[0054] A source metal layer 6, wherein the source metal layer 5 is respectively connected to the P-type well region 3, the P-type source region 32 and the N-type source region 31;

[0055] and a drain metal layer 7 , wherein the drain metal layer 7 is connected to the lower side of the silicon carbide substrate 1 .

[0056] In this embodiment, preferably, the P-type masking region 22 is not located directly above the N-type region 21, the lower side of each P-type masking region 22 and the upper side of each N-type region 21 are located in the same plane, and the doping concentrations of the P-type masking region 22 and the N-type region 21 are both greater than the doping concentration of the drift layer 2.

[0057] In this embodiment, preferably, the number of the P-type masking regions 22 is 4, wherein the upper side surfaces of two P-type masking regions 22 are connected to the lower side surface of the P-type well region 3, and the upper side surfaces of the other two P-type masking regions 22 are connected to the lower side surface of the gate dielectric layer 4, and these two P-type masking regions 22 are located on both sides of the bottom of the gate dielectric layer 4.

[0058] In this embodiment, preferably, the thickness of the N-type region 21 is 60%-80% of the thickness of the drift layer 2; the thickness of the P-type masking region 22 is 20%-40% of the thickness of the drift layer 2; and the sum of the thickness of the N-type region 21 and the thickness of the P-type masking region 22 is equal to the thickness of the drift layer 2.

[0059] In this embodiment, preferably, the thickness of the bottom of the gate dielectric layer 4 is less than or equal to the depth of the groove 23 .

[0060] In another embodiment of the present invention, the silicon carbide substrate 1 and the drift layer 2 are both N-type; the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 1-5e17cm -3 , the doping concentration of the N-type region 21 is 0.8-1.2e18cm -3 , the doping concentration of the P-type masking region 22 is 1-5e18cm -3 , the doping concentration of P-type well region 3 is 1-3e17 cm -3 The gate dielectric layer is silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm -3 , the doping concentration of the P-type source region 32 is 6-1.2e19cm -3 ; The concentration of the N-type silicon carbide substrate 1 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 7, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and the on-resistance of the device; the doping concentration of the N-type region 21 is to lead the potential of the silicon carbide substrate 1 upward to achieve a quasi-super junction structure of the device; the doping concentration of the P-type masking region 22 is to form a quasi-super junction structure with the N-type region 21, thereby improving the withstand voltage of the device; the P-type well region 3 is to form the longitudinal withstand voltage structure of the device and the gate control structure of the device; the N-type source region 31 and the P-type source region 32 are to form a low-resistance ohmic contact with the source metal layer 6.

[0061] The thickness of the N-type silicon carbide substrate 1 of the device is 1 μm, the thickness of the N-type drift layer 2 is 10-30 μm, and it is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device. The thickness of the N-type region 21 is 60%-80% of the thickness of the N-type drift layer 2, and the thickness of the P-type masking region 22 is 20%-40% of the thickness of the N-type drift layer 2 (under this thickness condition, a gate structure thickness of 600 nm needs to be reserved), the thickness of the N-type source region 31 and the P-type source region 32 is 200 nm, and the thickness of the P-type well region 3 The thickness below the N-type source region 31 and the P-type source region 32 is 100nm, the thickness of the P-type well region 3 is 300nm, the thickness of the bottom of the gate dielectric layer 4 is 50nm, the thickness of the source metal layer 6 is 200nm, and the thickness of the gate metal layer 5 is 550nm; the thickness of the N-type silicon carbide substrate 1 is to form an effective support for the device structure, the N-type drift layer 2 is the main longitudinal voltage-resistant structure of the device, and its thickness directly affects the voltage-resistant capability of the device, the N-type region 21 and the P-type masking region 22 are to form The lateral voltage-withstand structure of the device is formed, and the bottom of the N-type region 21 and the top of the P-type masking region 22 are designed to be at the same height. Due to the error caused by the process, the error shall not exceed 100nm. The P-type well region 3 is to realize the gate control structure of the device while minimizing the impact on the on-resistance of the device; the N-type region 21 and the P-type masking region 22 are constructed in the trench gate device, and the longitudinal pn junction voltage-withstand structure of the traditional device can be converted into a longitudinal pn junction and a transverse pn junction common voltage-withstand structure, so that the voltage-withstand capability of the device can be improved under the same thickness and the same lateral conditions, and a quasi-super junction structure can be realized. In addition to converting the voltage-withstand structure of the device, the N-type region 21 in the trench gate structure can also reduce the on-resistance of the device by partially increasing the doping concentration of the N-type drift layer 2. In addition to constructing the quasi-super junction structure, the P-type masking region 22 of the device also deliberately sets part of the structure at the gate corner at the bottom of the trench gate, which can solve the gate reliability problem caused by the electric field concentration at the bottom of the trench gate.

[0062] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a quasi-superjunction trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the upper side of the silicon carbide substrate to form a drift layer; Step 2: forming a barrier layer above the drift layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form a plurality of N-type regions; Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form through holes, and performing ion implantation into the drift layer to form multiple P-type masking areas; Step 4: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the drift layer to form a P-type well region; Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and performing ion implantation into the P-type well region to form an N-type source region; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation into the P-type well region to form a P-type source region; Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer to form a groove, and oxidizing to form a gate dielectric layer, wherein the gate dielectric layer is provided with a groove; Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing metal into the groove to form a gate metal layer; Step 9, remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

2. The method for preparing a quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, characterized in that: The P-type shielding regions are not located directly above the N-type regions, and the lower side surface of each P-type shielding region and the upper side surface of each N-type region are located in the same plane.

3. The method for preparing a quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentrations of the P-type shielding region and the N-type region are both greater than the doping concentration of the drift layer.

4. The method for preparing a quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, characterized in that: The number of the P-type shielding regions is 4, of which the upper side surfaces of two P-type shielding regions are connected to the lower side surface of the P-type well region, and the upper side surfaces of the other two P-type shielding regions are connected to the lower side surface of the gate dielectric layer, and these two P-type shielding regions are located on both sides of the bottom of the gate dielectric layer.

5. The method for preparing a quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the N-type region is 60%-80% of the thickness of the drift layer; the thickness of the P-type shielding region is 20%-40% of the thickness of the drift layer; the sum of the thickness of the N-type region and the thickness of the P-type shielding region is equal to the thickness of the drift layer.

6. The method for preparing a quasi-superjunction trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the bottom of the gate dielectric layer is less than or equal to the depth of the groove.

7. A quasi-superjunction trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 6.

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