Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel driving circuit, the pixel driving circuit comprises a silicon semiconductor transistor, an oxide transistor and a storage capacitor which are electrically connected, and the display panel comprises a first active layer, a first gate layer and a second active layer which are sequentially arranged in a stacked mode. A grid electrode of the oxide transistor, a grid electrode of the silicon semiconductor transistor and a first pole plate of the storage capacitor are located on a first grid electrode layer, an active pattern of the oxide transistor and a second pole plate of the storage capacitor are located on a second active layer, and the first grid electrode layer can be adopted to form a bottom grid of the oxide transistor. The active pattern of the transistor in the second active layer is prevented from being influenced by light, so that the photosensitivity and the electrical property of the transistor are improved, the performance of the display panel is improved, and the electrical property improvement effect of the oxide transistor is good due to the fact that the distance between the first gate layer and the second active layer is small.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen-to-body ratio are getting higher and higher. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will adopt low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors at the same time, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current. However, the existing display devices using LTPO technology have a large number of film layers, and the corresponding number of required masks is large, resulting in a more complex process and higher cost. In order to reduce the number of mask plates, existing display devices will remove some gate layers and insulating layers, but this will cause the bottom gate of the oxide thin-film transistor to be missing, and the photosensitivity and electrical properties of the thin-film transistor will deteriorate. In order to improve the electrical properties of the oxide thin-film transistor, the existing technology will use some film layers to form the bottom gate of the oxide thin-film transistor, but there will be some problems, for example, some film layers are too far away from the active layer of the oxide thin-film transistor, resulting in a small effect of the bottom gate.

[0003] Therefore, existing display devices using LTPO technology have technical problems such as poor photosensitivity and electrical properties caused by the absence of the bottom gate of the oxide thin film transistor. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem of poor photosensitivity and electrical properties caused by the bottom gate loss of oxide thin film transistors in existing display devices using LTPO technology.

[0005] In order to achieve the above-mentioned object, according to a first aspect of the present application, a display panel is provided, the display panel comprising a pixel driving circuit, the pixel driving circuit comprising a silicon semiconductor transistor, an oxide transistor and a storage capacitor which are electrically connected;

[0006] The display panel includes a first active layer, a first gate layer and a second active layer stacked in sequence, the active pattern of the silicon semiconductor transistor is located in the first active layer, a gate of the oxide transistor, a gate of the silicon semiconductor transistor and a first electrode plate of the storage capacitor are located in the first gate layer, and the active pattern of the oxide transistor and the second electrode plate of the storage capacitor are located in the second active layer.

[0007] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0008] The embodiments of the present application provide a display panel and a display device; the display panel includes a pixel driving circuit, the pixel driving circuit includes an electrically connected silicon semiconductor transistor, an oxide transistor and a storage capacitor, the display panel includes a first active layer, a first gate layer and a second active layer stacked in sequence, a gate of the oxide transistor, a gate of the silicon semiconductor transistor and a first electrode plate of the storage capacitor are located in the first gate layer, the active pattern of the oxide transistor and the second electrode plate of the storage capacitor are located in the second active layer, then the first gate layer can be used to form the bottom gate of the oxide transistor to prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor, improving the performance of the display panel, and because the distance between the first gate layer and the second active layer is small, the electrical property improvement effect of the oxide transistor is better.

[0009] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0011] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0012] Figure 1 A schematic diagram of a first comparative display device provided in an embodiment of the present application.

[0013] Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application.

[0014] Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application.

[0015] Figure 4 A schematic diagram of a fourth comparative display device provided in an embodiment of the present application.

[0016] Figure 5 for Figure 1 The comparison in the figure shows the stack-up diagram of each film layer of the device and the exploded diagram of some film layers.

[0017] Figure 6 A schematic diagram of a first film layer of a display panel provided in an embodiment of the present application.

[0018] Figure 7 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0019] Figure 8 This is a first stacking diagram of various film layers of the display panel provided in an embodiment of the present application.

[0020] Fig. 9 for Figure 8 Exploded view of the light shielding layer of the display panel.

[0021] Fig.10 for Figure 8 Exploded view of the first active layer of the display panel in FIG.

[0022] Fig.11 for Figure 8 An exploded view of the first gate layer of the display panel in FIG.

[0023] Fig.12 for Figure 8 Exploded view of the second active layer of the display panel in FIG.

[0024] Fig.13 for Figure 8 An exploded view of the second gate layer of the display panel in FIG.

[0025] Fig.14 for Figure 8 An exploded view of the first source-drain layer of the display panel in FIG.

[0026] Fig.15 for Figure 8 An exploded view of the second source-drain layer of the display panel in FIG.

[0027] Fig.16 for Figure 8 Exploded view of the first via hole of the display panel.

[0028] Fig.17 for Figure 8 Exploded view of the second via hole of the display panel.

[0029] Fig.18 for Figure 8 An exploded view of the third via hole of the display panel in FIG.

[0030] Fig.19 for Figure 8 An exploded view of the fourth via hole of the display panel in FIG.

[0031] Fig. 20 for Figure 8A stacking diagram of a light shielding layer, a first active layer and a first gate layer of a display panel in FIG.

[0032] Fig.21 for Figure 8 A stacking diagram of a light shielding layer, a first active layer, a first gate layer and a second active layer of a display panel.

[0033] Fig. 22 for Figure 8 A stacking diagram of a light shielding layer, a first active layer, a first gate layer, a second active layer and a second gate layer of a display panel.

[0034] Fig.23 for Figure 8 A stacked diagram of a light shielding layer, a first active layer, a first gate layer, a second active layer, a second gate layer and a first source and drain layer of a display panel.

[0035] Fig.24 A schematic diagram of a second film layer of a display panel provided in an embodiment of the present application.

[0036] Fig.25 This is a second stacking diagram of the film layers of the display panel provided in the embodiment of the present application.

[0037] Fig.26 for Fig.25 A stacking diagram of the first active layer and the first gate layer of the display panel.

[0038] Fig. 27 for Fig.25 A stacking diagram of a first active layer, a first gate layer and a second active layer of a display panel in FIG.

[0039] Fig.28 for Fig.25 A stacking diagram of a first active layer, a first gate layer, a second active layer and a second gate layer of a display panel.

[0040] Fig.29 for Fig.25 A stacked diagram of a first active layer, a first gate layer, a second active layer, a second gate layer and a first source and drain layer of a display panel. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0042] Figure 1A schematic diagram of a first comparative display device provided in an embodiment of the present application. Figure 2 A schematic diagram of a second comparative display device provided in an embodiment of the present application. Figure 3 A schematic diagram of a third comparative display device provided in an embodiment of the present application. Figure 4 A schematic diagram of a fourth comparative display device provided in an embodiment of the present application. Figure 5 for Figure 1 The comparison in the figure shows the stack-up diagram of each film layer of the device and the exploded diagram of some film layers.

[0043] As an introduction to the embodiments of the present application, some comparative display devices are provided to illustrate the principle of the technical problem to be solved by the embodiments of the present application. Figure 1 As shown, a comparative display device using LTPO technology includes a substrate 101, a light shielding film 102, a barrier film 103, a buffer film 104, a low-temperature polysilicon film 105, a first gate insulating film 106, a first gate film 107, a second gate insulating film 108, a second gate film 109, a first interlayer insulating film 111, an oxide semiconductor film 112, a third gate insulating film 113, a third gate film 114, a second interlayer insulating film 115, a first source-drain film 116, a first planarizing film 117, a second source-drain film 118, a second planarizing film 119, a third source-drain film 121, a third planarizing film 122, an anode film 123, a pixel definition film 124, and a support film 125. Figure 1 It can be seen that the comparative display device includes three layers of source and drain films and three layers of gate films, so that the comparative display device needs to be formed using 16 mask plates, the process is relatively complex and the cost is relatively high.

[0044] Specifically, Figure 5 As shown, Figure 5 (a) in Figure 1 The comparison in the display device shows the stacking diagram of each film layer. Figure 5 (b) in Figure 5 A magnified view of a portion of (a) in FIG. Figure 5 (c) in Figure 5 The exploded view of the light-shielding film in (a) is shown in FIG. Figure 5It can be seen that for the comparative display device having the first gate film 107, the second gate film 109 and the third gate film 114, the shading film 102 is used as the bottom gate of the driving thin film transistor T01, and parts of the second gate film 109 and the third gate film 114 are used as the top gate and bottom gate of the compensation thin film transistor T03, respectively. Parts of the second gate film 109 and the third gate film 114 are used as the top gate and bottom gate of the first initialization thin film transistor T04, respectively, and the top gate and bottom gate of the compensation thin film transistor T03 are connected together, and the top gate and bottom gate of the first initialization thin film transistor T04 are connected together. However, this requires the existence of three layers of gate films, and a large number of mask plates are required.

[0045] In order to solve the problem of complex process of the comparative display device, another comparative display device removes one layer of the gate film and the insulating film, such as Figure 2 As shown, it can be seen that the second gate film 109 and the second gate insulating film 108 are removed from the comparative display device, so that the number of mask plates can be reduced to 14, but there are still problems such as a large number of mask plates, a complex process, and a high cost.

[0046] In order to solve the problem of complex process of the comparative display device, another comparative display device further removes a layer of source and drain film and insulating film, such as Figure 3 As shown in FIG. 1 , by removing the third source-drain film 121 and the third planarization film 122, the number of mask plates can be reduced to 13; Figure 2 , Figure 3 It can be seen that there is no shielding under the oxide semiconductor film 112, resulting in the loss of the bottom gate of the oxide thin film transistor, and the photosensitivity and electrical properties of the thin film transistor are deteriorated. Therefore, the existing display devices using LTPO technology have the technical problem of poor photosensitivity and electrical properties caused by the loss of the bottom gate of the oxide thin film transistor.

[0047] Even in some comparative display devices, in order to solve the problem of bottom gate missing of oxide thin film transistors existing in the comparative display devices, a light shielding film is used to shield the oxide semiconductor film, such as Figure 4 As shown, it can be seen that a light shielding film 102 is provided under the oxide semiconductor film 112, but this will cause the light shielding film to be only connected horizontally but not vertically, which will cause the impedance of the light shielding film to gradually increase from both sides to the middle, which will cause differences in the electrical properties of the low-temperature polysilicon thin-film transistor, resulting in poor display, that is, it will introduce new problems, and the distance between the light shielding film and the oxide semiconductor film is large, the bottom gate effect is poor, and the light shielding effect is relatively poor. Therefore, the existing display devices using LTPO technology have technical problems such as poor photosensitivity and electrical properties caused by the lack of the bottom gate of the oxide thin-film transistor.

[0048] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0049] Figure 6 A schematic diagram of a first film layer of a display panel provided in an embodiment of the present application. Figure 7 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Figure 8 This is a first stacking diagram of various film layers of the display panel provided in an embodiment of the present application. Fig. 9 for Figure 8 Exploded view of the light shielding layer of the display panel. Fig.10 for Figure 8 Exploded view of the first active layer of the display panel in FIG. Fig.11 for Figure 8 An exploded view of the first gate layer of the display panel in FIG. Fig.12 for Figure 8 Exploded view of the second active layer of the display panel in FIG. Fig.13 for Figure 8 An exploded view of the second gate layer of the display panel in FIG. Fig.14 for Figure 8 An exploded view of the first source-drain layer of the display panel in FIG. Fig.15 for Figure 8 An exploded view of the second source-drain layer of the display panel in FIG. Fig.16 for Figure 8 Exploded view of the first via hole of the display panel. Fig.17 for Figure 8 Exploded view of the second via hole of the display panel. Fig.18 for Figure 8 An exploded view of the third via hole of the display panel in FIG. Fig.19 for Figure 8 An exploded view of the fourth via hole of the display panel in FIG. Fig. 20 for Figure 8 A stacking diagram of a light shielding layer, a first active layer and a first gate layer of a display panel in FIG. Fig.21 for Figure 8 A stacking diagram of a light shielding layer, a first active layer, a first gate layer and a second active layer of a display panel. Fig. 22 for Figure 8 A stacking diagram of a light shielding layer, a first active layer, a first gate layer, a second active layer and a second gate layer of a display panel. Fig.23 for Figure 8 A stacked diagram of a light shielding layer, a first active layer, a first gate layer, a second active layer, a second gate layer and a first source and drain layer of a display panel. Fig.24 A schematic diagram of a second film layer of a display panel provided in an embodiment of the present application. Fig.25 This is a second stacking diagram of the film layers of the display panel provided in the embodiment of the present application. Fig.26for Fig.25 A stacking diagram of the first active layer and the first gate layer of the display panel. Fig. 27 for Fig.25 A stacking diagram of a first active layer, a first gate layer and a second active layer of a display panel in FIG. Fig.28 for Fig.25 A stacking diagram of a first active layer, a first gate layer, a second active layer and a second gate layer of a display panel. Fig.29 for Fig.25 A stacked diagram of a first active layer, a first gate layer, a second active layer, a second gate layer and a first source and drain layer of a display panel.

[0050] like Figures 6 to 29 As shown, an embodiment of the present application provides a display panel 2 , which includes a substrate 201 and a driving circuit layer 22 disposed on one side of the substrate 201 , and the driving circuit layer 22 includes a pixel driving circuit 31 .

[0051] Specifically, the driving circuit layer 22 includes a first active layer 205, a first gate layer 207, a second active layer 209, a second gate layer 212, a first source-drain layer 214 and a second source-drain layer 216. The first active layer 205 is arranged on one side of the substrate 201, the first gate layer 207 is arranged on a side of the first active layer 205 away from the substrate 201, the second active layer 209 is arranged on a side of the first gate layer 207 away from the first active layer 205, the second gate layer 212 is arranged on a side of the second active layer 209 away from the first gate layer 207, the first source-drain layer 214 is arranged on a side of the second gate layer 212 away from the second active layer 209, and the second source-drain layer 216 is arranged on a side of the first source-drain layer 214 away from the second gate layer 212.

[0052] In some embodiments, Figures 6 to 29 As shown, the display panel 2 includes a pixel driving circuit 31, and the pixel driving circuit 31 includes an electrically connected silicon semiconductor transistor (such as a driving transistor T1), an oxide transistor (such as a compensation transistor T3) and a storage capacitor Cst;

[0053] In which, the display panel 2 includes a first active layer 205, a first gate layer 207 and a second active layer 209 which are stacked in sequence, the active pattern of the silicon semiconductor transistor (for example, the active pattern T1A of the driving transistor T1) is located in the first active layer 205, a gate of the oxide transistor (for example, the first gate T3Ga of the compensation transistor T3), a gate of the silicon semiconductor transistor (for example, the gate T1G of the driving transistor T1) and the first electrode plate of the storage capacitor Cst are located in the first gate layer 207, and the active pattern of the oxide transistor and the second electrode plate of the storage capacitor Cst are located in the second active layer 209.

[0054] An embodiment of the present application provides a display panel, which includes a pixel driving circuit, the pixel driving circuit includes an electrically connected silicon semiconductor transistor, an oxide transistor and a storage capacitor, the display panel includes a first active layer, a first gate layer and a second active layer stacked in sequence, a gate of the oxide transistor, a gate of the silicon semiconductor transistor and a first electrode plate of the storage capacitor are located in the first gate layer, the active pattern of the oxide transistor and the second electrode plate of the storage capacitor are located in the second active layer, and the first gate layer can be used to form a bottom gate of the oxide transistor to prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor, and improving the performance of the display panel. Moreover, since the distance between the first gate layer and the second active layer is small, the electrical property improvement effect of the oxide transistor is better.

[0055] In some embodiments, Figures 6 to 29 As shown, the pixel driving circuit 31 includes a switch transistor T2, a driving transistor T1, a compensation transistor T3 and a first initialization transistor T4, the switch transistor T2 and the driving transistor T1 are connected to a first node A; one electrode of the compensation transistor T3, one electrode of the first initialization transistor T4 and the driving transistor T1 are connected to a second node Q, and the other electrode of the compensation transistor T3 and the driving transistor T1 are connected to a third node B;

[0056] Among them, the switching transistor T2 and the driving transistor T1 are silicon semiconductor transistors, the compensation transistor T3 and the first initialization transistor T4 are oxide transistors, the first gate layer 207 includes the gate T1G of the driving transistor T1, the gate T2G of the switching transistor T2, the first gate T3Ga of the compensation transistor T3 and the first gate T4Ga of the first initialization transistor T4; the second active layer 209 includes the active pattern T3A of the compensation transistor T3 and the active pattern T4A of the first initialization transistor T4; the first gate T3Ga of the compensation transistor T3 is set corresponding to the active pattern T3A of the compensation transistor T3, and the first gate T4Ga of the first initialization transistor T4 is set corresponding to the active pattern T4A of the first initialization transistor T4.

[0057] An embodiment of the present application provides a display panel, in which a first gate layer includes a first gate of a compensation transistor and a first gate of a first initialization transistor, a second active layer includes an active pattern of the compensation transistor and an active pattern of the first initialization transistor, the first gate of the compensation transistor is arranged correspondingly to the active pattern of the compensation transistor, and the first gate of the first initialization transistor is arranged correspondingly to the active pattern of the first initialization transistor. The first gate layer can be used to form the bottom gate of the compensation transistor and the first initialization transistor to prevent the active pattern of the transistor in the second active layer from being affected by light, thereby improving the photosensitivity and electrical properties of the transistor, and improving the performance of the display panel. Moreover, since the distance between the first gate layer and the second active layer is small, the electrical properties of the compensation transistor and the first initialization transistor are better improved.

[0058] Specifically, compared with the comparative display device in which a shading film is used to form the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor respectively, and the bottom gate of the compensation transistor and the bottom gate of the first initialization transistor are respectively input with corresponding scanning signals or input with high-potential power supply signal lines, there will be problems that the bottom gate is far away and the bottom gate effect is weak; compared with the comparative display device with three layers of gate film, three mask plates are required to form the three layers of gate film respectively, the embodiment of the present application uses the first gate layer to form the bottom gate of the compensation transistor and the first initialization transistor, which reduces the number of mask plates, improves the bottom gate effect, and improves the electrical properties of the display panel.

[0059] In some embodiments, Figures 6 to 29 As shown, the display panel 2 further includes a high potential power line VDD, and at least one of the first gate T3Ga of the compensation transistor T3 and the first gate T4Ga of the first initialization transistor T4 is connected to the high potential power line VDD. By connecting at least one of the first gate of the compensation transistor and the first gate of the first initialization transistor to the high potential power line, at least one of the first gate of the compensation transistor and the first gate of the first initialization transistor can form a grid structure with the high potential power line, reduce the impedance of the high potential power line, the first gate of the compensation transistor and the first gate of the first initialization transistor, improve the electrical uniformity of the thin film transistor, and avoid at least one of the first gate of the compensation transistor and the first gate of the first initialization transistor being suspended and being interfered by other signals.

[0060] Specifically, the first gate of the compensation transistor can be connected to the high potential power line, so that the first gate of the compensation transistor and the high potential power line form a grid structure, reduce the impedance of the high potential power line and the first gate of the compensation transistor, improve the electrical uniformity of the thin film transistor, and avoid the first gate of the compensation transistor being suspended and being interfered by other signals. The first gate of the first initialization transistor can also be connected to the high potential power line, so that the first gate of the first initialization transistor and the high potential power line form a grid structure, reduce the impedance of the high potential power line and the first gate of the first initialization transistor, improve the electrical uniformity of the thin film transistor, and avoid the first gate of the first initialization transistor being suspended and being interfered by other signals. The first gate of the compensation transistor and the first gate of the first initialization transistor can also be connected to the high potential power line, so that the first gate of the compensation transistor and the first gate of the first initialization transistor can form a grid structure with the high potential power line, reduce the impedance of the high potential power line, the first gate of the compensation transistor and the first gate of the first initialization transistor, improve the electrical uniformity of the thin film transistor, and avoid the first gate of the compensation transistor and the first gate of the first initialization transistor being suspended and being interfered by other signals.

[0061] In some embodiments, Figures 6 to 29 As shown, the gate T2G of the switch transistor T2 is connected to the switch control line Pscan, the first gate layer 207 includes the switch control line Pscan, the switch control line Pscan extends along the first direction X, and in the second direction Y, the first gate T4Ga of the first initialization transistor T4 and the first gate T3Ga of the compensation transistor T3 are arranged on both sides of the switch control line Pscan; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. By arranging the first gate of the first initialization transistor and the first gate of the compensation transistor on both sides of the switch control line, the first gate of the first initialization transistor and the first gate of the compensation transistor can be arranged using the gap in the first gate layer, thereby avoiding reducing the resolution of the display panel.

[0062] In some embodiments, Figures 6 to 29As shown, the display panel 2 further includes a first source-drain layer 214 and a second source-drain layer 216, the first source-drain layer 214 includes a scan connection line SL, the second source-drain layer 216 includes the high potential power line VDD, the scan connection line SL is connected to the first gate T4Ga of the first initialization transistor T4, the scan connection line SL is connected to the first gate T3Ga of the compensation transistor T3, and the scan connection line SL is connected to the high potential power line VDD. By arranging the scan connection line in the first source-drain layer, connecting the first gate of the first initialization transistor, the first gate of the compensation transistor and the high potential power line through the scan connection line, the connection of the high potential power line with the first gate of the first initialization transistor and the first gate of the compensation transistor can be achieved, and the first source-drain layer can be used for switching, so as to avoid occupying other space and reducing the resolution of the display panel.

[0063] In some embodiments, Figure 6 , Figure 8 , Fig.24 , Fig.25 As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, and each of the repeating units 30 includes two pixel driving circuits 31 that are symmetrically arranged.

[0064] Specifically, it can be understood that the display panel may include a plurality of repeating units arranged in an array, and the pixel driving circuit in each repeating unit may refer to the design in a repeating unit described in the embodiment of the present application.

[0065] Specifically, it is understood that in order to illustrate the specific design of a certain film layer or a certain structure, the embodiments of the present application will name each part separately, but it is understood that multiple parts of a certain film layer or a certain structure will be formed at the same time, and when they are connected together, they will transmit the same signal. Multiple parts belonging to the same structure can actually use the same name. For example, Fig. 9 As shown, the light shielding layer 202 includes a light blocking pattern 202a and a connecting line 202b, but in fact, the light blocking pattern 202a and the connecting line 202b are multiple parts of the same structure, and the two are connected to each other. Without considering the voltage drop, the multiple parts of this structure transmit the same signal, and they can be named the same, for example, each part can be named as a part of the light blocking pattern. Similarly, for other film layers and other structures, please refer to the above description, and will not be repeated in the following embodiments.

[0066] like Figure 6 , Fig.24As shown, it can be seen that in the embodiment of the present application, there is only one first gate layer between the first active layer and the second active layer. Compared with the solution in which two gate layers are provided between the first active layer and the second active layer, the number of film layers is reduced, the number of mask plates is reduced, and the preparation efficiency of the display panel is improved.

[0067] In some embodiments, Figure 7 As shown, the pixel driving circuit 31 also includes a first light emitting control transistor T5, a second light emitting control transistor T6, a second initialization transistor T7 and a third initialization transistor T8, an electrode of the first light emitting control transistor T5 and an electrode of the driving transistor T1 are connected to the first node A, an electrode of the second light emitting control transistor T6 and another electrode of the driving transistor T1 are connected to the third node B, an electrode of the second initialization transistor T7 and another electrode of the second light emitting control transistor T6 are connected to a fourth node C, and an electrode of the third initialization transistor T8 and an electrode of the driving transistor T1 are connected to the first node A.

[0068] In some embodiments, Figure 7 As shown, the gate of the switching transistor T2 is connected to the switching control line Pscan, the first electrode of the switching transistor T2 is connected to the data line DATA, and the second electrode of the switching transistor T2 is connected to the first electrode of the driving transistor T1 at the first node A; the gate of the compensation transistor T3 is connected to the compensation control line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the gate of the first initialization transistor T4 is connected to the first initialization control line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q; the pixel driving circuit 31 also includes:

[0069] a first light emission control transistor T5, wherein a gate of the first light emission control transistor T5 is connected to the light emission control signal line EM, a first electrode of the first light emission control transistor T5 is connected to the high potential power line VDD, and a second electrode of the first light emission control transistor T5 is connected to the first electrode of the driving transistor T1 and a first node A;

[0070] A second light emission control transistor T6, wherein a gate of the second light emission control transistor T6 is connected to the light emission control signal line EM, and a first electrode of the second light emission control transistor T6 and a second electrode of the driving transistor T1 are connected to a third node B;

[0071] a second initialization transistor T7, wherein a gate of the second initialization transistor T7 is connected to a second initialization control line Pscan2, a first electrode of the second initialization transistor T7 is connected to a second initialization signal line VI-ANO, and a second electrode of the second initialization transistor T7 and a second electrode of the second light emission control transistor T6 are connected to a fourth node C;

[0072] a third initialization transistor T8, wherein a gate of the third initialization transistor T8 is connected to the second initialization control line Pscan2, a first electrode of the third initialization transistor T8 is connected to a third initialization signal line VI3, and a second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 to a first node A;

[0073] A storage capacitor Cst, one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q;

[0074] A boost capacitor Cboost, one plate of the boost capacitor Cboost is connected to the switch control line Pscan, and the other plate of the boost capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0075] Specifically, Figure 6 , Figure 7 , Fig.24 As shown, the display panel 2 also includes a light-emitting layer 23, which includes a light-emitting device LED. The light-emitting device LED is connected to the pixel driving circuit, the positive electrode of the light-emitting device LED is connected to the second electrode of the second initialization transistor T7, and the negative electrode of the light-emitting device LED is connected to the low potential power line VSS.

[0076] Specifically, the first light emission control transistor T5 , the second light emission control transistor T6 , the second initialization transistor T7 and the third initialization transistor T8 are silicon semiconductor transistors.

[0077] In some embodiments, Figure 6 , Fig.24 As shown, the driving circuit layer 22 further includes a second gate layer 212, a first source-drain electrode layer 214, and a second source-drain electrode layer 216. The second gate layer 212 is disposed between the second active layer 209 and the first source-drain electrode layer 214, and the first source-drain electrode layer 214 is disposed between the second gate layer 212 and the second source-drain electrode layer 216. By making the driving circuit layer include the first gate layer, the second gate layer, the first source-drain electrode layer, and the second source-drain electrode layer, the process steps of the display panel can be reduced, and the mask plates required to form the display panel can be reduced.

[0078] In some embodiments, Figure 6 , Figure 8 As shown, the driving circuit layer 22 further includes a light shielding layer 202, which is disposed between the substrate 201 and the first active layer 205. By providing the light shielding layer, the active pattern of the thin film transistor can be shielded by the light shielding layer to prevent light from irradiating the active pattern of the thin film transistor and affecting the performance of the thin film transistor.

[0079] In some embodiments, Fig.24 , Fig.25 As shown, the display panel 2 is not provided with a light shielding layer. By making the display panel not include a light shielding layer, the number of mask plates can be further reduced.

[0080] Specifically, Figures 6 to 9 As shown, the driving circuit layer 22 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two symmetrically arranged pixel driving circuits 31, and within the repeating unit 30, the light shielding layer 202 includes two light blocking patterns 202a and connecting lines 202b symmetrically arranged in the corresponding areas of the two pixel driving circuits 31, and the light blocking patterns 202a are arranged corresponding to the active patterns of the driving transistors T1. By making the light shielding layer include light blocking patterns and connecting lines, the electrical properties of the light shielding layer can be improved by realizing gridding of the light shielding layer, and the light blocking patterns can shield the active patterns of the driving transistors to prevent light from affecting the electrical properties of the driving transistors, thereby improving the electrical properties of the driving transistors.

[0081] In some embodiments, Figures 6 to 8 , Fig.10 , Figure 24 to Figure 25As shown, the first active layer 205 includes an active pattern T1A of a driving transistor T1, an active pattern T2A of a switching transistor T2, an active pattern T5A of a first light-emitting control transistor T5, an active pattern T6A of a second light-emitting control transistor T6, an active pattern T7A of a second initialization transistor T7, and an active pattern T8A of a third initialization transistor T8, the active pattern T1A of the driving transistor T1 is arranged along a first direction X, and the active pattern T1A of the driving transistor T1 is connected to the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6, the active pattern T2A of the switching transistor T2 is connected to the active pattern T5A of the first light-emitting control transistor T5, and the active pattern T6A of the second light-emitting control transistor T6. T5A is arranged along the second direction Y, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7 are arranged along the second direction Y, and the active pattern T6A of the second light-emitting control transistor T6 is connected to the active pattern T7A of the second initialization transistor T7, the active pattern T8A of the third initialization transistor T8 is arranged at intervals with the active pattern T1A of the driving transistor T1, the active pattern T2A of the switching transistor T2, the active pattern T5A of the first light-emitting control transistor T5, the active pattern T6A of the second light-emitting control transistor T6 and the active pattern T7A of the second initialization transistor T7; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0082] In some embodiments, Figures 6 to 29 As shown, the gate T2G of the switching transistor T2 is connected to the switching control line Pscan, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q, the gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, and the gate of the second initialization transistor T7 is connected to the second initialization control line Pscan2;

[0083] In some embodiments, Figures 6 to 8 , Fig.11 , Figure 24 to Figure 25As shown, the first gate layer 207 includes the first initialization signal line VI-G, the first gate T4Ga of the first initialization transistor T4, the switch control line Pscan, the first gate T3Ga of the compensation transistor T3, the first plate Cst1 of the storage capacitor Cst, the light-emitting control signal line EM and the second initialization control line Pscan2, the first initialization signal line VI-G, the switch control line Pscan, the light-emitting control signal line EM and the second initialization control line Pscan2 all extend along the first direction X, the first initialization signal line VI-G, the first gate T4Ga of the first initialization transistor T4, the switch control line Pscan, the first gate T3Ga of the compensation transistor T3, the first plate Cst1 of the storage capacitor Cst, the light-emitting control signal line EM and the second initialization control line Pscan2 are arranged in sequence along the second direction Y; the angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0084] Specifically, Fig.11 As shown, the first gate layer 207 also includes a gate T1G of the driving transistor T1, a gate T2G of the switching transistor T2, a gate T5G of the first light-emitting control transistor T5, a gate T6G of the second light-emitting control transistor T6, a gate T7G of the second initialization transistor T7, and a gate T8G of the third initialization transistor T8.

[0085] Specifically, from Fig.11 It can be seen that the gate T2G of the switch transistor T2 is a part of the switch control line Pscan. It can be understood that since the gates T2G of all the switch transistors T2 in a row of pixel units are connected to the same switch control line Pscan, when the switch control line Pscan is formed, the portion of the switch control line corresponding to the channel of the switch transistor T2 of each pixel unit serves as the gate of the switch transistor T2 of each pixel unit. Therefore, the same structure is identified by two reference numerals. Similarly, the gate T1G of the driving transistor T1 serves as both the gate and the first plate Cst1 of the storage capacitor Cst, the portion of the light emitting control signal line EM corresponding to the channel of the first light emitting control transistor T5 serves as the gate T5G of the first light emitting control transistor T5, the portion of the light emitting control signal line EM corresponding to the channel of the second light emitting control transistor T6 serves as the gate T6G of the second light emitting control transistor T6, the portion of the second initialization control line Pscan2 corresponding to the channel of the second initialization transistor T7 serves as the gate T7G of the second initialization transistor T7, and the portion of the second initialization control line Pscan2 corresponding to the channel of the third initialization transistor T8 serves as the gate T8G of the third initialization transistor T8.

[0086] Specifically, Fig. 20 As shown in FIG. 1 , the relative positions of the various structures when the light shielding layer, the first active layer and the first gate layer overlap can be seen. Fig.26 As shown in FIG. 1 , the relative positions of the structures when the first active layer and the first gate layer overlap can be seen. Figures 6 to 8 , Fig.12 , Figure 24 to Figure 25 As shown, the driving circuit layer 22 further includes a second active layer 209, the second active layer 209 includes an active pattern T3A of the compensation transistor T3, an active pattern T4A of the first initialization transistor T4, and a second plate Cst2 of the storage capacitor Cst, the active pattern T3A of the compensation transistor T3 is connected to the active pattern T4A of the first initialization transistor T4, the second plate Cst2 of the storage capacitor Cst is arranged on one side of the active pattern T3A of the compensation transistor T3 along the first direction X, and a through hole 331 is provided on the second plate Cst2 of the storage capacitor Cst. By forming the second plate of the storage capacitor with the second active layer, a storage capacitor can be provided in the pixel driving circuit, and a through hole is provided on the second plate of the storage capacitor, so that the first electrode of the compensation transistor can be normally connected to the gate of the driving transistor.

[0087] Specifically, it can be understood that the second active layer forms the second electrode of the storage capacitor. Therefore, it is necessary to make the second electrode of the storage capacitor have better electrical properties. The second electrode of the storage capacitor can be doped to ensure that the electrical properties of the second electrode of the storage capacitor are consistent with or even exceed the electrical properties of the doped portion of the active pattern, so that the electrical properties of the storage capacitor are better.

[0088] Specifically, by providing a through hole on the second electrode plate of the storage capacitor, the first electrode of the compensation transistor can pass through the second electrode plate of the storage capacitor and be connected to the gate of the driving transistor, so that the pixel driving circuit can work normally.

[0089] Specifically, Fig.11 , Fig.12 As shown, the first gate layer 207 also includes a first plate Cboost1 of the boost capacitor Cboost, the second active layer 209 also includes a second plate Cboost2 of the boost capacitor Cboost, the overlapping portion of the switch control line Pscan and the active pattern T4A of the first initialization transistor T4 is the first plate Cboost1 of the boost capacitor Cboost, and the overlapping portion of the active pattern T4A of the first initialization transistor T4 and the switch control line Pscan is the second plate Cboost2 of the boost capacitor Cboost.

[0090] Specifically, Fig.21As shown in FIG. 1 , the relative positions of the various structures when the light shielding layer, the first active layer, the first gate layer and the second active layer overlap can be seen. Fig. 27 As shown, the relative positions of the various structures when the first active layer, the first gate layer and the second active layer overlap can be seen.

[0091] In some embodiments, in some embodiments, as Figures 6 to 29 As shown, the gate of the compensation transistor T3 is connected to the compensation control line Nscan1, the gate of the first initialization transistor T4 is connected to the first initialization control line Nscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 at the first node A.

[0092] In some embodiments, Figures 6 to 8 , Fig.13 , Figure 24 to Figure 25 As shown, the display panel 2 also includes a second gate layer 212, the second gate layer 212 includes the compensation control line Nscan1, the first initialization control line Nscan2, the third initialization signal line VI3, the second gate T3Gb of the compensation transistor T3 and the second gate T4Gb of the first initialization transistor T4, and the first initialization control line Nscan2, the compensation control line Nscan1 and the third initialization signal line VI3 are arranged in sequence along the second direction Y.

[0093] Specifically, the projection of the first gate of the compensation transistor on the substrate may overlap with the projection of the compensation control line on the substrate, thereby reducing the coupling capacitance between the first gate of the compensation transistor and other signal lines. When the first gate of the compensation transistor is coupled with the compensation control line, both transmit the driving signal of the gate of the compensation transistor, which can improve the gate control capability of the compensation transistor.

[0094] Specifically, the projection of the first gate of the first initialization transistor on the substrate may overlap with the projection of the first initialization control line on the substrate, thereby reducing the coupling capacitance between the first gate of the first initialization transistor and other signal lines. When the first gate of the first initialization transistor is coupled to the first initialization control line, both transmit the driving signal of the gate of the first initialization transistor, which can improve the gate control capability of the first initialization transistor.

[0095] Specifically, Figure 8 , Fig.13 , Fig.25As shown, the projection of the third initialization signal line VI3 on ​​the substrate overlaps with the projection of the light-emitting control signal line EM on the substrate. By making the projection of the third initialization signal line on the substrate overlap with the projection of the light-emitting control signal line on the substrate, the light-emitting control signal line can be shielded to prevent parasitic capacitance from being formed between the light-emitting control signal line and the first node, thereby improving the electrical properties of the display panel.

[0096] Specifically, Fig. 22 As shown in FIG. 1 , the relative positions of the various structures when the light shielding layer, the first active layer, the first gate layer, the second active layer and the second gate layer overlap can be seen. Fig.28 As shown, the relative positions of the various structures when the first active layer, the first gate layer, the second active layer and the second gate layer overlap can be seen.

[0097] In some embodiments, Figures 6 to 29 As shown, the first electrode of the switch transistor T2 is connected to the data line, and the second electrode of the switch transistor T2 is connected to the first electrode of the driving transistor T1 at a first node; the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at a second node, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1; the first electrode of the first light-emitting control transistor T5 is connected to the high potential power line VDD, and the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1 at a first node A; the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T1 at a third node B; the first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and the second electrode of the second initialization transistor T7 is connected to the second electrode of the second light-emitting control transistor T6 at a fourth node C; the gate of the third initialization transistor T8 is connected to the second initialization control line Pscan2; one plate of the storage capacitor Cst is connected to the high potential power line VDD, and the other plate of the storage capacitor Cst is connected to the gate of the driving transistor T1 at a second node Q.

[0098] In some embodiments, Figures 6 to 8 , Fig.14 , Figure 24 to Figure 25As shown, the display panel 2 also includes a first source-drain layer 214, which includes a second initialization signal line VI-ANO, a first electrode T2S of the switch transistor T2, a second electrode T2D of the switch transistor T2, a first electrode T3S of the compensation transistor T3, a second electrode T3D of the compensation transistor T3, a first electrode T4S of the first initialization transistor T4, a second electrode T4D of the first initialization transistor T4, a first electrode T5S of the first light-emitting control transistor T5, a second electrode T5D of the first light-emitting control transistor T5, a first electrode T6S of the second light-emitting control transistor T6, a second electrode T6D of the second light-emitting control transistor T6, a first electrode T7S of the second initialization transistor T7, a second electrode T7D of the second initialization transistor T7, a first electrode T8S of the third initialization transistor T8, a second electrode T8D of the third initialization transistor T8 and a scan connection line SL.

[0099] Specifically, Fig.14 As shown, it can be seen that the structure marked by the first electrode T5S of the first light-emitting control transistor T5 will be connected to multiple other structures, the first electrode T5S of the first light-emitting control transistor T5 will be connected to the high-potential power line VDD through the via, and the first electrode T5S of the first light-emitting control transistor T5 will be connected to the second plate of the storage capacitor through the via, and the first electrode T5S of the first light-emitting control transistor T5 will be connected to the active pattern of the first light-emitting control transistor T5 through the via.

[0100] Specifically, Fig.14 As shown, it can be understood that, since the electrodes of each transistor are connected together, in order to improve the aperture ratio in actual design, the electrodes of each transistor will share the same structure. Fig.14 In the figure, multiple reference numerals are used to identify the same structure. For example, a structure serves as both the first electrode T3S of the compensation transistor T3 and the second electrode T4D of the first initialization transistor T4. Figure 7 As can be seen in , this is the location where the second node Q is connected. Similarly, other structures can also serve as multiple electrodes, and the location of each node can be determined accordingly.

[0101] Specifically, since some electrodes and / or signal lines are connected together, only one electrode or one signal line may be marked on a structure. It is understandable that the structure may also be other electrodes or signal lines connected to the electrode or signal line.

[0102] Specifically, Fig.23As shown in FIG. 1 , the relative positions of the various structures when the light shielding layer, the first active layer, the first gate layer, the second active layer, the second gate layer and the first source and drain layer overlap can be seen. Fig.29 As shown, the relative positions of the various structures when the first active layer, the first gate layer, the second active layer, the second gate layer and the first source and drain layer overlap can be seen.

[0103] In some embodiments, Figures 6 to 8 , Fig.15 , Figure 24 to Figure 25 As shown, the display panel 2 also includes a second source-drain layer 216, and the display panel 2 includes a plurality of repeating units 30 arranged in an array, each of the repeating units 30 includes two symmetrically arranged pixel driving circuits 31, and within the repeating unit 30, the second source-drain layer 216 includes two high-potential power lines VDD, two data lines DATA, two data connection lines DL and two anode connection lines AL, the two high-potential power lines VDD are symmetrically arranged, the two data lines DATA are symmetrically arranged, the two data connection lines DL are symmetrically arranged, and the two anode connection lines AL are symmetrically arranged.

[0104] Specifically, Fig.15 As shown, each data line connection line DL is provided with a break.

[0105] Specifically, Figure 8 As shown in FIG. 1 , the relative positions of the various structures when the light shielding layer, the first active layer, the first gate layer, the second active layer, the second gate layer, the first source-drain electrode layer and the second source-drain electrode layer overlap can be seen. Fig.25 As shown, the relative positions of the various structures when the first active layer, the first gate layer, the second active layer, the second gate layer, the first source-drain electrode layer and the second source-drain electrode layer overlap can be seen.

[0106] Specifically, it can be understood that due to the design of some pixel driving circuits in the display area shown in the embodiment of the present application, the connection points of some routing lines may be located in other pixel driving circuits or outside the display area. Therefore, some routing lines may not be connected together, but in fact, they will be connected. For example, in order to adopt the technology of setting the fan-out line in the display area (Fanout In AA, FIAA), the data line DATA will be set along the second direction. The data connection line DL is set, and the data connection line will be connected to some data lines. However, the embodiment of the present application shows the design of some pixel driving circuits, and therefore, its connection points are not shown, but in fact, they will be connected.

[0107] Specifically, since the active parts of some transistors are connected together, some nodes and electrodes in the circuit diagram are not marked. For example, the first node A is the connection node of the first electrode of the driving transistor T1, the second electrode of the switching transistor T2 and the second electrode of the first light-emitting control transistor T5, and the active parts of the driving transistor T1, the switching transistor T2 and the first light-emitting control transistor T5 share the same structure. Therefore, there is no need to separately set the first electrode of the driving transistor T1, the second electrode of the switching transistor T2 and the second electrode of the first light-emitting control transistor T5. Accordingly, the first node A does not exist in the exploded view of each film layer. It can be understood that the first node A is located at the connection point of the active parts of the driving transistor T1, the switching transistor T2 and the first light-emitting control transistor T5.

[0108] In some embodiments, Fig.16 As shown, Fig.16 The arrangement position of the first via hole 341 is shown. The first via hole 341 refers to a via hole etched from the first source and drain electrode layer to the first active layer or the first gate layer.

[0109] In some embodiments, Fig.17 As shown, Fig.17 The arrangement position of the second via hole 342 is shown. The second via hole 342 refers to a via hole etched from the first source and drain electrode layer to the second active layer or the second gate layer.

[0110] In some embodiments, Fig.18 As shown, Fig.18 The configuration position of the third via hole 343 is shown. The third via hole 343 refers to a via hole etched from the second source and drain electrode layer to the first source and drain electrode layer.

[0111] In some embodiments, Fig.19 As shown, Fig.19 The fourth via hole 344 is shown as a location where the fourth via hole 344 is etched from the anode of the light emitting layer to the second source and drain layer.

[0112] Specifically, in the above embodiments, when the transistor has a bottom gate and a top gate, the gate of the transistor refers to the first gate and / or the second gate of the transistor.

[0113] Specifically, the first active layer may include a channel portion and a doping portion, and the second active layer may include a channel portion and a doping portion.

[0114] Specifically, in the embodiments of the present application Figures 9 to 18 Shows Figure 8 The exploded view of the stacking diagram of each film layer of the display panel shown in FIG. 1 is understood that Fig.25 The exploded diagram of the stacking diagram of each film layer of the display panel shown can be seen in Figures 10 to 19 , Figure 8 The stacking diagram of each film layer of the display panel shown in FIG. Fig.25 The differences between the stackup diagrams of the film layers of the display panel shown are: Figure 8 The display panel includes a light shielding layer. Fig.25 The display panel shown does not include a light shielding layer, and for other film layers involved, Figure 8 The display panel shown is Fig.25 The display panels shown may be identical, e.g. Figure 8 The structure of the first gate layer in the display panel shown can be similar to Fig.25 The structure of the first gate layer in the display panel shown is the same, and Figure 8 The relative positions of the film layers in the display panel shown can be Fig.25 The relative positions of the corresponding film layers in the display panel shown are the same, for example Figure 8 The relative positions of the first gate layer and the first active layer in the display panel shown in FIG. Fig.25 The relative positions of the first gate layer and the first active layer in the display panel shown can be the same, that is, Fig.25 The exploded view of the display panel shown can be Figures 10 to 19 .

[0115] Specifically, Figure 6 , Fig.24 As shown, the driving circuit layer 22 further includes a blocking layer 203 , a buffer layer 204 , a first gate insulating layer 206 , a first interlayer insulating layer 208 , a second gate insulating layer 211 , a second interlayer insulating layer 213 , a first planarizing layer 215 and a second planarizing layer 217 .

[0116] Specifically, Figure 6 , Fig.24 As shown, the display panel 2 further includes a light-emitting layer 23 , and the light-emitting layer 23 includes a pixel electrode layer 231 , a pixel definition layer 232 , a light-emitting material layer 233 , a common electrode layer 234 and a support column 235 .

[0117] Specifically, Figure 6 , Fig.24 As shown, the display panel 2 further includes an encapsulation layer 24 .

[0118] Specifically, Figure 6 , Fig.24 As shown, the display panel 2 includes a display area 301 and a non-display area 302. A pixel driving circuit may be disposed in the display area 301, and a gate driving circuit may be disposed in the non-display area 302. Figure 6 In the description, the case where the corresponding area of ​​the transistor in the gate driving circuit has no light shielding layer is taken as an example, but the embodiments of the present application are not limited to this. The corresponding area of ​​the transistor in the gate driving circuit can be provided with a light shielding layer.

[0119] Specifically, the first electrode of the transistor in the above embodiment is a source, and the second electrode is a drain; or the first electrode of the transistor in the above embodiment is a drain, and the second electrode is a source.

[0120] Specifically, the switch control line Pscan, the compensation control line Nscan1, the first initialization control line Nscan2, the second initialization control line Pscan2 and the light-emitting control signal line EM can be respectively connected to different gate drive circuits. Specifically, five groups of gate drive circuits can be used to output signals to the switch control line Pscan, the compensation control line Nscan1, the first initialization control line Nscan2, the second initialization control line Pscan2 and the light-emitting control signal line EM, respectively. Among them, the gate drive circuit connected to the switch control line Pscan can adopt bilateral drive, and other gate drive circuits adopt unilateral drive.

[0121] Specifically, the material of the first active layer includes silicon semiconductor material, specifically low temperature polysilicon.

[0122] Specifically, the material of the second active layer includes an oxide semiconductor material, specifically a metal oxide semiconductor material, and more specifically, indium gallium zinc oxide.

[0123] Specifically, the material of the light shielding layer may include a metal material.

[0124] Specifically, the driving transistor, the switching transistor, the first light emission control transistor, the second light emission control transistor, the second initialization transistor and the third initialization transistor are P-type transistors, and the first initialization transistor and the compensation transistor are N-type transistors.

[0125] Specifically, the above embodiments respectively describe the display panel in detail from the perspectives of the pixel driving circuit, film layer structure, specific structure, materials, and potential of each layer in the display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the material of the first active layer includes silicon semiconductor material, and the material of the second active layer includes oxide semiconductor material.

[0126] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0127] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0128] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0129] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0130] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: A pixel driving circuit includes a silicon semiconductor transistor, an oxide transistor and a storage capacitor which are electrically connected; The display panel includes a first active layer, a first gate layer and a second active layer stacked in sequence, the active pattern of the silicon semiconductor transistor is located in the first active layer, a gate of the oxide transistor, a gate of the silicon semiconductor transistor and a first electrode plate of the storage capacitor are located in the first gate layer, and the active pattern of the oxide transistor and the second electrode plate of the storage capacitor are located in the second active layer.

2. The display panel according to claim 1, characterized in that: The pixel driving circuit includes a switch transistor, a driving transistor, a compensation transistor and a first initialization transistor, wherein the switch transistor and the driving transistor are connected to a first node; an electrode of the compensation transistor, an electrode of the first initialization transistor and the driving transistor are connected to a second node, and another electrode of the compensation transistor and the driving transistor are connected to a third node; Among them, the switching transistor and the driving transistor are silicon semiconductor transistors, the compensation transistor and the first initialization transistor are oxide transistors, the first gate layer includes the gate of the driving transistor, the gate of the switching transistor, the first gate of the compensation transistor and the first gate of the first initialization transistor; the second active layer includes the active pattern of the compensation transistor and the active pattern of the first initialization transistor, the first gate of the compensation transistor is set corresponding to the active pattern of the compensation transistor, and the first gate of the first initialization transistor is set corresponding to the active pattern of the first initialization transistor.

3. The display panel according to claim 2, characterized in that: The display panel further includes a high potential power line, and at least one of the first gate of the compensation transistor and the first gate of the first initialization transistor is connected to the high potential power line.

4. The display panel according to claim 3, characterized in that: The gate of the switching transistor is connected to the switching control line, the first gate layer includes the switching control line, the switching control line extends along a first direction, and in a second direction, the first gate of the first initialization transistor and the first gate of the compensation transistor are arranged on both sides of the switching control line; the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

5. The display panel according to claim 4, characterized in that: The display panel also includes a first source-drain layer and a second source-drain layer, the first source-drain layer includes a scan connection line, the second source-drain layer includes the high potential power line, the scan connection line is connected to the first gate of the first initialization transistor, the scan connection line is connected to the first gate of the compensation transistor, and the scan connection line is connected to the high potential power line.

6. The display panel according to any one of claims 2 to 5, characterized in that: The pixel driving circuit further includes: a first light emission control transistor, wherein an electrode of the first light emission control transistor and an electrode of the driving transistor are connected to the first node; a second light emission control transistor, wherein one electrode of the second light emission control transistor and the other electrode of the driving transistor are connected to the third node; a second initialization transistor, wherein one electrode of the second initialization transistor and the other electrode of the second light emission control transistor are connected to a fourth node; A third initialization transistor, wherein an electrode of the third initialization transistor and an electrode of the driving transistor are connected to the first node.

7. The display panel according to claim 6, characterized in that: The gate of the switch transistor is connected to the switch control line, the first electrode of the first initialization transistor is connected to the first initialization signal line, the second electrode of the first initialization transistor and the gate of the drive transistor are connected to a second node, the gate of the first light emission control transistor is connected to the light emission control signal line, the gate of the second light emission control transistor is connected to the light emission control signal line, and the gate of the second initialization transistor is connected to the second initialization control line; Among them, the first gate layer includes the first initialization signal line, the first gate of the first initialization transistor, the switch control line, the first gate of the compensation transistor, the first plate of the storage capacitor, the light-emitting control signal line and the second initialization control line, the first initialization signal line, the switch control line, the light-emitting control signal line and the second initialization control line all extend along the first direction, the first initialization signal line, the first gate of the first initialization transistor, the switch control line, the first gate of the compensation transistor, the first plate of the storage capacitor, the light-emitting control signal line and the second initialization control line are arranged in sequence along the second direction; the angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

8. The display panel according to claim 7, characterized in that: The gate of the compensation transistor is connected to the compensation control line, the gate of the first initialization transistor is connected to the first initialization control line, the first electrode of the third initialization transistor is connected to the third initialization signal line, and the second electrode of the third initialization transistor and the first electrode of the driving transistor are connected to a first node; Among them, the display panel also includes a second gate layer, the second gate layer includes the compensation control line, the first initialization control line, the third initialization signal line, the second gate of the compensation transistor and the second gate of the first initialization transistor, and the first initialization control line, the compensation control line and the third initialization signal line are arranged in sequence along the second direction.

9. The display panel according to claim 8, characterized in that: The first electrode of the switch transistor is connected to the data line, and the second electrode of the switch transistor is connected to the first electrode of the drive transistor at a first node; the first electrode of the compensation transistor is connected to the gate of the drive transistor at a second node, and the second electrode of the compensation transistor is connected to the second electrode of the drive transistor; the first electrode of the first light-emitting control transistor is connected to the high-potential power line, and the second electrode of the first light-emitting control transistor is connected to the first node. The first electrode of the second light emitting control transistor and the second electrode of the driving transistor are connected to a third node; The first electrode of the second initialization transistor is connected to the second initialization signal line, and the second electrode of the second initialization transistor and the second electrode of the second light-emitting control transistor are connected to a fourth node; the gate of the third initialization transistor is connected to the second initialization control line; one plate of the storage capacitor is connected to the high-potential power line, and the other plate of the storage capacitor is connected to the gate of the driving transistor at a second node.

10. The display panel according to claim 9, characterized in that: The display panel also includes a first source-drain layer, which includes a second initialization signal line, a first electrode of the switching transistor, a second electrode of the switching transistor, a first electrode of the compensation transistor, a second electrode of the compensation transistor, a first electrode of the first initialization transistor, a second electrode of the first initialization transistor, a first electrode of the first light-emitting control transistor, a second electrode of the first light-emitting control transistor, a first electrode of the second light-emitting control transistor, a second electrode of the second light-emitting control transistor, a first electrode of the second initialization transistor, a second electrode of the second initialization transistor, a first electrode of the third initialization transistor, a second electrode of the third initialization transistor, and a scan connection line.

11. The display panel according to claim 10, characterized in that: The display panel also includes a second source and drain layer. The display panel includes a plurality of repeating units arranged in an array. Each of the repeating units includes two symmetrically arranged pixel driving circuits. Within the repeating units, the second source and drain layer includes two high-potential power lines, two data lines, two data connection lines and two anode connection lines. The two high-potential power lines are symmetrically arranged, the two data lines are symmetrically arranged, the two data connection lines are symmetrically arranged, and the two anode connection lines are symmetrically arranged.

12. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 11.

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