Processing unit scheduling device and method, chip and related equipment

Abstract

The embodiment of the invention provides a processing unit scheduling device and method, a chip and related equipment, the processing unit scheduling device comprises a first arbiter and M processing units connected with the first arbiter, and M is a positive integer greater than or equal to 2; wherein each processing unit is used for sending a first request signal to the first arbiter, the first request signal is used for requesting to switch the corresponding processing unit from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than that of the second power consumption state; the first arbiter is used for receiving first request signals respectively sent by one or more of the M processing units, and arbitrating to obtain a first response sequence of the one or more first request signals; and controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence. By implementing the embodiment of the invention, the phenomenon of functional errors of the circuit caused by voltage undershoot can be reduced, and the circuit performance is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a processing unit scheduling device, method, chip and related equipment. Background Art

[0002] With the continuous advancement of technology, chips are also gradually developing. In current high-performance chips, such as central processing units (CPUs), neural network accelerators (NPUs) and general purpose graphics processing units (GPGPUs), dozens to hundreds of processing elements (PEs) are generally integrated. Inside each processor unit, there may be a module with high power density (High Power Unit, HPU), such as a vector / matrix accelerator. When all or even some of the HPUs in the PEs in the chip work at the same time, they may affect each other, resulting in signal integrity (PI) problems. Exemplarily, when the HPUs in all PEs on the chip quickly enter the second power consumption state from the standby mode (i.e., the idle state) at the same time, the on-chip power supply network is likely to be unable to provide enough current to all HPUs, resulting in a voltage undershoot in the voltage output of the on-chip power supply network, resulting in a reduction in the output voltage, so that the relevant functional modules in the internal circuit of the chip that require stable voltage power supply will have circuit function errors due to the voltage undershoot phenomenon, and ultimately cause functional errors in the chip. For example, when the instantaneous output voltage is lower than the minimum voltage Vmin at which a complementary metal oxide semiconductor (CMOS) tube can work normally, the CMOS tube will be shut down or malfunction.

[0003] Therefore, how to reduce the phenomenon of functional errors in circuits caused by voltage undershoot is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a processing unit scheduling device, method, chip and related equipment to reduce the phenomenon of functional errors in circuits caused by voltage undershoot and improve circuit performance.

[0005] In a first aspect, an embodiment of the present application provides a processing unit scheduling device, the device comprising a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; wherein,

[0006] Each of the processing units is used to: send a first request signal to the first arbitrator, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state;

[0007] The first arbitrator is used to: receive the first request signals respectively sent by one or more processing units among the M processing units, and arbitrate to obtain a first response sequence of one or more of the first request signals; based on the first response sequence, control the one or more processing units to switch from the first power consumption state to the second power consumption state.

[0008] In order to avoid voltage undershoot and functional errors caused by multiple processing units entering a high power state from a low power state at the same time, the embodiment of the present application provides a processing unit scheduling device, which can avoid multiple processing units entering a high power state from a low power state at the same time from a hardware perspective, reduce the undershoot amplitude of the voltage undershoot, so that the minimum instantaneous voltage of the voltage undershoot is higher than the working voltage of the normal circuit, thereby ensuring the signal integrity of the chip. Among them, the processing unit scheduling device can be applied to a chip or a related circuit module, and the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator. When any one of the multiple processing units connected to the first arbitrator is about to enter a high power state from a low power state (that is, from a first power state with lower power to a second power state with higher power), each processing unit must send a first request signal to the first arbitrator to request to switch the power consumption state. When the first arbitrator receives the above-mentioned first request signal sent by the processing unit connected to it, it can arbitrate the received first request signal and obtain the corresponding response sequence through arbitration, so that the first arbitrator can control the corresponding processing unit to enter the high power consumption state from the low power consumption state in sequence according to the response sequence, thereby avoiding that all the multiple processing units connected to the first arbitrator enter the high power consumption state from the low power consumption state at the same time, causing voltage undershoot, resulting in functional errors and affecting signal integrity. For example: when the instantaneous voltage is less than the minimum voltage Vmin for the MOS tube to work normally, the MOS tube is turned off, resulting in chip functional errors. In this case, an arbitrator is connected between multiple processing units, and each processing unit will pass the arbitration of the arbitrator when switching the power consumption state, so that the arbitrator can be used to schedule some of the multiple processing units to switch the power consumption state. Moreover, compared with the software algorithm scheduling inside the device or apparatus, the overhead of the device or apparatus is greatly reduced, and the probability of all processing units entering the high power consumption state from the low power consumption state at the same time due to scheduling errors is also reduced, thereby ensuring the signal performance of the chip.

[0009] In one possible implementation, the first arbitrator is specifically used to: based on the first response sequence, send a first response signal to the one or more processing units respectively, and the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0010] In an embodiment of the present application, the first arbitrator can control the processing unit to switch the power consumption state through a response signal. For example, when the processing unit receives the first response signal sent by the first punch, it can switch from a low power consumption state to a high power consumption state immediately or within a preset time. Wherein, when the first arbitrator sends the first response signal to one or more processing units in accordance with the first response sequence, the time interval between any two orders of sending the first response signal is greater than or equal to the first preset time interval. For example, based on the first request signal, when the first arbitrator continuously pulls up different processing units, or continuously pulls up the same processing unit multiple times, the time interval between any two orders needs to exceed the first preset time interval. The first preset time interval can be determined based on the number and performance of the processing units connected to the arbitrator, for example, it can be between 10 nanoseconds and 1 microsecond. This sending method in which the time interval between any two orders needs to exceed the first preset time interval can ensure that all processing units will not be pulled up at the same time, thereby avoiding the phenomenon that the voltage undershoot causes the instantaneous voltage to be less than the minimum voltage at which the circuit or functional module can work normally, resulting in functional errors.

[0011] In one possible implementation, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending mode; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending mode, the parallelism of the parallel sending is less than or equal to M.

[0012] In the embodiment of the present application, the first arbitrator may control one processing unit to switch to a high power consumption state at a time, or may control multiple processing units to switch to a high power consumption state at the same time, wherein, when the current total power consumption is low and controlling multiple processing units to switch to a high power consumption state at the same time will not affect the normal operation of the circuit, the maximum number of processing units that switch to a high power consumption state at the same time may be equal to the total number of processing units connected to the arbitrator, that is, at this time, the parallelism of the parallel transmission of the first arbitrator is less than or equal to M. When the current total power consumption is high and controlling multiple processing units to switch to a high power consumption state at the same time may cause voltage undershoot and cause the circuit to fail to work properly, the maximum number of processing units that switch to a high power consumption state at the same time must be less than the total number of processing units connected to the arbitrator, that is, at this time, the parallelism of the parallel transmission of the first arbitrator is less than M. The first arbitrator may control some processing units to switch to a high power consumption state at the same time on the basis of not controlling all processing units to switch to a high power consumption state at the same time, so as to improve the arbitration efficiency and ensure the performance of the processing units.

[0013] In one possible implementation, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0014] In the embodiment of the present application, each processing unit may include a high power consumption unit, such as a vector / matrix accelerator, etc. The high power consumption unit consumes high power when in operation, thereby increasing the power consumption of the corresponding processing unit. Therefore, after the processing unit receives the first response signal, it controls part or all of the high power consumption units inside it to switch from the first power consumption state to the second power consumption state, which can ensure that the high power consumption unit in the processing unit will not switch to the high power consumption state autonomously without receiving the first response signal.

[0015] In one possible implementation, each of the processing units also includes a prediction module; the prediction module is used to: detect the power consumption state of the one or more high-power consumption units in the corresponding processing unit; and send the first request signal to the first arbitrator when it is detected that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0016] In an embodiment of the present application, each processing unit may further include a prediction module, which can be used to detect the power consumption state of one or more high-power consumption units in the corresponding processing unit in real time or periodically, so that when some or all of the high-power consumption units are about to switch to the second power consumption state, a first request signal is sent to the first arbitrator in time to request that the high-power consumption unit be switched from the first power consumption state to the second power consumption state, thereby improving the accuracy and switching efficiency of the processing unit switching the power consumption state.

[0017] In one possible implementation, the processing unit also includes a task sending queue, which is used to send a task descriptor of the task; the task descriptor is used to indicate whether the task calls one or more high-power consumption units in the corresponding processing unit; the prediction module is specifically used to: when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0018] In an embodiment of the present application, each processing unit may also include a task sending queue, and one of the methods for the prediction module to predict that the high-power unit is about to enter the high-power state from the low-power state is to judge through the task descriptor of the current task in the task sending queue. The task descriptor can be used to indicate whether the current task needs to call the high-power unit in the processing unit. If it indicates that the high-power unit in the processing unit needs to be called, it means that the called high-power unit is about to enter the high-power state, and the prediction module needs to send a first request signal to the first arbitrator to control the high-power unit to enter the high-power state.

[0019] In one possible implementation, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0020] In an embodiment of the present application, one of the methods for the prediction module to predict that the processing unit is about to enter a high power consumption state from a low power consumption state is by detecting the number of operation instructions in the instruction sending queue of the processing unit; when the number of operation instructions corresponding to the high power consumption unit in the instruction sending queue is accumulated in large quantities (for example, exceeding a preset threshold number), it indicates that the high power consumption unit is about to enter a high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator to control the high power consumption unit to enter a high power consumption state.

[0021] In one possible implementation, the first arbitrator is specifically configured to arbitrate and obtain the first response order of one or more first request signals according to a preset polling rule or a response priority of one or more processing units among the M processing units.

[0022] In an embodiment of the present application, the first arbitrator can arbitrate the first response sequence of the first request signal according to a preset polling rule or response priority so as to reply to the first response signal in order. For example: the earlier the first request signal is received, the earlier the response sequence corresponding to the first request signal is replied. Another example: the first response signal of the same processing unit will not be replied to continuously at the same time. Another example: the higher the response priority of the corresponding processing unit, the earlier the response sequence corresponding to the first request signal is replied. This arbitration of the response sequence between multiple processing units according to preset rules can improve the arbitration accuracy of the first arbitrator and avoid poor chip performance caused by errors.

[0023] In a possible implementation manner, the first arbitrator is arranged in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0024] In the embodiment of the present application, the first arbitrator is set in the middle of multiple processing units or the sum of the communication distances between the first arbitrator and the multiple processing units is the shortest, which can greatly reduce the communication delay between the first arbitrator and the processing units, improve processing efficiency, and ensure processing performance.

[0025] In one possible implementation, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the response interfaces is used to send the first response signal to the corresponding processing unit.

[0026] In an embodiment of the present application, the first arbitrator can communicate with each processing unit through a dedicated interface module, that is, the first arbitrator includes multiple groups of communication interfaces, each group of communication interfaces corresponds to a processing unit, and each group of communication interfaces includes a request interface for transmitting a first request signal and a response interface for transmitting a response signal, so that the first arbitrator and the processing unit can communicate normally, and the communication efficiency between the first arbitrator and the multiple processing units is greatly improved, avoiding the first arbitrator being unable to receive the first request signal in time when multiple processing units send the first request signal to the first arbitrator at the same time.

[0027] In one possible implementation, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states whose power is less than that of the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0028] In the embodiment of the present application, the processing unit has multiple high power consumption states. Each time the processing unit switches to a higher power consumption state, it needs to send a first request signal to the first arbitrator, and then the first arbitrator determines the level of the corresponding adjusted high power consumption state, so that the processing unit can enter different high power consumption states at will, causing the voltage to undershoot, resulting in a decrease in output voltage. This adjustment method of the power consumption state of the processing unit controlled by the first arbitrator can globally control the overall power consumption of multiple processing units, which is conducive to ensuring the stability of the output voltage of the power supply network and the performance of the chip.

[0029] In one possible implementation, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

[0030] In the embodiment of the present application, since the processing unit may have multiple high power consumption states, in order to facilitate each processing unit to send its current power consumption state to the first arbitrator, each group of communication interfaces may also include an interface for transmitting current power consumption level information. In addition, in order to reduce control costs and improve control efficiency, each group of response interfaces may also be used to send target power consumption level information. For example, the first response signal may carry the corresponding target power consumption level information.

[0031] In one possible implementation, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, the second arbitrator is connected to the first arbitrator in each of the first processing clusters; each of the first arbitrators is specifically used to: send a second request signal to the second arbitrator when receiving the first request signal; the second arbitrator is used to: receive the second request signal sent by one or more of the first arbitrators; arbitrate to obtain a second response sequence of one or more of the second request signals; and control one or more of the first arbitrators based on the second response sequence.

[0032] In the embodiment of the present application, a multi-level arbitration architecture can also be provided, that is, the first arbitrator performs arbitration for switching the high power consumption state with a processing unit as the granularity, and the second arbitrator performs arbitration for switching the high power consumption state with a first processing cluster as the granularity, that is, only part of the first processing clusters are used at the same time, which greatly reduces the number of processing units that simultaneously enter high power consumption in the global state, and further ensures the stability of the output voltage of the power supply network and the performance of the chip.

[0033] In one possible implementation, the second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0034] In the embodiment of the present application, the response of the first arbitrator can be controlled by the second response signal. For example, after the second arbitrator sends the second response signal to the corresponding first arbitrator, the first arbitrator can sequentially control the corresponding processing unit to switch from the first power consumption state to the second power consumption state. This control method through the response signal can more easily control the arbitrators at all levels, reduce the error rate, and ensure the operating performance of the chip.

[0035] In a possible implementation, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0036] In the embodiment of the present application, similar to the first arbitrator, in order to ensure that the voltage undershoot does not cause the instantaneous voltage to be less than the voltage at which the circuit structure in the device can work normally, resulting in a chip function error, the time interval for each response of the second arbitrator to the first arbitration can be greater than or equal to the second preset time interval. The second preset time interval and the first preset time interval can be different or the same, and the maximum number of processing units that can be pulled up at a time can be adjusted by configuring the second preset time interval and the first preset time interval to adapt to more application scenarios.

[0037] In a second aspect, an embodiment of the present application provides a processing unit scheduling method, which is applied to a processing unit scheduling device, wherein the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; the method includes:

[0038] receiving first request signals respectively sent by one or more processing units among the M processing units, and obtaining a first response sequence of one or more of the first request signals by arbitration, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state;

[0039] Based on the first response sequence, the one or more processing units are controlled to switch from the first power consumption state to the second power consumption state.

[0040] In one possible implementation, controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence includes: sending a first response signal to the one or more processing units respectively based on the first response sequence, the first response signal being used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0041] In one possible implementation, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending mode; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending mode, the parallelism of the parallel sending is less than or equal to M.

[0042] In one possible implementation, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0043] In one possible implementation, each of the processing units also includes a prediction module; the method also includes: detecting the power consumption state of one or more high-power consumption units in the corresponding processing unit through the prediction module; and sending the first request signal to the first arbitrator when it is detected that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0044] In one possible implementation, each of the processing units also includes a task sending queue, which is used to send a task descriptor of the current task; the task descriptor is used to indicate whether the current task calls the one or more high-power consumption units in the corresponding processing unit; the power consumption state of the one or more high-power consumption units in the corresponding processing unit is detected by the prediction module, including: obtaining the task descriptor of the current task in the task sending queue, wherein, when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, it is determined that the some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0045] In one possible implementation, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the detection of the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: detecting the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue, wherein, when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, it is determined that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0046] In one possible implementation, the arbitration obtains the first response order of one or more of the first request signals, including: according to a preset polling rule or the response priority of one or more processing units among the M processing units, the arbitration obtains the first response order of one or more of the first request signals.

[0047] In a possible implementation manner, the first arbitrator is arranged in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0048] In one possible implementation, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the response interfaces is used to send the first response signal to the corresponding processing unit.

[0049] In one possible implementation, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states whose power is less than that of a high power consumption state in the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; the method also includes: receiving current power consumption level information sent by one or more of the M processing units respectively, and the current power consumption level information is used to indicate the first power consumption state that the corresponding processing unit is currently in.

[0050] In one possible implementation, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

[0051] In one possible implementation, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, and the second arbitrator is connected to the first arbitrator in each of the first processing clusters; the method also includes: receiving, through the second arbitrator, a second request signal sent by one or more of the first arbitrators when the first request signal is received; obtaining a second response sequence of one or more of the second request signals through arbitration by the second arbitrator; and controlling the corresponding one or more of the first arbitrators based on the second response sequence.

[0052] In one possible implementation, controlling the corresponding one or more first arbitrators based on the second response sequence includes: sending a second response signal to the corresponding one or more first arbitrators based on the second response sequence, the second response signal being used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0053] In a possible implementation, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0054] In a third aspect, an embodiment of the present application provides a chip, including a circuit and a processing unit scheduling device as described in the first aspect and the processing unit scheduling device involved in the first aspect applied to the circuit.

[0055] In a fourth aspect, an embodiment of the present application provides a server, comprising: a circuit board and the processing unit scheduling device as described in the first aspect and the processing unit scheduling device involved in the first aspect; the circuit board is electrically connected to the processing unit scheduling device.

[0056] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and the processing unit scheduling device as described in the above-mentioned first aspect and the first aspect; the circuit board is electrically connected to the processing unit scheduling device.

[0057] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer software instructions used for a processing unit scheduling device provided in the first aspect above, which includes a program for executing a processing unit scheduling method provided in the second aspect above.

[0058] In a seventh aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, the computer can execute the process executed by a processing unit scheduling device provided in the first aspect above.

[0059] It should be understood that the processing unit scheduling method provided in the second aspect of the present application, the chip provided in the third aspect, the server provided in the fourth aspect, the electronic device provided in the fifth aspect, the computer-readable storage medium provided in the sixth aspect, and the computer program provided in the seventh aspect are consistent with the technical solution of the first aspect of the present application. Their specific contents and beneficial effects can be referred to the processing unit scheduling device provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0061] Figure 1 It is a schematic diagram of the structure of a high-performance chip provided in an embodiment of the present application.

[0062] Figure 2 It is a structural diagram of a processing unit scheduling device provided in an embodiment of the present application.

[0063] Figure 3A It is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0064] Figure 3B It is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0065] Figure 4A and Figure 4BIt is a structural diagram of a group of processing unit scheduling devices provided in an embodiment of the present application.

[0066] Figure 5 It is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0067] Figure 6 It is a schematic diagram of a communication interface of a first arbitrator provided in an embodiment of the present application.

[0068] Figure 7 It is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application.

[0069] Figure 8 It is a flowchart of a processing unit scheduling method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0071] The terms "first" and "second" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0072] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0073] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0074] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0075] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0076] (1) Scheduling, which controls the timing or order of switching the processing unit from a low power state to a high power state. In the embodiment of the present application, each processing unit is independent of each other and has no dependencies, that is, each processing unit can switch from a low power state to a high power state at will. In order to ensure that all processing units do not switch from a low power state to a high power state at the same time, global scheduling can be achieved by controlling the order in which the processing units switch to a high power state.

[0077] (2) Processing Element (PE), which can be understood as a logic core. One or more tasks or one or more threads can be run on a logic core. A network composed of multiple identical processing elements PE according to certain interconnection rules can be called a systolic array. In the embodiments of the present application, the connection method between multiple processing elements is not limited.

[0078] (3) Arbiter: When multiple functional modules occupy the same resource, the arbiter can be used to arbitrate which module occupies the resource, or arbitrate which module occupies the resource first. For example, the module that proposes to occupy the resource must generate a request. After all requests are sent to the arbitrator, the arbitrator can arbitrate. In addition, the arbitrator can also return a grant, and the module that receives the grant can occupy the resource.

[0079] (4) High Power Unit (HPU): a functional module with high power consumption density, that is, when in operation, the functional module consumes more power or more resources. Among them, the high power unit can be a matrix accelerator, a vector accelerator, a multiplication accelerator, etc.

[0080] (5) Task sending queue: a container or queue that stores tasks or task descriptors during the task sending process. It can relay or send tasks or task descriptors from the source to the target and act as a container in the process. Its main purpose is to provide routing and ensure the delivery or sending of tasks or task descriptors.

[0081] (6) Instruction sending queue: a container or queue that stores operation instructions during the operation instruction issuance process. The operation instructions in the queue can be sent to the corresponding target. If the receiver of the sent operation instruction is unavailable or temporarily unable to receive it, the instruction sending queue will retain the operation instruction until it can be successfully delivered.

[0082] Secondly, in order to facilitate the understanding of the embodiments of the present application, the technical problems that need to be solved by the embodiments of the present application and the applicable application scenarios are analyzed in detail below.

[0083] With the continuous advancement of technology, chips have also gradually developed. Current high-performance chips, such as central processing units (CPUs), neural network accelerators (NPUs) and general purpose graphics accelerators (GPGPUs), generally integrate dozens to hundreds of processing elements (PEs). Figure 1: This is a structural diagram of a high-performance chip provided by an embodiment of the present application. Inside each processor unit, there may be a module with high power consumption density (High Power Unit, HPU), such as: vector / matrix accelerator, which can be called a high power consumption unit. When the HPUs in all or even some PEs in the chip start working at the same time, they may affect each other, resulting in signal integrity (Power Integrity, PI) problems. For example: when the HPUs in all or most PEs on the chip quickly enter the working state from the standby mode (i.e., idle state) to start the high power consumption mode at the same time, the on-chip power supply network is likely to be unable to provide enough current to all PEs, resulting in the voltage output by the on-chip power supply network. There is a voltage undershoot phenomenon, which reduces the output voltage. When the instantaneous voltage of the output is lower than the normal working voltage required in the internal circuit of the chip, the relevant functional module will have a circuit function error due to the voltage undershoot phenomenon, which eventually leads to a functional error in the chip. For example: when the minimum voltage Vmin at which the complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) tube can work normally, the CMOS tube function will be closed or erroneous, which eventually leads to a functional error in the chip. For example, when the voltage undershoots, it will cause voltage instability, and errors will also occur in some functional modules that require stable voltage.

[0084] In the prior art, in order to ensure that the output voltage of the on-chip power supply network is not less than the working voltage V that the chip can normally operate at any time, one solution is to increase the input voltage V of the on-chip power supply network. 0 In this way, when multiple HPUs are pulled up at the same time and voltage undershoot occurs, the output voltage V 1 Although less than V 0 , but it is still not less than the operating voltage V, so as to ensure the normal operation of the chip. However, since the power consumption of the chip is proportional to the square of the voltage, it is necessary to increase the input voltage V of the on-chip power supply network. 0 , which will lead to a significant increase in the power consumption of the chip.

[0085] Another solution is to circumvent the problem by scheduling the HPU in the PE through software. That is, by using software scheduling to avoid the HPU in multiple PEs from starting up at the same time, as long as the number of PEs started at the same time is small enough, there will be no voltage undershoot, thereby hoping to solve the problem of voltage undershoot from the source. However, because the software call is not precise enough, the possibility of starting multiple HPUs at the same time cannot be completely avoided. Moreover, the overhead of software scheduling is generally large, which will affect the original performance of the chip. In addition, this solution also requires the software designer or software user to understand the basic architecture of the software scheduling chip, which is difficult for most software designers or users to do.

[0086] In this regard, the embodiment of the present application provides a high-power unit scheduling device and a related method, which can ensure that the time for increasing the power consumption of HPU between multiple PEs is staggered from the hardware perspective, and avoid the instantaneous voltage caused by voltage undershoot being less than the normal working voltage of the MOS tube when multiple PEs enter the high power state from the low power state at the same time, thereby achieving the purpose of protecting the chip PI. The high-power unit scheduling device includes: a first arbitrator and M processing units PE connected to the first arbitrator, M is a positive integer greater than or equal to 2; wherein each processing unit is used to: send a first request signal to the first arbitrator, the first request signal is used to request that the corresponding processing unit be switched from the first power consumption state to the second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state; the first arbitrator is used to: receive the first request signal sent by one or more processing units in the M processing units respectively, arbitrate to obtain the first response sequence of one or more first request signals; based on the first response sequence, control one or more processing units to switch from the first power consumption state to the second power consumption state.

[0087] Among them, the specific implementation method of the embodiments of the present application can also refer to the relevant description of the following embodiments, and the embodiments of the present application will not be described in detail here.

[0088] Based on the technical issues raised above and to facilitate understanding of the embodiments of the present application, one of the processing unit scheduling devices on which the embodiments of the present application are based is described below.

[0089] See also Figure 2 , Figure 2 It is a structural diagram of a processing unit scheduling device provided in an embodiment of the present application.

[0090] like Figure 2 As shown, the processing unit scheduling device 001 can be applied to various high-performance chips or processing devices. The device includes a first arbitrator 01 and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2.

[0091] Each processing unit PE is used to send a first request signal to the first arbiter 01, wherein the first request signal is used to request that the corresponding processing unit PE be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state. For example, the first request signal is used to request that the corresponding processing unit PE be switched from a low power consumption state (i.e., the first power consumption state) to a high power consumption state (i.e., the second power consumption state). That is, it can be understood that, as described above Figure 2 The processing unit scheduling device shown is illustrative of an example in which a first arbitrator 01 is connected to four processing units PE. When any one of the four processing units PE connected to the first arbitrator 01 needs to enter a high power consumption state from a low power consumption state (i.e., from a first power consumption state with lower power consumption to a second power consumption state with higher power consumption), the processing unit PE must send a first request signal to the first arbitrator 01 to request switching of the power consumption state. The processing unit PE connected to the first arbitrator 01 cannot directly enter a higher power consumption state without arbitration by the first arbitrator 01.

[0092] The first arbitrator 01 is used to: receive the first request signal sent by one or more processing units PE in the M processing units PE respectively, arbitrate to obtain the first response sequence of one or more first request signals; based on the first response sequence, control the one or more processing units PE to switch from the first power consumption state to the second power consumption state. For example: when any one or more processing units PE in the four processing units PE connected to the first arbitrator 01 sends a first request signal to the first arbitrator 01, the first arbitrator 01 can arbitrate according to the received one or more first request signals, and arbitrate to obtain the first response sequence corresponding to the one or more first request signals, so as to control the processing units sending the first request signal to switch from the first power consumption state to the second power consumption state in sequence according to the first response sequence. In this case, an arbitrator is connected between multiple processing units, and each processing unit will be arbitrated by the arbitrator when switching the power consumption state, so that the arbitrator can be used to schedule some of the multiple processing units to switch the power consumption state. Moreover, compared with the software algorithm scheduling inside the device or apparatus, the overhead of the device or apparatus is greatly reduced, and the probability of all processing units entering the high power consumption state from the low power consumption state at the same time due to scheduling errors is also reduced, thereby ensuring the signal performance of the chip.

[0093] In addition, the embodiment of the present application is an example of a first arbitrator 01 connected to four processing units PE, and the embodiment of the present application does not make any specific limitation to this. For example, please refer to the attached Figure 3A , Figure 3A Schematic diagram of another processing unit scheduling device provided in an embodiment of the present application. Figure 3A As shown, one first arbitrator 01 can be connected to eight processing units PE, and the eight processing units PE will not all switch from a low power consumption state to a high power consumption state at the same time under the control of the first arbitrator 01 .

[0094] Please refer to the attached Figure 3B , Figure 3B is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application. Figure 3B As shown, the processing unit scheduling device may include multiple first arbitrators, and M processing units connected to each first arbitrator. The number of processing units connected to each first arbitrator is the same. When all processing units in the processing unit scheduling device are about to switch from a low power state to a high power state, arbitration is performed by multiple first arbitrators, which will make only some processing units in the global state switch from a low power state to a high power state at the same time, thereby improving the minimum instantaneous voltage when the voltage is undershot, and ensuring the performance of the chip. For example, when a first arbitrator is connected to 4 processing units, and each first arbitrator can only control one processing unit to enter a high power state at a time, then in the global state, at most only one quarter of the processing units can switch from a low power state to a high power state at the same time. Compared with the global state, when all processing units switch from a low power state to a high power state at the same time, the phenomenon of voltage undershoot will be greatly alleviated, which greatly reduces the probability of chip function errors caused by voltage undershoot.

[0095] In other embodiments, a processing unit may continuously send multiple first request signals to the first arbitrator, and when the sending time of the multiple first request signals is within a preset time range, the multiple first request signals have and only one first request signal (which may be the earliest sending time or the latest sending time) is valid, and the other first request signals are invalid. For example: if 3 first request signals are sent within 10 nanoseconds, the first arbitrator may only respond to or arbitrate one first request signal among the 3 first request signals. When the sending time of every two first request signals when sending the multiple first request signals is outside the preset time range, the multiple first request signals are all valid, for example: if the processing unit sends a first request signal every 100 nanoseconds, the sent first request signals are all valid until the processing unit switches to the highest power consumption state.

[0096] In some embodiments, the first arbitrator is specifically used to: based on the first response sequence, send a first response signal to the one or more processing units respectively, and the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0097] Based on the first response sequence, in response to one or more first request signals, the first arbitrator may send a first response signal to the one or more processing units respectively, and control the processing units to switch from a low power consumption state to a high power consumption state through the response signal. For example, the processing unit may switch from a low power consumption state to a high power consumption state immediately or within a preset time upon receiving the first response signal sent by the first arbitrator.

[0098] In addition, the first response sequence is the sequence in which the first arbitrator sends the first response signal to the processing unit. In the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal is sent to the corresponding processing unit is greater than or equal to the first preset time interval. When the first arbitrator receives multiple first request signals, the first arbitrator arbitrates to obtain the first response sequence corresponding to the multiple first request signals, and the time interval between any two times of sending the first response signal in the first response sequence is greater than or equal to the first preset time interval. Exemplarily, when the first arbitrator receives 4 first request signals, the first arbitrator arbitrates to obtain the first response sequence corresponding to the multiple first request signals, which is 1, 2, 3, and 4, respectively. Then, the time interval between the time point of sending the first response signal for the first time and the time point of sending the first response signal for the second time is greater than or equal to the first preset time interval.

[0099] It should be noted that, based on the first request signal, when the first arbitrator continuously pulls up different processing units, or continuously pulls up the same processing unit multiple times, the time interval between any two orders needs to exceed the first preset time interval. The first preset time interval can be determined according to the number of processing units connected to the arbitrator or the current global power consumption state or performance of the processing unit scheduling device, that is, it can be a time interval that can be adjusted according to the current state of the processing unit scheduling device. The first preset time interval can also be a default configured time interval, and the interval of the first preset time interval can be 0 or non-0.

[0100] For example: when the first preset time interval is the default configured time interval, the first preset time interval may not be 0, such as: it may be between 10 nanoseconds and 1 microsecond. This sending method in which the time interval between any two orders needs to be at least more than 10 nanoseconds can ensure that all processing units will not be pulled up at the same time, thereby avoiding the phenomenon that the voltage undershoot causes the instantaneous voltage to be less than the minimum voltage V for the circuit to work normally, resulting in the circuit not being able to work normally and the circuit function being erroneous. For another example: when the current global power consumption state of the processing unit scheduling device is lower or the performance is stronger, the preset time interval may be 0, that is, the first response signal may be sent at the same time to control the corresponding processing unit to switch from a low power consumption state to a high power consumption state. Moreover, the first preset time interval may be adjusted in time according to the current performance (such as: the instantaneous voltage of the output of the on-chip power supply network) to prevent the instantaneous voltage from being lower than the minimum voltage for the normal operation of the circuit.

[0101] It should also be noted that, in some embodiments, when only one first request signal is received, the first arbitrator needs to determine whether the last time the processing unit was controlled to switch to a high power consumption state is too close. If it is too close, it may easily cause multiple processing units to switch to a high power consumption state at similar time points. At the same time, in order to avoid the first arbitrator being unable to control the processing unit to switch to a high power consumption state in time, resulting in poor chip processing performance, therefore, when the first arbitrator only receives the first request signal sent by one processing unit, the first arbitrator needs to confirm whether the time interval from the last time the first response signal was sent to the processing unit is greater than or equal to the first preset time interval when sending a first response signal to the processing unit. If it is greater than or equal to the first preset time interval, the first response signal can be sent; if it is less than the first preset time interval, the first response signal cannot be sent immediately, and it is necessary to wait until the time interval from the last time the first response signal was sent to the processing unit is greater than or equal to the first preset time interval before sending it. That is, when only one first request signal is received or in the first response sequence, the time point when the control processing unit switches to a high power consumption state in the first order needs to be separated from the time point when the control processing unit last switched to a high power consumption state, for example, it can be between 10 nanoseconds and 1 microsecond.

[0102] In addition, in other embodiments, when the current global power consumption state is low or the first preset time interval is 0, when only one first request signal is received, the first arbitrator may not need to determine the last time the control processing unit switched to a high power consumption state, and may directly respond to the first request signal and reply with a corresponding first response signal.

[0103] In some embodiments, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending manner; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending manner, the parallelism of the parallel sending is less than or equal to M.

[0104] Among them, the first arbitrator can send the corresponding first response signal to one or more processing units in a serial or parallel manner each time according to the first response sequence. For example, the first arbitrator can send the corresponding first response signal to one or more processing units only in a serial manner, or can send the corresponding first response signal to one or more processing units only in a parallel manner, or can send the corresponding first response signal to one or more processing units in a combination of serial and parallel manners. That is, the first arbitrator can send one first response signal at a time to control one processing unit to switch to a high power consumption state; it can also send multiple first response signals at a time to control multiple processing units to switch to a high power consumption state at the same time.

[0105] In the case of controlling multiple processing units to switch to a high power consumption state at the same time, the number of processing units that switch to the high power consumption state at the same time may be less than the total number of processing units connected to the first arbitrator, that is, the parallelism of the parallel transmission of the first arbitrator is less than or equal to N, and N is a positive integer greater than 1 and less than M; the number of processing units that switch to the high power consumption state at the same time may be equal to the total number M of processing units connected to the first arbitrator.

[0106] Exemplarily, a total of four processing units send a first request signal to the first arbitrator. After arbitrating the four first request signals, the first arbitrator obtains the corresponding first response sequence, wherein the first response signal is sent to two processing units for the first time, and the first response signal is sent to the remaining two processing units for the second and third times. The number of the two processing units sent for the first time is less than the total number of processing units connected to the first arbitrator. It is understandable that the first arbitrator can control some processing units to switch to a high power consumption state at the same time without controlling all processing units to switch from a low power consumption state to a high power consumption state at the same time, so as to improve arbitration efficiency and ensure the performance of the processing units.

[0107] Exemplarily, when the first arbitrator determines that the current on-chip power supply can meet the normal operation of the circuit when all processing units are controlled to switch to a high power consumption state at the same time, for example: the first arbitrator obtains information that the current overall power consumption is low, or obtains indication information that all processing units can be controlled to switch to a high power consumption state at the same time, or is subject to higher-level regulation or scheduling. The first arbitrator can increase the power consumption state of all processing units after receiving the first request signal. That is, when controlling multiple processing units to switch to a high power consumption state at the same time does not affect the normal operation of the circuit, the maximum number of processing units that switch to a high power consumption state at the same time can be equal to the total number of processing units connected to the arbitrator, that is, at this time, the parallelism of the parallel transmission of the first arbitrator can be less than or equal to M. When the current total power consumption is high, controlling multiple processing units to switch to a high power consumption state at the same time may cause voltage undershoot and cause the circuit to fail to work properly, the maximum number of processing units that switch to a high power consumption state at the same time must be less than the total number of processing units connected to the arbitrator, that is, at this time, the parallelism of the parallel transmission of the first arbitrator is less than M. The first arbitrator can control some processing units to switch to the high power consumption state on the basis of not controlling all processing units to switch to the high power consumption state at the same time, so as to improve arbitration efficiency and ensure the performance of the processing units.

[0108] In some embodiments, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0109] As mentioned above Figure 2 and the above Figure 3A As shown, each processing unit may include one or more high-power consumption units, such as vector accelerators, matrix accelerators, etc. The high-power consumption unit consumes more power when in working state, which will also cause the corresponding processing unit to increase its power consumption. Therefore, the processing unit sending a first request signal to the first arbitrator can be understood as a request to switch some or all of the high-power consumption units in the processing unit from the standby state to the working state, that is, from the low-power consumption state to the high-power consumption state, and after the processing unit receives the first response signal, it controls the part or all of the high-power consumption units to switch from the low-power consumption state to the high-power consumption state. This method can ensure that the high-power consumption unit in the processing unit will not switch to the high-power consumption state autonomously without receiving the first response signal.

[0110] In some embodiments, each of the processing units also includes a prediction module; the prediction module is used to: detect the power consumption state of one or more high-power consumption units in the corresponding processing unit; each of the processing units is specifically used to: send the first request signal to the first arbitrator when the prediction module detects that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0111] Please refer to the attached Figure 4A and Figure 4B , Figure 4A and Figure 4B is a schematic diagram of the structure of a group of processing unit scheduling devices provided in an embodiment of the present application, wherein for the convenience of explanation, Figure 4A and Figure 4B Other processing units connected to the first arbitrator are not shown in the figure. Figure 4A and Figure 4B As shown, each processing unit may further include a prediction module, which may be used to detect the power consumption state of each high power consumption unit in the corresponding processing unit in real time or periodically, and when some or all of the high power consumption units are about to switch to the second power consumption state, a first request signal is promptly sent to the first arbitrator to request that the high power consumption unit be switched from the first power consumption state to the second power consumption state, thereby improving the accuracy and switching efficiency of the processing unit switching the power consumption state.

[0112] In some embodiments, the processing unit also includes a task sending queue, which is used to send a task descriptor of the task; the task descriptor is used to indicate whether the task calls one or more high-power consumption units in the corresponding processing unit; the prediction module is specifically used to: when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0113] like Figure 4AAs shown, a method for the prediction module to predict that the processing unit is about to enter the high power consumption state from the low power consumption state is to judge through the task descriptor of the current task in the task sending queue in the processing unit to determine whether the processing unit or the high power consumption unit in the processing unit is about to enter the high power consumption state from the low power consumption state. The task descriptor can be used to indicate whether the current task needs to call the high power consumption unit in the processing unit. In the case where it indicates that the high power consumption unit in the processing unit needs to be called, it means that the called high power consumption unit is about to enter the high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator to control the high power consumption unit to enter the high power consumption state. Exemplarily, the processing unit may include a matrix accelerator, and when the prediction module can predict based on the characteristics of the currently assigned task in the task sending queue (i.e., the task descriptor), whether the matrix accelerator will be used. For example: when the task descriptor of the currently assigned task in the task sending queue indicates that the task needs to call the matrix accelerator, it can be determined that the matrix accelerator in the processing unit is about to enter the high power consumption state from the low power consumption state to complete the corresponding task.

[0114] In some embodiments, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0115] like Figure 4B As shown, another method for the prediction module to predict that the processing unit is about to enter the high power consumption state from the low power consumption state is to determine whether the processing unit or the high power consumption unit in the processing unit is about to enter the high power consumption state from the low power consumption state by detecting the number of operation instructions in the instruction sending queue of the processing unit. In the case where the number of operation instructions corresponding to the high power consumption unit in the instruction sending queue is accumulated in large quantities (for example, exceeding the preset threshold number), it means that the processing unit is about to enter the high power consumption state, and the prediction module needs to send a first request signal to the first arbitrator so that the first arbitrator controls the processing unit to enter the high power consumption state. For example: when the prediction module detects that there are a large number of calls or instructions for the matrix accelerator in the instruction sending queue in the processing unit, it means that the matrix accelerator needs to enter the working state, that is, it means that the processing unit is about to enter the high power consumption state from the low power consumption state to complete the corresponding task. Among them, the preset threshold number can be set by default, and can also be dynamically adjusted according to the power consumption of the current processing unit or the total power consumption of the global processing unit. The embodiment of the present application does not specifically limit the specific value of the preset threshold number.

[0116] It should be noted that the manner in which the prediction module in each processing unit predicts the power consumption state of the processing unit may be the same or different, and the embodiments of the present application do not impose any specific limitation on this.

[0117] In some embodiments, the first arbitrator is specifically used to arbitrate and obtain the first response order of one or more first request signals according to a preset polling rule or a response priority of one or more processing units among the M processing units.

[0118] The first arbitrator can arbitrate the first response sequence of the first request signal according to a preset polling rule or response priority so as to reply to the first response signal in order. For example: the earlier the first request signal is received, the earlier the response sequence corresponding to the first request signal is replied. Another example: the first response signal of the same processing unit will not be replied to continuously at the same time. Another example: the higher the response priority of the corresponding processing unit, the earlier the response sequence corresponding to the first request signal is replied. This arbitration of the response sequence between multiple processing units according to preset rules can improve the arbitration accuracy of the first arbitrator and avoid poor chip performance caused by errors.

[0119] In some embodiments, the first arbitrator is disposed in the middle of the plurality of processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0120] It should be noted that the first arbitrator is disposed in the middle of the plurality of processing units, which can be roughly in the middle position, and can also be understood as the center of the geometric pattern formed by the plurality of processing units, and is not strictly in the middle position. In addition, the position where the sum of the communication distances between the first arbitrator and each of the processing units is the shortest can refer to the position where the time consumed when the first arbitrator communicates with all of the plurality of processing units is the shortest. As mentioned above Figure 2 and the above Figure 3A As shown, the first arbitrator can be set in the middle of multiple processing units or at a position where the sum of communication distances between multiple processing units is shortest. This setting in the middle can greatly reduce the communication delay between the first arbitrator and the processing units, improve processing efficiency, and ensure processing performance.

[0121] In some embodiments, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the above-mentioned response interfaces is used to send the first response signal to the corresponding processing unit.

[0122] The first arbitrator and each processing unit can communicate through a dedicated interface module. Please refer to the attached Figure 5 , Figure 5 is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application. Figure 5 As shown, the first arbitrator includes multiple groups of communication interfaces, each of which corresponds to a processing unit, for example: the first request signal req and the first response signal grant are transmitted between the processing unit A and the first arbitrator through the communication interface A; the first request signal req and the first response signal grant are transmitted between the processing unit B and the first arbitrator through the communication interface B. Each group of communication interfaces includes a request interface for transmitting the first request signal req and a response interface for transmitting the response signal grant, so that the first arbitrator communicates with the processing unit normally, and the communication efficiency between the first arbitrator and the multiple processing units is greatly improved, so as to avoid the first arbitrator being unable to receive the first request signal in time when multiple processing units send the first request signal to the first arbitrator at the same time.

[0123] Among them, in other embodiments, the request interface and response interface for transmitting signals include an input module and an output module respectively arranged at the corresponding processing unit and the first arbitrator. For example: the request interface is arranged at the output module of the corresponding processing unit and connected with the input module arranged at the first arbitrator, and is used to transmit the first request signal req; the response interface is arranged at the input module of the corresponding processing unit and connected with the output module arranged at the first arbitrator, and is used to transmit the first response signal grant.

[0124] In other embodiments, the request interface and response interface for transmitting signals may also be equivalent to a request output pin and a response output pin respectively arranged at the corresponding processing unit and the first arbitrator. It can be understood that when the electrical signal output by the request output pin changes from a low level to a high level, it can be regarded as the corresponding processing unit transmitting the first request signal req to the first arbitrator; when the electrical signal output by the response output pin changes from a low level to a high level, it can be regarded as the first arbitrator transmitting the first response signal grant to the corresponding processing unit, that is, the handshake signal is transmitted between the first arbitrator and the corresponding processing unit through each group of communication interfaces.

[0125] In some embodiments, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or one of the multiple high power consumption states whose power is less than that of the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0126] Among them, the processing unit will have multiple high power consumption states. For example, the highest power consumption level of the processing unit is 3 and the lowest is 0. Then the processing unit corresponds to 3 high power consumption states of levels 1-3 and 1 standby state of level 0, a total of 4 power consumption states. Among them, the power sizes of the 4 power consumption states are different. Each time the processing unit switches to the second power consumption state, it is one of the multiple high power consumption states, and the original first power consumption state is the standby state or the multiple high power consumption states, and the power is less than one of the high power consumption states in the second power consumption state. And each time the processing unit switches to a higher power consumption state, it is necessary to send a first request signal to the first arbitrator, and then the first arbitrator determines the level of the corresponding adjusted high power consumption state, so that the processing unit can enter different high power consumption states at will, causing the phenomenon of voltage undershoot, resulting in a decrease in output voltage. It should be noted that the definition of the power consumption level of each processing unit and the first arbitrator is consistent.

[0127] In other embodiments, one or more high power consumption units included in the processing unit may be consistent with the definition of power consumption levels by the processing unit and the first arbitrator. For example, the high power consumption unit also has three high power consumption states of levels 1-3 and one standby state of level 0, for a total of four power consumption states. Each time a high power consumption unit switches to a higher power consumption state, the corresponding processing unit needs to send a first request signal to the first arbitrator, and after receiving a response, the processing unit controls the corresponding high power consumption unit to switch to a higher power consumption state.

[0128] In other embodiments, one or more high-power consumption units included in the processing unit may be inconsistent with the definition of the power consumption level of the processing unit and the first arbitrator. For example, the high-power consumption unit has only two power consumption states, namely, the standby state and one high-power consumption state (i.e., the working state). In this case, the number of high-power consumption units in the working state corresponding to each high-power consumption state of the multiple high-power consumption states of the processing unit is different. For example, the processing unit includes three high-power consumption units. When one high-power consumption unit is in the working state and the remaining two high-power consumption units are in the standby state, the power consumption of the processing unit may be one-third of the highest power consumption, and the corresponding level may be 1; when two high-power consumption units are in the working state and the remaining one high-power consumption unit is in the standby state, the power consumption of the processing unit may be two-thirds of the highest power consumption, and the corresponding level may be 2; when all three high-power consumption units are in the working state, the power consumption of the processing unit may be the highest power consumption, and the corresponding level may be 3. It can also be understood that the number of multiple high-power consumption units in the processing unit that enter the high-power consumption state from the low-power consumption state is different, and the power of the high-power consumption state corresponding to the processing unit is also different.

[0129] The first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; each of the processing units is also used to: send current power consumption level information to the first arbitrator, and the current power consumption level information is used to indicate the first power consumption state that the processing unit is currently in.

[0130] When the processing unit has multiple power consumption levels, that is, multiple high power consumption states, each processing unit, when sending a first request signal to the first arbitrator, is also used to send the current power consumption level information indicating the first power consumption state currently in which the processing unit is in to the first arbitrator, and can also receive the target power consumption level information sent by the first arbitrator to indicate the second power consumption state in which the processing unit is in after switching. For example: if the processing unit is in a power consumption state of level 2 and needs to switch to a higher power consumption state, it is necessary to send a first request signal and the current power consumption level information indicating the current power consumption state (level 2) to the first arbitrator; then receive the first response signal carrying the target power consumption level information (such as level 4) returned by the first arbitrator, and the first response signal allows the processing unit to switch to a higher power consumption state, and can switch to a power consumption state of level 4. This adjustment method of the power consumption state of the processing unit controlled by the first arbitrator can globally control the overall power consumption of multiple processing units, which is conducive to ensuring the stability of the output voltage of the power supply network and the performance of the chip.

[0131] In some embodiments, each group of the communication interfaces also includes a power level (Power_level) interface, wherein each of the power level interfaces is used to receive the current power consumption level (Current Power_level) information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information (Grant Power_level).

[0132] Since the processing unit may have multiple high power consumption states, in order to facilitate each processing unit to send its current power consumption state to the first arbitrator in a timely manner, each group of communication interfaces may also include an interface for transmitting current power consumption level information. Figure 6 , Figure 6 is a schematic diagram of a communication interface of a first arbitrator provided in an embodiment of the present application, wherein for the sake of convenience of explanation, Figure 6 The processing unit connected to the first arbitrator is not shown in the figure. Figure 6 As shown, each group of communication interfaces in the first arbiter includes a request interface for transmitting a first request signal req, an energy level interface for transmitting current power consumption level information K1 bits, and a response interface for transmitting a first response signal grant carrying target power consumption level information K2 bits. In addition, in order to reduce control costs and improve control efficiency, the response interface in each group of communication interfaces can also be used to send target power consumption level information. For example, the first response signal can carry the corresponding target power consumption level information.

[0133] In other embodiments, each group of communication interfaces may also be provided with another energy level interface for transmitting target power consumption level information to the corresponding processing unit, and the embodiments of the present application do not impose specific limitations on this.

[0134] In some embodiments, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, the second arbitrator is connected to the first arbitrator in each of the first processing clusters; each of the first arbitrators is specifically used to: send a second request signal to the second arbitrator when receiving the first request signal; the second arbitrator is used to: receive the second request signal sent by one or more of the first arbitrators; arbitrate to obtain a second response sequence of one or more of the second request signals; and control one or more of the first arbitrators based on the second response sequence.

[0135] Please refer to the attached Figure 7 , Figure 7 is a structural diagram of another processing unit scheduling device provided in an embodiment of the present application. In an embodiment of the present application, a multi-level arbitration architecture may also be provided, such as Figure 7As shown, the embodiment of the present application provides a two-level arbitration architecture of the processing unit scheduling device, that is, the first-level arbitration architecture refers to the arbitration of multiple processing units PE switching to high power consumption state by the first arbitrator 01 with one processing unit PE as the granularity, and the second-level arbitration architecture refers to the arbitration of multiple processing units PE switching to high power consumption state by the second arbitrator 02 with one first processing cluster as the granularity. For example, as mentioned above Figure 7 As shown, when the processing unit PE-A is about to switch from the first power consumption state to the second power consumption state, it sends a first request signal to the first arbitrator 01-A; after receiving the first request signal, the first arbitrator 01-A sends a second request signal to the second arbitrator 02. The second arbitrator 02 arbitrates the received second request signal, obtains the corresponding second response sequence, and controls the first arbitrator 01-A to respond to the first request signal sent by the processing unit PE-A according to the second response sequence. Therefore, through this multi-level arbitration structure. In the global state, only some of the processing units in some of the first processing clusters can enter the high power consumption state at the same time, which greatly reduces the number of processing units that enter high power consumption at the same time, and further ensures the stability of the output voltage of the power supply network and the performance of the chip.

[0136] It should be noted that the multi-level arbitration structure of the processing unit scheduling device can be adaptively adjusted according to the application scenario. For example, the processing unit scheduling device can also include more levels of arbitration structures, such as a three-level arbitration structure or a four-level arbitration structure, etc., which is not specifically limited in the embodiments of the present application.

[0137] In some embodiments, the second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0138] Among them, the second arbitrator 02 controls the response of the first arbitrator through the second response signal. The second arbitrator 02 arbitrates the second request signal A sent by the first arbitrator 01-A, obtains the second response sequence corresponding to the second request signal A, and sends the second response signal to the first arbitrator 01-A according to the second response sequence. After receiving the second response signal, the first arbitrator 01-A controls the processing unit PE-A to switch from the first power consumption state to the second power consumption state according to the first response sequence obtained by its arbitration. After the second arbitrator sends the second response signal to the corresponding first arbitrator, the first arbitrator can control the corresponding processing unit to switch from the first power consumption state to the second power consumption state in sequence. That is, before the first arbitrator 01 receives the second response signal, it will not control the corresponding processing unit to switch to the high power consumption state according to the first response sequence. This control method through the response signal can more easily control the arbitrators at all levels, reduce the error rate, and ensure the operating performance of the chip.

[0139] In some embodiments, in the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0140] Similar to the first arbitrator, in order to ensure that the voltage undershoot does not cause the instantaneous voltage to be less than the minimum voltage V at which the circuit can work normally, and the chip function error phenomenon, the time interval of each response of the second arbitrator to the first arbitrator can be greater than or equal to the second preset time interval, and the embodiment of the present application does not specifically limit the second preset time interval. Among them, the second preset time interval can be 0 or not. Moreover, the second preset time interval and the first preset time interval can be different or the same.

[0141] Similar to the first arbitrator, when the second arbitrator determines that all processing units in multiple first processing clusters can be switched to a high power consumption state at the same time and the current on-chip power supply can still meet the normal operation of the circuit, the second preset time interval can be 0. For example: when the second arbitrator obtains information that the current overall power consumption is low, or is subject to a higher level of regulation or scheduling. After receiving the second request signal, the second arbitrator can control the first arbitrators in all the first processing clusters and instruct them to pull up the connected processing units. The second arbitrator can simultaneously control the processing units in all the first processing clusters to switch to a high power consumption state, which can improve arbitration efficiency and ensure the performance of the processing units.

[0142] In addition, the second preset time interval and the first preset time interval can be fixed time intervals set by default, or dynamically adjustable time intervals. In other embodiments, the maximum number of processing units that can be pulled up at a time can be adaptively adjusted by configuring the second preset time interval and the first preset time interval to adapt to more application scenarios. For example: when the global power consumption state is very low, the first preset time interval and the second preset time interval can both be set to 0, and the power consumption state of all processing units can be switched at the same time; when the global power consumption state is relatively low, the first preset time interval can be set to non-0, and the second preset time interval can be set to 0; or the first preset time interval is set to 0, and the second preset time interval is set to non-0, and the power consumption state of some processing units can be switched at the same time. When the global power consumption state is relatively high, the first preset time interval and the second preset time interval can both be set to non-0, and the power consumption state of a small number of processing units can be switched at the same time.

[0143] In other embodiments, the second arbitrator may be regulated by a higher-level controller, that is, it is understandable that the working state of the second arbitrator may also be controlled according to the current global power consumption state, for example: when only a small part of the current global processing units (that is, all the processing units in the first processing cluster) are about to switch to high power consumption, and the other processing units are in a low power consumption state, the second arbitrator may be in a standby state, at which time the first arbitrator of the first processing cluster may not need to send a second request signal to the second arbitrator, and may directly arbitrate and respond to the first request signal. Alternatively, the second arbitrator may be in a normal working state, at which time the second preset time interval may be directly set to 0, so as to respond to the first arbitrator faster and improve performance. When a large part of the current global processing units are about to switch to high power consumption, the second arbitrator may be in a normal working state, and the second preset time interval may be set not to 0, so as to reduce and weaken the phenomenon of voltage undershoot and maintain the normal function of the circuit.

[0144] In summary, in order to avoid voltage undershoot and functional errors caused by multiple processing units entering a high power state from a low power state at the same time, the embodiment of the present application provides a processing unit scheduling device, which can avoid multiple processing units entering a high power state from a low power state at the same time from a hardware perspective, reduce the undershoot amplitude of the voltage undershoot, so that the minimum instantaneous voltage of the voltage undershoot is higher than the working voltage of the normal circuit, thereby ensuring the signal integrity of the chip. Among them, the processing unit scheduling device can be applied to a chip or a related circuit module, and the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator. When any one of the multiple processing units connected to the first arbitrator is about to enter a high power state from a low power state (that is, from a first power state with lower power to a second power state with higher power), each processing unit must send a first request signal to the first arbitrator to request to switch the power consumption state. When the first arbitrator receives the above-mentioned first request signal sent by the processing unit connected to it, it can arbitrate the received first request signal and obtain the corresponding response sequence through arbitration, so that the first arbitrator can control the corresponding processing unit to enter the high power consumption state from the low power consumption state in sequence according to the response sequence, thereby avoiding that all the multiple processing units connected to the first arbitrator enter the high power consumption state from the low power consumption state at the same time, causing voltage undershoot, resulting in functional errors and affecting signal integrity. For example: when the instantaneous voltage is less than the minimum voltage Vmin for the MOS tube to work normally, the MOS tube is turned off, resulting in chip functional errors. In this case, an arbitrator is connected between multiple processing units, and each processing unit will pass the arbitration of the arbitrator when switching the power consumption state, so that the arbitrator can be used to schedule some of the multiple processing units to switch the power consumption state. Moreover, compared with the software algorithm scheduling inside the device or apparatus, the overhead of the device or apparatus is greatly reduced, and the probability of all processing units entering the high power consumption state from the low power consumption state at the same time due to scheduling errors is also reduced, thereby ensuring the signal performance of the chip.

[0145] Based on the above Figure 2 The structure of the processing unit scheduling device provided is combined with the processing unit scheduling method provided in the embodiment of the present application to specifically analyze and solve the technical problems raised in the present application.

[0146] See also Figure 8 , Figure 8 The present application provides a flowchart of a processing unit scheduling method, which is applied to the above Figure 2-Figure 7 The processing unit scheduling device shown in the figure comprises a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; the method comprises:

[0147] Step S201: receiving a first request signal respectively sent by one or more processing units among the M processing units.

[0148] Specifically, the first arbitrator receives a first request signal sent by one or more processing units among the M processing units connected to it, and the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state.

[0149] Optionally, each of the processing units also includes a prediction module; the method also includes: detecting the power consumption state of one or more high-power consumption units in the corresponding processing unit through the prediction module; when the prediction module detects that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state, sending the first request signal to the first arbitrator through the corresponding processing unit.

[0150] Optionally, each of the processing units also includes a task sending queue, which is used to send a task descriptor of the current task; the task descriptor is used to indicate whether the current task calls the one or more high-power consumption units in the corresponding processing unit; detecting the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: obtaining the task descriptor of the current task in the task sending queue, wherein, when the task descriptor indicates that the current task calls some or all of the high-power consumption units in the corresponding processing unit, determining that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0151] Optionally, each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; the detection of the power consumption state of the one or more high-power consumption units in the corresponding processing unit through the prediction module includes: detecting the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue, wherein, when it is detected that the number of operation instructions corresponding to some or all of the high-power consumption units in the instruction sending queue exceeds a preset threshold number, it is determined that some or all of the high-power consumption units will switch from the first power consumption state to the second power consumption state.

[0152] Optionally, the first arbitrator is arranged in the middle of the multiple processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

[0153] Step S202: Arbitrate and obtain a first response sequence of one or more first request signals.

[0154] Specifically, the first arbitrator performs arbitration on the received one or more first request signals, and obtains a first response sequence of the one or more first request signals through arbitration.

[0155] Optionally, the arbitration obtains the first response order of one or more of the first request signals, including: arbitrating according to a preset polling rule or the response priority of one or more processing units among the M processing units to obtain the first response order of one or more of the first request signals.

[0156] Step S203: Based on the first response sequence, control one or more processing units to switch from the first power consumption state to the second power consumption state.

[0157] Specifically, the first arbitrator controls one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence.

[0158] Optionally, controlling the one or more processing units to switch from the first power consumption state to the second power consumption state based on the first response sequence includes: sending a first response signal to the one or more processing units respectively based on the first response sequence, the first response signal being used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; wherein, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

[0159] Optionally, the first arbitrator sends the corresponding first response signal to the one or more processing units respectively through a serial and / or parallel sending manner; wherein, when the first arbitrator sends the corresponding first response signal to the one or more processing units through a parallel sending manner, the parallelism of the parallel sending is less than or equal to M.

[0160] Optionally, each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct some or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0161] Optionally, the first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the above-mentioned response interfaces is used to send the first response signal to the corresponding processing unit.

[0162] Optionally, each of the processing units corresponds to a standby state and multiple high power consumption states, each of the high power consumption states has a different power size, the second power consumption state is one of the multiple high power consumption states, and the first power consumption state is the standby state or a high power consumption state among the multiple high power consumption states whose power is less than that of the second power consumption state; wherein the first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state that the processing unit is in after switching; the method also includes: receiving current power consumption level information sent by one or more processing units among the M processing units, and the current power consumption level information is used to indicate the first power consumption state that the corresponding processing unit is currently in.

[0163] Optionally, each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

[0164] Optionally, the first arbitrator and the M processing units constitute a first processing cluster; the device also includes a second arbitrator and multiple first processing clusters, and the second arbitrator is connected to the first arbitrator in each of the first processing clusters; the method also includes: receiving, through the second arbitrator, a second request signal sent by one or more of the first arbitrators when the first request signal is received; obtaining a second response sequence of one or more of the second request signals through arbitration by the second arbitrator; and controlling the corresponding one or more of the first arbitrators based on the second response sequence.

[0165] Optionally, controlling the corresponding one or more first arbitrators based on the second response sequence includes: sending a second response signal to the corresponding one or more first arbitrators based on the second response sequence, the second response signal being used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

[0166] Optionally, in the second response sequence, a time interval between each time the second response signal is sent to the corresponding second arbitrator and the last time the second response signal was sent to the corresponding second arbitrator is greater than or equal to a second preset time interval.

[0167] It should be noted that the description of steps S201 to S203 in the method embodiment described in the embodiment of the present application can be found in the above Figure 2-Figure 7 The relevant description of the functions of each functional unit of the processing unit scheduling device in the device embodiment shown will not be repeated here in the embodiment of the present application.

[0168] In addition, an embodiment of the present application further provides a chip, which includes a circuit and a processing unit scheduling device as described in any of the above embodiments and applied to the circuit. The chip may also include a power supply network, which can be used to supply power to the processing unit scheduling device.

[0169] An embodiment of the present application further provides an electronic device, comprising: a circuit board and the processing unit scheduling device involved in any of the aforementioned embodiments; the circuit board is electrically connected to the processing unit scheduling device.

[0170] The embodiment of the present application further provides a server, the server comprising a circuit board and the processing unit scheduling device involved in any of the above embodiments; the circuit board is electrically connected to the processing unit scheduling device. Optionally, the server further comprises an on-chip power supply system to supply power to the processing unit scheduling device.

[0171] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When the above-mentioned processor executes the computer program code, the computer executes the method in any of the above-mentioned embodiments.

[0172] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer executes the method in any of the aforementioned embodiments.

[0173] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0174] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0175] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0176] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0177] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0178] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A processing unit scheduling device, characterized in that: The device comprises a first arbitrator and M processing units PE connected to the first arbitrator, where M is a positive integer greater than or equal to 2; wherein, Each of the processing units is used to: send a first request signal to the first arbitrator, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, wherein the power of the first power consumption state is lower than the power of the second power consumption state; The first arbitrator is used to: receive the first request signals respectively sent by one or more processing units among the M processing units, and arbitrate to obtain a first response sequence of one or more of the first request signals; based on the first response sequence, control the one or more processing units to switch from the first power consumption state to the second power consumption state.

2. The device according to claim 1, characterized in that: The first arbitrator is specifically configured to: send a first response signal to the one or more processing units respectively based on the first response sequence, wherein the first response signal is used to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state; Among them, in the first response sequence, the time interval between each time the first response signal is sent to the corresponding processing unit and the last time the first response signal was sent to the corresponding processing unit is greater than or equal to a first preset time interval.

3. The device according to claim 2, characterized in that: The first arbitrator sends the corresponding first response signal to the one or more processing units respectively in a serial and / or parallel sending manner; In which, when the first arbitrator sends the corresponding first response signal to the one or more processing units in a parallel sending manner, the parallel degree of the parallel sending is less than or equal to M.

4. The device according to claim 2 or 3, characterized in that: Each of the processing units includes one or more high power consumption units HPU, and the first response signal is used to instruct part or all of the high power consumption units in the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

5. The device according to claim 4, characterized in that: Each of the processing units also includes a prediction module; The prediction module is used to: detect the power consumption state of one or more high power consumption units in the corresponding processing unit; and send the first request signal to the first arbitrator when it is detected that some or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

6. The device according to claim 5, characterized in that: Each of the processing units further comprises a task sending queue, wherein the task sending queue is used to send a task descriptor of a current task; the task descriptor is used to indicate whether the current task calls the one or more high power consumption units in the corresponding processing unit; The prediction module is specifically used to: when the task descriptor indicates that the current task calls part or all of the high power consumption units in the corresponding processing unit, determine that the part or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

7. The device according to claim 5, characterized in that: Each of the processing units also includes an instruction sending queue; the instruction sending queue is used to send operation instructions; The prediction module is specifically used to: when it is detected that the number of operation instructions corresponding to some or all of the high power consumption units in the instruction sending queue exceeds a preset threshold number, determine that some or all of the high power consumption units will switch from the first power consumption state to the second power consumption state.

8. The device according to any one of claims 1 to 7, characterized in that: The first arbitrator is arranged in the middle of the plurality of processing units; or the sum of the communication distances between the first arbitrator and each of the processing units is the shortest.

9. The device according to any one of claims 1 to 8, characterized in that: The first arbitrator includes M groups of communication interfaces, each group of the communication interfaces corresponds to one of the processing units, and each group of the communication interfaces includes a request interface and a response interface; wherein each of the request interfaces is used to receive the first request signal sent by the corresponding processing unit, and each of the above-mentioned response interfaces is used to send a first response signal to the corresponding processing unit.

10. The device according to claim 9, characterized in that: Each of the processing units corresponds to a standby state and a plurality of high power consumption states, each of the high power consumption states has a different power level, the second power consumption state is one of the plurality of high power consumption states, and the first power consumption state is the standby state or a high power consumption state in the plurality of high power consumption states whose power is less than that in the second power consumption state; The first response signal includes target power consumption level information, and the target power consumption level information is used to indicate the second power consumption state of the processing unit after switching; Each of the processing units is further used for sending current power consumption level information to the first arbitrator, where the current power consumption level information is used for indicating the first power consumption state that the processing unit is currently in.

11. The device according to claim 10, characterized in that: Each group of the communication interfaces further includes an energy level interface, wherein each of the energy level interfaces is used to receive the current power consumption level information sent by the corresponding processing unit, and each of the response interfaces is also used to send the target power consumption level information.

12. The device according to any one of claims 1 to 11, characterized in that: The first arbitrator and the M processing units form a first processing cluster; the device further comprises a second arbitrator and a plurality of the first processing clusters, the second arbitrator being connected to the first arbitrator in each of the first processing clusters; Each of the first arbitrators is specifically configured to: upon receiving the first request signal, send a second request signal to the second arbitrator; The second arbitrator is used for: receiving the second request signal sent by one or more first arbitrators; Arbitrating to obtain a second response sequence of one or more of the second request signals; Based on the second response order, one or more of the first arbitrators are controlled.

13. The device according to any one of claim 12, characterized in that: The second arbitrator is specifically used to: send a second response signal to one or more of the first arbitrators based on the second response sequence, and the second response signal is used to instruct the corresponding first arbitrator to control the corresponding processing unit to switch from the first power consumption state to the second power consumption state.

14. The device according to any one of claim 12, characterized in that: In the second response sequence, a time interval between each sending of the second response signal to the corresponding second arbitrator and the last sending of the second response signal to the corresponding second arbitrator is greater than or equal to a second preset time interval.

15. A processing unit scheduling method, characterized in that: Applied to a processing unit scheduling device, the processing unit scheduling device includes a first arbitrator and M processing units PE connected to the first arbitrator, M being a positive integer greater than or equal to 2; the method includes: receiving first request signals respectively sent by one or more processing units among the M processing units, and obtaining a first response sequence of one or more of the first request signals by arbitration, wherein the first request signal is used to request that the corresponding processing unit be switched from a first power consumption state to a second power consumption state, and the power of the first power consumption state is lower than the power of the second power consumption state; Based on the first response sequence, the one or more processing units are controlled to switch from the first power consumption state to the second power consumption state.

16. A chip, characterized in that: It comprises a circuit and a processing unit scheduling device as claimed in any one of claims 1 to 14 applied to the circuit.

17. A server, characterized in that: The server comprises a circuit board and a device as described in any one of claims 1 to 14; the circuit board is electrically connected to the device.

18. An electronic device, characterized in that: The electronic device comprises: a circuit board and a device as described in any one of claims 1 to 14; the circuit board is electrically connected to the device.

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