Fault prediction method and device and storage medium

Abstract

The invention discloses a fault prediction method and device and a storage medium, and is applied to the technical field of computers, and the method comprises the steps: collecting ECS information, carrying out the statistics of error correction times completed in a memory particle, tracking an occurrence position, and positioning a potential weak address region where ECC frequently occurs in the particle; analyzing information such as fault types, fault addresses, error reporting time, error reporting memory temperatures, task types, task pressure and occupancy rates by the aid of the information reported by the BMC; through the above information, comprehensive working state information is obtained, the working state information is input into a probabilistic neural network PNN, probability distribution of different fault types occurring in a memory is predicted, the effect of assisting fault prediction and judgment is achieved, and prediction accuracy is improved. In addition, the working state information is input into the PNN, and the predicted probability that the memory bank has an uncorrectable fault can be obtained. Furthermore, the operation and maintenance personnel can set a fault excitation test scheme, and system risks brought by the CXL memory are eliminated.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a fault prediction method, device and storage medium. Background Art

[0002] Compute Express Link (CXL) memory usually carries a large capacity extended memory that can be used in conjunction with the host memory of a computer device. As a key component of a computer device, the health of the memory directly affects the operating efficiency of the operating system and the normal operation of the business. If the memory fails, the computer device's operating performance will be reduced or it will crash, causing problems such as loss of operating data.

[0003] At present, memory manufacturers provide memory for some companies. Users are not clear about the internal structure of memory and have no mechanism to detect memory with potential faults but not yet faulted. They can only return the faulty memory to the manufacturer for repair after the memory fails. At this time, the business is often interrupted, and the memory repair cycle is long, which has an adverse impact on the normal operation of the user's business. In order to ensure the reliability of CXL memory, it is very necessary to predict the fault of CXL memory. Summary of the invention

[0004] The embodiments of the present application provide a fault prediction method, device, and storage medium, which can predict the probability of different types of faults occurring in a CXL memory.

[0005] In a first aspect, an embodiment of the present application provides a fault prediction method, which includes: obtaining working status information of a computing fast link CXL memory to be tested, the working status information including error information inside memory particles and information during the memory working process reported by a baseboard management controller BMC; inputting the working status information into a probabilistic neural network to obtain a probability distribution of multiple fault categories.

[0006] In the embodiment of the present application, the probabilistic neural network analyzes the error mode of the memory to be tested through ECS information and BMC information, and predicts the probability of different faults occurring through the error mode exhibited by the memory to be tested. Furthermore, the equipment users and operation and maintenance personnel can analyze whether the memory to be tested will fail in the future based on the probability distribution of multiple fault categories, so as to discover possible faults in advance, thereby performing maintenance in a timely manner and improving the overall reliability of the system.

[0007] In addition, by obtaining the error information inside the memory particles and the information reported by the BMC during the memory working process, more comprehensive and diverse information is obtained. By using more comprehensive and diverse information, the fault characteristics of the probabilistic neural network can be enriched, and a more accurate probability distribution can be obtained, which is conducive to equipment users and operation and maintenance personnel to accurately predict memory faults and judge fault types based on memory working status information.

[0008] In addition, in the embodiment of the present application, PNN plays the role of auxiliary prediction. Fault prediction is performed through PNN, and probability distribution is given. The probability distribution and experience are then combined to analyze whether a fault occurs. In this way, it does not rely entirely on the results of machine learning and can more effectively predict possible memory failures.

[0009] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, the error information inside the memory particle includes: the number of error corrections that occur inside the memory particle and / or the location where each error correction occurs. The location where the memory error correction occurs includes, but is not limited to: a specific row and column unit inside the memory particle, a row, a column, a bank, and a bank group. The processor can access the corresponding register through the CXL control chip, obtain the error information inside the memory particle from the register, and then obtain the number of error corrections that occur inside the memory particle and the location where each error correction occurs.

[0010] Among them, the information during the memory working process may include fault type, fault address, CPU occupancy, memory capacity occupancy, memory insertion method, memory slot, error reporting time, error reporting memory temperature, task category, memory frequency, voltage and other information.

[0011] In combination with the first aspect above, in certain implementations of the first aspect, the above-mentioned inputting the working status information into the probabilistic neural network to obtain the probability distribution of multiple fault categories includes: inputting the working status information into the probabilistic neural network to obtain the probability distribution of multiple device-level fault categories. In this way, operation and maintenance personnel can discover possible device-level faults in advance, so as to perform maintenance in time and improve the reliability of CXL memory. By predicting the probability of occurrence of device-level fault categories, it can also help memory manufacturers optimize processes and design more stable memory.

[0012] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: inputting the working status information into a probabilistic neural network, and outputting the confidence level of the CXL memory having a UCE failure. The confidence level can then be used to predict whether the CXL memory will have a UCE failure. For example, when the confidence level is greater than a confidence level threshold, it is determined that the CXL memory will have a UCE failure. In this way, when it is predicted that a UCE failure may occur, preventive measures can be taken in a timely manner, such as isolation or replacement of a memory stick.

[0013] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, before inputting the working status information into the neural network, the above-mentioned method also includes: performing information screening and correlation analysis on the working status information to determine the correlation relationship between different features in the working status information. The above-mentioned inputting of the working status information into the probabilistic neural network includes: inputting the working status information and the correlation relationship into the probabilistic neural network. Among them, information screening can clean the features and eliminate abnormal features. Correlation analysis can find the hidden correlations between various features and determine the conditional relationship between various types of feature information, which helps PNN understand the relationship between features and improve the speed and accuracy of fault prediction.

[0014] In combination with the first aspect, in some implementations of the first aspect, after determining the association relationship between different features in the working state information, the method further includes: determining a correlation threshold corresponding to the association relationship; when the correlation of the association relationship is greater than the correlation threshold, determining that the association relationship is credible; inputting the working state information and the association relationship into the probabilistic neural network, including: inputting the credible association relationship among the working state information and the association relationship into the probabilistic neural network. In this way, the accuracy of fault prediction can be improved.

[0015] In combination with the first aspect, in some implementations of the first aspect, before inputting the working status information into the neural network, the method further includes: performing spatial and temporal correlation analysis on the working status information to obtain an estimated fault category, and a correspondence between the estimated fault category and information in the memory working process reported by the BMC. Inputting the working status information and the association relationship into the probabilistic neural network includes: inputting the working status information, the association relationship, the estimated fault category, and the correspondence relationship into the probabilistic neural network.

[0016] By analyzing the spatial and temporal correlation of different information in the working status information, we can preliminarily separate obvious error patterns, such as row, column, or row-column compound error patterns, which is conducive to the probabilistic neural network to recognize the error pattern more quickly and accelerate the network's cognition of the fault pattern. In this process, if a considerable number of faults show obvious temporal or spatial correlation, it is possible to preliminarily determine which type of fault the frequent errors are caused by spatially. For example, error records that show obvious row correlation represent that the memory may have row faults, and the possible fault types in the row faults can be further refined. If there is an obvious temporal correlation, the cause of the error can also be found from the characteristic information such as the task category, voltage, and temperature performed in the memory during this period. Inputting the results of the spatiotemporal correlation analysis into the PNN can predict a more accurate fault type and is also conducive to judging whether the fault will further deteriorate into a UCE fault.

[0017] In a second aspect, an embodiment of the present application provides a computing device, which includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to enable the computing device to implement a method as described in any one of the above-mentioned first aspects.

[0018] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, the computer executes any one of the methods described in the first aspect.

[0019] In a fourth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the methods described in the first aspect above.

[0020] The technical effects obtained by the above-mentioned second aspect, third aspect and fourth aspect are similar to the technical effects obtained by the corresponding technical means in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of a server provided in an embodiment of the present application is shown;

[0022] Figure 2 A schematic diagram of the structure of a storage unit of a memory provided in an embodiment of the present application is shown;

[0023] Figure 3 A flow chart of a training model provided in an embodiment of the present application is shown;

[0024] Figure 4 A schematic diagram of a process flow of a fault prediction method provided in an embodiment of the present application is shown;

[0025] Figure 5 A schematic diagram of the structure of a device provided in an embodiment of the present application is shown;

[0026] Figure 6 A schematic structural diagram of a chip provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the present application clearer, the implementation mode of the present application will be further described in detail below with reference to the accompanying drawings. Hereinafter, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present embodiment, unless otherwise specified, the meaning of "multiple" is two or more.

[0028] Compute Express Link (CXL) memory usually carries a large capacity extended memory, which can be used in conjunction with the host memory of the computer device. CXL technology is of great significance to the memory cluster application of future servers. At present, memory manufacturers provide memory to some companies (users). Users are not clear about the internal structure of the memory and have no mechanism to detect memory that has potential faults but has not yet failed. They can only return the faulty memory to the manufacturer for repair after the memory fails. At this time, the business is often interrupted, and the memory repair cycle is long, which has an adverse impact on the normal operation of the user's business.

[0029] In order to ensure the reliability of CXL memory, how to identify and handle risky memory in advance to prevent more memory failures from affecting business and reduce the risk of system downtime has become a great challenge. Therefore, it is very necessary to predict the failure of CXL memory. CXL memory can also be called CXL extended memory.

[0030] In view of this, the embodiment of the present application collects error check and scrub (ECS) information, counts the number of error corrections (ECC) completed in the memory particles and tracks the occurrence location, locates the potential weak address area where ECC frequently occurs in the particles; uses BMC to parse out the fault type, fault address, error reporting time, and collects information such as error reporting memory temperature, task category, task pressure, occupancy rate, etc.; the above information forms complete working status information, and inputs the working status information into the probabilistic neural network (PNN) to obtain the probability distribution of device-level faults of different categories in the memory, which plays a role in assisting fault prediction and judgment and improving the accuracy of prediction. In addition, by inputting the working status information into the probabilistic neural network, the probability of uncorrectable error (UCE) occurring in the memory bar to be predicted can also be obtained. Further, the operation and maintenance personnel can also set different fault excitation test schemes according to the fault category confidence output by the neural network to eliminate the system risks brought by CXL memory.

[0031] In order to facilitate understanding of the technical solution of the present application, the system architecture involved in the embodiment of the present application is first described below. Figure 1 , Figure 1 A structural schematic diagram of a computing device is shown.

[0032] Computing devices (also referred to as "servers") may include but are not limited to personal computers, physical servers, cloud servers, workstations, hyperterminals, etc. Figure 1 As shown, the hardware part of the computing device 10 includes a processor 110 , a CXL extended memory 120 , a management controller 130 , a CXL extended memory control chip 140 , and a register 150 .

[0033] The processor 110 may include various processing devices, such as a central processing unit (CPU), a system on chip (SOC), a processor integrated on a SOC, a separate processor chip or a controller, etc. The processor 110 may also include a dedicated processing device, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), etc. The processor 110 may be a processor group composed of multiple processors, and the multiple processors are coupled to each other through one or more buses.

[0034] The CXL extended memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. For example, a synchronous dynamic random access memory (DRAM), a double data rate synchronous dynamic random access memory DDR (double data rate) SDRAM, etc. The CXL extended memory includes at least one memory chip (device), each memory chip may be divided to indicate a storage array group (bank group, BG), each storage array group includes a plurality of storage arrays (bank), each storage array is divided into a plurality of storage cells (cell), each storage cell has a row address and a column address, and each storage cell includes one or more bits. In one division method, the memory may be divided into a memory chip, a storage array group, a storage array, a storage row / storage column, a storage cell, and a bit from the upper level to the lower level.

[0035] Among them, the management controller 130 is used to remotely maintain and manage the computing device 10 through a dedicated data channel. The management controller 130 is completely independent of the operating system of the computing device 10 and can communicate with the processor, memory, etc. through the out-of-band management interface of the computing device.

[0036] Exemplarily, the management controller 130 may include a management unit for computing the running status of the device, a management system in a management chip outside the processor, an out-of-band management controller (baseboard management controller, BMC), etc. It should be noted that the embodiments of the present application do not limit the specific form of the management controller, and the above is only an example. In the following embodiments, the out-of-band management controller BMC is used as an example for description.

[0037] The CXL control chip 140 and the register 150 are integrated on the CXL memory particle board. The CXL control chip 140 is used to uniformly manage the CXL memory, including controlling the issuance of memory operation instructions, data transmission operations, etc., and accessing memory-specific registers. The register 150 can record ECS information.

[0038] In a memory system, faults from different structural levels may affect the normal operation of the memory, and without isolation and repair measures, they may further evolve into more serious system-level problems. The types of memory system faults can be divided into device level, strip level and system level according to the degree of segmentation of the fault location. The device level focuses on the basic storage unit 1T1C of the memory and the surrounding wiring and control circuit structure. For example, Figure 2 A schematic diagram of the structure of a memory storage unit 1T1C is shown, Figure 2 As shown, the cell storage array is arranged into columns and rows. The cells in a column are connected to a single bitline sense amplifier (BLSA) in each column through bitlines (BL). One cell in each column can be electrically connected to a BLSA at any time, and a group of such cells forms a row. All cells in a row are connected to a sub-wordline driver through a sub-wordline, and a row is selected by operating the sub-wordline driver.

[0039] Device-level failures can be divided into three types of failures based on the area where the failure occurs. These three types of failures can be further divided into cell failures, row failures, column failures, and shielding failures from components such as pins or resistors.

[0040] According to the three types of failures, this application defines 32 common fault types, which are also the classification basis for fault classification in the following text. Cell failure comes from the failure of 1T1C unit, including but not limited to leakage between capacitors, leakage from word line to capacitor, channel leakage, PN junction leakage, capacitor leakage, gate-induced drain leakage (GIDL) leakage; Row failure includes but is not limited to leakage from word line to bit line, sub-word line (SWL) disconnection, SWL and sub-word line driver (SWD) short circuit, SWD and power or ground short circuit, M0C and BG open circuit, adjacent SWL / BG bridge, M0C and substrate short circuit, row decoding error; Column failure includes leakage between bit lines, BG and bit line contact BLC short circuit, M0C and GBL open circuit, BL disconnection, SA failure, M0 / M1C and SA Gate short circuit, adjacent BL / GBL bridge, column decoding error; Block failure includes but is not limited to leakage between word lines, main word line (MWL) bridge, MWL disconnection, SWD and M1C open circuit, SWD and M0C open circuit, copper migration, Bank control logic failure; Shield failure includes but is not limited to poor contact of gold fingers, power pin problems, and resistance and capacitance component failure on memory sticks. The probability of occurrence of these device-level fault types will be predicted later through the fault prediction method provided in the embodiments of the present application.

[0041] In the embodiment of the present application, a probabilistic neural network is used for probability prediction. It should be understood that before using the neural network model to predict the probability of the occurrence of a fault type, a neural network model needs to be trained first. The model training method provided in the embodiment of the present application is described in detail below. Figure 3 A flowchart of a model training method is shown.

[0042] S301, a computing device obtains a sample data set, each sample data includes ECS information corresponding to a memory particle and information of a memory working process reported by a baseboard management controller BMC.

[0043] When training the model, a sample data set can be collected in advance through multiple training memory bars. Each training memory bar can include multiple memory particles, including memory particles with device-level failures and normal memory particles without device-level failures. For each memory particle, the corresponding register is accessed through the CXL control chip to collect the corresponding ECS ​​information, which is the error information inside the memory particle.

[0044] The source of ECS information is the On-die ECC function unique to Double Data Rate Synchronous Dynamic Random Access Memory (DDR) 5 memory. On-die ECC is a technology that integrates the ECC mechanism on the memory particle chip. On-die ECC provides error detection and repair functions by embedding redundant circuits and detection mechanisms inside the chip.

[0045] Generally speaking, the area where error correction ECC may occur includes the inside of the memory chip and the signal path. In the embodiment of this application, the focus is mainly on the on-die ECC function of the memory chip, that is, the area inside the memory chip, which is where most faults occur. Therefore, the ECC behavior inside the memory chip is directly focused on through the ECS information inside the memory chip.

[0046] The on-die ECC function continuously refreshes the error status of the current array during periodic screening. Each refresh can obtain the current error status of the array, and the number of errors that have occurred will be refreshed and accumulated into the corresponding register. The number of failures can be obtained later by reading the register; at the same time, the addresses where frequent failures occur will also be recorded in the corresponding register, and the addresses will be compared and reloaded in each refresh. If the number of failures exceeding the last recorded address is not found in the new refresh, the address in the register will not be refreshed. Therefore, after the CXL memory generates ECS information, the corresponding register can be accessed through the CXL control chip to obtain the ECS information from the corresponding register. The ECS information can be used to count the number of ECCs completed in the memory particles and track the location where the ECC occurs, that is, to determine the distribution and number of errors, for example, to know where the error correction mainly occurs.

[0047] The location where the memory ECC occurs, or the potential weak address area, includes but is not limited to: a specific row and column unit inside the memory particle, a row, a column, a bank, or a bank group. For example, if a fault occurs at the unit in the first row and the first column, then the ECC occurrence location can be recorded as the unit in the first row and the first column. For another example, if multiple units in the first row fail, then the ECC occurrence location can be recorded as the first row.

[0048] Finally, the ECS information of each memory particle can be obtained. For example, the ECS information of a memory particle can be recorded as A0(a1, a2, a3), where a1 represents the total number of fault repairs that occurred in the memory particle in the past. a2 represents the number of rows where the memory particle had the most fault repairs in the past. a3 represents the row address information where the memory particle had the most repairs in the past.

[0049] The BMC records the information of the memory stick during its operation in the background. The information reported by the BMC can be used to parse the information of each training memory stick during its operation, including fault type, fault address, CPU occupancy, memory capacity occupancy, memory insertion method, memory slot, error reporting time, error reporting memory temperature, task category, memory frequency, voltage and other information. These factors affect the operation of the memory.

[0050] Among them, the fault type is the type of fault that has occurred outside the memory particle (different from the inside of the memory particle), including correctable errors (CE) and UCE. The outside of the memory particle includes the memory particle channel, components on the memory bar, and other structures. The fault address is the address where the fault occurred inside the chip. The memory capacity occupancy rate is the proportion of the occupied memory capacity. The CPU occupancy rate is the CPU resources occupied by the running program.

[0051] Memory insertion method refers to whether a memory channel can be inserted with one memory stick or two memory sticks. For the latter, the memory can split the storage task and store it in two memory sticks respectively, reducing the storage pressure of each memory stick. For the former, the pressure on the memory stick will be greater. Therefore, different memory insertion methods will affect the performance of the memory.

[0052] The memory slot may include a CPU ID, a memory channel ID, and a slot ID. A CPU may have multiple memory channels, and a memory channel may have two slots, for example, slot 0 and slot 1. That is, the memory slot refers to which slot under which memory channel under which CPU, to indicate which slot the error occurs in.

[0053] The error reporting time is the time when the error is detected. The error reporting memory temperature is the memory temperature when the error is detected. The task category is the category of tasks divided according to the read and write frequency. Different task categories correspond to different read and write frequencies, and the read and write frequencies have an impact on the performance of the memory. Therefore, the task category can be used to analyze whether the memory will fail. The memory frequency refers to the number of times the memory transmits data per unit time. The voltage refers to the voltage that powers the memory when the memory is working. During the operation of the memory, the voltage will fluctuate. The voltage fluctuation will affect the signal quality. If the signal quality is too poor, it may be considered that a failure has occurred. Therefore, the voltage can also be used as a feature information to predict whether a failure has occurred.

[0054] It should be understood that the process from the beginning of memory use to the occurrence of failure is a continuous process, so each item of the information of the memory bar in operation provided by the BMC includes multiple values. Finally, the information of each training memory bar in the working process can be obtained. For example, a piece of information corresponding to a training memory bar at a certain time in the working process can be recorded as BMC1 (B1, B2, B3...), where B1 can represent voltage, including motherboard voltage b1, memory bar voltage b2, etc., B2 can represent temperature, B3 can represent CPU occupancy, etc.

[0055] As described above, by collecting the BMC reporting information corresponding to multiple training memory bars and the ECS information of each memory particle in the memory bars, a sample data set can be obtained. One sample data may include the BMC reporting information corresponding to one memory bar and the ECS information corresponding to each memory particle, for example (A0, A1..., BMC0, BMC1...). The collected sample data set is input into the computing device, so that the computing device obtains the sample data set; or, the collected sample data set is stored in a specified location, and the computing device can obtain the sample data set from the specified location.

[0056] It should be noted that when collecting sample data sets, it is necessary to consider the number and distribution of samples, such as the number of samples of each fault category in the sample data set and its characteristic distribution. Since PNN is an instantiation model based on training samples, the richness and distribution of the sample data set directly affect the performance of the model. When collecting sample data sets, improving the richness of the sample data set and optimizing the data distribution will help the model converge faster and more stably.

[0057] S302: The computing device preprocesses the sample data set.

[0058] In the embodiment of the present application, the preprocessing process may include: data feature selection, data correlation statistical analysis, correlation threshold judgment, and error information spatiotemporal correlation analysis.

[0059] Among them, data feature selection is to select features that are useful for the current model learning task from the ECS information and BMC reported information. Since a variety of information in the working process is obtained, for a certain error in the ECS information, the occurrence of the error may be unrelated to some information in the working process. For example, the occurrence of a certain error is unrelated to the temperature, then the temperature is a useless feature for the error, and other BMC reported information is a useful feature for the error. In this way, useful features can be selected for each memory error. After selecting useful features, the features are cleaned, abnormal samples are removed, and additional sampling is performed for certain feature information to balance the sample weights. Furthermore, the feature information can be normalized, discretized, etc., and the format can be converted to unify the ECS information and BMC reported information into a form that can be recognized by the computer.

[0060] In addition, when selecting data features, the embodiments of the present application also consider whether the features diverge, that is, if the variance of a feature is close to 0, the feature divergence is small, and the feature basically does not change when an error occurs and when no error occurs, and has little distinguishing effect on subsequent probability predictions. Therefore, features with small divergence can be screened out to avoid subsequent redundant analysis.

[0061] After data feature selection, data association statistical analysis is performed on the sample data set to determine the association relationship between different features of the sample data set.

[0062] In an embodiment of the present application, some judgment algorithms can be used to make a preliminary judgment on the correlation between the features of a certain sample, and find out the hidden correlation between the various features. For example, after a certain type of ECC is queried that is higher than a threshold, frequent item sets are queried and mined in the feature data set collected by the BMC, such as querying and mining whether a certain type of feature appears frequently in the memory slot category and the task category. In other words, when a certain type of error is found to occur frequently in the ECS information, the BMC information is queried to find out which information appears frequently. If the frequency of occurrence of a certain type of information in the BMC reported information is higher than a predefined threshold, consider whether there is a correlation between the type of error and the type of information, and whether the latter causes the occurrence of the former. Among them, an item set is a collection of items, an item is a certain type of information or a certain type of error, and a frequent item set is a collection of a certain type of information and a certain type of error that often appear together.

[0063] For example, through ECS information, it can be determined that a type of error frequently occurs in the first row of memory, so the error record of the first row can be found, recorded as ECC error data set 1. Then, near the time point when ECC error data set 1 occurs, it is found that the temperature in the BMC reporting information frequently shows high temperature behavior. For example, the temperature is often around 80 degrees. Then, in the large temperature data set, a temperature data set 2 can be obtained, and temperature data set 2 includes multiple temperature values ​​around 80 degrees. ECC error data set 1 and temperature data set 2 are sets that often appear together, and it is believed that there may be a correlation between the two. After that, association rule mining can be used to determine whether ECC error data set 1 causes temperature data set 2 to appear, or temperature data set 2 causes ECC error data set 1 to appear.

[0064] After finding the correlation, association rules are mined for features that may be correlated, so as to determine the conditional relationship (also called association relationship) between various types of feature information, that is, to determine the conditional relationship between ECS information and various BMC reported information features. For example, A will cause error B to occur, so there is a conditional relationship between A and B. C will also cause error B to occur, so there is a conditional relationship between C and B. D and E will also cause error B to occur, so there is also a conditional relationship between D, E and B. After determining these conditional relationships, it can be determined based on these conditional relationships: when feature information A, C, D, E that has a conditional relationship with B appears, error B (ECC record or other memory failure) will also appear. The result of association rule mining is the value of the degree of association between different features, and the association relationship between features is represented by the value of the degree of association.

[0065] Among them, the frequent item set and association rule mining algorithm can adopt the FP-Growth algorithm and the Apriori algorithm, which is not limited in this application.

[0066] Furthermore, after the association relationship is determined, a correlation threshold corresponding to the association relationship may be determined; when the correlation threshold is greater than a preset correlation threshold, the association relationship is determined to be credible.

[0067] In an embodiment of the present application, after the association relationship is determined, a correlation threshold judgment may be performed. The correlation threshold judgment may be used to determine whether the association relationship obtained by the previous preprocessing step is credible. If the value of the correlation corresponding to the discovered association relationship exceeds the preset correlation threshold, it indicates that the association relationship is credible. In some implementations, the correlation threshold may be a fixed value, and different association relationships use the same correlation threshold. In other implementations, the correlation threshold may be a non-fixed value, and different association relationships use different correlation thresholds. For example, a correlation threshold 1 may be set between ECC error data set 1 and temperature data set 2. A correlation threshold 2 may be set between ECC error data set 3 and voltage data set 4.

[0068] During the model training process, the weight bias can be adjusted according to the correlation between different features in the sample data set. For example, if it is found that feature information A has a high threshold correlation with fault B, the weight corresponding to feature information A can be increased during the model training process. Among them, the correlation can be expressed by the Pearson Correlation Coefficient (PCCs). PCCs is used to measure the strength and direction of the linear correlation between two continuous variables. It is usually used in PNN to analyze the correlation between different features or between different categories. When training the model, the training set and PCCs are input into the model to be trained. PCCs can accurately describe the contribution of various types of error information to fault classification judgment. This helps PNN understand the relationship between features and optimize the network parameter settings.

[0069] In addition to the above correlation analysis to find the association relationship, the sample data can also be subjected to spatial and temporal correlation analysis to obtain the estimated fault category and the corresponding relationship between the estimated fault category and the BMC information.

[0070] The spatiotemporal correlation analysis can initially separate obvious error patterns, such as row, column, or row-column compound error patterns, to accelerate the subsequent training process. In the preprocessing process, if a considerable number of errors show obvious spatial correlation, it is possible to preliminarily determine which fault type causes the frequent memory errors in space, thereby obtaining the estimated fault category. For example, when the error records are mainly concentrated in a certain row, it means that the memory may have a row fault, and the probability of the memory bar having a row fault in the future increases. Then, in the model training stage, the possible device-level fault types in the row fault can be further refined. Specifically, in the spatiotemporal correlation analysis results, the estimated fault category can be represented by an identifier, which can be a field, a characteristic value, a value, or a value range, etc. For example, the analysis result can be represented by R=0, indicating that the memory bar may have a row fault; for example, the analysis result can be represented by R=1, indicating that the memory bar may have a column fault.

[0071] Moreover, when a row fails, its adjacent positions are also likely to fail. When training the model, a larger weight can be set for these high-risk positions so that the model focuses on the risk of row failures in these positions. If a considerable number of errors show obvious time correlation, for example, the number of row errors increases abnormally in a certain time period, the cause of the error can be found from the characteristic information such as task category, voltage, temperature, etc. stored in this time period, thereby obtaining the correspondence between the estimated fault category and BMC information. For example, in the results of spatiotemporal correlation analysis, there is a correspondence between row failure and temperature, and the two can obtain a coupling relationship, which can be expressed as R*T=0.2, for example.

[0072] Through the spatiotemporal correlation analysis, we can obtain the features that characterize the spatiotemporal correlation, provide a training basis for the confidence of fault classification, improve the model's understanding of fault modes, help the PNN training convergence, and accelerate the subsequent training process.

[0073] In short, through preprocessing, different information can be coupled to obtain feature data with high correlation, less redundant information, and directly corresponding to the memory failure mode.

[0074] S303, training a probabilistic neural network PNN based on the preprocessed sample data set.

[0075] After data preprocessing, the sample data set is divided into a training set, a validation set, and a test set, where each sample data is marked with a label. The sample label corresponding to the faulty memory cell in the memory bar is the device-level fault category that actually occurred in the memory cell, and the sample label corresponding to the normal memory cell is that no device-level fault occurred. And for the UCE prediction mode, the sample label is that UCE occurred or did not occur.

[0076] When training the model, you can use stochastic gradient descent, mini-batch gradient descent and other methods for training. For example, the process of a sample training is: input a sample in the training set, the spatiotemporal correlation analysis results and the correlation coefficient (such as PCCs) into the model to be trained. After one iteration of the model to be trained, the probability of multiple fault categories of the sample is predicted, and the PCCs after this iteration are output. Then, according to the gap between the predicted results and the label data, the model parameters are updated, and the PCCs and training sample data obtained from this iteration training are continuously input into the model, and iterated until the model converges. Repeat the sample training process with the next sample data until the stopping condition is reached to obtain a probabilistic neural network.

[0077] After the training is completed, the validation set and the test set are used to evaluate the classification performance of the PNN model. According to the evaluation results, the parameters of the model are adjusted to optimize the model performance. Among them, the parameters that can be optimized include but are not limited to smoothing parameters, class prior probabilities, activation functions, etc.

[0078] Among them, the smoothing parameter affects the smoothness of the classification boundary and the generalization ability of the model. A smaller smoothing parameter value may lead to overfitting, while a larger value may lead to underfitting. Inappropriate smoothing parameter values ​​may cause the training process to fail to achieve the desired classification effect. The class prior probability defines the probability of each category appearing in the entire data set. This parameter affects the formation of the decision boundary, especially in the case of unbalanced class classification. Accurately estimating the class prior probability helps the network better converge to a reasonable classification decision. PNN usually uses a Gaussian activation function, which determines how each node responds to the input. A suitable activation function helps improve the stability and classification performance of the model.

[0079] Through the above model training process, the adaptive neural network parameters can be trained to obtain a PNN model with better performance. Then, the PNN model can be used to predict the probability distribution of different types of faults, which plays a role in assisting fault prediction and judgment. Therefore, a solution to reduce system risk can be selected based on the prediction results. In addition, the PNN model can be used to obtain the confidence of UCE faults in the memory, so as to avoid the risk of UCE faults in time.

[0080] The fault prediction method provided in the embodiment of the present application is described in detail below. Figure 4 A schematic flow chart of a fault prediction method is shown.

[0081] S401: The CPU obtains working status information of the CXL memory to be tested, where the working status information includes error information inside the memory particles and information reported by the BMC.

[0082] During actual prediction, the working status information of the CXL memory to be tested is obtained. The working status information is a set of operating parameters used to indicate the operating status of the memory. The working status information may include error information inside the memory particles, namely, ECS information. After the CXL memory generates ECS information, the corresponding registers can be accessed through the CXL control chip to obtain the ECS information from the corresponding registers. The ECS information can be used to count the number of ECCs completed in the memory particles and track the location where the ECC occurs, that is, to determine the error distribution and number, for example, to know where the error correction mainly occurs.

[0083] The working status information also includes the information reported by the BMC. The BMC records the information of the memory under test during the working process in the background. When making predictions, the CPU requests to obtain the information recorded by the BMC, and the BMC reports the information during the working process. The CPU can use the information reported by the BMC to parse the information of the memory under test during the working process, including the fault type, fault address, CPU occupancy, memory capacity occupancy, memory insertion method, memory slot, error reporting time, error memory temperature, task category, memory frequency, voltage and other information.

[0084] Thus, the working status information of the memory to be tested can be obtained, that is, the characteristics of the input probabilistic neural network.

[0085] S402, inputting the working status information of the memory to be tested into the PNN to obtain the probability of occurrence of multiple fault types.

[0086] PNN is a feedforward neural network. Figure 4 The structure of the PNN shown in FIG. 1 may include an input layer, a pattern layer, a summation layer, and an output layer. Specifically, the working state information is input into the input layer and converted into the neural network feature {x 1 ,x 2 ,…,x n The input layer is connected to the pattern layer, and explicit feature crossover is performed before entering the pattern layer to capture the correlation between features. The pattern layer performs a weighted summation operation and sends it to the next layer after the activation function operation. After that, each network unit in the summation layer is connected to the pattern layer unit of the corresponding category. The summation layer estimates the probability of occurrence of different fault types and sends it to the output layer, thereby outputting the probability of occurrence of multiple fault types {y 1 ,y 2 ,…,y m}.

[0087] In the embodiment of the present application, the PNN model is pre-trained, and the PNN model learns the relationship between the feature vectors under fault conditions and the relationship between the feature vectors under normal conditions, and learns the feature vector relationship corresponding to different fault modes, that is, what kind of feature vector or feature vector combination may cause what kind of fault to occur. In actual prediction, after the working status information of the memory to be tested is input into the PNN, the PNN can output the probability of different faults occurring in the memory to be tested in the future, and the output probability relationship should satisfy 100% = normal probability X% + fault A probability a% + fault B probability b% + fault C probability c% .... Among them, the fault type is the aforementioned 32 device-level fault types. For example, the probability of capacitor leakage is 10%, the probability of row decoding error is 1%, etc. The sum of the probability of all fault categories occurring and the probability of no failure is 1.

[0088] It should be noted that the above-mentioned memory to be tested may include one or more memory particles. When the memory to be tested includes multiple memory particles, the ECS information of a specific memory particle is obtained, and the PNN can output the probability of different device-level failures occurring in the specific memory particle in the future.

[0089] After obtaining the probability distribution of multiple fault categories, the CXL extended memory can be predicted for faults based on the probability distribution of multiple fault categories. For example, the technician can combine the probability distribution with some experience or other methods to analyze whether the memory will have the aforementioned device-level faults in the future.

[0090] It should be understood that the error event inside the memory particle is a manifestation of the failure of the physical structure of the memory. In the embodiment of the present application, the error mode affected by the fault is analyzed through ECS information and BMC information, and it is mapped to the fundamental device-level fault that causes the error. By identifying all error modes and classifying the faults based on the faults that are most likely to cause a certain error mode, the above-mentioned more than 30 types of device-level faults are divided.

[0091] For example, when the working temperature of the memory is high, the task category involves multiple refresh operations, and the time interval between two refresh operations is long, capacitor leakage faults are prone to occur, and leakage faults between capacitors are also prone to occur; then, if the error of the memory to be tested is caused by the high working temperature of the memory and the task category involves multiple refresh operations, the memory to be tested is likely to have capacitor leakage faults and / or leakage faults between capacitors. For another example, when the working task of the memory involves activating the storage unit for a long time, but no write operation is performed or only a very small number of read operations are performed, and the time interval between two refresh operations is long, channel leakage faults are prone to occur. For another example, when the working state of the memory involves the memory working capacitor being full, but the storage unit is not activated, and the time interval between two refresh operations is long, GIDL faults are prone to occur. For another example, during work, it is recorded that the working voltage of the memory bar is relatively large, exceeding the normal threshold range, the activation selection time of the memory bar becomes longer, and no read or write operations are performed at this time, and leakage faults from word line to bit line are prone to occur.

[0092] When actually predicting, the probability of different device-level failures can be predicted through the error patterns of the memory to be tested. In this way, equipment users and maintenance personnel can discover possible device-level failures in advance, so that they can perform maintenance in time and improve the overall reliability of the system. In addition, it can also help memory manufacturers optimize processes and design more stable memory.

[0093] In addition, in the embodiment of the present application, more comprehensive and diverse information is obtained by obtaining the error information inside the memory particles and the information reported by the BMC during the working process. By using more comprehensive and diverse information, the fault characteristics of the probabilistic neural network can be enriched, and thus more accurate predictions can be made. In this way, it is beneficial for equipment users and operation and maintenance personnel to make accurate memory fault predictions and fault type judgments based on memory working status information.

[0094] In addition, for some network models that output relatively absolute results of yes or no, completely relying on the output results of the neural network model when predicting faults is not suitable for scenarios that require high accuracy, because once the results of machine learning are wrong, it will not be possible to predict in time that the memory will fail, resulting in failure to handle in time, which will bring very serious consequences. In the embodiment of the present application, compared with other neural network models, PNN plays an auxiliary prediction role. PNN is used to predict faults, give probability distribution, and then combine probability distribution and experience to analyze whether a fault occurs. In this way, it does not completely rely on the results of machine learning, and can more effectively predict possible memory failures.

[0095] In some other embodiments, the PNN has two modes of output, one is to output the probability distribution of the above-mentioned multiple device-level fault categories, and the other is to output the confidence of the occurrence of UCE fault in the memory.

[0096] Since CE will be converted into UCE if it occurs too many times, external factors such as time, task pressure, temperature, etc. are related to the occurrence of UCE. Therefore, in the embodiment of the present application, it is possible to predict whether a UCE failure may occur based on the working status information of the memory to be tested. That is to say, after the working status information of the memory to be tested is input into the PNN, the PNN can also output the confidence level of the UCE failure of the CXL memory to be tested. When the confidence level is greater than the confidence threshold, it can be determined that the CXL memory to be tested will have a UCE failure.

[0097] The confidence here represents the probability that the PNN prediction result falls within the calibration interval, and the calibration interval includes the occurrence or non-occurrence of UCE failure in the memory (two calibration intervals). The working status information is input into the PNN network. After the PNN network performs reasoning and judgment, the confidence of the occurrence or non-occurrence of UCE failure will be given. Then, it can be determined whether the memory to be tested may have UCE failure in the future based on the confidence. In the embodiment of the present application, a confidence threshold can be set. When the confidence of the occurrence of UCE failure output by PNN is greater than the confidence threshold, it is considered that the memory to be tested may have UCE in the future. For example, the confidence threshold can be 80%. When the confidence of the judgment result falling within the interval of occurrence of UCE failure is 90%, it indicates that the memory to be tested will have UCE failure in the future.

[0098] For many companies, they do not have the ability to further analyze faults, and only focus on whether the memory will have a UCE fault. However, the occurrence of a UCE fault is difficult to predict and judge, and after a UCE fault occurs in the memory, the system is at risk of downtime, affecting the operation of the system. In the embodiment of the present application, by outputting the probability of a UCE fault occurring in the memory to be tested in the future through PNN, preventive measures can be taken in a timely manner when it is predicted that the memory to be tested may have a UCE fault, such as isolation or replacement of the memory stick.

[0099] In the embodiment of the present application, after obtaining the working status information, the working status information may be preprocessed first, and the preprocessed data may be input into the PNN to obtain the probability of occurrence of multiple fault types.

[0100] The preprocessing process may include: data feature selection, data correlation statistical analysis, correlation threshold judgment, error information spatiotemporal correlation analysis, etc. Preprocessing can reduce the task pressure of the network model and speed up the reasoning process.

[0101] In some implementations, after obtaining the working status information, the working status information is screened and correlation analyzed; the correlation between different features in the working status information is determined; the working status information and the correlation are input into a probabilistic neural network; and the probability distribution of multiple fault categories is obtained.

[0102] Among them, information screening, that is, data feature selection, is to select features useful for the current model learning task from the ECS information and BMC reported information. Since a variety of information in the working process is obtained, for a certain error in the ECS information, the occurrence of the error may be unrelated to some information in the working process. For example, if the occurrence of a certain error is unrelated to temperature, then temperature is a useless feature for the error, and other BMC reported information is a useful feature for the error. In this way, useful features can be selected for each memory error.

[0103] After selecting useful features, the useful features can be cleaned and abnormal features can be removed. Furthermore, the feature information can be normalized, discretized, etc., and formatted, so that the ECS information and BMC reporting information are unified into a form that can be recognized by the computer.

[0104] In addition, when screening information, the embodiments of the present application also consider whether the features diverge, that is, if the variance of a feature is close to 0, the feature divergence is small, and it can be considered that there is basically no difference when errors occur on this feature, and the distinguishing effect on subsequent probability predictions is very small. Therefore, features with small divergence can be screened out to avoid subsequent redundant analysis.

[0105] After data feature selection, correlation analysis can be performed, such as statistical analysis of data association. In an embodiment of the present application, some judgment algorithms can be used to find the hidden correlations between the various features, and a preliminary judgment can be made on the correlations between the features. For example, after a certain type of ECC is queried that is higher than a threshold, frequent item sets are queried and mined in the feature data set collected by the BMC, such as querying and mining whether a certain type of feature appears frequently in the memory slot category and task category. In other words, when a certain type of error is found to occur frequently in the ECS information, the BMC information is queried to find out which information appears frequently. If the frequency of occurrence of a certain type of information in the BMC reported information is higher than a predefined threshold, consider whether there is a correlation between this type of error and this type of information, and whether the latter causes the occurrence of the former.

[0106] For example, through ECS information, it can be determined that a type of error frequently occurs in the first row of memory, so the error record of the first row can be found, recorded as ECC error data set 1. Then, near the time point when ECC error data set 1 occurs, it is found that the temperature in the BMC reporting information frequently shows high temperature behavior. For example, the temperature is often around 80 degrees. Then, in the large temperature data set, a temperature data set 2 can be obtained, and temperature data set 2 includes multiple temperature values ​​around 80 degrees. ECC error data set 1 and temperature data set 2 are sets that often appear together, and it is believed that there may be a correlation between the two. After that, association rule mining can be used to determine whether ECC error data set 1 causes temperature data set 2 to appear, or temperature data set 2 causes ECC error data set 1 to appear.

[0107] After finding the correlation, association rule mining is performed on the features that may be correlated, so as to determine the conditional relationship (also called association relationship) between various types of feature information, that is, to determine the conditional relationship between ECS information and various BMC reported information features. For example, A will cause error B to occur, so there is a conditional relationship between A and B, C will also cause error B to occur, so there is a conditional relationship between C and B, D and E will also cause error B to occur, so there is also a conditional relationship between D, E and B. After determining these conditional relationships, it can be determined based on these conditional relationships: when feature information A, C, D, E that has a conditional relationship with B appears, error B (ECC record or other memory failure) will also occur. The result of association rule mining is to obtain the value of the degree of correlation between multiple features. The value of the degree of correlation will be input into the probabilistic neural network PNN as a feature parameter, which is used by the probabilistic neural network PNN to calculate the probability of device-level failures, provide contributions to the prediction of memory failures, and improve the accuracy of memory failure prediction from a feature perspective.

[0108] Furthermore, after determining the association relationship, the association degree threshold corresponding to the association relationship can be determined; when the association degree threshold is greater than the preset association degree threshold, the association relationship is determined to be credible; then, the working status information and the credible association relationship in the association relationship are input into the probabilistic neural network to obtain the probability distribution of multiple fault categories.

[0109] In an embodiment of the present application, after determining the association relationship, a correlation threshold judgment may also be performed. The correlation threshold judgment may be used to determine whether the association relationship of the previous step is credible. If the value of the correlation corresponding to the discovered association relationship exceeds the preset correlation threshold, it indicates that the association relationship is credible. In some implementations, the correlation threshold may be a fixed value, and different association relationships use the same correlation threshold. In other implementations, the correlation threshold may be a non-fixed value, and different association relationships use different correlation thresholds. For example, a correlation threshold 1 may be set between ECC error data set 1 and temperature data set 2. A correlation threshold 2 may be set between ECC error data set 3 and voltage data set 4.

[0110] Among them, the correlation can be expressed by the Pearson Correlation Coefficient (PCCs) between different data. PCCs is used to measure the strength and direction of the linear correlation between two continuous variables. It is usually used in PNN to analyze the correlation between different features or between different categories, which helps to understand the relationship between features.

[0111] In some implementations, in addition to the above correlation analysis to find the association relationship, spatial and temporal correlation analysis may be performed on different information in the working status information to obtain an estimated fault category and the corresponding relationship between the estimated fault category and the BMC information.

[0112] Spatiotemporal correlation analysis can be used for deeper mining. This process can initially separate obvious error patterns, such as row, column, or row-column compound error patterns, to accelerate the subsequent prediction process. In this preprocessing process, if a considerable number of errors show obvious spatial correlation, it is possible to preliminarily determine which type of fault causes the frequent errors in space. For example, error records that show obvious row correlation represent that the memory may have row failures, and the probability of row failures in the memory bar in the future increases. Then, PNN can further refine the possible device-level fault types in row failures during prediction. Moreover, when a row fails, there is a high probability that its adjacent positions will also fail. If there is an obvious temporal correlation, the cause of the error can also be found from the characteristic information such as the task category, voltage, and temperature performed during this period.

[0113] Through the time-space correlation analysis, the characteristics that characterize the time-space correlation can be obtained. This characteristic is input into the probabilistic neural network PNN as a parameter, and the probabilistic neural network PNN is used to calculate the probability of device-level failures, which contributes to the prediction of memory failures. It improves the accuracy of memory failure prediction from a characteristic perspective, and then predicts a more accurate fault type, which is also helpful to determine whether the fault will further deteriorate into a UCE failure.

[0114] In short, through preprocessing, different information can be coupled to obtain feature representation data with high correlation, less redundant information, and directly corresponding to the memory failure mode, thereby improving the credibility of the PNN output results.

[0115] In the above, by obtaining ECS ​​information and BMC reporting information, and preprocessing the data, the preprocessed data is input into PNN, and the memory fault classification is accurately classified to the device level. The probability of possible device-level faults is predicted by PNN, providing operation and maintenance personnel with more accurate fault classification.

[0116] In other implementations, after the PNN outputs the probability distribution of different fault categories, the operation and maintenance personnel can also design a fault stimulation test. Specifically, the corresponding fault stimulation scheme can be designed according to the output fault type result. If the stimulation is successful, it verifies that the reliability of the probabilistic neural network judgment result is high.

[0117] The above is a fault prediction method provided in an embodiment of the present application. The method can predict the probability of a device-level fault in a CXL memory and solve the problem that it is difficult to predict and judge the occurrence of a UCE fault, resulting in a high risk of system downtime.

[0118] Next, combine Figure 5 The fault prediction device 500 provided in the embodiment of the present application is described. Figure 5 As shown, the device 500 includes an acquisition module 510 and a processing module 520 .

[0119] The acquisition module 510 is used to support the fault prediction device 500 to perform the above acquisition steps. The processing module 520 is used to support the fault prediction device 500 to perform the above processing steps.

[0120] In a possible implementation, the device 500 may further include a storage module. The storage module is connected to the acquisition module 510 and the processing module 520 via a line. The storage module may include one or more memories, and the memory may be a device used to store programs or data in one or more devices or circuits. The storage module may exist independently and be connected to the acquisition module 510 and the processing module 520 via a communication bus. The storage module may also be integrated with the acquisition module 510 and the processing module 520.

[0121] The storage module can store computer-executable instructions of the method in the apparatus 500 so that the apparatus 500 executes the method in the above embodiment. The storage module can be a register, a cache memory, or a random access memory (RAM), etc. The storage module can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions.

[0122] Figure 6 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 6 As shown, the chip 600 includes one or more (including two) processors 601 , a communication line 602 and a communication interface 603 . Optionally, the chip 600 also includes a memory 604 .

[0123] In some implementations, the memory 604 stores the following elements: executable modules or data structures, or a subset thereof, or an extended set thereof.

[0124] The method described in the above embodiment of the present application can be applied to the processor 601, or implemented by the processor 601. The processor 601 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware or software instructions in the processor 601. The above processor 601 can be a general-purpose processor (for example, a microprocessor or a conventional processor), a digital signal processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates, transistor logic devices or discrete hardware components. The processor 601 can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.

[0125] The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. Among them, the software module can be located in a mature storage medium in the field such as a random access memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable read only memory (EEPROM). The storage medium is located in the memory 604, and the processor 601 reads the information in the memory 604 and completes the steps of the above method in combination with its hardware.

[0126] The processor 601 , the memory 604 , and the communication interface 603 may communicate with each other via the communication line 602 .

[0127] In the above embodiments, the instructions stored in the memory for execution by the processor may be implemented in the form of a computer program product, wherein the computer program product may be pre-written in the memory, or may be downloaded and installed in the memory in the form of software.

[0128] The present application embodiment also provides a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server, a data center, etc. that includes one or more available media integrated. For example, the available medium can include a magnetic medium (e.g., a floppy disk, a hard disk or a tape), an optical medium (e.g., a digital versatile disc (digital versatile disc, DVD)), or a semiconductor medium (e.g., a solid state drive (solid state disk, SSD)), etc.

[0129] An embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory is used to store a computer program, and the processor is used to execute the computer program to perform the above method.

[0130] The embodiment of the present application provides a chip. The chip includes a processor, and the processor is used to call a computer program in a memory to execute the technical solution in the above embodiment. Its implementation principle and technical effect are similar to those of the above related embodiments, and will not be repeated here.

[0131] In the embodiments provided in the present application, it should be understood that the disclosed device / electronic device and method can be implemented in other ways. For example, the device / electronic device embodiments described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. In addition, each functional unit in each embodiment of the present application can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0132] The embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned various method embodiments can be implemented. The computer-readable storage medium stores a computer program or instruction. The above-mentioned method is implemented when the computer program or instruction is executed by the processor. The method described in the above embodiment can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media may include computer storage media and communication media, and may also include any medium that can transfer a computer program from one place to another. The storage medium may be any target medium accessible by a computer.

[0133] As a possible design, the computer-readable medium may include a compact disc read-only memory (CD-ROM), RAM, ROM, EEPROM or other optical disc storage; the computer-readable medium may include a magnetic disk storage or other magnetic disk storage device. Moreover, any connecting line may also be appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave), the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of the medium. Disks and optical discs as used herein include compact discs (CDs), laser discs, optical discs, DVDs, floppy disks and Blu-ray discs, where disks generally reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included in the scope of computer-readable media.

[0134] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] In the above description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0136] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0137] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A fault prediction method, characterized in that: Applied to a CPU, the method comprises: Obtaining working status information of a computing fast link CXL memory, wherein the working status information includes error information inside a memory particle and information during the memory working process reported by a baseboard management controller BMC; The working status information is input into a probabilistic neural network to obtain probability distributions of multiple fault categories.

2. The method according to claim 1, characterized in that The error information inside the memory cell includes: the number of times error correction occurs in the memory cell and / or the location of each error correction in the memory cell.

3. The method according to claim 1 or 2, characterized in that: The working state information is input into a probabilistic neural network to obtain probability distributions of multiple fault categories, including: The working state information is input into a probabilistic neural network to obtain probability distributions of multiple device-level fault categories.

4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: The working status information is input into the probabilistic neural network, and the confidence level of the UCE failure of the CXL memory is output.

5. The method according to any one of claims 1 to 4, characterized in that Before inputting the working status information into the neural network, the method further includes: Performing information screening and correlation analysis on the work status information to determine the correlation relationship between different features in the work status information; The step of inputting the working state information into a probabilistic neural network comprises: The working status information and the association relationship are input into the probabilistic neural network.

6. The method according to claim 5, characterized in that The method further comprises: Determine a correlation threshold corresponding to the correlation relationship; In the case where the association degree of the association relationship is greater than the association degree threshold, determining that the association relationship is credible; Inputting the working state information and the association relationship into the probabilistic neural network includes: The working status information and the credible association relationships among the association relationships are input into the probabilistic neural network.

7. The method according to claim 5, characterized in that Before inputting the working state information and the association relationship into the neural network, the method further includes: Performing spatial and temporal correlation analysis on the working status information to obtain an estimated fault category and a corresponding relationship between the estimated fault category and information in the memory working process reported by the BMC; Inputting the working state information and the association relationship into a probabilistic neural network includes: The working status information, the association relationship, the estimated fault category and the corresponding relationship are input into a probabilistic neural network.

8. A computing device, characterized in that The computing device comprises a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, and the computer instructions are loaded and executed by the processor to enable the computing device to implement the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method according to any one of claims 1 to 7.

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