Gate drive circuit, display panel and display device

Abstract

The invention provides a gate drive circuit, a display panel and a display device, and relates to the technical field of display. The gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit and a turn-off unit. The first reset unit is used for writing turn-off voltage into the first node; the first reset unit comprises a first reset transistor, and a grid electrode of the first reset transistor is connected to a first clock signal end or a third clock signal end; the first pole of the first reset transistor is connected to the first node; the control end of the turn-off unit is connected to the first node, the first end of the turn-off unit is connected to the second electrode of the first reset transistor, and the turn-off unit is used for writing the turn-on voltage into the second electrode of the first reset transistor when the first node controls the turn-off unit to be turned on. According to the embodiment of the invention, the electric leakage of the shift register is reduced, and the electric leakage of the gate drive circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving circuit, a display panel and a display device. Background Art

[0002] The display panel usually includes a display area and a non-display area. The display area is provided with a plurality of pixel driving circuits and light-emitting elements. The pixel driving circuit is used to drive the light-emitting elements to emit light to display images. The non-display area is provided with a gate driving circuit for providing a control signal to the pixel driving circuit so that the light-emitting elements are lit up row by row under the drive of the pixel driving circuit.

[0003] In the related art, the gate driving circuit has a leakage problem. Summary of the invention

[0004] The present invention provides a gate driving circuit, a display panel and a display device, so as to reduce the leakage of a shift register and reduce the leakage of a gate driving circuit.

[0005] In a first aspect, an embodiment of the present invention provides a gate driving circuit, comprising a plurality of cascaded shift registers, wherein the shift register comprises a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit and a shutdown unit;

[0006] The output end of the first input unit and the control end of the first output unit are connected to a first node, and the output end of the second input unit and the control end of the second output unit are connected to a third node;

[0007] The first reset unit is used to write a shutdown voltage to the first node, and the shutdown voltage is a voltage for controlling the first output unit to be turned off; the first reset unit includes a first reset transistor, and the gate of the first reset transistor is connected to the first clock signal terminal or the third clock signal terminal; the first electrode of the first reset transistor is connected to the first node;

[0008] The control end of the shutdown unit is connected to the first node, and the first end of the shutdown unit is connected to the second electrode of the first reset transistor, and is used to write a turn-on voltage into the second electrode of the first reset transistor when the first node controls the shutdown unit to be turned on. The turn-on voltage is the voltage that controls the first output unit to be turned on.

[0009] In a second aspect, an embodiment of the present invention provides a display panel, comprising the gate driving circuit described in the first aspect.

[0010] In a third aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the second aspect.

[0011] In the gate drive circuit provided by the embodiment of the present invention, a shutoff unit is provided, and the control end of the shutoff unit is connected to the first node. When the voltage of the first node is the on-voltage, the shutoff unit is turned on, and the on-voltage is written to the second electrode of the first reset transistor. The first electrode of the first reset transistor and the second electrode of the first reset transistor are both on-voltages. The gate of the first reset transistor is the shutoff voltage, and the on-voltage applied to the second electrode of the first reset transistor turns off the first reset transistor more thoroughly, reduces the leakage through the first reset transistor, and reduces the leakage of the first node and the circuit branch where the first reset unit is located. Among them, leakage refers to the leakage current in the off state, or the voltage change caused by leakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A circuit diagram of a gate drive circuit provided by an embodiment of the present invention;

[0013] Figure 2 A circuit diagram of a shift register provided by an embodiment of the present invention;

[0014] Figure 3 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0015] Figure 4 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0016] Figure 5 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0017] Figure 6 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0018] Figure 7 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0019] Figure 8 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0020] Fig. 9 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0021] Fig.10 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0022] Fig.11 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0023] Fig.12A driving timing diagram of a shift register provided by an embodiment of the present invention;

[0024] Fig.13 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0025] Fig.14 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0026] Fig.15 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0027] Fig.16 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0028] Fig.17 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0029] Fig.18 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0030] Fig.19 A driving timing diagram of another shift register provided by an embodiment of the present invention;

[0031] Fig. 20 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0032] Fig.21 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0033] Fig. 22 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0034] Fig.23 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0035] Fig.24 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0036] Fig.25 A driving timing diagram of another shift register provided by an embodiment of the present invention;

[0037] Fig.26 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0038] Fig. 27 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0039] Fig.28 A circuit diagram of another shift register provided by an embodiment of the present invention;

[0040] Fig.29 A circuit diagram of another gate driving circuit provided by an embodiment of the present invention;

[0041] Fig.30 A circuit diagram of another gate driving circuit provided by an embodiment of the present invention;

[0042] Fig.31 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0043] Fig.32 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0045] Figure 1 A circuit diagram of a gate drive circuit provided by an embodiment of the present invention, Figure 2 A circuit diagram of a shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 2 , the gate driving circuit includes a plurality of cascaded shift registers 100. The shift register 100 includes a first input unit 110, a second input unit 120, a first output unit 130, a second output unit 140, a first reset unit 150 and a shut-off unit 160. The output end of the first input unit 110 and the control end of the first output unit 130 are connected to a first node Q1. The output end of the first input unit 110 is coupled to the first node Q1, and the control end of the first output unit 130 is coupled to the first node Q1. The output end of the second input unit 120 and the control end of the second output unit 140 are connected to a third node QB.

[0046] The first reset unit 150 is used to write a turn-off voltage to the first node Q1, and the turn-off voltage is a voltage for controlling the first output unit 130 to be turned off. The turn-off voltage can also be a voltage for controlling the second output unit 140 to be turned off. The first reset unit 150 includes a first reset transistor T7, and the gate of the first reset transistor T7 is connected to the first clock signal terminal CK1 or the third clock signal terminal CK3. The first reset transistor T7 is turned on or off under the control of the first clock signal terminal CK1. Alternatively, the first reset transistor T7 is turned on or off under the control of the third clock signal terminal CK3. Among them, the first clock signal terminal CK1 and the third clock signal terminal CK3 provide clock signals. The first electrode of the first reset transistor T7 is connected to the first node Q1.

[0047] The control end of the shutoff unit 160 is connected to the first node Q1, and the first end of the shutoff unit 160 is connected to the second electrode of the first reset transistor T7. The shutoff unit 160 is used to write a turn-on voltage into the second electrode of the first reset transistor T7 when the shutoff unit 160 is turned on at the first node Q1, and the turn-on voltage is a voltage for controlling the first output unit 130 to be turned on. The turn-on voltage can also be a voltage for controlling the second output unit 140 to be turned on.

[0048] In the gate drive circuit provided by the embodiment of the present invention, a shutoff unit 160 is provided, and the control end of the shutoff unit 160 is connected to the first node Q1. When the voltage of the first node Q1 is the on-voltage, the shutoff unit 160 is turned on, and the on-voltage is written to the second electrode of the first reset transistor T7. The first electrode of the first reset transistor T7 and the second electrode of the first reset transistor T7 are both on-voltages. The gate of the first reset transistor T7 is the off-voltage, and the on-voltage applied to the second electrode of the first reset transistor T7 turns off the first reset transistor T7 more thoroughly, reduces the leakage through the first reset transistor T7, and reduces the leakage of the circuit branch where the first node Q1 and the first reset unit 150 are located. Among them, leakage refers to the leakage current in the off state, or the voltage change caused by leakage.

[0049] Exemplarily, the gate driving circuit includes a plurality of thin film transistors, at least one of which is an oxide transistor. The semiconductor layer of the oxide transistor includes a metal oxide, wherein the metal oxide may include, for example, indium gallium zinc oxide (IGZO).

[0050] Exemplarily, the thin film transistor includes an N-type transistor. The gate of the N-type transistor is turned on under the control of a positive voltage (including a high voltage), and the gate of the N-type transistor is turned off under the control of a negative voltage. For the N-type transistor, the turn-off voltage is a negative voltage (including a low voltage), and the turn-on voltage is a positive voltage. In other embodiments, the thin film transistor includes a P-type transistor. The gate of the P-type transistor is turned off under the control of a positive voltage, and the gate of the P-type transistor is turned on under the control of a negative voltage. For the P-type transistor, the turn-off voltage is a positive voltage, and the turn-on voltage is a negative voltage. Among them, the positive voltage is greater than the negative voltage. For simplicity, in various embodiments of the present invention, the thin film transistor includes an N-type transistor as an example for explanation, but it is not limited to this.

[0051] Exemplarily, the first reset transistor T7 is an N-type transistor. The off voltage is a negative voltage, and the on voltage is a positive voltage. The first electrode of the first reset transistor T7 and the second electrode of the first reset transistor T7 are both positive voltages, the gate of the first reset transistor T7 is a negative voltage, and the gate-source voltage difference of the first reset transistor T7 is a very negative value. The first reset transistor T7 is turned off more thoroughly, reducing the leakage through the first reset transistor T7.

[0052] Figure 3 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 3 The shut-off unit 160 includes a shut-off transistor T9. The gate of the shut-off transistor T9 is connected to the first node Q1, and the first electrode of the shut-off transistor T9 is connected to the second electrode of the first reset transistor T7. When the shut-off transistor T9 is turned on, the turn-on voltage is written to the second electrode of the first reset transistor T7.

[0053] Optionally, refer to Figure 3 The second electrode of the turn-off transistor T9 is connected to the first power supply voltage terminal VGH, and the first power supply voltage terminal VGH provides a conduction voltage. During the period when the turn-off transistor T9 is turned on, the conduction voltage of the first power supply voltage terminal VGH can be written into the second electrode of the first reset transistor T7, which increases the time length for completely turning off the first reset transistor T7, and further improves the effect of reducing the leakage of the gate drive circuit.

[0054] For example, reference Figure 4 , when the first node Q1 is a positive voltage, the positive voltage of the first node Q1 controls the turn-off transistor T9 to turn on, and writes the positive voltage of the first power supply voltage terminal VGH into the second electrode of the first reset transistor T7. In one embodiment, the voltage of the first power supply voltage terminal VGH is a high voltage, and the high voltage is, for example, greater than or equal to 8V. In other embodiments, the voltage of the first power supply voltage terminal VGH can also be a low voltage, and the low voltage is less than or equal to -8V.

[0055] Figure 4 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 4 The second electrode of the turn-off transistor T9 is connected to the first clock signal terminal CK1. During the period when the clock signal provided by the first clock signal terminal CK1 is the conduction voltage, the conduction voltage can be written into the second electrode of the first reset transistor T7.

[0056] Figure 5 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 5 The second electrode of the turn-off transistor T9 is connected to the second clock signal terminal 220. During the period when the clock signal provided by the second clock signal terminal 220 is the conduction voltage, the conduction voltage can be written into the second electrode of the first reset transistor T7.

[0057] Figure 6 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 6 The shift register 100 further includes an isolation transistor T4. The gate of the isolation transistor T4 is connected to the first clock signal terminal CK1, the first electrode of the isolation transistor T4 is connected to the first node Q1, and the second electrode of the isolation transistor T4 and the control terminal of the first output unit 130 are connected to the second node Q2.

[0058] For example, reference Figure 6 , the isolation transistor T4 is an N-type transistor. The off voltage is a negative voltage, and the on voltage is a positive voltage. During the period when the clock signal provided by the first clock signal terminal CK1 is a positive voltage, the isolation transistor T4 is turned on, and the first node Q1 and the second node Q2 have the same voltage. During the period when the clock signal provided by the first clock signal terminal CK1 is a negative voltage, the isolation transistor T4 is turned off, and the first node Q1 and the second node Q2 have the same or different voltages.

[0059] Figure 7 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 7 , the first output unit 130 includes a first output transistor T5 and a first capacitor C1. The gate of the first output transistor T5 is connected to the second node Q2, the first electrode of the first output transistor T5 is connected to the second clock signal terminal 220, and the second electrode of the first output transistor T5 is connected to the output signal terminal 210. The second node Q2 has a different voltage from the first node Q1. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is set to open the first output unit 130 more thoroughly, thereby improving the voltage transmission capability of the first output unit 130 and improving the driving capability of the enable voltage output by the output signal terminal 210.

[0060] For example, reference Figure 7 , the first output transistor T5 is an N-type transistor. The off voltage is a negative voltage, and the on voltage is a positive voltage. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5, the more thoroughly the first output transistor T5 is turned on, and the voltage transmission capability of the first output transistor T5 is stronger, thereby improving the driving capability of the enable voltage output by the output signal terminal 210.

[0061] Figure 8 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Figure 8 , the shift register 100 also includes a second capacitor C2, a first plate of the second capacitor C2 is connected to the first node Q1, and a second plate of the second capacitor C2 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The capacitance value of the second capacitor C2 is greater than the capacitance value of the first capacitor C1. Thus, when the isolation transistor T4 is turned on, a second capacitor C2 with a larger capacitance value is set to change the voltage of the second node Q2 toward the voltage of the first node Q1. For example, the voltage of the first node Q1 is less than the voltage of the second node Q2. When the isolation transistor T4 is turned on, a second capacitor C2 with a larger capacitance value is set to pull the voltage of the second node Q2 down to the voltage of the first node Q1. The effect of resetting the voltage of the second node Q2 is achieved.

[0062] For example, reference Figure 8 , the second output unit 140 includes a third output transistor T6 and a third capacitor C3, the gate of the third output transistor T6 is connected to the third node QB, the first electrode of the third output transistor T6 is connected to the second power supply voltage terminal 230, and the second power supply voltage terminal 230 provides a shutdown voltage. For example, the voltage of the second power supply voltage terminal 230 is a low voltage, and the low voltage is, for example, less than or equal to -8V. In other embodiments, the voltage of the second power supply voltage terminal 230 can also be a high voltage, and the high voltage is greater than or equal to 8V. The second electrode of the third output transistor T6 is connected to the output signal terminal 210. The first plate of the third capacitor C3 is connected to the third node QB, and the second plate of the third capacitor C3 is connected to the second power supply voltage terminal 230. The third capacitor C3 is used to maintain the voltage of the third node QB.

[0063] Fig. 9 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig. 9, the second clock signal terminal 220 includes a second clock first sub-signal terminal CK2 and a second clock second sub-signal terminal BCK2, and the second clock first sub-signal terminal CK2 and the second clock second sub-signal terminal BCK2 provide voltages with the same timing and different voltage values. The same timing means that the second clock first sub-signal terminal CK2 and the second clock second sub-signal terminal BCK2 have a turn-on voltage at the same time in the same period, and have a turn-off voltage at the same time in the same period. The output signal terminal 210 includes a first output signal terminal OUT and a second output signal terminal CR. The first electrode of the first output transistor T5 is connected to the second clock first sub-signal terminal CK2, and the second electrode of the first output transistor T5 is connected to the first output signal terminal OUT. The first output unit 130 also includes a second output transistor T10, the gate of the second output transistor T10 is connected to the second node Q2, the first electrode of the second output transistor T10 is connected to the second clock first sub-signal terminal CK2 or the second clock second sub-signal terminal BCK2, and the second electrode of the second output transistor T10 is connected to the second output signal terminal CR.

[0064] For example, reference Fig. 9 , the voltage of the second clock second sub-signal terminal BCK2 at a low voltage is less than the voltage of the second clock first sub-signal terminal CK2 at a low voltage.

[0065] Fig.10 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.10 , the first reset unit 150 also includes a second reset transistor T8, the gate of the second reset transistor T8 is connected to the third node QB, the first electrode of the second reset transistor T8 is connected to the second electrode of the first reset transistor T7, and the second electrode of the second reset transistor T8 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The turn-on voltage applied to the second electrode of the first reset transistor T7 turns off the first reset transistor T7 more thoroughly, reduces the leakage through the first reset transistor T7, and reduces the leakage of the circuit branch where the first node Q1 - the first reset transistor T7 - ​​the second reset transistor T8 - the second power supply voltage terminal 230 is located.

[0066] Fig.11 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.11, the first input unit 110 includes a first input transistor T1, the gate of the first input transistor T1 is connected to the cascade signal input terminal STV, and the first electrode of the first input transistor T1 is connected to the first power supply voltage terminal VGH. The first power supply voltage terminal VGH provides a turn-on voltage, and the second electrode of the first input transistor T1 is connected to the first node Q1. When the turn-on voltage provided by the cascade signal input terminal STV turns on the first input transistor T1, the turn-on voltage provided by the first power supply voltage terminal VGH is transmitted to the first node Q1. The turn-on voltage of the first node Q1 turns on the turn-off transistor T9, and the turn-off transistor T9 transmits the turn-on voltage provided by the first power supply voltage terminal VGH to the second electrode of the first reset transistor T7, turning off the first reset transistor T7 more thoroughly, reducing the leakage through the first reset transistor T7.

[0067] For example, reference Fig.11 , the second input unit 120 includes a second input transistor T2, the gate of which is connected to the third clock signal terminal CK3. The first electrode of the second input transistor T2 is connected to the first power supply voltage terminal VGH, and the second electrode of the second input transistor T2 is connected to the third node QB. During the period when the third clock signal terminal CK3 provides the conduction voltage, the second input transistor T2 is turned on, and the second input transistor T2 transmits the conduction voltage provided by the first power supply voltage terminal VGH to the third node QB.

[0068] For example, reference Figure 1 and Fig.11 , the second output signal terminal CR of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100.

[0069] For example, reference Figure 1 and Figure 8 , the first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100.

[0070] Optionally, refer to Figure 1 and Fig.11, the shift register 100 includes a second power supply voltage terminal 230 for providing a shutdown voltage. The second power supply voltage terminal 230 includes a second power supply first sub-voltage terminal VGL and a second power supply second sub-voltage terminal LVGL. The voltage provided by the second power supply first sub-voltage terminal VGL is greater than the voltage provided by the second power supply second sub-voltage terminal LVGL. The second output unit 140 includes a third output transistor T6, the gate of the third output transistor T6 is connected to the third node QB, the first electrode of the third output transistor T6 is connected to the second power supply second sub-voltage terminal LVGL, and the second electrode of the third output transistor T6 is connected to the output signal terminal 210. The shift register 100 also includes a third reset transistor T3, the gate of the third reset transistor T3 is connected to the first node Q1, the first electrode of the third reset transistor T3 is connected to the third node QB, and the second electrode of the third reset transistor T3 is connected to the second power supply second sub-voltage terminal LVGL.

[0071] For example, reference Fig.11 , the second electrode of the third output transistor T6 is connected to the second output signal terminal CR. The second output unit 140 also includes a fourth output transistor T11. The gate of the fourth output transistor T11 is connected to the third node QB, the first electrode of the fourth output transistor T11 is connected to the first sub-voltage terminal VGL of the second power supply, and the second electrode of the fourth output transistor T11 is connected to the first output signal terminal OUT. When the first node Q1 is a positive voltage, the third reset transistor T3 is turned on. The voltage provided by the second sub-voltage terminal LVGL of the second power supply is transmitted to the third node QB through the third reset transistor T3. When the voltage of the first output signal terminal OUT is a high voltage, the gate-source voltage difference of the fourth output transistor T11 is a negative value. Even if the threshold voltage of the fourth output transistor T11 drifts negatively, the fourth output transistor T11 can be turned off, thereby improving the working stability of the shift register 100. As an example, the voltage provided by the first sub-voltage terminal VGL of the second power supply is, for example, -8V, and the voltage provided by the second sub-voltage terminal LVGL of the second power supply is, for example, -10V.

[0072] For example, reference Fig.11, the low voltage of the second clock first sub-signal terminal CK2 is equal to the voltage provided by the second power supply second sub-voltage terminal LVGL, and the voltage of the second clock second sub-signal terminal BCK2 at low voltage is equal to the voltage provided by the second power supply first sub-voltage terminal VGL. Therefore, the low voltage transmitted to the second output signal terminal CR through the first output transistor T5 is equal to the low voltage transmitted to the second output signal terminal CR through the third output transistor T6. The low voltage transmitted to the first output signal terminal OUT through the second output transistor T10 is equal to the low voltage transmitted to the first output signal terminal OUT through the fourth output transistor T11. It not only reduces the competition risk caused by different voltages, but also reduces the leakage of the two circuit branches. The two circuit branches include: the second clock first sub-signal terminal CK2 - the first output transistor T5 - the third output transistor T6 - the second power supply second sub-voltage terminal LVGL; and the second clock second sub-signal terminal BCK2 - the second output transistor T10 - the fourth output transistor T11 - the second power supply first sub-voltage terminal VGL.

[0073] Fig.12 A driving timing diagram of a shift register provided by an embodiment of the present invention, referring to Fig.11 and Fig.12 , in the first time period t1, the voltage of the cascade signal input terminal STV is a high voltage, the first input transistor T1 is turned on, and the first node Q1 becomes a high voltage. The voltage of the first clock signal terminal CK1 is a high voltage, the isolation transistor T4 is turned on, and the second node Q2 becomes a high voltage. When the first node Q1 is a high voltage, the turn-off transistor T9 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the second pole of the first reset transistor T7, and the first reset transistor T7 is turned off more thoroughly, reducing the leakage through the first reset transistor T7. The first node Q1 is a high voltage, charging the second capacitor C2. The second capacitor C2 maintains the high potential of the first node Q1. When the first node Q1 is a high voltage, the third reset transistor T3 is turned on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the third node QB, and the third node QB becomes a low voltage. The third node QB is a low voltage, and the third output transistor T6, the second reset transistor T8 and the fourth output transistor T11 are turned off. When the second node Q2 is a high voltage, the first output transistor T5 and the second output transistor T10 are turned on. The second clock first sub-signal terminal CK2 is a low voltage, and the second output signal terminal CR is a low voltage. The second clock second sub-signal terminal BCK2 is a low voltage, and the first output signal terminal OUT is a low voltage. The third clock signal terminal CK3 is a low voltage, and the second input transistor T2 and the first reset transistor T7 are turned off.

[0074] In the second period t2, the voltage of the cascade signal input terminal STV is a low voltage, and the first input transistor T1 is turned off. The first node Q1 is maintained at a high voltage. When the first node Q1 is a high voltage, the turn-off transistor T9 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the second pole of the first reset transistor T7, and the first reset transistor T7 is turned off more thoroughly, reducing the leakage through the first reset transistor T7. When the first node Q1 is a high voltage, the third reset transistor T3 is turned on, and the low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the third node QB, and the third node QB becomes a low voltage. The third node QB is a low voltage, and the third output transistor T6, the second reset transistor T8 and the fourth output transistor T11 are turned off. The voltage of the first clock signal terminal CK1 is a low voltage, the isolation transistor T4 is turned off, and the second node Q2 maintains a high voltage. When the second node Q2 is a high voltage, the first output transistor T5 is turned on, the second clock first sub-signal terminal CK2 becomes a high voltage, and the second output signal terminal CR is a high voltage. The second output transistor T10 is turned on, the second clock second sub-signal terminal BCK2 is a high voltage, and the first output signal terminal OUT is a high voltage. In the second period t2, the shift register 100 outputs an enable voltage. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5 and the second output transistor T10, the more thoroughly the first output transistor T5 and the second output transistor T10 are turned on, and the first output transistor T5 and the second output transistor T10 have a stronger ability to transmit voltage, thereby improving the driving ability of the enable voltage output by the first output signal terminal OUT and the second output signal terminal CR. The third clock signal terminal CK3 is a low voltage, and the second input transistor T2 and the first reset transistor T7 are turned off. In the first period t1 and the second period t2, the high voltage of the first power supply voltage terminal VGH is transmitted to the second pole of the first reset transistor T7, and the first reset transistor T7 is turned off more thoroughly.

[0075] In the third period t3, the voltage of the cascade signal input terminal STV is a low voltage, and the first input transistor T1 is turned off. The voltage of the first clock signal terminal CK1 is a low voltage, and the isolation transistor T4 is turned off. The third clock signal terminal CK3 becomes a high voltage, the second input transistor T2 is turned on, and the third node QB becomes a high voltage. When the third clock signal terminal CK3 and the third node QB are high voltages, the first reset transistor T7 and the second reset transistor T8 are turned on, and the low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the first node Q1, and the first node Q1 becomes a low voltage. When the first node Q1 is a low voltage, the third reset transistor T3 and the turn-off transistor T9 are turned off. When the second node Q2 is a high voltage, the first output transistor T5 and the second output transistor T10 are turned on. The second clock first sub-signal terminal CK2 is a low voltage, and the low voltage of the second clock first sub-signal terminal CK2 is transmitted to the second output signal terminal CR through the first output transistor T5, and the second output signal terminal CR is a low voltage. The second clock second sub-signal terminal BCK2 is a low voltage, and the low voltage of the second clock second sub-signal terminal BCK2 is transmitted to the first output signal terminal OUT through the second output transistor T10, and the first output signal terminal OUT is a low voltage. When the third node QB is a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on, and the low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the second output signal terminal CR through the third output transistor T6, and the voltage of the second power supply second sub-voltage terminal LVGL is equal to the low voltage of the second clock second sub-signal terminal BCK2. The low voltage of the second power supply first sub-voltage terminal VGL is transmitted to the first output signal terminal OUT through the fourth output transistor T11, and the voltage of the second power supply first sub-voltage terminal VGL is equal to the low voltage of the second clock first sub-signal terminal CK2. It not only reduces the competition risk caused by the voltage difference, but also reduces the leakage of the two circuit branches. The two circuit branches include: the second clock first sub-signal terminal CK2 - the first output transistor T5 - the third output transistor T6 - the second power supply second sub-voltage terminal LVGL; and the second clock second sub-signal terminal BCK2 - the second output transistor T10 - the fourth output transistor T11 - the second power supply first sub-voltage terminal VGL. In the third period t3, when the voltage of the first output signal terminal OUT is a high voltage, the gate-source voltage difference of the fourth output transistor T11 is a negative value. Even if the threshold voltage of the fourth output transistor T11 drifts negatively, the fourth output transistor T11 can be turned off, thereby improving the working stability of the shift register 100.

[0076] In the fourth period t4, the voltage of the cascade signal input terminal STV is a low voltage, and the first input transistor T1 is turned off. The first node Q1 maintains a low voltage. The voltage of the first clock signal terminal CK1 is a low voltage, and the isolation transistor T4 is turned off. The second node Q2 maintains a high voltage, and the first output transistor T5 and the second output transistor T10 are turned on. The low voltage of the second clock first sub-signal terminal CK2 is transmitted to the second output signal terminal CR through the first output transistor T5, and the second output signal terminal CR is a low voltage. The low voltage of the second clock second sub-signal terminal BCK2 is transmitted to the first output signal terminal OUT through the second output transistor T10, and the first output signal terminal OUT is a low voltage. The third node QB maintains a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on, the low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the second output signal terminal CR through the third output transistor T6, and the low voltage of the second power supply first sub-voltage terminal VGL is transmitted to the first output signal terminal OUT through the fourth output transistor T11.

[0077] In the fifth period t5, the voltage of the cascade signal input terminal STV is a low voltage, the first input transistor T1 is turned off, and the first node Q1 maintains a low voltage. The voltage of the first clock signal terminal CK1 is a high voltage, the isolation transistor T4 is turned on, the voltage of the second node Q2 is pulled down by the low voltage of the first node Q1, and the second node Q2 becomes a low voltage. When the first node Q1 is a low voltage, the turn-off transistor T9 is turned off. When the second node Q2 is a high voltage, the first output transistor T5 and the second output transistor T10 are turned off. In other words, wait until the next high voltage of the first clock signal terminal CK1 to reset the potential of the second node Q2 to a low voltage. When the first node Q1 is a low voltage, the third reset transistor T3 is turned off. The third node QB maintains a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on, the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second output signal terminal CR through the third output transistor T6, and the low voltage of the first sub-voltage terminal VGL of the second power supply is transmitted to the first output signal terminal OUT through the fourth output transistor T11.

[0078] Fig.13 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.13 , the first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100. Fig.13 The shift register circuit shown is suitable for Fig.12 The driving timing is shown.

[0079] Fig.14 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.14, a first electrode of the first output transistor T5 is connected to the second clock first sub-signal terminal CK2, and a first electrode of the second output transistor T10 is connected to the second clock first sub-signal terminal CK2. Fig.14 The shift register circuit shown is suitable for Fig.12 The drive timing is shown.

[0080] Fig.15 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.15 , the second electrode of the turn-off transistor T9 is connected to the second clock signal terminal 220 . Fig.15 The shift register circuit shown is suitable for Fig.12 The driving timing is shown in Figure 2. Fig.12 and Fig.15 In the second period t2, the clock signal provided by the second clock signal terminal 220 is a high voltage, the turn-off transistor T9 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the second electrode of the first reset transistor T7, so that the first reset transistor T7 is turned off more thoroughly, and the leakage through the first reset transistor T7 is reduced. It should be noted that in the second period t2, the voltage of the second node Q2 is coupled and pulled up, which is more likely to cause leakage. Therefore, in the second period t2, the first reset transistor T7 is turned off more thoroughly, which can more significantly reduce the leakage of the shift register and the leakage of the gate drive circuit.

[0081] Fig.16 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.16 , the gate of the first reset transistor T7 is connected to the first clock signal terminal CK1, and the second electrode of the first reset transistor T7 is connected to the output terminal of the first input unit 110. When the voltage of the first node Q1 is the on-voltage, the turn-off unit 160 is turned on, and the on-voltage is written to the second electrode of the first reset transistor T7. The first electrode of the first reset transistor T7 and the second electrode of the first reset transistor T7 are both on-voltages. The gate of the first reset transistor T7 is the off-voltage, and the on-voltage applied to the second electrode of the first reset transistor T7 turns off the first reset transistor T7 more thoroughly, reduces the leakage through the first reset transistor T7, and reduces the leakage of the circuit branch where the first node Q1 and the first reset unit 150 are located.

[0082] Fig.17 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.17, the first input unit 110 includes a first input transistor T1. The gate of the first input transistor T1 is connected to the first clock signal terminal CK1, the first electrode of the first input transistor T1 is connected to the cascade signal input terminal STV, and the second electrode of the first input transistor T1 is connected to the second electrode of the first reset transistor T7. When the first input transistor T1 is turned on by the turn-on voltage provided by the first clock signal terminal CK1, the voltage of the cascade signal input terminal STV is transmitted to the second electrode of the first reset transistor T7. And when the first reset unit 150 is turned on, the voltage of the cascade signal input terminal STV is transmitted to the first node Q1.

[0083] For example, reference Fig.17 , the second input unit 120 includes a second input transistor T2, the gate of which is connected to the first clock signal terminal CK1. The first electrode of the second input transistor T2 is connected to the first power supply voltage terminal VGH, and the second electrode of the second input transistor T2 is connected to the third node QB. During the period when the first clock signal terminal CK1 provides the conduction voltage, the second input transistor T2 is turned on, and the second input transistor T2 transmits the conduction voltage provided by the first power supply voltage terminal VGH to the third node QB.

[0084] Fig.18 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.18 The shut-off unit 160 includes a shut-off transistor T9. The gate of the shut-off transistor T9 is connected to the first node Q1, and the first electrode of the shut-off transistor T9 is connected to the second electrode of the first reset transistor T7. When the shut-off transistor T9 is turned on, the turn-on voltage is written to the second electrode of the first reset transistor T7, so that the first reset transistor T7 is turned off more completely.

[0085] For example, reference Fig.18 , the first electrode of the first reset transistor T7 is connected to the first node Q1. When the first input transistor T1 and the first reset transistor T7 are turned on by the turn-on voltage provided by the first clock signal terminal CK1, the voltage of the cascade signal input terminal STV is transmitted to the first node Q1 through the first input transistor T1 and the first reset transistor T7. The second electrode of the third reset transistor T3 is connected to the first clock signal terminal CK1.

[0086] Fig.19 Another driving timing diagram of a shift register provided by an embodiment of the present invention is shown in FIG. Fig.18 and Fig.19, in the first period t1, the voltage of the first clock signal terminal CK1 is a high voltage, and the first input transistor T1 and the first reset transistor T7 are turned on. The voltage of the cascade signal input terminal STV is a high voltage, and the high voltage of the cascade signal input terminal STV is transmitted to the first node Q1. When the first node Q1 is a high voltage, the third reset transistor T3 is turned on, and the high voltage of the first clock signal terminal CK1 is transmitted to the third node QB. The first clock signal terminal CK1 is a high voltage, the second input transistor T2 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the third node QB through the second input transistor T2, and the third node QB becomes a high voltage. When the first node Q1 is a high voltage, the first output transistor T5 is turned on, and the low voltage of the second clock first sub-signal terminal CK2 is transmitted to the first output signal terminal OUT. When the third node QB is a high voltage, the third output transistor T6 is turned on, and the low voltage of the second power supply first sub-voltage terminal VGL is transmitted to the first output signal terminal OUT. The first output signal terminal OUT is a low voltage.

[0087] In the second period t2, the voltage of the first clock signal terminal CK1 is a low voltage, and the first input transistor T1, the second input transistor T2 and the first reset transistor T7 are turned off. The first node Q1 maintains a high voltage, the third reset transistor T3 is turned on, and the low voltage of the first clock signal terminal CK1 is transmitted to the third node QB. The third node QB becomes a low voltage. The third output transistor T6 is turned off. The second node Q2 maintains a high voltage, the first output transistor T5 is turned on, the second clock signal terminal 220 becomes a high voltage, and the high voltage of the second clock signal terminal 220 is transmitted to the first output signal terminal OUT through the first output transistor T5, and the first output signal terminal OUT is a high voltage. The first node Q1 is a high voltage, the turn-off transistor T9 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the second electrode of the first reset transistor T7 through the turn-off transistor T9, and the first reset transistor T7 is turned off more thoroughly, reducing the leakage through the first reset transistor T7, and reducing the leakage of the circuit branch where the first node Q1-the first reset transistor T7-the first input transistor T1-the cascade signal input terminal STV is located. The voltage of the first clock signal terminal CK1 is a low voltage, and the isolation transistor T4 is turned off. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5, the more thoroughly the first output transistor T5 is turned on, and the voltage transmission capability of the first output transistor T5 is stronger, thereby improving the driving capability of the enable voltage output by the first output signal terminal OUT.

[0088] In the third period t3, the voltage of the first clock signal terminal CK1 is a high voltage, and the first input transistor T1 and the first reset transistor T7 are turned on. The voltage of the cascade signal input terminal STV is a low voltage, and the low voltage of the cascade signal input terminal STV is transmitted to the first node Q1. The first node Q1 becomes a low voltage. When the first node Q1 is a low voltage, the third reset transistor T3 is turned off. The voltage of the first clock signal terminal CK1 is a high voltage, the isolation transistor T4 is turned on, the voltage of the second node Q2 is pulled down by the low voltage of the first node Q1, and the second node Q2 becomes a low voltage. The first output transistor T5 is turned off. The voltage of the first clock signal terminal CK1 is a high voltage, the second input transistor T2 is turned on, and the high voltage of the first power supply voltage terminal VGH is transmitted to the third node QB through the second input transistor T2, and the third node QB becomes a high voltage. When the third node QB is a high voltage, the third output transistor T6 is turned on, and the low voltage of the second power supply first sub-voltage terminal VGL is transmitted to the first output signal terminal OUT. The first output signal terminal OUT is a low voltage.

[0089] Fig. 20 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Fig. 20 , a first electrode of the first output transistor T5 is connected to the second clock first sub-signal terminal CK2, and a first electrode of the second output transistor T10 is connected to the second clock first sub-signal terminal CK2. Fig. 20 The shift register circuit shown is suitable for Fig.19 The second output signal terminal CR of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100 .

[0090] Fig.21 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.21 , a first electrode of the first output transistor T5 is connected to the second clock first sub-signal terminal CK2, and a first electrode of the second output transistor T10 is connected to the second clock second sub-signal terminal BCK2. Fig.21 The shift register circuit shown is suitable for Fig.19 The drive timing is shown.

[0091] Fig. 22 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Fig. 22, the shift register 100 further includes a second reset unit 170, and the second reset unit 170 is used to write the turn-off voltage to the second node Q2. The second reset unit 170 includes a fourth reset transistor T12, and the gate of the fourth reset transistor T12 is connected to the third clock signal terminal CK3. The first electrode of the fourth reset transistor T12 is connected to the second node Q2. The first end of the turn-off unit 160 is connected to the second electrode of the fourth reset transistor T12, and is used to write the turn-on voltage to the second electrode of the fourth reset transistor T12 when the turn-off unit 160 is turned on at the first node Q1. When the voltage of the first node Q1 is the turn-on voltage, the turn-off unit 160 is turned on, and the turn-on voltage is written to the second electrode of the fourth reset transistor T12. The first electrode of the fourth reset transistor T12 and the second electrode of the fourth reset transistor T12 are both the turn-on voltage. The gate of the fourth reset transistor T12 is a turn-off voltage, and the turn-on voltage applied to the second electrode of the fourth reset transistor T12 turns off the fourth reset transistor T12 more completely, reducing the leakage through the fourth reset transistor T12, and reducing the leakage of the circuit branch where the second node Q2 and the second reset unit 170 are located. On the other hand, the second reset unit 170 is used to write the turn-off voltage to the second node Q2, thereby resetting the second node Q2.

[0092] Fig.23 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.23 , the second reset unit 170 also includes a fifth reset transistor T13. The gate of the fifth reset transistor T13 is connected to the third clock signal terminal CK3, the first electrode of the fifth reset transistor T13 is connected to the second electrode of the fourth reset transistor T12, and the second electrode of the fifth reset transistor T13 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The turn-on voltage applied to the second electrode of the fourth reset transistor T12 turns off the fourth reset transistor T12 more thoroughly, reduces the leakage through the fourth reset transistor T12, and reduces the leakage of the circuit branch where the second node Q2 - the fourth reset transistor T12 - the fifth reset transistor T13 - the second power supply voltage terminal 230 is located.

[0093] For example, reference Fig.23 The same shut-off unit 160 not only shuts down the first reset transistor T7 more completely to reduce the leakage through the first reset transistor T7, but also shuts down the fourth reset transistor T12 more completely to reduce the leakage through the fourth reset transistor T12.

[0094] Fig.24 A circuit diagram of another shift register provided by an embodiment of the present invention, Fig.25 Another driving timing diagram of a shift register provided by an embodiment of the present invention, Fig.25 and Fig.12 The same process is not repeated here. Fig.24 and Fig.25 , in the first time period t1, the first node Q1 becomes a high voltage, and the second node Q2 becomes a high voltage. When the first node Q1 is a high voltage, the turn-off transistor T9 is turned on, and the high voltage is transmitted to the second electrode of the first reset transistor T7, and the first reset transistor T7 is turned off more thoroughly. The third clock signal terminal CK3 is a low voltage, and the fourth reset transistor T12 is turned off. The turn-off transistor T9 is turned on, and the high voltage is transmitted to the second electrode of the fourth reset transistor T12, and the fourth reset transistor T12 is turned off more thoroughly.

[0095] In the second period t2, the first node Q1 maintains a high voltage. When the first node Q1 is at a high voltage, the transistor T9 is turned off, and the high voltage is transmitted to the second electrode of the first reset transistor T7, so that the first reset transistor T7 is turned off more thoroughly. The third clock signal terminal CK3 is at a low voltage, and the fourth reset transistor T12 is turned off. The transistor T9 is turned off, and the high voltage is transmitted to the second electrode of the fourth reset transistor T12, so that the fourth reset transistor T12 is turned off more thoroughly.

[0096] In the third period t3, the first clock signal terminal CK1 is a low voltage, and the isolation transistor T4 is turned off. The third clock signal terminal CK3 is a high voltage, the second input transistor T2 is turned on, and the third node QB becomes a high voltage. When the third clock signal terminal CK3 and the third node QB are high voltages, the first reset transistor T7 and the second reset transistor T8 are turned on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the first node Q1, and the first node Q1 becomes a low voltage. When the first node Q1 is a low voltage, the third reset transistor T3 and the turn-off transistor T9 are turned off. The third clock signal terminal CK3 is a high voltage, the fourth reset transistor T12 is turned on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second node Q2 through the second reset transistor T8 and the fourth reset transistor T12, and the second node Q2 is pulled down from a high voltage to a low voltage. The reset of the second node Q2 is realized. In the third period t3, the second node Q2 is a low voltage, and the first output transistor T5 and the second output transistor T10 are turned off. The third node QB is a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on, the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second output signal terminal CR through the third output transistor T6, and the low voltage of the first sub-voltage terminal VGL of the second power supply is transmitted to the first output signal terminal OUT through the fourth output transistor T11.

[0097] Fig.26 A circuit diagram of another shift register provided by an embodiment of the present invention, Fig.26 The shift register circuit shown is suitable for Fig.25The driving timing shown is shown in Fig.25 and Fig.26 , the second reset unit 170 also includes a fifth reset transistor T13. The gate of the fifth reset transistor T13 is connected to the third clock signal terminal CK3, the first electrode of the fifth reset transistor T13 is connected to the second electrode of the fourth reset transistor T12, and the second electrode of the fifth reset transistor T13 is connected to the second power supply second sub-voltage terminal LVGL. In the third period t3, the third node QB is a high voltage, and the second reset transistor T8 is turned on. The third clock signal terminal CK3 is a high voltage, and the fourth reset transistor T12 and the fifth reset transistor T13 are turned on. The low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the second node Q2 through the second reset transistor T8 and the fourth reset transistor T12, and the low voltage of the second power supply second sub-voltage terminal LVGL is transmitted to the second node Q2 through the fifth reset transistor T13 and the fourth reset transistor T12, so as to achieve the reset of the second node Q2.

[0098] Fig. 27 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Figure 1 and Fig. 27 , the first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100. Fig. 27 The shift register circuit shown is suitable for Fig.25 The drive timing is shown.

[0099] Fig.28 A circuit diagram of another shift register provided by an embodiment of the present invention is shown in FIG. Fig.28 , the second electrode of the turn-off transistor T9 is connected to the second clock signal terminal 220 . Fig.28 The shift register circuit shown is suitable for Fig.25 The drive timing is shown.

[0100] Fig.29 A circuit diagram of another gate drive circuit provided by an embodiment of the present invention, referring to Fig.29The gate driving circuit further includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3 and a fourth clock signal line CLK4. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the i-th shift register 100, the third clock signal terminal CK3 of the i+2-th shift register 100 and the second clock signal terminal 220 of the i+3-th shift register 100. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the i-th shift register 100, the first clock signal terminal CK1 of the i+1-th shift register 100 and the third clock signal terminal CK3 of the i+3-th shift register 100. The third clock signal line CLK3 is electrically connected to the third clock signal terminal CK3 of the i-th shift register 100, the second clock signal terminal 220 of the i+1-th shift register 100 and the first clock signal terminal CK1 of the i+3-th shift register 100. The fourth clock signal line CLK4 is electrically connected to the third clock signal terminal CK3 of the i+1th shift register 100, the second clock signal terminal 220 of the i+2th shift register 100, and the first clock signal terminal CK1 of the i+3th shift register 100. The first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 provide corresponding clock signals to the clock signal terminals connected thereto. i is a positive integer.

[0101] For example, reference Fig.29 , a plurality of cascaded shift registers 100 include a first shift register VSR1, a second shift register VSR2, a third shift register VSR3 and a fourth shift register VSR4. A first clock signal line CLK1 is electrically connected to a first clock signal terminal CK1 of the first shift register VSR1, a third clock signal terminal CK3 of the third shift register VSR3 and a second clock signal terminal 220 of the fourth shift register VSR4. A second clock signal line CLK2 is electrically connected to a second clock signal terminal 220 of the first shift register VSR1, a first clock signal terminal CK1 of the second shift register VSR2 and a third clock signal terminal CK3 of the fourth shift register VSR4. A third clock signal line CLK3 is electrically connected to a third clock signal terminal CK3 of the first shift register VSR1, a second clock signal terminal 220 of the second shift register VSR2 and a first clock signal terminal CK1 of the third shift register VSR3. The fourth clock signal line CLK4 is electrically connected to the third clock signal terminal CK3 of the second shift register VSR2, the second clock signal terminal 220 of the third shift register VSR3, and the first clock signal terminal CK1 of the fourth shift register VSR4.

[0102] For example, reference Fig.29The gate driving circuit further includes an initial signal line STVL, and the initial signal line STVL is electrically connected to the cascade signal input terminal STV of the first shift register VSR1.

[0103] For example, reference Fig.12 and Fig.29 , Fig.12 The driving timing shown may be the driving timing of the first shift register VSR1. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1, and provides a clock signal to the first clock signal terminal CK1 of the first shift register VSR1. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1, and provides a clock signal to the second clock signal terminal 220 of the first shift register VSR1. The third clock signal line CLK3 is electrically connected to the third clock signal terminal CK3 of the first shift register VSR1, and provides a clock signal to the third clock signal terminal CK3 of the first shift register VSR1.

[0104] Fig.30 A circuit diagram of another gate drive circuit provided by an embodiment of the present invention, referring to Fig.30 The gate driving circuit further includes a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the i-th shift register 100 and the second clock signal terminal 220 of the i+1-th shift register 100. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the i-th shift register 100 and the first clock signal terminal CK1 of the i+1-th shift register 100. The first clock signal line CLK1 and the second clock signal line CLK2 provide corresponding clock signals to the clock signal terminals connected thereto. i is a positive integer.

[0105] For example, reference Fig.30 The plurality of cascaded shift registers 100 include a first shift register VSR1, a second shift register VSR2, and a third shift register VSR3. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1 and the second clock signal terminal 220 of the second shift register VSR2. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1 and the first clock signal terminal CK1 of the second shift register VSR2.

[0106] For example, reference Fig.19 and Fig.30 , Fig.19The driving timing shown can be the driving timing of the first shift register VSR1. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1, and provides a clock signal to the first clock signal terminal CK1 of the first shift register VSR1. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1, and provides a clock signal to the second clock signal terminal 220 of the first shift register VSR1.

[0107] Fig.31 A schematic diagram of a display panel provided by an embodiment of the present invention, referring to Fig.31 The display panel includes the gate driving circuit 200 in the above embodiment. Since the display panel provided by the embodiment of the present invention includes the gate driving circuit 200 in the above embodiment, the shift register 100 in the gate driving circuit 200 can have a smaller leakage.

[0108] For example, reference Fig.31 The display panel includes a display area AA and a non-display area NAA, the gate driving circuit 200 is located in the non-display area NAA, the pixel driving circuit 330 is located in the display area AA, and a plurality of pixel driving circuits 330 are arranged in an array along a first direction X and a second direction Y. The display panel also includes a plurality of scan lines 121, and the plurality of scan lines 121 extend along the first direction X and are arranged along the second direction Y. The first output signal terminal OUT of the shift register 100 is electrically connected to a scan line 121. Among them, the pixel driving circuit 330 can adopt, for example, a pixel driving circuit known in the art such as 2T1C or 7T1C, which will not be described in detail here.

[0109] Fig.32 A schematic diagram of a display device provided by an embodiment of the present invention. Fig.32 The display device includes any one of the display panels provided in the embodiments of the present invention. The display device may specifically be a mobile phone, a tablet computer, a vehicle-mounted display device, a smart wearable device, and the like.

[0110] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate drive circuit, comprising a plurality of cascaded shift registers, characterized in that: The shift register comprises a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit and a shut-down unit; The output end of the first input unit and the control end of the first output unit are connected to a first node, and the output end of the second input unit and the control end of the second output unit are connected to a third node; The first reset unit is used to write a shutdown voltage to the first node, and the shutdown voltage is a voltage for controlling the first output unit to be turned off; the first reset unit includes a first reset transistor, and the gate of the first reset transistor is connected to the first clock signal terminal or the third clock signal terminal; the first electrode of the first reset transistor is connected to the first node; The control end of the shutdown unit is connected to the first node, and the first end of the shutdown unit is connected to the second electrode of the first reset transistor, and is used to write a turn-on voltage into the second electrode of the first reset transistor when the first node controls the shutdown unit to be turned on. The turn-on voltage is the voltage that controls the first output unit to be turned on.

2. The gate driving circuit according to claim 1, characterized in that: The shutoff unit includes a shutoff transistor, a gate of the shutoff transistor is connected to the first node, and a first electrode of the shutoff transistor is connected to a second electrode of the first reset transistor.

3. The gate driving circuit according to claim 2, characterized in that: The second electrode of the turn-off transistor is connected to a first power supply voltage terminal, and the first power supply voltage terminal provides the turn-on voltage.

4. The gate driving circuit according to claim 2, characterized in that: The second electrode of the turn-off transistor is connected to the first clock signal terminal or the second clock signal terminal.

5. The gate driving circuit according to claim 1, characterized in that: The shift register further includes an isolation transistor, a gate of the isolation transistor is connected to the first clock signal terminal, a first electrode of the isolation transistor is connected to the first node, and a second electrode of the isolation transistor and a control terminal of the first output unit are connected to a second node.

6. The gate driving circuit according to claim 5, characterized in that: The first output unit includes a first output transistor and a first capacitor, the gate of the first output transistor is connected to the second node, the first electrode of the first output transistor is connected to the second clock signal terminal, and the second electrode of the first output transistor is connected to the output signal terminal.

7. The gate driving circuit according to claim 6, characterized in that: The shift register further comprises a second capacitor, a first plate of the second capacitor is connected to the first node, a second plate of the second capacitor is connected to a second power supply voltage terminal, and the second power supply voltage terminal provides the shutdown voltage; The capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

8. The gate driving circuit according to claim 6, characterized in that: The second clock signal terminal includes a second clock first sub-signal terminal and a second clock second sub-signal terminal, and the second clock first sub-signal terminal and the second clock second sub-signal terminal provide voltages with the same timing and different voltage values; The output signal terminal includes a first output signal terminal and a second output signal terminal; the first electrode of the first output transistor is connected to the second clock first sub-signal terminal, and the second electrode of the first output transistor is connected to the first output signal terminal; The first output unit also includes a second output transistor, the gate of the second output transistor is connected to the second node, the first electrode of the second output transistor is connected to the second clock first sub-signal terminal or the second clock second sub-signal terminal, and the second electrode of the second output transistor is connected to the second output signal terminal.

9. The gate driving circuit according to claim 1, characterized in that: The first reset unit also includes a second reset transistor, the gate of the second reset transistor is connected to the third node, the first electrode of the second reset transistor is connected to the second electrode of the first reset transistor, the second electrode of the second reset transistor is connected to a second power supply voltage terminal, and the second power supply voltage terminal provides the shutdown voltage.

10. The gate driving circuit according to claim 9, characterized in that: The first input unit includes a first input transistor, a gate of the first input transistor is connected to the cascade signal input terminal, a first electrode of the first input transistor is connected to a first power supply voltage terminal, the first power supply voltage terminal provides the turn-on voltage, and a second electrode of the first input transistor is connected to the first node.

11. The gate driving circuit according to claim 1, characterized in that: The shift register comprises a second power supply voltage terminal for providing the shutdown voltage, the second power supply voltage terminal comprises a second power supply first sub-voltage terminal and a second power supply second sub-voltage terminal, the voltage provided by the second power supply first sub-voltage terminal is greater than the voltage provided by the second power supply second sub-voltage terminal; The second output unit comprises a third output transistor, the gate of the third output transistor is connected to the third node, the first electrode of the third output transistor is connected to the second sub-voltage terminal of the second power supply, and the second electrode of the third output transistor is connected to the output signal terminal; The shift register further includes a third reset transistor, a gate of the third reset transistor is connected to the first node, a first electrode of the third reset transistor is connected to the third node, and a second electrode of the third reset transistor is connected to the second sub-voltage terminal of the second power supply.

12. The gate driving circuit according to claim 1, characterized in that: A gate of the first reset transistor is connected to a first clock signal terminal, and a second electrode of the first reset transistor is connected to an output terminal of the first input unit.

13. The gate driving circuit according to claim 12, characterized in that: The first input unit includes a first input transistor, a gate of the first input transistor is connected to the first clock signal terminal, a first electrode of the first input transistor is connected to the cascade signal input terminal, and a second electrode of the first input transistor is connected to the second electrode of the first reset transistor.

14. The gate driving circuit according to claim 5, characterized in that: The shift register further includes a second reset unit, and the second reset unit is used to write the turn-off voltage to the second node; The second reset unit comprises a fourth reset transistor, and the gate of the fourth reset transistor is connected to the third clock signal terminal; A first electrode of the fourth reset transistor is connected to the second node; The first end of the shutoff unit is connected to the second electrode of the fourth reset transistor, and is used to write the turn-on voltage into the second electrode of the fourth reset transistor when the first node controls the shutoff unit to be turned on.

15. The gate driving circuit according to claim 14, characterized in that: The second reset unit also includes a fifth reset transistor; The gate of the fifth reset transistor is connected to the third clock signal terminal, the first electrode of the fifth reset transistor is connected to the second electrode of the fourth reset transistor, the second electrode of the fifth reset transistor is connected to the second power supply voltage terminal, and the second power supply voltage terminal provides the shutdown voltage.

16. The gate driving circuit according to claim 1, characterized in that: Also includes a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; The first clock signal line is electrically connected to the first clock signal terminal of the i-th shift register, the third clock signal terminal of the i+2-th shift register, and the second clock signal terminal of the i+3-th shift register; The second clock signal line is electrically connected to the second clock signal terminal of the i-th shift register, the first clock signal terminal of the i+1-th shift register, and the third clock signal terminal of the i+3-th shift register; The third clock signal line is electrically connected to the third clock signal terminal of the i-th shift register, the second clock signal terminal of the i+1-th shift register, and the first clock signal terminal of the i+2-th shift register; The fourth clock signal line is electrically connected to the third clock signal terminal of the i+1th shift register, the second clock signal terminal of the i+2th shift register, and the first clock signal terminal of the i+3th shift register; i is a positive integer.

17. The gate driving circuit according to claim 1, characterized in that: Also includes a first clock signal line and a second clock signal line; The first clock signal line is electrically connected to the first clock signal terminal of the i-th shift register and the second clock signal terminal of the (i+1)-th shift register; The second clock signal line is electrically connected to the second clock signal terminal of the i-th shift register and the first clock signal terminal of the i+1-th shift register; i is a positive integer.

18. A display panel, characterized in that: The gate drive circuit comprises the gate drive circuit as described in any one of claims 1 to 17.

19. A display device, characterized in that: Comprising the display panel as claimed in claim 18.

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