Logic gate circuit based on black phosphorus ferroelectric field effect transistor

Abstract

The invention discloses a logic gate circuit based on black phosphorus ferroelectric field effect transistors, relates to the technical field of logic gate circuits, and utilizes the black phosphorus ferroelectric field effect transistors to form various fixed logic gate circuits and adjustable logic gate circuits. The first fixed logic application and the first variable logic application of the black phosphorus ferroelectric field effect transistor are achieved, compared with the prior art, the black phosphorus ferroelectric field effect transistor is applied to the fixed logic gate circuit and the adjustable logic gate circuit, and due to the fact that the black phosphorus ferroelectric field effect transistor has a better switching current ratio, the switching current ratio of the black phosphorus ferroelectric field effect transistor is improved. Therefore, the switching rate can be improved, and the delay of the logic gate is improved.

Description

Technical Field

[0001] The present application relates to the technical field of logic gate circuits, and in particular to a logic gate circuit based on a black phosphorus iron electric field effect transistor. Background Art

[0002] Black phosphorus (BP) ferroelectric field effect transistor has a very high switching current ratio and has obvious ferroelectric characteristics at 200K (200K is lower than the Curie temperature of black phosphorus ferroelectric field effect transistor). When a low-frequency scanning voltage is applied to the gate of the black phosphorus ferroelectric field effect transistor, when the source-drain voltage (the voltage across the drain and source) is constant, the output current presents a butterfly hysteresis curve. This is because the large-scale low-frequency scanning voltage significantly changes the polarization of the ferroelectric material. When resetting, a voltage exceeding a certain value (coercive voltage) needs to be applied to the gate to restore the polarization direction and completely close the channel. From the experimental results, when the gate-drain voltage is negative, the black phosphorus ferroelectric field effect transistor is turned on and the overall device appears to be a P-type device. When the frequency of the scanning voltage applied to the gate increases, the polarization of the ferroelectric material attenuates. At this time, the degree of opening of the channel is positively correlated with the polarization strength. When the gate voltage returns to zero, a source-drain voltage V is applied between the source and the drain. ds (about 1V), source-drain current I ds The size of can directly reflect the frequency of the scanning voltage. Conversely, it can be understood that: the gate is loaded with a scanning voltage of a certain frequency (lower frequency, larger amplitude) to adjust the size of the channel resistance. After the layout design of the black phosphorus iron electric field effect transistor is applied to the actual tape-out, two adjacent black phosphorus iron electric field effect transistors have the most similar electrical characteristics. This adjustable resistor can form a good impedance match with the black phosphorus iron electric field effect transistor.

[0003] Compared with traditional MOS devices (Metal-Oxide-Semiconductor Field-Effect-Transistor, metal oxide synthetic semiconductor field effect transistor), the switching current ratio of black phosphorus iron electric field effect transistor has been greatly improved, which provides the most solid guarantee for the overall anti-interference performance of digital circuits. In analog circuits, a high switching current ratio often means a steep device on / off curve, which brings high gain in the equivalent small signal model, which shows that black phosphorus iron electric field effect transistor has broad prospects and deep potential in analog circuit design.

[0004] However, currently most logic gate circuits are constructed based on MOS devices, and the delay of the logic gate is long. Summary of the invention

[0005] The purpose of the present application is to provide a logic gate circuit based on black phosphorus iron electric field effect transistor, which improves the delay of the logic gate.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOT gate, and the NOT gate includes: a black phosphorus iron electric field effect transistor and a pull-down resistor;

[0008] The source of the black phosphorus iron electric field effect transistor is connected to a power supply, the drain of the black phosphorus iron electric field effect transistor is connected to a first end of a pull-down resistor, and a second end of the pull-down resistor is grounded;

[0009] Among them, the gate of the black phosphorus iron field effect transistor is the input end, and the connection end between the drain of the black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output end. The input end is used to receive an input signal, and the output end is used to output an output signal obtained after performing a negation operation on the input signal.

[0010] In a second aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOR gate, and the NOR gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor and a pull-down resistor;

[0011] The source of the first black phosphorus iron electric field effect transistor and the source of the second black phosphorus iron electric field effect transistor are both connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor and the drain of the second black phosphorus iron electric field effect transistor are both connected to a first end of a pull-down resistor, and a second end of the pull-down resistor is grounded;

[0012] Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the first black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an OR operation on the first input signal and the second input signal.

[0013] In a third aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NAND gate, and the NAND gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor and a pull-down resistor;

[0014] The source of the first black phosphorus iron electric field effect transistor is connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor is connected to the source of the second black phosphorus iron electric field effect transistor, the drain of the second black phosphorus iron electric field effect transistor is connected to the first end of the pull-down resistor, and the second end of the pull-down resistor is grounded;

[0015] Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the second black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an AND-NOT operation on the first input signal and the second input signal.

[0016] In a fourth aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input AND gate, and the two-input AND gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a first pull-down resistor, and a second pull-down resistor;

[0017] The source of the first black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor are both connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor is connected to the source of the second black phosphorus iron electric field effect transistor, the drain of the second black phosphorus iron electric field effect transistor is respectively connected to the gate of the third black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the third black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded;

[0018] Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the third black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an AND operation on the first input signal and the second input signal.

[0019] In a fifth aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input OR gate, and the two-input OR gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a first pull-down resistor, and a second pull-down resistor;

[0020] The source of the first black phosphorus iron electric field effect transistor, the source of the second black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor are all connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor and the drain of the second black phosphorus iron electric field effect transistor are respectively connected to the gate of the third black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the third black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded;

[0021] Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the third black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an OR operation on the first input signal and the second input signal.

[0022] In a sixth aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input AND gate, and the multi-input AND gate includes a plurality of cascaded two-input AND gates;

[0023] The first input end of the first two-input AND gate is connected to the first input signal, the second input end of the first two-input AND gate is connected to the second input signal, the first input end of the i-th two-input AND gate is connected to the i+1-th input signal, the second input end of the i-th two-input AND gate is connected to the output end of the i-1-th two-input AND gate, and the output end of the I-th two-input AND gate is the output end of the multi-input AND gate; wherein i=2, 3, ..., I, I is the total number of two-input AND gates, and the output end of the multi-input AND gate is used to output an output signal obtained after performing an AND operation on I+1 input signals;

[0024] Alternatively, the first input of the first two-input AND gate is connected to the first input signal, the second input of the first two-input AND gate is connected to the second input signal, the first input of the i-th two-input AND gate is connected to the output of the i-1-th two-input AND gate, the second input of the i-th two-input AND gate is connected to the i+1-th input signal, and the output of the I-th two-input AND gate is the output of the multi-input AND gate; wherein i=2, 3, ..., I, I is the total number of two-input AND gates, and the output of the multi-input AND gate is used to output the output signal obtained after performing an AND operation on I+1 input signals.

[0025] In a seventh aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes a plurality of cascaded two-input OR gates;

[0026] The first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the i+1-th input signal, the second input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein i=2, 3, ..., I, I is the total number of the two-input OR gates, and the output end of the multi-input OR gate is used to output an output signal obtained after performing an OR operation on the I+1 input signals;

[0027] Alternatively, the first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, the second input end of the i-th two-input OR gate is connected to the i+1-th input signal, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein i=2, 3, ..., I, I is the total number of two-input OR gates, and the output end of the multi-input OR gate is used to output the output signal obtained after performing an OR operation on I+1 input signals.

[0028] In an eighth aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes J black phosphorus iron electric field effect transistors, a first pull-down resistor, and a second pull-down resistor;

[0029] The sources of the J black phosphorus iron electric field effect transistors are all connected to a power supply, the drain of the jth black phosphorus iron electric field effect transistor is respectively connected to the gate of the Jth black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the Jth black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded;

[0030] Among them, j=1, 2, ..., J-1; the gate of the j-th black phosphorus iron field effect transistor is the j-th input terminal, the connection terminal between the drain of the J-th black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the j-th input terminal is used to receive the j-th input signal, and the output terminal is used to output the output signal obtained after performing an OR operation on the J-1 input signals.

[0031] In a ninth aspect, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is an adjustable logic gate, and the adjustable logic gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a fourth black phosphorus iron electric field effect transistor, and a fifth black phosphorus iron electric field effect transistor;

[0032] The drain of the first black phosphorus iron electric field effect transistor is connected to a negative power supply, the source of the first black phosphorus iron electric field effect transistor is respectively connected to the drain of the second black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor, the source of the second black phosphorus iron electric field effect transistor is connected to a positive power supply, the drain of the third black phosphorus iron electric field effect transistor is respectively connected to the source of the fourth black phosphorus iron electric field effect transistor and the drain of the fifth black phosphorus iron electric field effect transistor, the drain of the fourth black phosphorus iron electric field effect transistor is connected to a negative power supply, and the source of the fifth black phosphorus iron electric field effect transistor is connected to a positive power supply; wherein, the connection end of the drain of the third black phosphorus iron electric field effect transistor and the source of the fourth black phosphorus iron electric field effect transistor is an output end;

[0033] When the adjustable logic gate is a NOT gate, the gate of the first black phosphorus iron electric field effect transistor and the gate of the third black phosphorus iron electric field effect transistor are both connected to a first reverse bias, the gate of the second black phosphorus iron electric field effect transistor is an input terminal, and the gate of the fourth black phosphorus iron electric field effect transistor and the gate of the fifth black phosphorus iron electric field effect transistor are both connected to a forward bias; wherein the input terminal is used to receive an input signal, and when the input terminal receives the input signal, the gate of the third black phosphorus iron electric field effect transistor is connected to a second reverse bias, and the output terminal is used to output an output signal obtained after performing a NOT operation on the input signal;

[0034] When the adjustable logic gate is an NOR gate, the gates of the first black phosphorus iron electric field effect transistor, the gates of the third black phosphorus iron electric field effect transistor and the gates of the fourth black phosphorus iron electric field effect transistor are all connected to a first reverse bias voltage, the gate of the second black phosphorus iron electric field effect transistor is a first input terminal, and the gate of the fifth black phosphorus iron electric field effect transistor is a second input terminal; wherein the first input terminal is used to receive a first input signal, and the second input terminal is used to receive a second input signal, when the first input terminal receives the first input signal and the second input terminal receives the second input signal, the gate of the third black phosphorus iron electric field effect transistor is connected to the second reverse bias voltage, and the output terminal is used to output an output signal obtained after performing an NOR operation on the first input signal and the second input signal;

[0035] When the adjustable logic gate is a NAND gate, the gate of the first black phosphorus iron electric field effect transistor and the gate of the fifth black phosphorus iron electric field effect transistor are both connected to a forward bias, the gate of the second black phosphorus iron electric field effect transistor is a first input terminal, the gate of the third black phosphorus iron electric field effect transistor is a second input terminal, and the gate of the fourth black phosphorus iron electric field effect transistor is connected to a first reverse bias; wherein the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing a NAND operation on the first input signal and the second input signal.

[0036] In a tenth aspect, the present application provides a logic gate circuit based on a black phosphorus iron field effect transistor, wherein the logic gate circuit based on a black phosphorus iron field effect transistor comprises: a plurality of cascade-connected controllable logic gates.

[0037] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0038] The present application provides a logic gate circuit based on black phosphorus iron electric field effect transistors. Black phosphorus iron electric field effect transistors are used to build logic gate circuits. By taking advantage of the high switching current ratio of black phosphorus iron electric field effect transistors, the switching rate can be increased, thereby improving the delay of the logic gate, solving the problem of long delay in existing logic gate circuits built based on MOS devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 This is a schematic diagram of the structure of the black phosphorus iron electric field effect transistor provided in this application.

[0041] Figure 2 This is a schematic diagram of the circuit structure of the NOT gate provided in this application.

[0042] Figure 3 This is a schematic diagram of the circuit structure of the NOR gate provided in this application.

[0043] Figure 4 This is a schematic diagram of the circuit structure of the NAND gate provided in this application.

[0044] Figure 5 This is a schematic diagram of the relationship between source-drain voltage and source-drain current under different resistance values ​​provided in this application.

[0045] Figure 6 This is a schematic diagram of the circuit structure of a two-input AND gate provided in this application.

[0046] Figure 7 This is a schematic diagram of the circuit structure of a two-input OR gate provided in this application.

[0047] Figure 8 This is a schematic diagram of the circuit structure of a three-input AND gate provided in this application.

[0048] Fig. 9 This is a schematic diagram of the circuit structure of a three-input OR gate provided in this application.

[0049] Fig.10 A schematic diagram of the circuit structure of the adjustable logic gate provided in this application.

[0050] Fig.11 A schematic diagram of the relationship between source-drain voltage and source-drain current under forward polarization, non-polarization and reverse polarization provided in this application.

[0051] Fig.12 This is a schematic diagram of the equivalent circuit of the NOT gate provided in this application.

[0052] Fig.13 This is a schematic diagram of the equivalent circuit of the NOR gate provided in this application.

[0053] Fig.14 This is a schematic diagram of an equivalent circuit of a NAND gate provided in this application.

[0054] Figure numerals: 1 - device substrate; 2 - metal antenna; 3 - black phosphorus material layer; 4 - two-dimensional ferroelectric material layer; 5 - gate metal contact layer. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] The present application utilizes black phosphorus iron field effect transistors to form logic gate circuits, which can form fixed logic gate circuits as well as adjustable logic gate circuits, thereby expanding the application of black phosphorus iron field effect transistors to fixed or adjustable logic gates, and utilizing the advantage of a high switching current ratio of black phosphorus iron field effect transistors to increase the switching rate of logic gates and improve the delay of logic gates.

[0057] like Figure 1As shown, the black phosphorus ferroelectric field effect transistor includes a device substrate 1, two metal antennas 2, a black phosphorus material layer 3, a two-dimensional ferroelectric material layer 4 and a gate metal contact layer 5. The two-dimensional ferroelectric material layer 4 is located on the device substrate 1 and is in contact with the device substrate 1. Both metal antennas 2 are located on the two-dimensional ferroelectric material layer 4, partly in contact with the two-dimensional ferroelectric material layer 4, and partly in contact with the device substrate 1. Both metal antennas 2 are used to receive electromagnetic waves, one of the metal antennas 2 serves as the source of the black phosphorus ferroelectric field effect transistor, and the other metal antenna 2 serves as the drain of the black phosphorus ferroelectric field effect transistor. The black phosphorus material layer 3 is located on the two metal antennas 2, partly in contact with the two metal antennas 2, and partly in contact with the two-dimensional ferroelectric material layer 4. The gate metal contact layer 5 is located on the black phosphorus material layer 3, partly in contact with the black phosphorus material layer 3, and partly in contact with the device substrate 1. The gate metal contact layer 5 serves as the gate of the black phosphorus ferroelectric field effect transistor.

[0058] The present application does not change the structure of the black phosphorus iron electric field effect transistor, but directly uses the black phosphorus iron electric field effect transistor to form a logic gate circuit. The logic gate logic formed by the prior art is completely fixed and unchanged. The AND gate array realizes AND logic, the OR gate array realizes OR logic, and the NOT gate array realizes NOT logic. The present application uses the black phosphorus iron electric field effect transistor to form various fixed logic gate circuits and adjustable logic gate circuits, realizing the first fixed logic application and the first variable logic application of the black phosphorus iron electric field effect transistor. Compared with the prior art, the fixed logic gate circuit and the adjustable logic gate circuit are applied The new black phosphorus iron electric field effect transistor has a better switching current ratio, so it can increase the switching rate and improve the delay of the logic gate. The adjustable logic gate circuit saves wiring resources for large-scale logic interconnection. The function of each module (i.e., the adjustable logic gate circuit) can be changed multiple times, making the logic of the device connection closer to the logic of natural language. Compared with the existing FPGA layout with separate AND gate and OR gate arrays, each module in the array composed of this module can be used as an AND gate / OR gate / NOT gate, creating a more convenient, fast and diverse logic combination mode.

[0059] In one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOT gate, such as Figure 2 As shown, the NOT gate includes: a black phosphorus iron electric field effect transistor BP1 and a pull-down resistor R down The source of the black phosphorus iron field effect transistor BP1 is connected to the power supply VCC, and the drain of the black phosphorus iron field effect transistor BP1 is connected to the pull-down resistor R down The first end of the pull-down resistor R down The second end is grounded.

[0060] The gate of the black phosphorus iron field effect transistor BP1 is the input terminal, and the drain of the black phosphorus iron field effect transistor BP1 is connected to the pull-down resistor R down The first end of the connection end is the output end, and the input end is used to receive the input signal V in , the output terminal is used to output the input signal V in The output signal V obtained after the NOT operation out .

[0061] Figure 2 The NOT gate shown consists of a black phosphorus iron electric field effect transistor BP1 and a pull-down resistor R down When the input signal V in When the potential is close to the power supply VCC, the black phosphorus iron field effect transistor BP1 is in a high resistance (off) state and the output signal V out Pull-down resistor R down Pulled close to ground potential, equivalent to the input signal V in When it is high level 0, the output signal V out is low level 1. On the contrary, when the input signal V in When the potential is not close to the power supply VCC, the black phosphorus iron field effect transistor BP1 is in a low resistance (on) state and the output signal V out Close to the power supply VCC potential, equivalent to the input signal V in When it is low level 1, the output signal V out It is high level 0, achieving the logical effect of a NOT gate.

[0062] The present application can distinguish between similar and dissimilar by defining a preset difference value. in If the difference between the potential of the power supply VCC is less than the preset difference, it is close; otherwise, it is not close. The preset difference is 10% of the difference between the highest potential of the whole circuit and the lowest potential of the whole circuit. Figure 2 For the NOT gate shown, the default differential is 10% VCC.

[0063] In one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOR gate, such as Figure 3 As shown, the NOR gate includes: a first black phosphorus iron field effect transistor BP1, a second black phosphorus iron field effect transistor BP2 and a pull-down resistor R down The source of the first black phosphorus iron field effect transistor BP1 and the source of the second black phosphorus iron field effect transistor BP2 are both connected to the power supply VCC, and the drain of the first black phosphorus iron field effect transistor BP1 and the drain of the second black phosphorus iron field effect transistor BP2 are both connected to the pull-down resistor R down The first end of the pull-down resistor R down The second end is grounded.

[0064] The gate of the first black phosphorus iron field effect transistor BP1 is the first input terminal, the gate of the second black phosphorus iron field effect transistor BP2 is the second input terminal, and the drain of the first black phosphorus iron field effect transistor BP1 is connected to the pull-down resistor R down The first terminal of the connection end is the output terminal, and the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after the OR operation out .

[0065] Figure 3 The NOR gate shown is composed of two black phosphorus iron electric field effect transistors connected in parallel, and then a pull-down resistor R in series. down When the first input signal V of the first black phosphorus iron field effect transistor BP1 is in1 or the second input signal V of the second black phosphorus iron field effect transistor BP2 in2 When the potential of the power supply VCC is not close, the resistance of the first black phosphorus iron field effect transistor BP1 and the second black phosphorus iron field effect transistor BP2 in parallel (ie, V out The equivalent resistance above the end) is much smaller than the pull-down resistor R down The output signal V out Close to the power supply VCC potential, equivalent to the first input signal V in1 Or the second input signal V in2 When it is low level 1, the output signal V out is high level 0, when the first input signal V in1 and the second input signal V of the second black phosphorus iron field effect transistor BP2 in2 When the potential of the first black phosphorus iron field effect transistor BP1 and the second black phosphorus iron field effect transistor BP2 are close to the potential of the power supply VCC, the resistance value (ie, V out The equivalent resistance above the end) is much larger than the pull-down resistor R down The output signal V out Pull-down resistor R down Pulled close to ground potential, equivalent to the first input signal V in1 and the second input signal V in2 When both are high level 0, the output signal V out It is low level 1, achieving the logical effect of an NOR gate.

[0066] In one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a NAND gate, such as Figure 4 As shown, the NAND gate includes: a first black phosphorus iron field effect transistor BP1, a second black phosphorus iron field effect transistor BP2 and a pull-down resistor R down The source of the first black phosphorus iron field effect transistor BP1 is connected to the power supply VCC, the drain of the first black phosphorus iron field effect transistor BP1 is connected to the source of the second black phosphorus iron field effect transistor BP2, and the drain of the second black phosphorus iron field effect transistor BP2 is connected to the pull-down resistor R down The first end of the pull-down resistor R down The second end is grounded.

[0067] The gate of the first black phosphorus iron field effect transistor BP1 is the first input terminal, the gate of the second black phosphorus iron field effect transistor BP2 is the second input terminal, and the drain of the second black phosphorus iron field effect transistor BP2 is connected to the pull-down resistor R down The first terminal of the connection end is the output terminal, and the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after the AND-NOT operation out .

[0068] Figure 4 The NAND gate shown is composed of two black phosphorus iron electric field effect transistors connected in series, and then a pull-down resistor R is connected in series. down When the first input signal V of the first black phosphorus iron field effect transistor BP1 is in1 and the second input signal V of the second black phosphorus iron field effect transistor BP2 in2 When the potential of the first black phosphorus iron field effect transistor BP1 and the second black phosphorus iron field effect transistor BP2 are not close to the power supply VCC, the resistance value (ie, V out The equivalent resistance above the end) is much smaller than the pull-down resistor R down The output signal V out Close to the power supply VCC potential, equivalent to the first input signal V in1 and the second input signal V in2 When both are low level 1, the output signal V out is high level 0, when the first input signal V in1 or the second input signal V of the second black phosphorus iron field effect transistor BP2 in2When the potential of the power supply VCC is close to the potential of the power supply VCC, the resistance of the first black phosphorus iron field effect transistor BP1 and the second black phosphorus iron field effect transistor BP2 in parallel (ie, V out The equivalent resistance above the end) is much larger than the pull-down resistor R down The output signal V out Pull-down resistor R down Pulled close to ground potential, equivalent to the first input signal V in1 Or the second input signal V in2 When it is high level 0, the output signal V out It is low level 1, achieving the logical effect of NAND gate.

[0069] The present application uses a pull-down resistor and a black phosphorus iron electric field effect transistor coupling circuit architecture to build a logic gate. The large switching current ratio means that under the same bias voltage, the black phosphorus iron electric field effect transistor can reflect a large switching resistance ratio. For a fixed pull-down resistor, a 100-fold resistance change in the black phosphorus iron electric field effect transistor in series with it can reduce its voltage division from 10:1 to 1:10, satisfying the low level less than 1:9 (10% VCC) and the high level greater than 9:1 (90% VCC). It is known that the switching characteristic curve of the black phosphorus iron electric field effect transistor has a second-order derivative with opposite poles, which is a prerequisite for ensuring that the logic can return to correctness after large-scale device cascading. The large switching current ratio ensures the fault tolerance space of the pull-down resistor resistance value and improves the robustness of the logic gate built based on the black phosphorus iron electric field effect transistor. The pull-down resistor selection in the logic gate must meet the following conditions: the output logic "1" level is lower than 10% VCC, and the logic "0" level is higher than 90% VCC. Specifically, a low level is used to represent logic "1". The low level uses logic "1" because the black phosphorus iron electric field effect transistor is a P-type device. When the gate voltage (gate-source voltage) is low (the gate potential is lower than the source potential by a turn-on voltage Vth), the black phosphorus iron electric field effect transistor is turned on. Figure 5 As shown, it is the source-drain voltage V ds and source-drain current I ds relationship.

[0070] For the NOT gate structure, which consists of a black phosphorus iron field effect transistor and a pull-down resistor, the resistance of the pull-down resistor should be less than 1 / 9 times the off-channel resistance (i.e., the equivalent resistance when the black phosphorus iron field effect transistor is turned off) and greater than 9 times the on-channel resistance (i.e., the equivalent resistance when the black phosphorus iron field effect transistor is turned on). The switching current ratio only needs to be greater than 9×9=81.

[0071] For the NAND gate structure, it is composed of two black phosphorus iron field effect transistors connected in series and then a pull-down resistor in series. When any input terminal is logic "0", that is, when the channel of one black phosphorus iron field effect transistor is in a closed state, the output signal at the output terminal should be close to the ground potential (less than 10% VCC), so the resistance of the pull-down resistor needs to be less than 1 / 9 times the single closed channel resistance; when both input terminals are logic "1", that is, when the channels of the two black phosphorus iron field effect transistors are in an open state, the output signal at the output terminal should be close to the VCC potential (greater than 90% VCC), so the resistance of the pull-down resistor needs to be greater than 9×2 times the single open channel resistance. The resistance greater than 9 times is to ensure that the pull-down resistor reaches a voltage division of 90% VCC to ensure the correctness of the output logic. The resistance of 2 times is because the two black phosphorus iron field effect transistors are connected in series, and the resistance is twice the single open channel resistance.

[0072] For the NOR gate structure, it consists of two black phosphorus iron electric field effect transistors connected in parallel and then a pull-down resistor in series. When logic "1" is loaded on any input terminal, the output terminal is pulled up and outputs logic "0". The pull-down resistor needs to be less than 1 / 18 times the single closed channel resistance and greater than 9 / 2 times the single open channel resistance. Similarly, the magnitude of the switch current ratio is much greater than the magnitude of 18×2 / 9=91, and the pull-down resistor has a wide range of choices.

[0073] According to the gate voltage scanning data of the black phosphorus iron field effect transistor at room temperature, when the gate voltage changes from 0 to -5V, the channel resistance of the black phosphorus iron field effect transistor changes by four orders of magnitude, which is much larger than the order of magnitude of 2×9×9=162, so there is a wide range of choices when selecting the pull-down resistor. There is a cascade relationship between gates. When the master gate controls the slave gate, the output of the master gate will add the VCC potential or ground potential to the input end (gate) of the slave gate, so it is most convenient to cascade when the source-drain voltage is equal to the gate voltage. Therefore, VCC=5V can be taken.

[0074] In a circuit, any combinational logic can be described using the above three logic gates (NOT gate, NOR gate and NAND gate), so the present application further uses the above three logic gates to form a combinational logic gate. The present application has demonstrated the reliability and convenience of circuit cascading in the principle part. If you want to implement AND gates and OR gates, you can achieve it by cascading NAND gates and NOT gates, as well as cascading NOR gates and NOT gates.

[0075] In one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input AND gate, such as Figure 6 As shown, it is Figure 4 The NAND gate and Figure 2The NOT gate cascade is shown, and the two-input AND gate includes: a first black phosphorus iron electric field effect transistor BP1, a second black phosphorus iron electric field effect transistor BP2, a third black phosphorus iron electric field effect transistor BP3, a first pull-down resistor R down1 and the second pull-down resistor R down2 The source of the first black phosphorus iron field effect transistor BP1 and the source of the third black phosphorus iron field effect transistor BP3 are both connected to the power supply VCC, the drain of the first black phosphorus iron field effect transistor BP1 is connected to the source of the second black phosphorus iron field effect transistor BP2, and the drain of the second black phosphorus iron field effect transistor BP2 is respectively connected to the gate of the third black phosphorus iron field effect transistor BP3 and the first pull-down resistor R down1 The drain of the third black phosphorus iron field effect transistor BP3 is connected to the second pull-down resistor R down2 The first end of the first pull-down resistor R down1 The second end and the second pull-down resistor R down2 The second ends of are grounded.

[0076] The gate of the first black phosphorus iron field effect transistor BP1 is the first input terminal, the gate of the second black phosphorus iron field effect transistor BP2 is the second input terminal, and the drain of the third black phosphorus iron field effect transistor BP3 is connected to the second pull-down resistor R down2 The first terminal of the connection end is the output terminal, and the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after AND operation out .

[0077] In one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input OR gate, such as Figure 7 As shown, it is Figure 3 The NOR gate and Figure 2 The NOT gate cascade is shown, and the two-input OR gate includes: a first black phosphorus iron electric field effect transistor BP1, a second black phosphorus iron electric field effect transistor BP2, a third black phosphorus iron electric field effect transistor BP3, a first pull-down resistor R down1 and the second pull-down resistor R down2The source of the first black phosphorus iron field effect transistor BP1, the source of the second black phosphorus iron field effect transistor BP2 and the source of the third black phosphorus iron field effect transistor BP3 are all connected to the power supply VCC, and the drain of the first black phosphorus iron field effect transistor BP1 and the drain of the second black phosphorus iron field effect transistor BP2 are respectively connected to the gate of the third black phosphorus iron field effect transistor BP3 and the first pull-down resistor R down1 The drain of the third black phosphorus iron field effect transistor BP3 is connected to the second pull-down resistor R down2 The first end of the first pull-down resistor R down1 The second end and the second pull-down resistor R down2 The second ends of are grounded.

[0078] The gate of the first black phosphorus iron field effect transistor BP1 is the first input terminal, the gate of the second black phosphorus iron field effect transistor BP2 is the second input terminal, and the drain of the third black phosphorus iron field effect transistor BP3 is connected to the second pull-down resistor R down2 The first terminal of the connection end is the output terminal, and the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after OR operation out .

[0079] like Figure 8 As shown in the figure, two two-input AND gates are cascaded to form a three-input AND gate. If it needs to be expanded to an n-input AND gate, just repeat the steps of cascading two two-input AND gates to form a three-input AND gate. Since there is a delay in signal transmission between gates (generally determined by the equivalent parasitic capacitance and equivalent input resistance in a single logic gate), logic changes take time. More cascades mean that the logic value of the main gate (the first-level two-input AND gate) input needs to be maintained for a longer time to ensure the correctness of the combinational logic operation. Therefore, the upper limit of the number of inputs of the multi-input AND gate depends on the clock cycle of the timing circuit that works with it. The specific number n is estimated as follows:

[0080]

[0081] In formula (1), f is the operating frequency of the sequential circuit, R1 and C1 are the equivalent input resistance and equivalent parasitic capacitance of a single two-input AND gate, respectively.

[0082] Based on this, in one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron field effect transistor, wherein the logic gate circuit based on the black phosphorus iron field effect transistor is a multi-input AND gate, and the multi-input AND gate includes multiple cascaded two-input AND gates.

[0083] The first input end of the first two-input AND gate is connected to the first input signal, the second input end of the first two-input AND gate is connected to the second input signal, the first input end of the i-th two-input AND gate is connected to the i+1-th input signal, the second input end of the i-th two-input AND gate is connected to the output end of the i-1-th two-input AND gate, and the output end of the I-th two-input AND gate is the output end of the multi-input AND gate; wherein, i=2, 3, ..., I, I is the total number of two-input AND gates, and the output end of the multi-input AND gate is used to output the output signal obtained after performing an AND operation on I+1 input signals.

[0084] Alternatively, the first input of the first two-input AND gate is connected to the first input signal, the second input of the first two-input AND gate is connected to the second input signal, the first input of the i-th two-input AND gate is connected to the output of the i-1-th two-input AND gate, the second input of the i-th two-input AND gate is connected to the i+1-th input signal, and the output of the I-th two-input AND gate is the output of the multi-input AND gate; wherein i=2, 3, ..., I, I is the total number of two-input AND gates, and the output of the multi-input AND gate is used to output the output signal obtained after performing an AND operation on I+1 input signals.

[0085] There are two ways to construct a multi-input OR gate. The first construction method is consistent with the idea of ​​the multi-input AND gate mentioned above. Multiple two-input OR gates are cascaded, and the output of the master gate is used as one of the inputs of the slave gate. The upper limit of the number of inputs of the multi-input OR gate constructed by this method is consistent with the calculation method of the multi-input AND gate mentioned above. The second construction method is to connect two pull-down resistors R down The black phosphorus iron electric field effect transistors between are changed into multiple ones. This method will cause the maximum channel equivalent resistance and the minimum channel equivalent resistance to decrease in proportion, so the pull-down resistor value needs to be recalculated. The calculation idea is the same as the idea of ​​determining the pull-down resistor value mentioned above. The logic gate delay will in turn limit the operating frequency of the timing circuit that cooperates with it. The main factor that limits its logic number is the current carrying capacity of the pull-down resistor. When the number of black phosphorus iron electric field effect transistors is very large, the parallel resistance of the closed channel will decrease. In order to meet the above output conditions, the pull-down resistor needs to be reduced proportionally. When all channels are turned on, at least 90% of the voltage of VCC = 4.5V is applied to both ends of the pull-down resistor. If the resistance is too small and the current exceeds its safe current, there will be a risk of device burning. At this time, the resistance of the pull-down resistor needs to be less than 1 / 9A of the closed channel resistance and greater than 9 / A of the open channel resistance. A is the number of black phosphorus iron electric field effect transistors in parallel. Fig. 9 As shown, it forms a three-input OR gate.

[0086] Based on this, when the first construction method is adopted, in one embodiment, the present application provides a logic gate circuit based on black phosphorus iron electric field effect transistor, and the logic gate circuit based on black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes multiple cascaded two-input OR gates.

[0087] The first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the i+1-th input signal, the second input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein, i=2, 3, ..., I, I is the total number of two-input OR gates, and the output end of the multi-input OR gate is used to output the output signal obtained after performing an OR operation on the I+1 input signals.

[0088] Alternatively, the first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, the second input end of the i-th two-input OR gate is connected to the i+1-th input signal, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein i=2, 3, ..., I, I is the total number of two-input OR gates, and the output end of the multi-input OR gate is used to output the output signal obtained after performing an OR operation on I+1 input signals.

[0089] When the second construction method is adopted, in one embodiment, the present application provides a logic gate circuit based on a black phosphorus iron electric field effect transistor, wherein the logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes J black phosphorus iron electric field effect transistors, a first pull-down resistor, and a second pull-down resistor. The sources of the J black phosphorus iron electric field effect transistors are all connected to a power supply, the drain of the jth black phosphorus iron electric field effect transistor is respectively connected to the gate of the Jth black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the Jth black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded.

[0090] Wherein, j=1, 2, ..., J-1; the gate of the j-th black phosphorus iron field effect transistor is the j-th input terminal, the connection terminal between the drain of the J-th black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the j-th input terminal is used to receive the j-th input signal, and the output terminal is used to output the output signal obtained after performing an OR operation on the J-1 input signals. At this time, the resistance value of the first pull-down resistor needs to be less than 1 / 9 (J-1) of the closed channel resistance value and greater than 9 / (J-1) of the open channel resistance value.

[0091] A multi-input gate can AND or OR multiple input logic values ​​to obtain the result.

[0092] In one embodiment, the present application provides a logic gate circuit based on black phosphorus iron electric field effect transistor, such as Fig.10 As shown, the logic gate circuit based on black phosphorus iron electric field effect transistor is an adjustable logic gate, and the adjustable logic gate includes: a first black phosphorus iron electric field effect transistor BP1, a second black phosphorus iron electric field effect transistor BP2, a third black phosphorus iron electric field effect transistor BP3, a fourth black phosphorus iron electric field effect transistor BP4 and a fifth black phosphorus iron electric field effect transistor BP5. The drain of the first black phosphorus iron field effect transistor BP1 is connected to the negative power supply -VCC, the source of the first black phosphorus iron field effect transistor BP1 is respectively connected to the drain of the second black phosphorus iron field effect transistor BP2 and the source of the third black phosphorus iron field effect transistor BP3, the source of the second black phosphorus iron field effect transistor BP2 is connected to the positive power supply VCC, the drain of the third black phosphorus iron field effect transistor BP3 is respectively connected to the source of the fourth black phosphorus iron field effect transistor BP4 and the drain of the fifth black phosphorus iron field effect transistor BP5, the drain of the fourth black phosphorus iron field effect transistor BP4 is connected to the negative power supply -VCC, and the source of the fifth black phosphorus iron field effect transistor BP5 is connected to the positive power supply VCC. Among them, the connection end of the drain of the third black phosphorus iron field effect transistor BP3 and the source of the fourth black phosphorus iron field effect transistor BP4 is the output end.

[0093] Fig.10 The controllable logic gate shown is composed of five identical black phosphorus iron field effect transistors. Since the current of the forward polarized and reverse polarized gates at the same source-drain voltage differs by about two orders of magnitude, it can be assumed that when no gate bias is applied, the channel resistance of the forward polarized channel is R↑, and the channel resistance of the reverse polarized channel is R↓, R↓≈100R↑, as shown in Fig.11 As shown, Fig.11Fresh in the figure represents the curve when there is no polarization, P up represents the curve when there is forward polarization, and P down represents the curve when there is reverse polarization. The VCC level represents the logic "0", and the -VCC level represents the logic "1". This ensures that the switching current ratio is greater than four orders of magnitude, while the digital signal loaded on the gate has the least effect on the change of ferroelectric polarization. The gate of each black phosphorus iron field effect transistor can be loaded with a large negative bias (i.e. -VCC) to form a forward polarization state and be used as a resistor. While being forward polarized, a small negative bias (generally -1 / 2VCC) is loaded on the gate to further reduce the channel resistance. At this time, the black phosphorus iron field effect transistor can be regarded as a conductor. A large forward bias (i.e. VCC) is loaded on the gate of the black phosphorus iron field effect transistor to form a reverse polarization state. The channel resistance of the black phosphorus iron field effect transistor will be about two orders of magnitude higher than all other cases, and can be regarded as an open circuit. When a large forward bias and a large negative bias are not loaded, it is used as a device.

[0094] Based on this, the present application can convert the above adjustable logic gate into a NOT gate, a NOR gate and a NAND gate, and the specific implementation method is as follows:

[0095] (1) When the controllable logic gate is a NOT gate, through the above control scheme, BP4 and BP5 are set as open circuits, BP3 is set as a wire, BP2 is set as a device, and BP1 is set as a resistor to form a NOT gate. The equivalent circuit is as follows: Fig.12 As shown, at this time, the gate of the first black phosphorus iron field effect transistor BP1 and the gate of the third black phosphorus iron field effect transistor BP3 are both connected to the first reverse bias voltage (i.e. -VCC), the gate of the second black phosphorus iron field effect transistor BP2 is the input terminal, and the gate of the fourth black phosphorus iron field effect transistor BP4 and the gate of the fifth black phosphorus iron field effect transistor BP5 are both connected to the forward bias voltage (i.e. VCC). Among them, the input terminal is used to receive the input signal V in , when the input terminal receives the input signal V in When the gate of the third black phosphorus iron field effect transistor BP3 is connected to the second reverse bias voltage (ie -1 / 2VCC), the output terminal is used to output the input signal V in The output signal V obtained after the NOT operation out .

[0096] (2) When the controllable logic gate is a NOR gate, through the above control scheme, BP1 and BP4 are set as resistors, BP3 is set as a wire, and BP2 and BP5 are set as devices to form a NOR gate. The equivalent circuit is as follows: Fig.13As shown, at this time, the gate of the first black phosphorus iron field effect transistor BP1, the gate of the third black phosphorus iron field effect transistor BP3 and the gate of the fourth black phosphorus iron field effect transistor BP4 are all connected to the first reverse bias, the gate of the second black phosphorus iron field effect transistor BP2 is the first input terminal, and the gate of the fifth black phosphorus iron field effect transistor BP5 is the second input terminal. Among them, the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , when the first input terminal receives the first input signal V in1 And the second input terminal receives the second input signal V in2 When the gate of the third black phosphorus iron field effect transistor BP3 is connected to the second reverse bias voltage, the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after the OR operation out .

[0097] (3) When the controllable logic gate is a NAND gate, through the above control scheme, BP1 and BP5 are set as open circuits, BP4 is set as a resistor, and BP2 and BP3 are set as devices to form a NAND gate. The equivalent circuit is as follows: Fig.14 As shown, at this time, the gate of the first black phosphorus iron field effect transistor BP1 and the gate of the fifth black phosphorus iron field effect transistor BP5 are both connected to the forward bias, the gate of the second black phosphorus iron field effect transistor BP2 is the first input terminal, the gate of the third black phosphorus iron field effect transistor BP3 is the second input terminal, and the gate of the fourth black phosphorus iron field effect transistor BP4 is connected to the first reverse bias. Among them, the first input terminal is used to receive the first input signal V in1 The second input terminal is used to receive the second input signal V in2 , the output terminal is used to output the first input signal V in1 and the second input signal V in2 The output signal V obtained after the AND-NOT operation out .

[0098] In one embodiment, the present application also provides a logic gate circuit based on black phosphorus iron field effect transistors, and the logic gate circuit based on black phosphorus iron field effect transistors includes: a plurality of cascade-connected adjustable logic gates, wherein the cascade connection is such that the output end of the equivalent circuit corresponding to the adjustable logic gate as the main level (previous level) and any one of the input ends of the equivalent circuit corresponding to the adjustable logic gate as the slave level (current level) are connected.

[0099] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0100] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOT gate, and the NOT gate includes: a black phosphorus iron electric field effect transistor and a pull-down resistor; The source of the black phosphorus iron electric field effect transistor is connected to a power supply, the drain of the black phosphorus iron electric field effect transistor is connected to a first end of a pull-down resistor, and a second end of the pull-down resistor is grounded; Among them, the gate of the black phosphorus iron field effect transistor is the input end, and the connection end between the drain of the black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output end. The input end is used to receive an input signal, and the output end is used to output an output signal obtained after performing a negation operation on the input signal.

2. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a NOR gate, and the NOR gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor and a pull-down resistor; The source of the first black phosphorus iron electric field effect transistor and the source of the second black phosphorus iron electric field effect transistor are both connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor and the drain of the second black phosphorus iron electric field effect transistor are both connected to a first end of a pull-down resistor, and a second end of the pull-down resistor is grounded; Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the first black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an OR operation on the first input signal and the second input signal.

3. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a NAND gate, and the NAND gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor and a pull-down resistor; The source of the first black phosphorus iron electric field effect transistor is connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor is connected to the source of the second black phosphorus iron electric field effect transistor, the drain of the second black phosphorus iron electric field effect transistor is connected to the first end of the pull-down resistor, and the second end of the pull-down resistor is grounded; Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the second black phosphorus iron field effect transistor and the first end of the pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an AND-NOT operation on the first input signal and the second input signal.

4. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input AND gate, and the two-input AND gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a first pull-down resistor and a second pull-down resistor; The source of the first black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor are both connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor is connected to the source of the second black phosphorus iron electric field effect transistor, the drain of the second black phosphorus iron electric field effect transistor is respectively connected to the gate of the third black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the third black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded; Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the third black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an AND operation on the first input signal and the second input signal.

5. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a two-input OR gate, and the two-input OR gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a first pull-down resistor and a second pull-down resistor; The source of the first black phosphorus iron electric field effect transistor, the source of the second black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor are all connected to a power supply, the drain of the first black phosphorus iron electric field effect transistor and the drain of the second black phosphorus iron electric field effect transistor are respectively connected to the gate of the third black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the third black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded; Among them, the gate of the first black phosphorus iron field effect transistor is the first input terminal, the gate of the second black phosphorus iron field effect transistor is the second input terminal, the connection terminal between the drain of the third black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing an OR operation on the first input signal and the second input signal.

6. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input AND gate, and the multi-input AND gate includes a plurality of cascaded two-input AND gates, and the two-input AND gate is the logic gate circuit based on the black phosphorus iron electric field effect transistor according to claim 4; The first input end of the first two-input AND gate is connected to the first input signal, the second input end of the first two-input AND gate is connected to the second input signal, the first input end of the i-th two-input AND gate is connected to the i+1-th input signal, the second input end of the i-th two-input AND gate is connected to the output end of the i-1-th two-input AND gate, and the output end of the I-th two-input AND gate is the output end of the multi-input AND gate; wherein i=2, 3, ..., I, I is the total number of two-input AND gates, and the output end of the multi-input AND gate is used to output an output signal obtained after performing an AND operation on I+1 input signals; Alternatively, the first input of the first two-input AND gate is connected to the first input signal, the second input of the first two-input AND gate is connected to the second input signal, the first input of the i-th two-input AND gate is connected to the output of the i-1-th two-input AND gate, the second input of the i-th two-input AND gate is connected to the i+1-th input signal, and the output of the I-th two-input AND gate is the output of the multi-input AND gate; wherein i=2, 3, ..., I, I is the total number of two-input AND gates, and the output of the multi-input AND gate is used to output the output signal obtained after performing an AND operation on I+1 input signals.

7. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes a plurality of cascaded two-input OR gates, and the two-input OR gate is the logic gate circuit based on the black phosphorus iron electric field effect transistor according to claim 5; The first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the i+1-th input signal, the second input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein i=2, 3, ..., I, I is the total number of the two-input OR gates, and the output end of the multi-input OR gate is used to output an output signal obtained after performing an OR operation on the I+1 input signals; Alternatively, the first input end of the first two-input OR gate is connected to the first input signal, the second input end of the first two-input OR gate is connected to the second input signal, the first input end of the i-th two-input OR gate is connected to the output end of the i-1-th two-input OR gate, the second input end of the i-th two-input OR gate is connected to the i+1-th input signal, and the output end of the I-th two-input OR gate is the output end of the multi-input OR gate; wherein i=2, 3, ..., I, I is the total number of two-input OR gates, and the output end of the multi-input OR gate is used to output the output signal obtained after performing an OR operation on I+1 input signals.

8. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is a multi-input OR gate, and the multi-input OR gate includes J black phosphorus iron electric field effect transistors, a first pull-down resistor and a second pull-down resistor; The sources of the J black phosphorus iron electric field effect transistors are all connected to a power supply, the drain of the jth black phosphorus iron electric field effect transistor is respectively connected to the gate of the Jth black phosphorus iron electric field effect transistor and the first end of the first pull-down resistor, the drain of the Jth black phosphorus iron electric field effect transistor is connected to the first end of the second pull-down resistor, and the second end of the first pull-down resistor and the second end of the second pull-down resistor are both grounded; Among them, j=1, 2, ..., J-1; the gate of the j-th black phosphorus iron field effect transistor is the j-th input terminal, the connection terminal between the drain of the J-th black phosphorus iron field effect transistor and the first end of the second pull-down resistor is the output terminal, the j-th input terminal is used to receive the j-th input signal, and the output terminal is used to output the output signal obtained after performing an OR operation on the J-1 input signals.

9. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on the black phosphorus iron electric field effect transistor is an adjustable logic gate, and the adjustable logic gate includes: a first black phosphorus iron electric field effect transistor, a second black phosphorus iron electric field effect transistor, a third black phosphorus iron electric field effect transistor, a fourth black phosphorus iron electric field effect transistor and a fifth black phosphorus iron electric field effect transistor; The drain of the first black phosphorus iron electric field effect transistor is connected to a negative power supply, the source of the first black phosphorus iron electric field effect transistor is respectively connected to the drain of the second black phosphorus iron electric field effect transistor and the source of the third black phosphorus iron electric field effect transistor, the source of the second black phosphorus iron electric field effect transistor is connected to a positive power supply, the drain of the third black phosphorus iron electric field effect transistor is respectively connected to the source of the fourth black phosphorus iron electric field effect transistor and the drain of the fifth black phosphorus iron electric field effect transistor, the drain of the fourth black phosphorus iron electric field effect transistor is connected to a negative power supply, and the source of the fifth black phosphorus iron electric field effect transistor is connected to a positive power supply; wherein, the connection end of the drain of the third black phosphorus iron electric field effect transistor and the source of the fourth black phosphorus iron electric field effect transistor is an output end; When the adjustable logic gate is a NOT gate, the gate of the first black phosphorus iron electric field effect transistor and the gate of the third black phosphorus iron electric field effect transistor are both connected to a first reverse bias, the gate of the second black phosphorus iron electric field effect transistor is an input terminal, and the gate of the fourth black phosphorus iron electric field effect transistor and the gate of the fifth black phosphorus iron electric field effect transistor are both connected to a forward bias; wherein the input terminal is used to receive an input signal, and when the input terminal receives the input signal, the gate of the third black phosphorus iron electric field effect transistor is connected to a second reverse bias, and the output terminal is used to output an output signal obtained after performing a NOT operation on the input signal; When the adjustable logic gate is an NOR gate, the gates of the first black phosphorus iron electric field effect transistor, the gates of the third black phosphorus iron electric field effect transistor and the gates of the fourth black phosphorus iron electric field effect transistor are all connected to a first reverse bias voltage, the gate of the second black phosphorus iron electric field effect transistor is a first input terminal, and the gate of the fifth black phosphorus iron electric field effect transistor is a second input terminal; wherein the first input terminal is used to receive a first input signal, and the second input terminal is used to receive a second input signal, when the first input terminal receives the first input signal and the second input terminal receives the second input signal, the gate of the third black phosphorus iron electric field effect transistor is connected to the second reverse bias voltage, and the output terminal is used to output an output signal obtained after performing an NOR operation on the first input signal and the second input signal; When the adjustable logic gate is a NAND gate, the gate of the first black phosphorus iron electric field effect transistor and the gate of the fifth black phosphorus iron electric field effect transistor are both connected to a forward bias, the gate of the second black phosphorus iron electric field effect transistor is a first input terminal, the gate of the third black phosphorus iron electric field effect transistor is a second input terminal, and the gate of the fourth black phosphorus iron electric field effect transistor is connected to a first reverse bias; wherein the first input terminal is used to receive a first input signal, the second input terminal is used to receive a second input signal, and the output terminal is used to output an output signal obtained after performing a NAND operation on the first input signal and the second input signal.

10. A logic gate circuit based on black phosphorus iron electric field effect transistor, characterized in that: The logic gate circuit based on black phosphorus iron electric field effect transistor includes: a plurality of cascade-connected adjustable logic gates, and the adjustable logic gates are the logic gate circuit based on black phosphorus iron electric field effect transistor according to claim 9.

Images