Digital multi-beam synthesis chip

Abstract

The invention relates to a digital multi-beam forming chip. The digital multi-beam forming chip comprises a receiving multi-beam forming link, a transmitting multi-beam forming link, a daisy chain SerDes high-speed interface and a frequency synthesizer; the receiving multi-beam synthesis link is used for realizing receiving multi-beam synthesis; the transmitting multi-beam forming link is used for realizing transmitting multi-beam forming, and the daisy chain SerDes high-speed interface comprises a beam forming data daisy chain SerDes high-speed interface and a control data daisy chain SerDes high-speed interface; the digital multi-beam forming chip is in serial expansion connection through a daisy chain SerDes interface to realize large-scale array formation; the frequency synthesizer provides a synchronous sampling clock between the digital multi-beam forming chips. By adopting the digital multi-beam synthesis chip, a universal core basic component support can be provided for engineering implementation of large-scale digital phased array multi-beam synthesis.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a digital multi-beam synthesis chip. Background Art

[0002] The ultimate information experience that future communications need to achieve depends on high spectrum efficiency and large-capacity wireless access. Traditional time / frequency / code division multiple access technologies face severe challenges in spectrum efficiency and access capacity. How to reasonably and efficiently allocate system resources under limited frequency band resources has become one of the key issues that need to be solved urgently. Multi-beam antenna technology, which has the advantages of beam space isolation and frequency reuse, has become a key way to resolve these contradictions. Multi-beam technology enables antennas to send and receive signals in multiple directions at the same time, thereby improving the spectrum utilization efficiency and user access capacity of the communication system. The leap in 5G / 6G data rates depends on broadband phased array antennas with multiple beams. Multi-beam phased array antennas significantly improve spectrum utilization efficiency through space division, greatly increasing the number of 5G / 6G user access. In the field of radar detection, multi-beam phased array antennas can improve the detection capability and tracking accuracy of targets, scan the entire airspace in a short time, and realize the simultaneous discovery, positioning and tracking of multiple targets; in addition, multi-beam synthesis technology can give full play to the advantages of modern radars such as multi-function, multi-mode and multi-target detection, and realize the integrated functions of radar reconnaissance, detection, perception, tracking and communication. In the field of satellite communications, in order to solve the problem of insufficient coverage caused by insufficient number of beams, beam hopping technology is usually used, which leads to complex access system, frequent terminal beam hopping, and the need to increase message redundancy to reduce random interruptions of access, which greatly affects the continuity and reliability of communication. At the same time, large LEO and MEO satellite constellations of SpaceX, OneWeb, Telesat, SES, StarNet and other commercial aerospace companies need communication payloads with multi-beam capabilities to ensure efficient terminal access efficiency and massive terminal access capabilities; in addition, ground terminal antennas that track multiple satellites are also required. The multi-beam capability of the terminal makes it possible for the terminal to connect with multiple satellites at the same time and to ensure seamless connectivity when switching beams of high-speed LEO satellites under the condition of full coverage.

[0003] Traditional Sub-6 GHz spectrum resources are severely crowded. The contradiction between the tight spectrum resources and the urgent need for extreme communication has led to the large-scale application of carrier aggregation technology and various high-order modulation methods, but this method will greatly increase the design complexity of the receiver. At the same time, crowded low-frequency wireless applications will also cause mutual interference between spectrums, severely limiting the performance of the receiver. In order to overcome the inherent limitations of low-frequency wireless applications, future high-speed wireless communication frequency resources (especially 5G / 6G and satellite communications) will inevitably evolve to higher frequency bands, especially millimeter wave bands. Multi-beams and large bandwidth have become a typical feature of future communication systems.

[0004] The methods of generating multi-beams include partially connected analog multi-beam synthesis, fully connected analog multi-beam synthesis, digital-analog hybrid multi-beam synthesis and digital multi-beam synthesis. Partially connected analog multi-beam synthesis is to divide the planar phased array antenna array into multiple sub-arrays, each sub-array provides a receive / transmit beam through a combiner / power splitter network, and each sub-array operates independently, so it can provide a multi-beam combination covering different frequencies and spaces, with the significant advantages of simple structure, low power consumption and low cost. However, when the number of beams is large, each sub-array contains a small number of antenna elements, and the synthesized beam is more sensitive to the random mismatch of the T / R components of each channel, and the waveform distortion is serious. At the same time, the small number of elements will also cause the beam angle of the synthesized beam to become larger and the gain to decrease, reducing the beam resolution and coverage. Fully connected analog multi-beam synthesis is achieved by adding parallel T / R components through a power splitter / combiner network on the basis of the active phased array. The multi-beam generation capability of this solution is heavily dependent on the number of T / R components, and the phased array antenna has gone through a development process from a single array to an integrated transceiver, and then to an integrated dual-polarized transceiver. The integration density has also increased to four times the original, so the beam control network and hardware structure are very complex. Furthermore, the fully connected analog multi-beam synthesis requires the parallel multi-channel output function of a multi-stage power divider. Due to the power attenuation characteristics of the power divider, it will seriously affect the G / T value of the receiver and deteriorate the sensitivity of the receiving multi-beam synthesis link. The digital-analog hybrid multi-beam synthesis is based on the collaborative work of analog beam synthesis of the phase shifter and digital beam synthesis in the baseband. The beam synthesis algorithm is complex (the number of matrices has increased), limited by the adjustable degrees of freedom (the matrix may not be full rank), and the synthesis beam pointing resolution is not high. In addition, the above three typical structures all use T / R components. Since the phase shifter used for beam synthesis in the T / R component has obvious nonlinear group delay characteristics in a wide frequency range, there is a serious beam skew effect in broadband communication applications, resulting in a frequency divergence effect in the synthesized beam, which significantly deteriorates the antenna frequency domain flatness. In digital multi-beam synthesis, each receive / transmit antenna array element needs to be connected to a receive / transmit multi-beam synthesis link, and connected to the back-end baseband processing module in the form of parallel digital output / input or Serdes high-speed serial port through A / D and D / A conversion. Digital multi-beam synthesis performs lossless distribution of multi-channel parallel signals in the baseband domain, and can perform large-scale flexible beam synthesis according to demand. At the same time, digital multi-beam synthesis has extremely high-precision true time delay TTD modules and amplitude and phase compensation modules, which can provide high-precision beam synthesis capabilities while supporting large-capacity communications and avoid beam skew. In addition, the core signal processing algorithms of digital beamforming are all performed in the baseband, and the connection structure is simple, which facilitates high-performance calibration functions, such as multi-channel phase mismatch calibration, I / Q mismatch calibration, power amplifier digital pre-distortion, etc., which greatly improves the synthesis quality of multiple beams. At the same time, it has flexible and adaptive interference direction zero-point cancellation function and has strong anti-interference ability.

[0005] The digital multi-beam synthesis solution is currently the most ideal multi-beam synthesis solution. The TTD function in digital beam synthesis can be compatible with all wide / narrowband communications without beam deflection. At the same time, the full array unit can be used for fine beam synthesis. The beam synthesis resolution and scanning resolution can be optimized at the same time. It is the best choice for current high-performance multi-beam synthesis solutions.

[0006] However, when the number of antenna elements is large, the digital multi-beam synthesis solution places strict requirements on the number of baseband component pins or the number of integrated SerDes cores, which is difficult to implement in engineering. Taking 512 elements as an example, the receiver usually adopts a zero intermediate frequency structure with I / Q dual outputs. Assuming that the ADC bit number of the analog-to-digital converter is 12 bits, the back-end baseband processing part must be able to provide up to 12288 pins. Considering the receive / transmit properties, the number of pins must reach 24576, which is basically impossible to achieve. Even if a SerDes high-speed serial port is used, 2048 SerDes modules are required (even if a highly integrated receive / transmit multi-channel integrated chip, such as 4 channels, is used, the number of SerDes required reaches 512), and the system complexity, cost, power consumption and feasibility face very severe challenges. Summary of the invention

[0007] Based on this, it is necessary to provide a digital multi-beam synthesis chip with high performance, high resolution, and high precision multi-beam synthesis capability to address the above technical problems. It is also necessary to provide a digital multi-beam synthesis chip that is highly configurable, highly scalable, highly integrated with multiple channels, and has extremely strong calibration and compensation capabilities to provide general core basic components support for the engineering realization of large-scale digital phased array multi-beam synthesis.

[0008] A digital multi-beam synthesis chip, comprising a digital multi-beam synthesis chip receiving multi-beam synthesis link, a transmitting multi-beam synthesis link, a daisy chain SerDes high-speed interface and a frequency synthesizer;

[0009] The receiving multi-beam synthesis link is used to connect the sub-array antenna unit and the radio frequency receiving link, and send the received signals amplified and down-converted by the sub-array antenna unit and the radio frequency receiving link to multiple orthogonal / co-directional ADCs. Each ADC is output to multiple digital beam synthesis modules after synchronous sampling. The outputs of the multiple digital beam synthesis modules corresponding to each channel are combined and accumulated to obtain multiple receiving beams.

[0010] The daisy chain SerDes high-speed interface is used to perform parallel / serial conversion on the receiving beam and output it to the next-level digital multi-beam synthesis chip or baseband processing module, and receive the beam signal of the previous-level digital multi-beam synthesis chip to perform serial / parallel conversion and accumulate and output with the corresponding receiving beam to realize the daisy chain function of the SerDes interface;

[0011] The transmitting multi-beam synthesis link is used to receive the beam signal from the previous level digital multi-beam synthesis chip or baseband processing module and perform serial / parallel conversion through the deserializer of the daisy chain SerDes high-speed interface. Each parallel branch represents one beam signal, and each beam signal is sent to multiple digital beam synthesis modules respectively. The outputs of the multiple digital beam synthesis modules corresponding to each beam signal and the outputs of the multiple digital beam synthesis modules corresponding to other beams are combined and accumulated respectively. After forming multiple transmit beams, they are sent to the RF transmission link through multiple orthogonal / co-directional ADCs, and are output to the corresponding subarray antenna unit after up-conversion and power amplification of the RF transmission link.

[0012] The frequency synthesizer has an output clock synchronization function to ensure the synchronization of the sampling clock after multi-chip expansion.

[0013] A digital phased array system mismatch calibration method based on a digital multi-beam synthesis chip, the method comprising:

[0014] After the digital multi-beam synthesis chip is serially extended and connected through a daisy chain SerDes interface to form a large-scale digital phased array system, a serial calibration method is used to sequentially compensate for the multi-channel amplitude-phase mismatch in the digital phased array system, including far-field calibration and field calibration, to obtain a compensated time domain response; after configuring the tap coefficients of the equalization filter / pre-equalization filter in the digital multi-beam synthesis chip according to the compensated time domain response, the multi-channel amplitude-phase mismatch is compensated to complete the multi-channel amplitude-phase mismatch calibration;

[0015] After the digital multi-beam synthesis chip is serially extended and connected through the daisy chain SerDes interface to form a large-scale digital phased array system, the orthogonal mismatch of the RF transceiver link itself is far-field calibrated, and then the near-field mutual coupling calibration is performed in the same way as the multi-channel amplitude and phase mismatch calibration to complete the I / Q mismatch calibration; the RF transceiver link includes the RF receiving front end and ADC, the RF transmitting front end and the digital-to-analog converter DAC;

[0016] For each transmitting link in the digital multi-beam synthesis chip, a receiving link is arbitrarily selected as the observation receiving link, and the received signal is fed back to the digital pre-distortion estimation model to estimate the digital pre-distortion parameters of the power amplifier and write them into the non-volatile memory to complete the digital pre-distortion of the power amplifier.

[0017] The digital multi-beam synthesis chip designed in this application adopts the TTD beam synthesis scheme, is compatible with multi-band, large-bandwidth input signals, and has no beam skew effect. It can flexibly adjust the number of array elements involved in beam synthesis, beam width, beam gain, number of generated beams, anti-interference null orientation, etc. according to the corresponding application scenarios, and has agile characteristics. The digital multi-beam synthesis chip integrates multiple high-speed ADC / ADC, a frequency synthesizer with synchronization function, and a daisy-chain SerDes interface to ensure that the chip can achieve the expansion of antenna array elements only through serial connection to meet the beam resolution and beam gain requirements in different application scenarios, realize the serial superposition of multi-beam synthesis data and the configuration of control registers, greatly reduce the complexity of large-scale phased array hardware wiring and the massive access and output pin requirements for baseband signal processing equipment, and has a highly scalable property, providing general core basic components support for the engineering implementation of large-scale digital phased arrays. It also has functions such as single-channel I / Q mismatch calibration, multi-channel amplitude and phase mismatch calibration, and digital pre-distortion of the power amplifier of the transmission link for any receive / transmit link before / after the expansion. Finally, a highly configurable equalization filter / pre-equalization filter is used to ensure the strong robustness of the chip, which greatly alleviates the high-performance requirements of the high-performance phased array system for the receive / transmit link and the baseband signal processing module. This application is highly configurable, highly scalable, highly integrated in multiple channels, and has extremely strong calibration and compensation capabilities, providing general core basic components support for the engineering realization of large-scale digital phased array multi-beam synthesis. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a digital phased array structure based on a digital multi-beam synthesis chip in one embodiment;

[0019] Figure 2 A schematic diagram of multi-beam synthesis of a receiving link of a digital multi-beam synthesis chip in one embodiment;

[0020] Figure 3 A schematic diagram of multi-beam synthesis of a digital multi-beam synthesis chip transmit link in an embodiment;

[0021] Figure 4 A multi-channel amplitude and phase mismatch calibration working mechanism for a receiving link of a digital multi-beam synthesis chip in another embodiment;

[0022] Figure 5 A diagram of a connection method for multi-channel amplitude and phase mismatch calibration of a receiving link of a digital multi-beam synthesis chip in one embodiment;

[0023] Figure 6 A diagram of a working mechanism of multi-channel amplitude and phase mismatch calibration of a digital multi-beam synthesis chip transmit link in one embodiment;

[0024] Figure 7A diagram of a connection method for multi-channel amplitude and phase mismatch calibration of a digital multi-beam synthesis chip transmit link in one embodiment;

[0025] Figure 8 The figure is a calibration process of mutual coupling of antenna elements in one embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0027] In one embodiment, Figure 1 As shown, a digital multi-beam synthesis chip and a digital phased array structure schematic diagram based on the digital multi-beam synthesis chip are provided.

[0028] The digital multi-beam synthesis chip includes a receive multi-beam synthesis link, a transmit multi-beam synthesis link, a daisy-chain SerDes high-speed interface and a frequency synthesizer;

[0029] The receiving multi-beam synthesis link is used to connect the sub-array antenna unit and the RF receiving link, and send the received signals amplified and down-converted by the sub-array antenna unit and the RF receiving link to multiple orthogonal / co-directional ADCs. Each ADC is output to multiple digital beam synthesis modules after synchronous sampling. The outputs of the multiple digital beam synthesis modules corresponding to each channel are combined and accumulated to obtain multiple receiving beams.

[0030] The daisy chain SerDes high-speed interface is used to perform parallel / serial conversion on the receiving beam and output it to the next-level digital multi-beam synthesis chip or baseband processing module, and receive the beam signal of the previous-level digital multi-beam synthesis chip for serial / parallel conversion and accumulate and output it with the corresponding receiving beam to realize the daisy chain function of the SerDes interface;

[0031] Digital multi-beam synthesis chip The digital multi-beam synthesis chip transmits a multi-beam synthesis link for receiving beam signals from the previous digital multi-beam synthesis chip or baseband processing module, and performs serial / parallel conversion through the deserializer of the daisy chain SerDes high-speed interface. Each parallel branch represents a beam signal, and each beam signal is sent to multiple digital beam synthesis modules respectively. The outputs of the multiple digital beam synthesis modules corresponding to each beam signal and the outputs of the multiple digital beam synthesis modules corresponding to other beams are combined and accumulated to form multiple transmit beams. After that, they are sent to the RF transmission link through multiple orthogonal / co-directional ADCs, and are output to the corresponding subarray antenna unit after up-conversion and power amplification of the RF transmission link.

[0032] The frequency synthesizer has an output clock synchronization function to ensure the synchronization of the sampling clock after multi-chip expansion.

[0033] Digital multi-beam synthesis chips can be serially extended and connected through the daisy-chain SerDes high-speed interface to form a large-scale digital phased array system. This modular design is conducive to standardized production and function optimization, and reduces R&D and production costs. For example, multiple digital multi-beam synthesis chips can work serially through the daisy-chain SerDes high-speed interface to share processing tasks. Compared with complex integrated designs, it is more convenient to troubleshoot and maintain, and reduces overall costs. The receiving multi-beam synthesis link and the transmitting multi-beam synthesis link complete the integration of key processes from antenna units to beam synthesis inside the chip. The receiving link directly synthesizes the receiving beam after a series of processing of the signals received by the subarray antenna unit, reducing the signal loss in the intermediate links and the need for additional processing circuits, which helps to achieve miniaturization and reduce power consumption. Similarly, the transmitting link improves efficiency from the input of the beam signal to the transmission by the antenna unit after processing. The daisy-chain SerDes high-speed interface realizes efficient connection and data transmission between multiple chips. Through parallel / serial and serial / parallel conversion, the orderly transmission and accumulation of beam signals between multiple chips are realized without increasing excessive wiring and interface complexity. Its daisy chain function allows the chip to be flexibly expanded, and a large-scale multi-beam synthesis system can be built by simply connecting adjacent chips. This simple and efficient connection method reduces a large number of complex wiring and transit circuits in traditional multi-chip connections, reduces power consumption and costs, and is conducive to miniaturized design. For example, in a large phased array system, as the number of antenna units increases, only digital multi-beam synthesis chips need to be added and connected through daisy chains, without the need to redesign the entire system architecture, which reflects good scalability. By integrating a frequency synthesizer with synchronization function, the dependence on external frequency sources and additional frequency calibration circuits is reduced, reducing system complexity and cost, and contributing to miniaturized design.

[0034] In the receiving multi-beam synthesis link, multiple digital beam synthesis modules can be flexibly configured according to needs. For example, by adjusting the parameters of each module or the number of modules involved in the synthesis, different receiving beam requirements can be met, which reflects the high configurability. The parameters of each beam synthesis module can be adjusted independently for different receiving directions or signal characteristics to achieve high-resolution beam reception. For example, in a complex electromagnetic environment, signal sources of different directions and intensities can be accurately distinguished, improving reconnaissance and perception capabilities.

[0035] In the transmit multi-beam synthesis link, after the beam signal from the previous chip is converted from serial to parallel, it is processed by multiple digital beam synthesis modules and combined and accumulated to form a transmit beam. In multi-channel transmission, each beam signal can be processed and optimized independently to ensure the accuracy and performance of the transmit beam. By combining and accumulating the outputs of multiple digital beam synthesis modules, a high-power, high-directional transmit beam can be achieved to meet the needs of different application scenarios such as communication and detection. In communication applications, the parameters of the transmit beam can be flexibly adjusted according to the location and channel conditions of the communication object to improve communication efficiency and capacity. For example, in a multi-user communication scenario, targeted transmit beams can be generated for different users to reduce signal interference and improve spectrum utilization.

[0036] The chip designed in this application fully considers the multiple functional requirements of reconnaissance, detection, perception, tracking, communication, etc. under the multi-domain platform. Through the high-performance, high-resolution, and high-precision multi-beam synthesis capabilities of the digital multi-beam synthesis chip, it is possible to integrate multiple functions under the same chip architecture. For example, during reconnaissance and detection, the target signal can be quickly and accurately detected by using a high-resolution receiving beam; during communication, the communication quality and capacity can be improved by precisely controlling the transmitting beam; during tracking, the beam direction and parameters are dynamically adjusted according to the movement of the target. This integrated design avoids the use of multiple chips or modules with different functions in the multi-domain platform, reduces system complexity, power consumption and cost, and is conducive to miniaturization and integration into multi-domain platform devices. The equalization / pre-equalization capability of the multi-channel receive / transmit link enables the signal processing of different channels in the multi-domain platform to remain consistent and stable. Whether receiving or transmitting, each channel can achieve equalization / pre-equalization parameter adjustment under the control of the chip, ensuring the stability and reliability of the entire system in the multi-beam working mode. This is crucial for the continuous operation of the multi-domain platform in a complex environment, improves the overall performance and adaptability of the system, and further improves key indicators such as communication efficiency and communication capacity. It has broken through the difficulties in realizing low-power, low-cost, and miniaturized engineering of large-scale digital phased array multi-beam synthesis, and proposed a minimalist and optimal multi-beam synthesis solution under the current technical level. It fully considered the high configurability, scalability, and balancing capabilities of multi-channel receive / transmit links, and designed a general-purpose all-digital multi-beam synthesis chip that can provide high-performance, high-resolution, and high-precision multi-beam synthesis capabilities. It provides phased array multi-beam technology for integrated reconnaissance, detection, perception, tracking, and communication in multi-domain platforms, accurate situational awareness, and efficient information exchange, greatly improving communication efficiency and capacity.

[0037] In one embodiment, the receiving multi-beam synthesis link includes a multi-channel orthogonal / co-directional ADC, a direct digital frequency synthesizer, a digital down converter, an extraction filter, a digital beam synthesis module, a delay module and an equalization filter; the equalization filter includes a receiving link I / Q mismatch calibration module and a multi-channel receiving link amplitude and phase mismatch calibration module; the delay module is used to compensate for the time difference of the same beam signal during the cascading of multi-stage digital multi-beam synthesis chips, wherein the time difference in the receiving multi-beam synthesis link is T D,k =kT D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain. If the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, it is added by 1 in sequence according to the serial extension of the daisy chain, kT D,det It is the deterministic delay of the daisy-chain SerDes high-speed interface; the digital beamforming module includes a high-precision TTD module and a digital gain / phase compensation module; the high-precision TTD module includes an integer delay module implemented by a shift register and a fractional delay module implemented by a Farrow filter, which is mainly used to provide the time delay of the broadband signal; the digital gain / phase compensation module can be implemented by a complex domain multiplier, which is mainly used to adjust the amplitude of the broadband signal and the phase of the carrier signal.

[0038] In a specific embodiment, the specific implementation scheme of receiving the multi-beam synthesis link is as follows: Figure 2 As shown in the figure, each digital multi-beam synthesis chip is connected to a sub-array (n antenna units) of the receiving antenna. The received signal is sent to multiple orthogonal / co-directional ADCs through amplification and down-conversion of the sub-array antenna unit and the RF receiving link. Each ADC is output to m digital beam synthesis modules after synchronous sampling. Therefore, n×m digital beam synthesis modules need to be integrated in a single digital multi-beam synthesis chip.

[0039] By combining and accumulating the outputs of the m digital beamforming modules corresponding to each channel and the outputs of the m digital beamforming modules corresponding to other channels, m receiving beams can be formed (each beam corresponds to n laterally arranged digital beamforming modules, and the corresponding receiving beamforming is achieved by changing the delay time of each internal TTD and the gain / phase value in the digital gain / phase adjustment module).

[0040] Considering the scalability, the m receiving beams are converted into parallel / serial signals through the serializer of the SerDes high-speed interface and output to the next-level digital multi-beam synthesis chip; the beam signal from the previous-level digital multi-beam synthesis chip is converted into serial / parallel signals through the deserializer of the SerDes high-speed interface and is accumulated and output with the corresponding receiving synthesis beam, thereby realizing the daisy chain function of the SerDes interface. In order to ensure the synchronization of the accumulation process, a delay module T is required. D,kTo compensate for the time difference of the same beam signal during the cascade of multi-stage digital multi-beam synthesis chips. D,k =kT D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain (the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, and it is increased by 1 according to the serial extension of the daisy chain), kT D,det Deterministic latency for SerDes high-speed interfaces.

[0041] In one embodiment, the transmitting multi-beam synthesis link includes a pre-equalization filter, an interpolation filter, a digital beam synthesis module, a digital up-converter, a direct digital frequency synthesizer, a delay module and an ADC; the pre-equalization filter includes a transmitting link I / Q mismatch calibration module, a multi-channel transmitting link amplitude and phase mismatch calibration module and a power amplifier digital pre-distortion module; the delay module is used to compensate for the time difference of the same beam signal during the cascading of multi-stage digital multi-beam synthesis chips, wherein the time difference in the transmitting multi-beam synthesis link is T D,k =(pk)T D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain. If the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, it is incremented by 1 in sequence according to the serial extension of the daisy chain. p is the number of digital multi-beam synthesis chips connected in the daisy chain. kT D,det It is the deterministic delay of the daisy-chain SerDes high-speed interface; the digital beamforming module includes a high-precision TTD module and a digital gain / phase compensation module; the high-precision TTD module includes an integer delay module implemented by a shift register and a fractional delay module implemented by a Farrow filter, which is mainly used to provide the time delay of the broadband signal; the digital gain / phase compensation module can be implemented by a complex domain multiplier, which is mainly used to adjust the amplitude of the broadband signal and the phase of the carrier signal.

[0042] The specific implementation scheme of multi-beam synthesis in the transmission link is as follows: Figure 3 As shown in the figure, the beam signal from the previous digital multi-beam synthesis chip is converted into serial / parallel through the deserializer of the SerDes high-speed interface. Each parallel branch represents one beam signal, and there are m beam signals in total. Each beam signal is sent to n digital beam synthesis modules respectively, so a single digital multi-beam synthesis chip needs to integrate m×n digital beam synthesis modules.

[0043] The outputs of the n digital beam synthesis modules corresponding to each beam are combined and accumulated with the outputs of the n digital beam synthesis modules corresponding to other beams to form n transmit channel signals (each beam corresponds to n transversely arranged digital beam synthesis modules, and the corresponding transmit beam synthesis is achieved by changing the delay time of each internal TTD and the gain / phase value in the digital gain / phase adjustment module).

[0044] Each digital multi-beam synthesis chip is connected to a subarray of the transmitting antenna (n antenna units). The n transmit channel signals are sent to the RF transmit link through a multi-channel DAC, and are output to the corresponding antenna units after up-conversion and power amplification at the RF transmit front end.

[0045] Considering the scalability, the m receiving beams from the previous Des module are converted into parallel / serial signals through the Ser module and output to the next digital multi-beam synthesis chip. In order to ensure the synchronization of the accumulation process, a delay module T is required. D,k To compensate for the time difference of the same beam signal during the cascade of multi-stage digital multi-beam synthesis chips. D,k =(pk)T D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain (the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, and it is increased by 1 according to the serial extension of the daisy chain, and p is the number of digital multi-beam synthesis chips connected in the daisy chain), kT D,det Deterministic latency for SerDes high-speed interfaces.

[0046] In one of the embodiments, the daisy-chain SerDes high-speed interface includes a service data SerDes high-speed interface and a control data SerDes high-speed interface; the service data SerDes high-speed interface is mainly responsible for the transmission of multi-beam synthesis data; and the control data SerDes high-speed interface is mainly responsible for the transmission of chip configuration data.

[0047] In a specific embodiment, the configuration function of the digital multi-beam synthesis chip is implemented through the control data SerDes high-speed interface. The baseband signal processing module includes the node number of the chip in the SerDes daisy chain in the configuration data sent. Each time a node is passed, the node number is reduced by 1 until it reaches 1. The corresponding node chip reads the corresponding configuration data to complete the functional configuration of the node chip.

[0048] In the digital multi-beam synthesis process, the delay value of TTD and the amplitude / phase compensation value of the amplitude / phase compensation module are both calculated under the assumption that there is no delay and amplitude / phase error in the multi-channel transceiver link. However, in reality, due to the random time delay and gain deviation introduced by the low noise amplifier, mixer, filter, variable gain amplifier, ADC, DAC, power amplifier, etc., and the random phase jitter introduced by the local oscillator signal, the multi-channel transceiver link has inherent random time delay deviation, gain deviation and phase deviation, which will significantly deteriorate the performance of digital multi-beam synthesis. Therefore, it is necessary to calibrate the amplitude and phase mismatch of the multi-channel transceiver link.

[0049] Multi-channel amplitude and phase mismatch calibration is performed by combining far-field calibration and near-field mutual coupling calibration. Far-field calibration is a factory calibration, which mainly completes the one-time amplitude and phase mismatch compensation between each channel of the RF transceiver link and stores the compensation results; near-field mutual coupling calibration is mainly responsible for real-time calibration during the normal working stage to compensate for the random amplitude and phase offset between multiple channels caused by aging, temperature changes and other phenomena.

[0050] Far-field calibration is divided into far-field calibration of RF receiving link and far-field calibration of RF transmitting link. The far-field calibration of RF receiving link is calibrated by placing an RF transmitting source at a relatively far distance and coinciding with the central axis of the planar phased array. The RF signal emitted by the transmitting source reaches the planar phased array antenna in parallel and is simultaneously received by the receiving antenna element of the phased array. The signal received by one element is arbitrarily selected as the reference signal (or the transmitting RF signal source is selected as the reference signal). The signals received by other elements are compared with the reference signal, and the corresponding gain and phase deviations are respectively given, and then stored in the non-volatile memory on the chip (the non-volatile memory can be EEPROM, Flash or standard CMOS process MTP memory). For the RF transmitting link, a digital reference signal source is used to transmit through the RF transmitting link in sequence, and the far-field antenna is used to receive in sequence. The received results are compared with the reference signal source, and the amplitude and phase deviations obtained are respectively stored in the non-volatile memory on the chip. Then the near-field mutual coupling calibration method is used, and the amplitude and phase deviation information of each antenna element relative to the reference element is recorded and stored in the non-volatile memory.

[0051] Then, the near-field mutual coupling calibration method is used to divide the phased array planar antenna into multiple sub-arrays. Each sub-array is further divided into multiple transceiver arrays according to the internal receiving and transmitting antenna units. The transmitting units in each transceiver array transmit serially, and the receiving units receive in parallel. The amplitude and phase values ​​of the receiving link corresponding to the receiving unit are recorded to form a transceiver matrix until all transceiver arrays are covered and all transceiver matrices are recorded.

[0052] During the normal working stage, as the phased array antenna ages and the external environment temperature changes, the gain and phase random deviations of the RF transceiver link gradually change, so it is necessary to re-compensate for such deviations. The method used is: restart the near-field mutual coupling calibration method, re-record all the transceiver matrices, and compare them with the corresponding transceiver matrices that have been stored to obtain the amplitude and phase error compensation results of the transceiver link. The compensation results are used to compensate for the amplitude and phase deviation information in the far-field calibration.

[0053] Therefore, a mismatch calibration method for a digital multi-beam synthesis chip is provided, including:

[0054] After the digital multi-beam synthesis chip is serially extended and connected through the daisy chain SerDes interface to form a large-scale digital phased array system, the multi-channel amplitude-phase mismatch in the digital phased array system is compensated in sequence by serial calibration, including far-field calibration and field calibration, to obtain a compensated time domain response; after the tap coefficients of the equalization filter / pre-equalization filter in the digital multi-beam synthesis chip are configured according to the compensated time domain response, the multi-channel amplitude-phase mismatch is compensated to complete the multi-channel amplitude-phase mismatch calibration;

[0055] After the digital multi-beam synthesis chip is serially extended and connected through the daisy chain SerDes interface to form a large-scale digital phased array system, the orthogonal mismatch of the RF transceiver link itself is far-field calibrated, and then the near-field mutual coupling calibration is performed in the same way as the multi-channel amplitude and phase mismatch calibration to complete the I / Q mismatch calibration; the RF transceiver link includes the RF receiving front end and ADC, the RF transmitting front end and the digital-to-analog converter DAC;

[0056] For each transmitting link in the digital multi-beam synthesis chip, a receiving link is arbitrarily selected as the observation receiving link, and the received signal is fed back to the digital pre-distortion estimation model to estimate the digital pre-distortion parameters of the power amplifier and write them into the non-volatile memory to complete the digital pre-distortion of the power amplifier.

[0057] In one embodiment, a serial calibration method is used to sequentially compensate for the multi-channel amplitude and phase mismatch in a digital phased array system, including far-field calibration and field calibration, to obtain a compensated time domain response, including:

[0058] like Figure 4 As shown in FIG. 1 , the far-field calibration source generates a broadband signal covering the entire frequency band as a calibration baseband input signal through DDS, and reaches the antenna subarray unit corresponding to each digital multi-beam synthesis chip at the same time. The calibration is performed from the digital multi-beam synthesis chip farthest from the baseband processing module in the digital phased array system, and the receiving input end of the deserializer of the farthest digital multi-beam synthesis chip is set to zero. The receiving link is selected by configuring the MUX module through the daisy-chain SerDes high-speed interface. The connection method of the receiving signal link and the digital beamforming module is shown in FIG. Figure 5 As shown, it ensures that the receiving link connected to each antenna array element can be effectively output to the baseband signal processing module through the SerDes interface. Usually, m is an integer multiple of n. After m / n times of signal acquisition, the test coverage of all antenna array elements in the corresponding receiving antenna subarray can be completed. Other digital multi-beam synthesis chips select 0 input signals through MUX;

[0059] The baseband processing module is configured in calibration mode, and the output signals of the receiving link are sequentially sent to the FFT module for frequency domain estimation to generate corresponding amplitude and phase spectra and record them. One receiving / transmitting connection is arbitrarily selected as the reference branch, and other receiving / transmitting connections are used as calculation compensation branches. The quotient of the two is the frequency domain compensation amplitude and phase spectrum of other connection branches; IFFT is performed on the frequency domain compensation amplitude and phase spectrum to obtain the time domain compensation impulse response, and the time domain compensation impulse response is fed back to the equalization compensation register of the corresponding receiving link to perform relative amplitude and phase mismatch compensation on the multi-channel receiving link, and the equalization filter coefficients are configured through the daisy chain SerDes interface.

[0060] In one embodiment, the multi-channel amplitude and phase mismatch calibration of the transmission chain is as follows: Figure 6 As shown in FIG. 1 , the transmit link is far-field calibrated, and serial calibration is performed in units of antenna array elements. Calibration is performed from the digital multi-beam synthesis chip closest to the baseband processing module to the farthest digital multi-beam synthesis chip. The baseband signal processing module generates a multi-tone signal covering the full frequency band through DDS, and sends the multi-tone signal to the first parallel channel. The data of the remaining parallel channels is 0, and is sent to the nearest digital multi-beam synthesis chip after passing through the SerDes module. The digital multi-beam synthesis chip receives the transmit baseband signal from the baseband signal processing module through the receiving port of the deserializer; the connection relationship between the transmit baseband signal and the digital beam synthesis module in the digital multi-beam synthesis chip is shown in FIG. Figure 7 shown.

[0061] The MUX module in the nearest digital multi-beam synthesis chip is ordered to select the signal links corresponding to the antenna array elements in turn, and send them to the far-field calibration antenna through the transmission link via the antenna array elements. The multi-tone signal received by the far-field calibration antenna and the transmission baseband signal are subjected to FFT processing respectively, and the amplitude and phase error compensation coefficients at the corresponding frequencies are given. After IFFT, the time domain coefficients of the compensation equalization filter are obtained and written into the non-volatile memory through the daisy chain SerDes interface.

[0062] As the transceiver link ages with the change of working time, working environment and temperature, the amplitude and phase of the transceiver link will fluctuate randomly or change slowly, which will also cause the amplitude and phase mismatch of the transceiver link. These problems cannot be solved by far-field calibration, especially when the phased array antenna is used on satellite platforms, ground motion platforms, space-based Internet ground terminals and other platforms, so it is necessary to study the corresponding on-site calibration methods. The on-site calibration method usually includes two forms: one is to use an additional external calibration antenna or an embedded calibration antenna for on-site near-field or mutual coupling calibration, and the other is to directly use functional antenna elements and calibrate using the mutual coupling between antenna elements. The former consumes additional antenna elements and the corresponding transceiver link, increasing the complexity of antenna design. The latter completes the corresponding calibration function on the basis of the existing functional unit. The hardware design is simple, but the phased array antenna is required to have both transceiver and transceiver functions.

[0063] In one of the embodiments, the present application is designed to be applicable to any calibration form and calibration platform, and only the mutual coupling calibration between antenna array elements is used as an example for explanation. Other calibration forms have similar working principles, and the specific process is as follows:

[0064] Step 1: After completing the far-field calibration, switch to the antenna array mutual coupling calibration. The antenna array elements send the same multi-tone signal in sequence. The baseband signal processing module records the frequency domain amplitude and phase values ​​of the corresponding receiving link and writes them into the non-volatile memory through the daisy chain SerDes interface. Taking the planar 16-element array as an example, the transmission and reception process is as follows: Figure 8 As shown, serial transmission and parallel reception are performed until all the transmitting and receiving elements are covered. Considering that the coupling strength between antenna elements is inversely proportional to the square of the distance between the elements, in order to avoid excessive coupling strength leading to receiver saturation or too weak coupling strength leading to receiver failure, the distance between the coupled elements needs to be limited to ensure that the receiving link can work properly.

[0065] Step 2: Perform on-site calibration of the phased array antenna, assuming that the transmitting units are T1~T M , the receiving unit is R1~R N After completing the far-field factory calibration, the recorded mutual coupling matrix is ​​C, which is an M×N matrix with c as the internal matrix element. mn (t), represents the mth transmitting element T m With the nth receiving element R n The transfer function between

[0066] Step 3: Record the transfer function matrix C' that needs to be calibrated, perform Fourier transform on each element in the matrices C and C' to convert them to the frequency domain, and record the transformed matrices as FC and FC'. The matrix after element-wise division of the two matrices is E (= FC' / FC), and the elements ec in E aremn (f) represents the mth transmitting array element T m The corresponding frequency domain transfer function change of the transmission link ΔT m (f) and the nth receiving element R n The corresponding frequency domain transfer function change of the receiving link ΔR n (f) the product between;

[0067] Step 4: Perform a complex logarithmic transformation on the elements in the matrix E, and perform a ln operation on the frequency domain transfer function change of each element in the matrix E. At this time, the multiplication operation becomes an addition operation, which is expressed as ΔLT m (f)+ΔLR n (f), where ΔLT m (f) = ln(T m (f)), ΔLR n (f) = ln(R n (f));

[0068] Step 5: Construct an overdetermined matrix equation Ax=b based on the matrix in step 4; use the least squares method to determine the matrix x=(A T A) -1 A T b;

[0069] Step 6: Perform a complex exponential operation on each element in the matrix x obtained in step 5, and perform an inverse Fourier transform on each element to obtain a time domain compensation response.

[0070] In a specific embodiment, it should be noted that step 5 needs to have a signal-to-noise ratio calibration function (the ratio of in-band signal power to out-band noise power). If the signal-to-noise ratio is too weak, it is considered to be caused by physical damage to the antenna array element, and this item needs to be eliminated.

[0071] In one embodiment, constructing an overdetermined matrix equation Ax=b according to the matrix in step 4 includes:

[0072] x is a (M+N)×1 matrix, the first M elements are the changes in the frequency domain transfer function of the M transmitting array elements, and the last N elements are the changes in the frequency domain transfer function of the N receiving array elements; b is a P×1 matrix, P=M×N is the number of elements in the matrix E, and the elements in b are formed by expanding the elements in the matrix E in order of rows and columns.

[0073] In one embodiment, a far-field calibration is performed on the orthogonality mismatch of the RF transceiver link itself, including:

[0074] In the far-field calibration stage, for the I / Q mismatch calibration of the receiving link, all antenna array elements simultaneously receive the RF signal from the transmitting source and send it to the corresponding digital multi-beam synthesis chip through the receiving link. The digital multi-beam synthesis chip integrates an I / Q mismatch adaptive calibration algorithm, and calibrates the orthogonal mismatch of each receiving link of the digital multi-beam synthesis chip in turn, and writes the calibration values ​​into the non-volatile memory respectively; for the I / Q mismatch calibration of the transmitting link, the baseband signal processing module uses the same method as the multi-channel amplitude and phase mismatch calibration of the transmitting link to send the RF signal to the far-field receiving antenna through the transmitting link in turn. After the far-field receiving antenna receives the signal, it estimates the orthogonal mismatch parameters of the received signal in turn, and writes them into the non-volatile memory of the digital multi-beam synthesis chip in turn through the SerDes daisy chain interface.

[0075] After the far-field calibration is completed, the near-field mutual coupling calibration is performed in the same manner as the multi-channel amplitude-phase mismatch calibration. The specific process is the same as Figure 8 same.

[0076] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A digital multi-beam synthesis chip, characterized in that: The digital multi-beam synthesis chip includes a receiving multi-beam synthesis link, a transmitting multi-beam synthesis link, a daisy chain SerDes high-speed interface and a frequency synthesizer; The receiving multi-beam synthesis link is used to connect the sub-array antenna unit and the radio frequency receiving link, and send the received signals amplified and down-converted by the sub-array antenna unit and the radio frequency receiving link to multiple orthogonal / co-directional ADCs. Each ADC is output to multiple digital beam synthesis modules after synchronous sampling. The outputs of the multiple digital beam synthesis modules corresponding to each channel are combined and accumulated to obtain multiple receiving beams. The daisy chain SerDes high-speed interface is used to perform parallel / serial conversion on the receiving beam and output it to the next-level digital multi-beam synthesis chip or baseband processing module, and receive the beam signal of the previous-level digital multi-beam synthesis chip to perform serial / parallel conversion and accumulate and output with the corresponding receiving beam to realize the daisy chain function of the SerDes interface; The transmitting multi-beam synthesis link is used to receive the beam signal from the previous level digital multi-beam synthesis chip or baseband processing module and perform serial / parallel conversion through the deserializer of the daisy chain SerDes high-speed interface. Each parallel branch represents one beam signal, and each beam signal is sent to multiple digital beam synthesis modules respectively. The outputs of the multiple digital beam synthesis modules corresponding to each beam signal and the outputs of the multiple digital beam synthesis modules corresponding to other beams are combined and accumulated respectively. After forming multiple transmit beams, they are sent to the RF transmission link through multiple orthogonal / co-directional ADCs, and are output to the corresponding subarray antenna unit after up-conversion and power amplification of the RF transmission link. The frequency synthesizer has an output clock synchronization function to ensure the synchronization of the sampling clock after multi-chip expansion.

2. The digital multi-beam synthesis chip according to claim 1, characterized in that: The receiving multi-beam synthesis link includes a multi-channel orthogonal / co-directional ADC, a direct digital frequency synthesizer, a digital down converter, a decimation filter, a digital beam synthesis module, a delay module and an equalization filter; The equalization filter includes a receiving link I / Q mismatch calibration module and a multi-channel receiving link amplitude and phase mismatch calibration module; the delay module is used to compensate for the time difference of the same beam signal during the cascade of multi-stage digital multi-beam synthesis chips, wherein the time difference in the receiving multi-beam synthesis link is T D,k =kT D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain. If the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, it is added by 1 in sequence according to the serial extension of the daisy chain, kT D,det It is a deterministic delay of a daisy-chain SerDes high-speed interface; the digital beamforming module includes a high-precision TTD module and a digital gain / phase compensation module; the high-precision TTD module includes an integer delay module implemented by a shift register and a fractional delay module implemented by a Farrow filter, which is mainly used to provide a time delay for a broadband signal; the digital gain / phase compensation module can be implemented by a complex domain multiplier, which is mainly used to adjust the amplitude of the broadband signal and the phase of the carrier signal.

3. The digital multi-beam synthesis chip according to claim 1, characterized in that: The transmitting multi-beam synthesis link includes a pre-equalization filter, an interpolation filter, a digital beam synthesis module, a digital up-converter, a direct digital frequency synthesizer, a delay module and an ADC; the pre-equalization filter includes a transmitting link I / Q mismatch calibration module, a multi-channel transmitting link amplitude and phase mismatch calibration module and a power amplifier digital pre-distortion module; the delay module is used to compensate for the time difference of the same beam signal during the cascading process of multi-stage digital multi-beam synthesis chips, wherein the time difference in the transmitting multi-beam synthesis link is T D,k =(pk)T D,det , k is the node number of the digital multi-beam synthesis chip in the daisy chain. If the node number of the digital multi-beam synthesis chip connected to the digital baseband processing module is 1, it is incremented by 1 in sequence according to the serial extension of the daisy chain. p is the number of digital multi-beam synthesis chips connected in the daisy chain. kT D,det It is a deterministic delay of a daisy-chain SerDes high-speed interface; the digital beamforming module includes a high-precision TTD module and a digital gain / phase compensation module; the high-precision TTD module includes an integer delay module implemented by a shift register and a fractional delay module implemented by a Farrow filter, which is mainly used to provide a time delay for a broadband signal; the digital gain / phase compensation module can be implemented by a complex domain multiplier, which is mainly used to adjust the amplitude of the broadband signal and the phase of the carrier signal.

4. The digital multi-beam synthesis chip according to claim 1, characterized in that: The daisy-chain SerDes high-speed interface includes a service data SerDes high-speed interface and a control data SerDes high-speed interface; the service data SerDes high-speed interface is mainly responsible for the transmission of multi-beam synthesis data; and the control data SerDes high-speed interface is mainly responsible for the transmission of chip configuration data.

5. A method for calibrating mismatch of a digital phased array system based on the digital multi-beam synthesis chip according to claims 1 to 4, characterized in that: The method comprises: After the digital multi-beam synthesis chip is serially extended and connected through a daisy chain SerDes interface to form a large-scale digital phased array system, the multi-channel amplitude-phase mismatch in the digital phased array system is compensated in sequence by serial calibration, including far-field calibration and field calibration, to obtain a compensated time domain response; after the tap coefficients of the equalization filter / pre-equalization filter in the digital multi-beam synthesis chip are configured according to the compensated time domain response, the multi-channel amplitude-phase mismatch is compensated to complete the multi-channel amplitude-phase mismatch calibration; After the digital multi-beam synthesis chip is serially extended and connected through a daisy chain SerDes interface to form a large-scale digital phased array system, the orthogonal mismatch of the RF transceiver link itself is far-field calibrated, and then the near-field mutual coupling calibration is performed in the same way as the multi-channel amplitude and phase mismatch calibration to complete the I / Q mismatch calibration; the RF transceiver link includes an RF receiving front end and ADC, an RF transmitting front end and a digital-to-analog converter DAC; For each transmitting link in the digital multi-beam synthesis chip, a receiving link is arbitrarily selected as the observation receiving link, and the received signal is fed back to the digital pre-distortion estimation model to estimate the digital pre-distortion parameters of the power amplifier and write them into the non-volatile memory to complete the digital pre-distortion of the power amplifier.

6. The method according to claim 5, characterized in that The multi-channel amplitude and phase mismatch in the digital phased array system is compensated in sequence by serial calibration, including far-field calibration and field calibration, to obtain the compensated time domain response, including: Perform far-field calibration on the receiving link, calibrate the digital multi-beam synthesis chip farthest from the baseband processing module in the digital phased array system, set the receiving input of the deserializer of the farthest digital multi-beam synthesis chip to zero, configure the MUX module to select the receiving link through the daisy-chain SerDes high-speed interface, and ensure that the receiving link connected to each antenna array element can be output to the baseband signal processing module through the daisy-chain SerDes high-speed interface; The baseband processing module is configured in calibration mode, and the output signals of the receiving link are sequentially sent to the FFT module for frequency domain estimation to generate corresponding amplitude and phase spectra and record them. One receiving / transmitting connection is arbitrarily selected as the reference branch, and other receiving / transmitting connections are used as calculation compensation branches. The quotient of the two is the frequency domain compensation amplitude and phase spectrum of other connection branches; IFFT is performed on the frequency domain compensation amplitude and phase spectrum to obtain the time domain compensation impulse response, and the time domain compensation impulse response is fed back to the equalization compensation register of the corresponding receiving link to perform relative amplitude and phase mismatch compensation on the multi-channel receiving link, and the equalization filter coefficients are configured through the daisy chain SerDes interface.

7. The method according to claim 6, characterized in that The method further comprises: Perform far-field calibration on the transmit link, perform serial calibration in units of antenna elements, and gradually calibrate from the digital multi-beam synthesis chip closest to the baseband processing module to the farthest digital multi-beam synthesis chip. The baseband signal processing module generates a multi-tone signal covering the full frequency band through DDS, and sends the multi-tone signal to the first parallel channel. The data of the remaining parallel channels is 0, and is sent to the nearest digital multi-beam synthesis chip after passing through the SerDes module. The digital multi-beam synthesis chip receives the transmit baseband signal from the baseband signal processing module through the receiving port of the deserializer. The MUX module in the nearest digital multi-beam synthesis chip is ordered to select the signal links corresponding to the antenna array elements in turn, and send them to the far-field calibration antenna through the transmission link via the antenna array elements. The multi-tone signal received by the far-field calibration antenna and the transmission baseband signal are subjected to FFT processing respectively, and the amplitude and phase error compensation coefficients at the corresponding frequencies are given. After IFFT, the time domain coefficients of the compensation equalization filter are obtained and written into the non-volatile memory through the daisy chain SerDes interface.

8. The method according to claim 7, characterized in that: The method further comprises: Step 1: After completing the far-field calibration, switch to the antenna array mutual coupling calibration. The antenna array elements send the same multi-tone signal in sequence. The baseband signal processing module records the frequency domain amplitude and phase values ​​of the corresponding receiving link and writes them into the non-volatile memory through the daisy chain SerDes interface. Step 2: Perform on-site calibration of the phased array antenna, assuming that the transmitting units are T1~T M , the receiving unit is R1~R N After completing the far-field factory calibration, the recorded mutual coupling matrix is ​​C, which is an M×N matrix with c as the internal matrix element. mn (t), represents the mth transmitting array element T m With the nth receiving array element R n The transfer function between Step 3: Record the transfer function matrix C' that needs to be calibrated, perform Fourier transform on each element in the matrices C and C' to convert them to the frequency domain, and record the transformed matrices as FC and FC'. The matrix after element-wise division of the two matrices is E (= FC' / FC), and the elements ec in E are mn (f) represents the mth transmitting array element T m The corresponding frequency domain transfer function change of the transmission link ΔT m (f) and the nth receiving element R n The corresponding frequency domain transfer function change of the receiving link ΔR n (f) the product between; Step 4: Perform a complex logarithmic transformation on the elements in the matrix E, and perform a ln operation on the frequency domain transfer function change of each element in the matrix E. At this time, the multiplication operation becomes an addition operation, which is expressed as ΔLT m (f)+ΔLR n (f), where ΔLT m (f) = ln(T m (f)), ΔLR n (f) = ln(R n (f)); Step 5: Construct an overdetermined matrix equation Ax=b based on the matrix in step 4; use the least squares method to determine the matrix x=(A T A) -1 A T b; Step 6: Perform a complex exponential operation on each element in the matrix x obtained in step 5, and perform an inverse Fourier transform on each element to obtain a time domain compensation response.

9. The method according to claim 8, characterized in that Construct an overdetermined matrix equation Ax=b based on the matrix in step 4, including: x is a (M+N)×1 matrix, the first M elements are the changes in the frequency domain transfer function of the M transmitting array elements, and the last N elements are the changes in the frequency domain transfer function of the N receiving array elements; b is a P×1 matrix, P=M×N is the number of elements in the matrix E, and the elements in b are formed by expanding the elements in the matrix E in order of rows and columns.

10. The method according to claim 5, characterized in that Perform far-field calibration of the orthogonality mismatch of the RF transmit and receive link itself, including: In the far-field calibration stage, for the I / Q mismatch calibration of the receiving link, all antenna array elements simultaneously receive the RF signal from the transmitting source and send it to the corresponding digital multi-beam synthesis chip through the receiving link. The digital multi-beam synthesis chip integrates an I / Q mismatch adaptive calibration algorithm, and calibrates the orthogonal mismatch of each receiving link of the digital multi-beam synthesis chip in turn, and writes the calibration values ​​into the non-volatile memory respectively; for the I / Q mismatch calibration of the transmitting link, the baseband signal processing module uses the same method as the multi-channel amplitude and phase mismatch calibration of the transmitting link to send the RF signal to the far-field receiving antenna through the transmitting link in turn. After the far-field receiving antenna receives the signal, it estimates the orthogonal mismatch parameters of the received signal in turn, and writes them into the non-volatile memory of the digital multi-beam synthesis chip in turn through the SerDes daisy chain interface.

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